JP2587415B2 - Data processing system with variable memory bank selection - Google Patents

Description

The present invention relates to the field of computer graphics. In particular, the invention relates to the field of bitmapped computer graphics where the computer memory stores data for each pixel or pixel of the display in a memory location corresponding to the location of the pixel on the display. The field of bitmapped computer graphics has provided a significant advantage in lowering the cost per bit of dynamic random access memory (DRAM). The lower cost per bit of memory allows the formation of larger and more complex displays in a bit-mapped fashion.

2. Description of the Related Art The reduction in the cost per bit of memory and the accompanying increase in the capability of bit-mapped computer graphics are:
A need has arisen for a processing device that allows the bitmap memory to be advantageously used in computer graphics applications. That is, devices have emerged that include the ability to draw simple graphics such as lines and circles under the control of the main processor of the computer. In addition, some devices of this type
Bit block transfers (known as BIT-BLT or raster operations), including the transfer of image data from one part of the memory to another, as well as a logical or arithmetic combination of the data with data at a specified location in the memory Etc. with limited capabilities.

PROBLEM TO BE SOLVED The bitmap controller having a hard-wired function of drawing a line and performing other basic graphic operations represents one method of meeting the performance requirements of a bitmap display. The incorporation of algorithms that perform some of the most frequently used graphics operations provides a way to improve overall system performance. However, useful graphics systems often require many features in addition to those implemented with such hardwired controllers. These necessary additional functions must be performed in software by the main processor of the computer. In general, such hardwired bitmap controllers allow only limited access to the bitmap memory to the processor, limiting the extent to which software can increase the hardwired controller's fixed functional capabilities. Thus, by providing a more powerful graphics controller, improving access to bitmap memory by the system processor, or both, a more flexible solution to the problems associated with controlling the contents of bitmap memory. It would be very useful if a solution could be given.

SUMMARY OF THE INVENTION The present invention relates to a method for generating row and column address signals and bank select signals for easy connection of a processor to a plurality of memory banks. In accordance with the invention, a processor generates a set of overlapping bit signals for row and column address signals at different times. This set of overlapping address bits enables a second strobe signal corresponding to a column address strobe cycle to be used to select a memory bank.

In the preferred embodiment of the present invention, a 64K DRAM is used. 6
A typical way to provide the 16 address bits needed to specify individual bits in the 0K DRAM is to use two address cycles. First, an 8-bit row address is applied to the address input during a row address strobe cycle indicated by a row address strobe (RAS) signal. Next, a column address, also eight bits, is applied to the address input during a column address strobe cycle indicated by the column address strobe (CAS) signal.
The row and column addresses must be consecutive in order to have a continuous linear address from the lowest possible address to the highest possible address. That is, one least significant bit of these two addresses must be adjacent to the other most significant bit. This is typically achieved by having the row address occupy the most significant bit and the column address the least significant bit.

The address register of the processor is longer than necessary to specify individual bits in the DRAM. According to the present invention, a set of contiguous bits in an address register is applied to the local address / data bus during a row address strobe cycle. Another set of consecutive bits is applied to the local address / data bus during the column address strobe cycle. This second set of address register bits is different from, but duplicates, the first set of bits output during the row address strobe cycle. That is, some of the same bits that were previously output during the row address strobe cycle from the address register are output during the column address strobe cycle. These repetitions or duplicate bits are determined by the processor's local address /
Output to different pins of the data bus.

This overlap is provided so that each pin of the local address / data bus has a column address output from a location in the address register that differs by a predetermined amount from the row address appearing on the same pin. . This predetermined amount is related to the size of the memory, and thus the width of the row and column addresses required to specify individual bits in the memory. In a preferred embodiment using 64K DRAM,
The difference in bit positions is eight.

The invention also helps to minimize the circuitry external to the processor required to interface with any number of memory banks. A set of bank select bits are selected from the least significant bit output during a column address strobe cycle. The row and column addresses applied to the memory are taken from the next most significant local address / data bus contiguous bit zone above the bank select bits. The above-described duplicate output scheme ensures that such zones, equal in length and width in row and column addresses, contain address bits from the address register and specify an ungapped address space. That is, the present scheme provides a convenient way to provide each row and column address and bank select bit.

The above and other objects of the present invention will be easily understood from the following description with reference to the drawings.

FIG. 1 shows a block diagram of a graphics computer system 100 constructed in accordance with the principles of the present invention.
The graphics computer system 100 includes a host processing system 110, a graphics processor 120, and a memory 13.
0, a shift register 140, a video palette 150, a digital / video converter 160, and a video display 170.

Host processing system 110 provides the primary computing power for graphics computer system 100. Host processing system 110 preferably includes at least one microprocessor, read-only memory, random access memory, and various peripherals to form a complete computer system. Also host processing system 110
It is also preferable to have some form of input device, such as a keyboard or mouse, and some form of long-term storage, such as a disk drive. The details of the configuration of the host processing system 110 are conventional in nature and well known in the art, and will not be described in further detail here. As far as the present invention is concerned, an important feature of the host processing system 110 is that
Determines the content of the visible display presented to the user.

Graphics processor 120, in accordance with the present invention, provides key data manipulation for generating a particular video display to be presented to a user. The graphics processor 120 is bidirectionally connected to the host processing system 110 via the host bus 115. According to the present invention, the graphics processor 120 operates as a data processor independent of the host processing system 110, while the host bus 115
Is required to respond to requests from the host processing system 110 via the. Graphics processor 120 further communicates with memory 130 and video palette 150 via video memory bus 122. That is, the graphics processor 120 controls the data stored in the video RAM 132 via the video memory bus 122. Graphics processor 120 may also be controlled by programs stored in video RAM 132 or read-only memory (RAM) 134. The read-only memory 134 further includes various graphic image data such as alphanumeric characters of one or more font styles and frequently used microcomputers. Further, graphics processor 120 controls data stored in video palette 150. This feature will be described in more detail later. Finally, graphics processor 120 controls digital / video converter 160 via video control bus 124. In other words, the graphics processor 120 can control the line length and the number of lines per video image of one frame presented to the user by controlling the digital / video converter 160 via the video control bus 124.

The video memory 130 includes a video RAM 132 bidirectionally connected to the graphics processor 120 via a video memory bus 122, and a read-only memory 134. As mentioned above, video RAM 132 contains bitmapped graphics data that controls the video images presented to the user. This video data may be manipulated by the graphics processor 120 via the video memory bus 122. The video data corresponding to the current display screen is output from the video RAM 132 via the video output bus 136. Data from the video output bus 136 corresponds to the pixels presented to the user. In the preferred embodiment, the video RAM 132 is the Texas Inst.
It is formed of a plurality of TMS4161 dynamic random access integrated circuits commercially available from rument. TMS416
One integrated circuit has dual ports, allowing display refresh and update without interference.

Shift register 140 receives video data from video RAM 130 and assembles it into a display bit stream. According to the general configuration of video RAM 132, this memory consists of several separate banks of RAM integrated circuits. The output of each of these integrated circuits is typically a single bit wide. Therefore, in order to specify a picture to be presented to the user with a sufficiently high data output speed, it is necessary to aggregate data from a plurality of integrated circuits. Shift register
140 are loaded in parallel from video output bus 136. This data is output serially on line 145. That is, shift register 140 aggregates the display bit stream and provides video data at a rate sufficient to specify each bit in a raster-scan video display.

The video palette 150 is transferred from the shift register 140 to the bus 14
Receive video data fast through 5. The video palette 150 also receives data from the graphics processor 120 via the video memory bus 122. The video pallet 150 transfers the data received from the bus 145 to the bus 15
Convert to video level output on 5. This conversion is accomplished by a look-up table specified by the graphics processor 120 via the video memory bus 122. The output of video palette 150 consists of the hue and saturation of each pixel, or the three primary levels of red, green and blue for each pixel. The conversion table based on the code stored in the video memory 132 and the digital level output via the bus 155 are controlled by the graphics processor 120 via the video memory bus 122.

Digital / video converter 160 receives digital video information from video palette 150 via bus 155.
Digital / video converter 160 is controlled by graphics processor 120 via video control bus 124.
The digital / video converter 160 converts the digital output of the video palette 150 to a desired analog level and outputs the video output.
Add to video display 170 via 165. Digital / video display 160 is also controlled by graphics processor 120 via video control bus 124,
For example, the number of pixels per horizontal line and the number of lines per frame are specified. Data in the graphics processor 120 is controlled by the digital / video converter 160 to generate synchronization and blanking and replacement signals. These portions of the video signal form the control signals required to specify the desired video output, rather than being specified by data stored in video memory 132.

Finally, the video display 170 is connected to video output line 1
A video output is received from the digital / video converter 160 via 65. Video display 170 generates a predetermined video image that is viewed by an operator of graphics computer system 100. Note that the video palette 150, digital / video converter 160, and video display 170 may operate according to two main video formats. In the first method, video data is specified by hue and saturation for each pixel. In the second scheme, each of the three primary levels of red, blue and green is specified for each pixel. Depending on the design choice of which of these key schemes to use, the Video Palette 15
0, digital / video converter 160 and video display
170 must be configured to be compatible with the scheme. However, the principles of the present invention with respect to the operation of graphics processor 120 remain unchanged regardless of the particular design choice of the video format.

FIG. 2 shows the graphics processor 120 in more detail. The graphics processor 120 includes a central processing unit (CPU) 200 and special graphics hardware 21
0, register file 220, instruction cache 230, host interface 240, memory interface 250, input / output register 260, and video display controller 2
70 is provided.

The central part of the graphics processor 120 is the central processing unit 2
00. Central processing unit 200 is capable of performing general purpose data processing, including many arithmetic and logical operations normally included in general purpose central processing units. Also, the central processing unit 200 alone or in cooperation with the special graphics hardware 210 controls a number of special purpose graphics instructions.

Graphics processor 120 includes a main bus 205 connected to a majority of graphics processor 120, including central processing unit 200. Central processing unit 200 is bi-directionally connected through a bi-directional register bus 202 to a set of register files containing a number of data registers. The register file 220 functions as a storage location for readily accessible data used by the central processing unit 200. As will be described in greater detail below, register file 220 includes a number of data registers used to store implicit operands for graphics instructions in addition to the general purpose registers used by central processing unit 200.

Further, the central processing unit 200 is connected to the instruction cache 230 via the instruction cache bus 204. Instruction cache 2
30 is further connected to a general-purpose bus 205 and a video memory bus 1
Video memory 130 via 22 and memory interface 250
Can be loaded. The purpose of the instruction cache 230 is to increase the execution speed of some functions of the central processing unit 200. Iterative functions, or functions that are often used within a specific part of the program executed by the central processing unit 200,
It may be stored in the instruction cache 230. Accessing the instruction cache 230 via the instruction cache bus 204 is much faster than accessing the video memory 130. Thus, a program executed by the central processing unit 200 stores a series of repeated or frequently used instructions in the instruction cache.
Speed up by loading in advance into the 230. These instructions can then be executed more quickly because they are fetched more quickly. The instruction cache 230 need not always contain the same set of instructions and the central processing unit 200
Can load a particular set of instructions that are commonly used within a particular part of the program that is executed.

The host interface 240 is connected to the central processing unit 200 via the host interface bus 206. Further, the host interface 240 is connected to the host processing system 110 via the host system bus 115. The host interface 240 controls communication between the host processing system 110 and the graphics program 120. That is, the host interface 240 is connected to the host processing system 110.
And the graphics processor 120 to control the timing of data transmission. This control allows the host interface 240 to interrupt the graphics processor 120 from the host processing system 110 or vice versa. Further, the host interface 240 is connected to the main bus 205, and the host processing system 11
0 makes it possible to directly control the data stored in the memory 130. Typically, host interface 240 communicates graphics requests from host processing system 110 to graphics processor 120, allowing the host processing system to specify the type of display to be generated on video display 170, and
At 120, the desired graphic function is executed.

The central processing unit 200 is connected to the special graphics hardware 210 via the graphics hardware bus 208. The special graphics hardware 210 is further connected to the main bus 205. Special graphics hardware 210 cooperates with central processing unit 200 to perform special graphics processing operations. The central processing unit 200 performs general purpose data processing functions and also controls special graphics hardware 210 to execute special purpose graphics instructions. These special purpose graphics instructions
Associated with data manipulation in the video map portion of video RAM 132. The special graphics hardware 210 operates under the control of the central processing unit 200 and enables particularly useful data operations on the data in the video RAM 132.

The memory interface 250 is connected to the main bus 205 and the video memory bus 122. Memory interface 250
Controls the exchange of data and instructions between the graphics processor 120 and the memory 130. The memory 130 includes bitmap data to be displayed via the video display 170, and instructions and data necessary for controlling the operation of the graphics processor 120. This control function includes control of memory access timing and control of multiplexing of data and memory. In the preferred embodiment, video memory bus 122 contains multiplexed address and data information. The memory interface 250 provides the graphics processor 12 with access to the memory 130 at a suitable time.
0 allows for providing an appropriate output on video memory bus 122.

Graphics processor 120 further includes an input / output register 260 and a video display controller 270. An input / output register 260 is bi-directionally connected to the main bus 205 and allows reading and writing within the register. ON /
Output register 260 is preferably in the normal memory space of central processing unit 200. Input / output register 26
0 includes data specifying the control parameters of the video display controller 270. Based on the data stored in the input / output registers 260, the video display controller 270 generates signals on the video control bus 124 necessary for the desired control of the digital / video converter 160. The data in input / output register 260 includes data specifying the number of pixels per horizontal line, the horizontal sync and blanking interval, the number of horizontal lines per frame, the vertical sync and blanking interval. The input / output register 260 may include data for specifying the type of frame interlace or data for specifying another type of video control function. Further, the input / output register 260 also serves as a storage location for special input / output parameters other than those described above in detail.

Graphics processor 120 operates in two different address modes to address memory 130.
The two address modes are XY addressing and linear addressing. Since the graphics processor 120 operates on both bit-mapped graphics data and regular data and instructions, different portions of the memory 130 may be most advantageously accessed with different addressing modes. Regardless of which addressing mode is selected, memory interface 250 generates the correct physical address for the data to be accessed. In linear addressing, the start address of the field is formed by one multi-bit linear address. The field size is determined by the data in the status register in the central processing unit 200. In XY address designation, a start address is given by a pair of X and Y coordinate values. The field size is equal to the pixel size, which is the number of bits required to specify the particular data at the specified pixel.

FIG. 3 shows the structure of pixel data based on the XY addressing mode. FIG. 4 also shows a similar data structure based on the linear addressing mode. FIG. 3 shows an origin 310 which is a reference point of an XY matrix of pixels. The origin 310 is specified as the XY start address and need not be the first address location in memory. The data position corresponding to the pixel array of the specific image or the like is specified with respect to the origin address 310. This data location is X
A start address 340 and a Y start address 330 are included.
The X start address 340 and the Y start address 330 together with the origin indicate the start address of the first pixel data 371 of the desired specific image. The image width in pixels is indicated by the quantity Delta X350. Also, the image height in pixels is indicated by the quantity delta Y360. In the example shown in FIG. 3, the image contains nine pixels designated 371-379. The final parameter required to specify the physical address for each of these pixels is the image pitch 320, which indicates the width of the memory in bits. These parameters are: X Start Address 340, Y Start Address 330, Delta X350, Delta Y360 and Screen Pitch 3
With the designation of 20, the memory interface 250 can give the designated physical address based on the designated XY addressing scheme.

FIG. 4 also shows the configuration of the memory in a linear fashion. A set of fields 441-446 similar to the pixels 371-376 shown in FIG. 3 are shown in FIG. To specify a specific image using the linear addressing method, the following parameters are required. The first is the start address 410
Where this is a linear start address indicating the beginning of the first field 441 of the desired array. Second quantity Delta X420
Indicates the length of a particular segment in the field in bits. Third quantity Delta Y (not shown in FIG. 4)
Indicates the number of specific segments in a specific array. Finally, a linear pitch 430 indicates the difference in linear start address between adjacent array segments. XY
As with addressing, the specification of these linear addressing parameters allows memory interface 250 to generate the correct physical address specified.

The two addressing modes are advantageous for different purposes. That is, the XY addressing mode is a memory portion for controlling the display, which is called a screen memory, and is most effective for a portion of the video RAM 132 including bitmap data. The linear addressing mode is most useful for off-screen memories for instructions, image data not currently displayed, and the like. The latter category includes various standard symbols used in computer systems, such as alphanumeric fonts and icons. It is often desirable to be able to translate XY addresses to linear addresses. This conversion is performed based on the following equation: LA = OFF + (Y × SP) + (X × PS) where: LA is a linear address; OFF is a screen offset, that is, a linear address of the origin in the XY coordinate system; Y is Y
Address; SP is the screen pitch in bits; X is the X address; and PS is the pixel size in bits. Regardless of which addressing mode is used, memory interface 250 generates the correct physical address for accessing memory 130.

FIG. 5 shows a method of storing pixels in a data word of the memory 130. According to a preferred embodiment of the present invention,
Memory 130 consists of 16-bit data words each. These 16 bits are hexadecimal digits OF, and are schematically shown in FIG. Also, in accordance with a preferred embodiment of the present invention, the number of bits per pixel in memory 130 is an integer power of 2 and is less than or equal to 16 bits. With this limitation, each 16-bit word in memory 130 may include such an integer number of pixels. FIG. 5 shows five available pixel formats corresponding to pixel lengths of 1, 2, 4, 8, and 16 bits. Data word 510 is 16
Shows one 1-bit pixel 511-516, with 16 1-bit pixels located within each 16-bit word. Data word 530
Shows eight 2-bit pixels 531 to 538 arranged in a 16-bit data word. Data word 540 shows four 4-bit pixels 541-544 in a 16-bit data word. Data word 550 is two 8-bit pixels 5 in a 16-bit data word
Shows 51 and 552. Finally, data word 560 shows one 16-bit pixel 561 in the 16-bit data word. By manipulating the pixels in the above format, i.e., having each pixel have an integer power of two bits and align with a physical word boundary, pixel manipulation through the graphics processor 120 is enhanced.
This is because the processing of each physical word operates on an integer number of pixels. In the portion of the video RAM 132 that specifies the video display, the pixels of the horizontal line are specified by a sequence of consecutive words as shown in FIG.

FIG. 6 shows the contents of a portion of a register file 220 that stores implicit operands for various graphics instructions. Each of the registers 601 to 611 shown in FIG. 6 is included in the register address space of the central processing unit 200 of the graphics processor 120. However, the register file shown in FIG. 6 does not include all registers that can be arranged in the register file 220. Conversely, a typical system includes a number of general purpose unregistered registers that can be used in the central processing unit 200 for various program specific functions.

Register 601 stores the source address. This is the address of the lower left corner of the source array. That is, this source address is X in the XY addressing mode.
It is a combination of address 340 and Y address 330, or a linear start address in linear addressing mode.

Register 602 stores the source pitch, that is, the difference between the linear start addresses between adjacent columns in the source array. This is either the screen pitch 340 shown in FIG. 3 or the linear pit 430 shown in FIG. 4, depending on whether an XY addressing style or a linear addressing style is used.

Registers 603 and 604 are registers 601 and 6 respectively, except that they contain the destination start address and the destination pitch.
Same as 02. The destination address stored in register 603 is the address of the lower left corner of the destination array in XY addressing mode or linear addressing mode. Similarly, the destination pitch stored in register 604 is the difference between the linear start addresses of adjacent rows, either screen pitch 320 or linear pitch 430, depending on the addressing mode selected.

Register 605 stores the offset. This offset is a linear bit address corresponding to the coordinate origin of the XY addressing method. As described above, the origin 310 of the XY addressing method does not necessarily have to be the physical start address of the memory. The offset stored in register 605 is the linear start address of origin 310 in the XY coordinate system. This offset is used to convert between linear and XY addressing.

Registers 606 and 607 store addresses corresponding to windows in the screen memory. The window start stored in the register 606 is the XY address of the lower left corner of the display window. Similarly, the register 607 stores the window end which is the XY address of the upper right corner of the display window. Each address in these two registers is used to delimit the specified display window. According to the known graphics technology, the image in the window in the graphics display can be different from the background image. The window start and end addresses contained in both registers specify the range of the window and allow the graphics processor 120 to determine whether a particular XY address is inside or outside the window.

Register 608 stores delta Y / delta X data. This register is divided into two independent halves, the upper half (higher bits) being the height of the source array (Delta Y)
And the lower half (lower bit) specifies the width (delta X) of the source array. The Delta Y / Delta X data stored in register 608 is provided in either an XY addressing format or a linear addressing depending on how the source array is specified. The meaning of the quantities delta X, Y has been described above in connection with FIGS.

Registers 609 and 610 each contain pixel data. The color 0 data stored in the register 609 includes a pixel value repeated through the register corresponding to the first color value designation color 0. The color 1 data also stored in the register 610 includes a pixel value repeated through the register corresponding to the second color value designation color 1.
Some of the graphics instructions of the graphics processor 120 use either or both of the above color values in their data operations. The use of both registers will be described in detail later.

Finally, register file 220 includes a register 611 that stores the stack pointer address. The stack pointer address stored in register 611 specifies a bit address in video RAM 132 that is the top of the data stack. As data is pushed onto the data stack, i.e., popping out of the data stack,
Its value changes. Therefore, this stack pointer address indicates the address of the last data put on the data stack.

FIG. 7 schematically illustrates the process of moving an array from off-screen memory to screen memory. FIG. 7 shows the video RAM 132 including the screen memory 705 and the off-screen memory 715. In FIG. 7, the pixel array 780 (more precisely, data corresponding to the pixel array) is transferred from the off-screen memory 715 to the screen memory 7.
The data is transferred to 05 and becomes a pixel array 790.

Certain data must be stored in designated registers of register file 220 before performing an array move operation. That is, the start address 710 of the source pixel array must be loaded into the register 601. In the example shown in FIG. 7, this is specified in the linear addressing mode. Source pitch 720 is stored in register 602. The destination address is specified in the register 603. In the example shown in FIG.
And XY address specification mode including Y address 740. Register 604 stores destination pitch 745. Linear address of origin of XY coordinate system, offset address 770
Is stored in the register 605. Finally, Delta Y750 and Delta X760 are stored in separate halves of register 608, respectively.

The array move operation schematically illustrated in FIG. 7 is performed with the data stored in each register of the register file 220. According to a preferred embodiment, the number of bits per pixel is chosen such that an integer number of pixels are stored in one physical data word. This choice allows the graphics processor to transfer the entire data word,
Pixel array 780 may be transferred to pixel array 790 on a large scale. Despite this choice of bits per pixel, it is necessary to deal with subwords at the boundaries of the array, possibly in relation to the bits per physical data word.
However, the above design choices serve to minimize the need to access and transfer partial data words.

According to a preferred embodiment of the present invention, the data transfer schematically illustrated in FIG. 7 is a special case among a number of different data transformations. Pixel data from corresponding address locations in the source and destination images are combined in a manner specified by the instructions. The combination of data consists of logical functions (AND, OR, etc.) or arithmetic functions (addition, subtraction, etc.). The new data thus stored in pixel array 790 is a function of both the data in pixel array 780 and the current data in pixel array 790. Seventh
The illustrated data transfer is a special case of such a more general data transformation in which the last data stored in the destination array does not depend on the data previously stored therein.

The above process is shown in the flowchart of FIG. According to a preferred embodiment, the transfer occurs continuously by physical data words. When the process starts (start block 801), the data stored in the register 601 is read to obtain a source address (processing block 80).
2). Next, graphics processor 120 fetches the indicated physical data word corresponding to the indicated source address from memory 130 (processing block 803). If the source address is specified in XY format,
This recall of data includes a snap that converts the XY address to the corresponding physical address. Recall the destination address from register 603 (processing block 804) and fetch the indicated physical data word (processing block 80).
5) A similar process is performed on the data contained in the destination location.

Next, the combined data is restored to the previously determined destination location (processing block 806). Then, both the source and destination pixel data are combined based on the combination mode indicated by the particular data transfer instruction being executed. This process is performed on a pixel-by-pixel basis, even if the physical data word contains data corresponding to pixels greater than one. Thereafter, the combination data is written to the specified destination location (processing block 807).

Based on the Delta Y / Delta X information stored in register 608, graphics processor 120 determines whether the entire data transfer has occurred by detecting whether the last data was transferred (decision block).
808). If the entire data transfer is not performed, the source address is updated. Based on the source address previously stored in register 601 and the source pitch data stored in register 602, the source address stored in register 601 is updated to cause the next data word to be transferred (processing block 809). Similarly, the destination address stored in register 603 is updated based on the destination pitch data stored in register 604 to move the next data word to the destination location (processing block 810). This process is repeated with the new source stored in register 601 and the new destination data stored in register 603.

As described above, the delta Y stored in register 608
/ DeltaX is used to limit the limits of the image to be transferred. If the entire image is transferred as instructed with reference to the Delta Y / Delta X data stored in the register 608 (decision block 808), execution of the instruction is completed (end block 811), and the graphics processor 120 Proceed to execute the next instruction in the program. In the preferred embodiment, as described above, the process shown in FIG. 8 is implemented in instruction microcode, and the entire data conversion process, referred to as array movement, is performed by the graphics processor 120.
It is executed according to one instruction.

FIG. 9 shows the structure of the preferred embodiment of the address register of the central processing unit 200. The address register 900 includes two parts, a bit address 901 and a word address 902. In the preferred embodiment, address register 900 contains 3
Includes 2 bits. These 32 bits correspond to bit address 901
4 bits (bits 0-3) for the word address 902 and 2 bits for the word address 902
It is divided into 8 bits (bits 4 to 31). The bit address 901 is used inside the graphics processor 120 to specify a field starting with an arbitrary bit in the memory 130. In the preferred embodiment, memory 130 is organized into 16-bit words each. The higher order bits of the address register 900 comprising the word address 902 are used to select a particular word in the memory 130.

In the preferred embodiment of the present invention, graphics processor 120 uses a triple local address data bus 122. During the first cycle, a row address is generated on the local address / data bus. During the next column address strobe cycle, a column address is generated on the same local address / data bus. Finally, during a data cycle, data is received from the local address / data bus for a read operation and generated on the local address / data bus by the graphics processor 120 for a write operation.

FIG. 10 shows the relationship between a particular pin of the local address / data bus and the address bits generated during two address cycles. FIG. 10 shows a local address / data bus pin 1010, where each bit of the bus is represented by 0-15. Reference numeral 1020 in FIG. 10 indicates bits from the address register 900 generated for the corresponding pin of the local address / data bus during the row address strobe cycle. It can be seen from 1020 in FIG. 10 that during the row address trobe signal, address bits 12-27 from address register 900 are continuously generated on local address / data bus pins 0-15.
During a column address strobe cycle, each bit of the address register 900 shown at 1030 is applied to a local address / data bus pin. As can be seen from 1030, address register bits 4-15 are continuously generated on local address / data bus pins 0-11. Local address / data bus pin 12 produces bit 28 from address register 900,
13 produces bit 29 from address register 900. Bits 14 and 15 of the local address data bus pin correspond to the inverted shift register transfer signal (TR-) and the instruction acquisition signal (IA
Q) is output. The inverted shift register transfer signal is used for controlling data transmission in a multi-port video RAM such as TMS4161 manufactured by Texas Instruments. The use of this signal will be further described later. The instruction acquisition signal is used in a special case where the use of the instruction cache is prohibited. Since this signal does not form part of the present invention,
No further explanation is given. Note in particular that the scheme outputs some of the bits from address register 900, though on different pins during both address cycles. The reason for giving this overlap will be described later.

FIG. 11 shows a local address /
The assignment of data bus pins 1010 to row / column addresses and bank selection is shown. In the preferred embodiment, the row / column address includes 8 bits. These 8 bits of the row / column address correspond to the 8-bit row and column addresses required in modern 64K DRAMs. As is well known in the DRAM art, 64K DRAMs require an 8-bit row address sent during a row address strobe cycle, followed by an 8-bit column address sent during a column address strobe cycle. This multiplexed into two 8-bit words
16-bit data is sufficient to specify different address of 2 ^16, i.e. 65,356. This number of bits is usually 64
Called K bits. As will be described in greater detail below, this addressing scheme can also be used with memories of sizes other than 64K bits by correspondingly adjusting the number of row / column address bits and the bit duplication during the two address cycles.

Generally, DRAM is stacked to a depth equal to the number of bits in a word used in memory. That is, the stacked DR
Each of the AMs receives the same row and column address and provides a different one of the bits of a particular word. According to a preferred embodiment of the present invention, memory 130 uses 16-bit words. Therefore, the addressing scheme of the present invention uses 16 RAs.
The bank composed of M will be described. However, it will be obvious to those skilled in the art that if the memory word used has more or fewer bits, the addressing scheme can be used for memory banks of more or less memory.

FIG. 11 illustrates the division of the local address / data bus into row / column address bits and bank select bits according to a preferred embodiment of the present invention. Element 1010 is
The distribution of bits 0 to 15 of the local address / data bus is the same as that shown in FIG. According to the present invention,
If 16 memory banks are used, the same address outputs as shown in FIG. 10 can be used. When using one memory bank, the address is divided as indicated by 1110. In this case, the row / column address occupies bits 0-7 of the local address / data bus, and the other bits are unused. The case where two memory banks are used is indicated by 1120. The row / column address occupies bits 1-8, with the least significant bit 0 being used as the bank select bit. The state of this bank select bit determines which of the two memory banks is selected. The case of using up to four memory banks is indicated by 1130. The row / column address occupies bits 2-9, and bits 0 and 1 are used as bank select bits. These two bank select bits can specify up to four states, and one of the four memory banks can be specified. 8
The case where up to three memory banks are used is indicated by 1140. line/
The column address bits correspond to bits 3-10 of the local address / data bus. The bank selection bits are 0-2. These bank select bits allow the designation of one of up to eight memory banks. Finally, the case where up to 16 memory banks are used is indicated by 1150. Row / column address bits correspond to bits 4-11 of the local address / data bus, and bits 0-3 correspond to bank select bits.
These four bits allow one of up to 16 memory banks to be selected.

Next, the reason why bits are overlapped between the row address strobe cycle and the column address strobe cycle will be described.
This will be described with reference to FIGS. Note that any of the eight consecutive row / column address bits specified in FIG. 11 can make the combined row and column address 16 consecutive bits. For example, the row / column address shown at 1110 is bits 0-7 of the local address / data bus. Therefore, during the row address strobe cycle, address register bits 12-19 are output. During the subsequent column address strobe cycle, address register bits 4 to 11
Is output. That is, the combined row and column addresses are bits 4-19 of address register 900, which are the 16 least significant bits of word address 902. In the example of up to two memory banks shown at 1120, the row / column address is taken from bits 1-8 of the local address / data bus. The row address corresponds to bits 13 to 20 of the address register 900, and the column address is
Correspond to bits 5 to 13. Thus, the combined row and column address occupies bits 5-20 of address register 900 and the bank select bit is bit 4 of address register 900. In the example of up to four memory banks shown at 1130, row / column addresses correspond to bits 2-9 of the local address / data bus. In this case, address register bits 14-21 are generated during the row address strobe cycle. The next lower bits 6 to 13 are output during the column address strobe cycle. In this case, bits 4 and 5 are bank select bits. In the example shown at 1140, the combined row and column addresses are
Corresponding to bits 7 to 22 of 900, bits 4 to 6 are bank selection bits. Finally, for up to 16 memory banks, indicated by 1160, the combined row / column address corresponds to bits 8-23 of address register 900 and bits 4-23
7 is a bank selection bit. That is, 111 in FIG.
The arbitrary selection of row / column address bits and bank select bits, indicated at 0, 1120, 1130, 1140 and 1150, allows for continuous addressing of the entire memory without creating gaps in the memory space.

FIG. 12 shows timings of various signals for controlling the DRAM forming the memory 130. These signals are typically provided using a logic inversion where the low voltage corresponds to the active signal. Signals appearing on the local address / data bus are shown at 1210. The signals appearing on the local address / data bus are multiplexed in three parts between the row address, the column address and the data. During period 1211,
The row address appears on the local address / data bus. This row address output corresponds to bit 1020 shown in FIG. During a subsequent period 1212, the column address is output. This output corresponds to 1030 shown in FIG.
Finally, during a further period 1213, data is generated or received by the local address / data bus depending on whether the memory cycle is a write cycle or a read cycle.

FIG. 12 further illustrates an inverted row address strobe signal 1220.
Is shown. During the period 1221, the inverted row address strobe signal is at a low level, indicating an active state. Leading edge 1222 of row address strobe active signal 1221
Indicates that the bit appearing on the local address / data bus corresponds to the row address. Similarly, inverted column address strobe signal 1230 is active during period 1231. The leading edge 1232 of the active portion of the inverted column address strobe signal 1231 is the local address /
Indicates when the column address appears on the data bus.

FIG. 12 also shows an inverted local address latch signal 1240 and an inverted data enable signal 1250. The inverted local address latch signal 1240 includes an active period 1241 with a leading edge 1242. That is, the inverted local address latch signal 1240 is output from the local address / data bus 1210
It has its leading edge during the period when the column address is valid. The use of a transparent latch circuit controlled by this inverted local address latch signal allows the capture of column addresses for storage until the local address latch becomes inactive. The latch signal will be described in detail later.
Used to enable storage of column addresses for application to DRAM. The inverted data enable signal 1250 has an active period 1251 and a leading edge 1252. That is, inverted data enable signal 1250 has its leading edge during the period when the local address data bus generates data. As before, the signal controls the transparent latch circuit and is used to capture data for retention until the data enable signal becomes inactive again. That is, the signal is DR
Enables data to be latched for application to AM.

FIG. 13 illustrates the connection of graphics processor 120 to a single bank of DRAMs in accordance with the principles of the present invention. Gfix processor 120 generates a set of signals including a local address / data signal, an inverted local address latch signal, an inverted column address strobe signal, an inverted column address strobe signal, an inverted memory write signal, and an inverted shift register transfer / output signal. Occur. The set of signals is applied to a DRAM as described below.

The local address data output is applied to data bus 1310. Data bus 1310 is applied to the memory via two paths. First, the sub-bus 1311 corresponding to bits 0 to 7 of the local address / data output is applied to the input of the transparent latch 1322. Next, the output of latch 1322 appears on address bus 1320, and video RAM O 1370 and video RAM
N 1375 is added to the address input of each video RAM, symbolically indicated. These video RAMs are special DRAMs suitable for use as bitmap memories and will be described in more detail later.

The transparent latch 1322 is controlled by the inverted local latch signal. Inverted local address latch signal is line
1321 is applied to the enable input of transparent latch 1322. When the local address latch signal is inactive, the transparent latch 1322 is in a transparent state, and the input of the sub bus 1311 can be directly applied to the address bus 1320. line
When the local address latch signal on 1321 goes active, the input state on sub-bus 1311 is captured and
As long as the local address latch signal is active regardless of the change on 1311, that state is output. Twelfth
Referring to the figure, it will be apparent that during the period 1211 when the local address / data bus is generating a row address, the inverted local address latch signal 1240 is inactive. Thus, the row address appearing during period 1211 is added to the address input of each memory in a single memory bank. However, column address is local address / data bus
At the leading edge 1242 of the period output on 1310, the local address latch signal becomes active. Therefore, during the period when the local address latch signal is active 1241
In the middle, the column address is held in the transparent latch 1322 and output to the address bus 1320.

The local address / data bus is also connected to data input / output of each memory. That is, one bit of the local address / data bus 1310 is added to each memory. Bit 0 is the data input D of the local address / data bus 1310 and video RAM 1370 via line 1312
(O) and the output Q (O). Similarly, line 1313 is bidirectionally connected to local address / data bus 1310 and to both data input D (N) and output Q (N) of video RAM N 1375. The representative nth bit corresponds to a representative connection to another memory.

Other signals output from the graphics processor 120 control the video RAM. The inverted column address strobe signal appearing on line 1330 is applied to the column address strobe signal input of each memory. Similarly, a column address strobe signal on line 1340, an inverted write signal on line 1350, and an inverted transfer register signal on line 1360 are applied to each memory.

In the preferred embodiment of the present invention, each memory used is a multiport video R such as TMS4161 from Texas Instrument.
AM. These memories allow two types of access. When used in the parallel access mode, these memories have a standard DRAM per DRAM with 256 rows and 256 columns.
Works as 64K. In this mode of access, one bit access requires transmission of an 8-bit row address and an 8-bit column address. These memories also include a serial access mode, in which a 256-bit internal shift register can be loaded from or written to one row. The particular row involved in this transfer is specified by the row address received on the address bus. The shift register can be loaded or read independently of a serial input port or a serial output port.
These extra data ports allow serial video display access to memory to be achieved without interfering with the processor writing to or reading from the bitmap. Bit 14 or 13 of the local address / data bus during the column address strobe cycle,
The inverted transfer register signal from the TR- output of the graphics processor 120 shown in FIG. 14 is used to control data transfer between the selected row and the internal shift register. The operation of the invert transfer register signal is not necessary to practice the present invention and will not be described further.

The system shown in FIG. 13 operates almost as follows.
During the row address strobe cycle, a signal appears on line 1340, which is the video RAM O 1370 and video RAM N
1375 is added to each memory represented. At this point, the signal on sub-bus 1311 corresponds to the row address signal as shown at 1020. As described above, since latch 1322 is in a transparent state, the signal is applied to each address input via address bus 1320. In subsequent periods,
An inverted column address strobe signal is generated on line 1330 and applied to each memory. At the same time, local address / data bus 1310 generates a column address on sub-bus 1311. This signal is the local address latch signal 1321
, And is captured by a latch 1322 and added to an address bus 1320. This address bus 1320 is added to each memory to specify a column address in each memory. In the second half of the cycle, the column address strobe signal
When both 1330 and row address strobe signal 1340 become inactive, data is exchanged between graphics processor 1220 and memory. This transfer direction is line 1350
Specified by the inverted write signal that appears above. If a write operation is specified, graphics processor 120 generates a signal on local address / data bus 1310 and applies it to the D input of each memory. If a read operation is specified, each memory is connected to one of the bits of bus 1310 by Q
Generates an output signal at the output, the graphics processor 12
Add to 0.

The utility of the method of generating the row and column address signals shown in FIG. 10 will become apparent from a review of FIG.
FIG. 14 illustrates a typical connection of the graphics processor 120 to a plurality of RAM banks. A local address / data bus 1410 is connected to the data input and output ports of each RAM bank. The local address / data bus of graphics processor 120 drives latches 1412, 1416 and 1418 and receives input from latch 1414.
Guided to 1405.

Latch 1412 is controlled by the inverted data enable signal on line 1401. When graphics processor 120 is performing a write operation, latch 1412 asserts line 1401
The operation is enabled by the above inverted data available signal, and the output data from the local address / data bus 1405 is stored. This data is applied to local address / data bus 1410 and applied to each of the plurality of RAM banks.

Similarly, when latch 1414 is enabled by a signal on line 1402, local address / data bus 14
Receive data on 10 The signal on line 1402 is based on the inverted column address strobe signal on line 1430 or the inverted transfer register signal appearing on line 1470,
Generated from OR gate 1420. The signal on line 1402 allows latch 1414 to store the signal on local address / data bus 1410 during a read operation. In this case, the signal from latch 1414 is applied to local address / data bus port of graphics processor 120 via local address / data bus 1405.

A local address / data bus 1410 is connected to each RAM bank. Bus 1411 connects the bits of bus 1410 to video RAM bank O 1480. Here, the video memory of each bank is connected as described above with reference to FIG. 13, ie, each memory of video RAM bank O 1480 is connected to only one of the bits of bus 1411. Bus 14
12 shows a representative connection of the local address / data bus 1410 to a memory bank in a representative video RAM bank N 1485.

Sub-bus 1404 connects the bit selected as the row / column address bit to latch 1416. Also sub bus 14
06 latches the bit corresponding to the bank select bit 1418
Connect to Table 1 shows specific bits of the local address / data bus corresponding to each range of the number of memory banks in a part of each sub-bus. The two latches are transparent latches similar to the latch 1322 described above, and are controlled by the inverted local address latch signal on line 1403.
That is, these latches hold their outputs during the active period 1241 of the inverted local address latch signal. The output of latch 1416 appears on address bus 1415 and is applied to the address input of each memory in each memory bank.

The column address strobe signal applied to each memory bank is obtained from decoder 1435. Decoder 1435 receives an input from latch 1418 corresponding to the bank select bit. As is apparent from a review of FIGS. 10 and 11, the band select bits are the lower bits of the column address generated during the column address strobe cycle. These bits are captured in a latch 1418 enabled with the inverted local address latch signal on line 1403 and then applied to the decoder 1435. Decoder 1435 is a line
An inverted column address strobe signal on 1430 is also received. Decoder 1435 generates a plurality of outputs 1440, each corresponding to a respective memory bank. For example, output 1441 is a video RA
In addition to the column address strobe input of M bank O 1480. Similarly, a representative connection of the Nth memory bank 1485 is also shown. That is, line 1442 is applied to the column address strobe input of each of the memory banks. The decoder 1435 also generates a column address strobe output signal on one of the outputs 1440 while the column address strobe signal is being received on line 1430. The one line selected depends on the signal received from latch 1418. Eleventh
As will be apparent from a consideration of the figure, it consists of a plurality of bits that can select one of the video RAM banks.

Row address strobe signal on line 1450, line 14
The connections of the write signal on 60 and the transfer register signal on line 1470 are the same as shown in FIG. If the output signal from graphics processor 120 is of insufficient power to drive multiple memory banks, these lines can be buffered for each memory drive. Otherwise, the memory operates in the same manner as described in connection with FIG.

The system shown in FIG. 14 applies a column address strobe signal only to a memory bank selected by a bank selection bit generated simultaneously with a column address. When the memory receives the column address strobe signal, it recognizes the column address appearing on bus 1415 and selects the correct row and column for access. On the other hand, if the column address strobe signal is not received, the memory will not recognize the column address signal and will not access the designated memory location. That is, decoder 1435
Selects only the memory in the selected memory bank,
An interface with the graphics processor 120 is enabled.

The above description relates to the preferred embodiment using 64K DRAM. One skilled in the art will appreciate that the principles of the present invention are applicable to other, differently sized memories. Referring again to FIG. 10, for pins 0 to 11 of the local address / data bus, each bit of the column address output is the same as that of the preceding row address output except that the same bit is separated by 8 bit positions from the address register.
It will be clear that it corresponds to a bit in 100.
For example, for pin 0, the row address output is bit 12 of the address register 900 and the column address output is bit 4, which is 8 bits away. This means that during a row and column address strobe cycle, any contiguous zone of 8 pins of the local address / data bus will have 16 bits from the address register.
Can be output. The row address is the upper bit address and the column address is the lower bit.
The same output scheme can be used for a number of different memory banks because any 8-pin zone provides 16 consecutive bits from address registers 900 and the bank select bit is the least significant bit output. This output method also reduces the amount of circuitry external to the graphics processor 120 required for bank selection. The bit position difference between the row and column addresses output on the same local address / data bus pin is
Related to the size of the memory. In the preferred embodiment described above, a 64K DRAM was used. Since these memories require 8-bit row and column addresses, the required difference in bit positions is eight. When using 256K DRAM,
The difference must be changed. Modern 256K DRAMs require 9-bit row addresses and 9-bit column addresses. If the bit position difference between the row address and the column address appearing on the same local address / data bus pin is changed to 9, the latest technology using 256K DRAM can be used. In this case, an arbitrary 9-pin wide zone in the local address / data bus specifies 18 consecutive bits from address register 900. Similarly, if the bit position difference of the address register 900 between the bit output in the row address strobe cycle and the bit output in the column address strobe cycle is 10, 1M DRAM can be used. That is, any 10-pin-wide zone in the local address / data bus includes 20 consecutive bits of the address register 900.

Although the present invention has been described in terms of a preferred embodiment of a 16-bit word, it will be apparent to those skilled in the art that this is not essential to the practice of the invention. Any desired word length can be used in the present invention as well, provided the necessary parallel data paths exist. That is, the present invention is not limited to 16-bit data words.

The preferred embodiments of the present invention have been described with reference to the drawings. It will be apparent to those skilled in the art that the present invention can be implemented in various modified embodiments not described herein. Accordingly, the scope of the present invention should be limited by the appended claims.

 In connection with the above description, the following items are disclosed.

1. comprising a plurality of memory banks, each memory bank having a plurality of address locations designated by a J-bit row address and a J-bit column address to store an N-bit data word, It has a J-bit multiplexed row / column address input bus, an N-bit data input / output port and a read / write control input; comprising a central processing unit, the central processing unit comprising a memory read operation and a memory write operation. An arithmetic logic unit that performs arithmetic, logical and control operations including: an address register connected to the arithmetic logic unit and storing a unique address having a bit number greater than 2J; and an arithmetic logic unit, an address resist and a bank memory. A memory interface having more than J-bit multiplexed row / column output buses, wherein the multiplexed row / column address of each memory bank is Address input bus is connected to a sequential set of J-bits of the multiplexed row / column address output bus that does not include a predetermined set of bank select bits, and the memory interface is connected to the serial address of the fixed address. Adding a first subset of more than J bits to the multiplexed row / column address output during a row address, wherein the first subset is different from the first subset but more than J consecutive bits of the unique address. Are added to the multiplexed row / column address output during the column address so that the bits of the second subset correspond to the bits of the first subset, respectively, of the multiplexed row / column address output bus. Are different from each other so as to be separated by the J-bit position in the unique address between the row address period and the column address period. Generating a read control signal in response to the operation to receive data from the data input / output port; and further generating a write control signal in response to the write memory operation to generate on the data input / output port; And a bank selection device, which is connected to the predetermined set of bank selection bits of the multiplexed row / column address output bus, and wherein the multiplexed row / column address during the column address. A data processing device, wherein only one of the memory banks in the output bus can respond to the central processing unit in response to the predetermined set of bank selection bits.

2. The data of claim 1 wherein a predetermined set of bank select bits of a multiplexed row / column address output bus of said memory interface includes a predetermined number of least significant bits of said multiplexed row / column address output bus. Processing equipment.

3. The memory interface further has a row address strobe output for generating a row address strobe signal indicating a period of a row address, and a column address strobe output for generating a column address strobe signal indicating a period of a column address; The bank selection device is further connected to a column address strobe output and has a plurality of bank column address strobe outputs corresponding to each of the memory banks, and only one of the bank column address strobe outputs corresponding to the selected bank is provided. Generating a bank column address strobe signal; and said memory bank is connected to a row address strobe output and as an input on a multiplexed row / column address input bus during a row address indicated by the row address strobe signal. Receive line address and respond Connected to the multiplexed row / column address input bus during the period of the column address indicated by the bank column address strobe signal. 2. The data processing device according to claim 1, wherein an address for data transfer is designated only when a signal is received.

4. The data processing apparatus according to claim 3, wherein J is 8, and each of said memory banks includes N 64K element random access memories.

5. The data processing apparatus according to claim 3, wherein J is 9; and each of said memory banks includes N 256K element random access memories.

6. The data processing apparatus according to claim 3, wherein J is 10; and each of said memory backs includes N 1M element random access memories.

7. An address register for storing a unique address having more than 2J bits, and a memory interface connected to the address register and having a multiplexed row / column output bus of more than J bits, wherein the memory interface comprises the unique address. A first subset of more than J consecutive bits of the address is added to the multiplexed row / column address output during a row address, and more than J consecutive bits of the unique address are different from the first subset. A memory interface characterized by adding a second subset overlapping the first subset to the multiplexed row / column address output during a column address.

8. The bits of the second subset are different from the bits of the first subset in that the individual outputs of the multiplexed row / column address output bus have J bits in the unique address between the row address period and the column address period. 8. The memory interface of claim 7, wherein said memory interface differs by a distance.

9. The method according to claim 7, further comprising: a row address strobe output for generating a row address strobe signal indicating a row address period; and a column address strobe output for generating a column address strobe signal indicating a column address period. Memory interface.

10. A multiplexed row / column address output bus that is connected to a predetermined set of bank select bits and a column address strobe output, has a plurality of bank column address strobe outputs, and has a multiplexed row during column address period. 10. A bank selecting device according to claim 9, further comprising a bank selecting device for generating a bank column address strobe signal for only one of the bank column address strobe outputs according to the predetermined set of bank selecting bits of the / column address output bus. Memory interface.

11. The memory interface of claim 10, wherein said predetermined set includes a predetermined number of least significant bits of a multiplexed row / column address output bus.

[Brief description of the drawings]

FIG. 1 shows a block diagram of a computer with graphics capabilities constructed in accordance with the principles of the present invention; FIG. 2 shows a block diagram of a preferred embodiment of the graphics processing circuit of the present invention; FIG. FIG. 4 illustrates a method of specifying individual pixel addresses in a mapped memory based on an XY addressing scheme; FIG. 4 illustrates a method of specifying a field address based on a linear addressing scheme; FIG. FIG. 6 shows a preferred embodiment of storage for pixel data of different lengths within one data word according to the embodiment; FIG. 6 shows the contents of the implicit operand stored in the register memory according to the preferred embodiment of the invention; FIG. 7 shows a characteristic of an array moving operation in the bit map type memory of the present invention; FIG. 9 shows an address register of the graphics processor of the present invention. FIG. 10 shows each pin of the local address / data bus and each address register of the graphics processor of the present invention. FIG. 11 shows the relationship between the bits during the row address strobe cycle and the column address strobe cycle; FIG. 11 shows the relationship between the pins of the local address / data bus of the graphics processor and the row / column address bits and the bank select bits; FIG. 12 is a timing diagram showing various timing functions during operation of the memory; FIG. 13 shows a connection between the graphics processor and one memory bank; and FIG. 14 shows a connection between the graphics processor and a plurality of memory banks. Show typical connections 120 arithmetic logic unit (graphics processor), 1
30; 1370, 1375; 1480, 1485 ... Memory banks, 1312, 13
13; 1411, 1412 ... Row / column address input bus, 1320; 1415
…… Row / column address output bus, 200 …… Central processing unit (C
PU), 250 Memory interface, 900 Address register, 1020, 1030 First and second subset, 1435
... Bank selection device (decoder).

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-59-79481 (JP, A) JP-A-57-13561 (JP, A) JP-A-58-62752 (JP, A) JP-A 60-794 151743 (JP, A)

Claims (1)

(57) [Claims] An address signal comprising a plurality of bits including an address bit and a bank selection bit, and first and second address signals.
A processor circuit for generating an address strobe signal of each of the following types: each memory is composed of rows and columns, has a multi-bit serial output, and is based on address bits of the address signal and the first or second address strobe signal. And a bank selection circuit for selecting a desired bank based on a bank selection bit of the address signal and the first address strobe signal.