JP2586309B2 - Manufacturing method of bipolar semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a bipolar semiconductor device and a method of manufacturing the same, and more particularly, to a bipolar transistor having a fine emitter and a method of manufacturing the same.

[0002]

2. Description of the Related Art In order to improve the performance of applied equipment, the speed of bipolar transistors has been increasingly required in recent years. As means for increasing the speed of the bipolar transistor, means for reducing the width of the emitter and forming a self-aligned base extraction layer together with the shallow junction of the base have been adopted. Thus, in a transistor having a miniaturized emitter, it is common that the emitter is formed to be self-aligned with the base. This is because by making full use of the self-alignment technique, it is possible to realize an emitter having a width smaller than the limit of the photolithography technique.

FIG. 4 is a process sectional view showing a conventional method for manufacturing a bipolar transistor in which a base extraction layer and an emitter are formed by using a self-alignment technique, which is proposed in Japanese Patent Application Laid-Open No. 2-304932. It was done. First, an n-type silicon substrate 101 having an insulating region 102 on its surface is prepared, and a 50 nm-thick first silicon substrate 101 is formed thereon.
A silicon oxide film 103, a 100-nm-thick silicon nitride film 104, a 400-nm-thick first polycrystalline silicon layer 105 containing a p-type impurity, and a 300-nm-thick second silicon oxide film 106 are sequentially stacked. Then, the second silicon oxide film 106 and the first polycrystalline silicon layer 1
05 is selectively removed to form an opening in the region where the emitter is to be formed (FIG. 4A).

Next, the first polycrystalline silicon layer 1 in the opening is
The third silicon oxide film 107 is formed by oxidizing the side surface of the silicon nitride film 105, and then the silicon nitride film 104 at the bottom of the opening is removed by etching with a hot phosphoric acid solution. Part of the bottom surface of 105 is exposed. Next, the first silicon oxide film 10 exposed in the opening is formed.
3 is etched to form a cavity, a second polycrystalline silicon layer 108 having a thickness of about 300 nm is grown on the exposed n-type silicon substrate 101, and a third silicon oxide film 1 is formed.
07, filling the cavity below the first polycrystalline silicon layer 105. Subsequently, the second polysilicon layer 108 other than the cavity is removed by a reactive plasma etching method (FIG. 4).
(B)].

Next, a fourth silicon oxide film 109 having a thickness of about 70 nm is formed by thermal oxidation in a region where silicon is exposed in the opening. Due to this heat treatment, boron in the p ⁺ -type first polysilicon layer 105 diffuses into the second polysilicon layer 108 to turn it into a p-type, and further diffuses into the silicon substrate through the second polysilicon layer 108, thereby forming an external base region. 11
0 is formed. Next, boron is applied at 20 keV and 2 × 10 ¹³
Ion implantation is performed under the condition of cm ⁻² to form an internal base region 111 on the surface of the silicon substrate. Next, the portion of the fourth silicon oxide film 109 formed in the opening on the silicon substrate is removed by anisotropic etching to expose the surface of the silicon substrate [FIG. 4 (c)].

Next, a third polycrystalline silicon layer 112 is formed to be thick, and this is etched back by reactive plasma etching, so that the third polycrystalline silicon layer 1 is formed only in the opening.
The surface of the opening is flattened, leaving 12. Next, 5 arsenic
Ion implantation is performed under the conditions of 0 keV and 1 × 10 ¹⁶ cm ⁻² , and heat treatment is performed to diffuse arsenic doped in the third polycrystalline silicon layer 112 into the internal base region 111 to form the emitter region 113. The final outer base region and inner base region are formed. Next, an aluminum film is formed by a sputtering method and is patterned to form an emitter electrode 114 on the opening [FIG. 4 (d)].

[0007]

In the above-mentioned conventional bipolar transistor, the emitter can be formed in a self-aligned manner, and a narrow width emitter can be realized. However, in the transistor of the conventional structure, the emitter is taken out through the thick polycrystalline silicon layer 112, so that the emitter resistance increases in inverse proportion to the emitter area. The characteristic deterioration becomes remarkable by the increase.
The method of reducing the emitter resistance is to reduce the step at the opening. However, in the prior art, the silicon oxide film 103, 1
06 and the thickness of the silicon nitride film 104,
There was a limit in reducing the opening step. Further, in a transistor having a conventional structure, the emitter opening is buried with polycrystalline silicon. Therefore, when a transistor having a wide emitter width is to be formed, the inside of the emitter opening cannot be buried with polycrystalline silicon. There was an inconvenience. Furthermore, in the above-mentioned conventional example, since the inside of the cavity is filled with polycrystalline silicon, it is difficult in terms of steps, and it is difficult to produce with a high yield.

[0008]

According to the present invention, an insulating region (2) is formed on a surface, and a first conductivity type (n-type) is formed in a region surrounded by the insulating region. Forming a first polycrystalline silicon layer (4) on the insulating region by growing silicon on a semiconductor substrate (1) having a substantially flat surface on which the first semiconductor region is formed; Forming a second semiconductor region of a first conductivity type single crystal on the first semiconductor region; and doping a second conductivity type impurity in the first polycrystalline silicon layer. Converting the first polycrystalline silicon layer to a second conductivity type (p-type); and forming the second polycrystalline silicon layer on the first polycrystalline silicon layer (8) and the second semiconductor region (3). Forming an insulating film (9, 17) having an opening at a central portion of the semiconductor region; The second semiconductor region (3)
A first diffusion layer of a second conductivity type (p type) in a surface region of the second semiconductor region by doping with a conductivity type impurity;
Forming a first conductive type (n-type) in the surface region of the first diffusion layer by doping a first conductivity type impurity into the first diffusion layer through the opening. Forming a second diffusion layer (13).

Further, according to the present invention, (1) an insulating region is formed on a surface, and a first semiconductor region of a first conductivity type is formed in a region surrounded by the insulating region; Forming a first polycrystalline silicon film on the insulating region by growing silicon on the semiconductor substrate formed as described above, and a second semiconductor region of the first conductivity type and single crystal on the first semiconductor region. (2) forming a first silicon oxide film and a silicon nitride film on the first polycrystalline silicon film and on the second semiconductor region;
(3) forming a photoresist film on the silicon nitride film to cover the second semiconductor region; and (4) forming a second conductivity type on the first polysilicon film using the photoresist film as a mask. Doping impurities to make the first polycrystalline silicon film the second conductivity type; (5) selectively removing the silicon nitride film using the photoresist film as a mask; Performing an oxidation process to form a second silicon oxide film on a region not covered with the silicon nitride film; and (7) doping a second conductivity type impurity using the second silicon oxide film as a mask. Forming a first diffusion layer of a second conductivity type in a surface region of the second semiconductor region; and (8) forming a first diffusion layer on a region where the second silicon oxide film is not formed. Etching removal of silicon oxide film (9) forming a second polycrystalline silicon film of the first conductivity type in contact with the first diffusion layer in a region where the first silicon oxide film has been removed; and (10) performing a heat treatment. And diffuses impurities in the second polycrystalline silicon film into the first diffusion layer to form the first polycrystalline silicon film.
Forming a second diffusion layer of the first conductivity type in the surface region of the diffusion layer.

[0010]

Next, embodiments of the present invention will be described with reference to the drawings. Hereinafter, an npn-type transistor will be described as an example. FIG. 1 is formed by an embodiment of the present invention.
FIG. 2 is a cross-sectional view of a bipolar transistor according to the first embodiment. As shown in the figure, a thickness of 0.2 to 1 μm buried under the surface
An n-type collector region 3 is provided on a single-crystal silicon region of an n-type silicon substrate 1 having a substantially flat surface, and a p-type polycrystal serving as a base extraction layer is provided on the insulating region 2. A silicon layer 8 is provided. A p-type base region 11 is formed in the surface region of the n-type collector region, and an n-type emitter region 13 is formed in the surface region of the p-type base region 11.

At the outer peripheral portion of n-type collector region 3, p-type single-crystal silicon region 1 is surrounded by n-type emitter region 13.
0 is formed, and the p-type base region 11 is connected to the p-type polycrystalline silicon layer 8 by this region. Also,
On the p-type polycrystalline silicon layer 8 and the n-type collector region 3, a film having a thickness of 50
A silicon oxide film 9 having a thickness of about 100 nm is formed, and an n-type polycrystalline silicon layer 12 having a thickness of 200 nm is formed on silicon oxide film 9 to be in contact with n-type emitter region 13 through this opening. . The n-type polycrystalline silicon layer 12 is covered with an insulating film 14 and is connected to an emitter electrode 15 via an opening provided in the insulating film 14.

The feature of this structure is that a single-crystal silicon layer (3) serving as an active region of a transistor and a polycrystalline silicon layer 8 serving as a base lead are substantially flat on an n-type silicon substrate 1 having an insulating region 2. The point is that there is almost no step at the connection between the n-type polycrystalline silicon layer 12 and the emitter region 13 formed. Therefore, the n-type polycrystalline silicon layer 12
The emitter resistance caused by the thickness of the film can be reduced.

FIGS. 2A to 2E are process sectional views for explaining a first embodiment of a method of manufacturing a bipolar semiconductor device according to the present invention. First, the n-type silicon substrate 1
The insulating region 2 is formed so that the surface is substantially flat. In this structure, for example, trenches having a depth of 400 nm are provided on both sides of an active region having a width of 600 nm, and a silicon oxide film is grown to a thickness of 400 nm by thermal oxidation. It can be formed by performing backing and removing the projections of the silicon oxide film. Next, by the epitaxial growth method,
A thickness of 300 nm containing about 1 × 10 ¹⁶ cm ^{−3 of} n-type impurities
Is formed. This silicon layer becomes a single-crystal n-type collector region 3 on the region where the silicon substrate is exposed, and becomes an n-type polycrystalline silicon layer 4 on the insulating region 2. Next, the surfaces of the collector region 3 and the polycrystalline silicon layer 4 are oxidized to form a silicon oxide film 5 having a thickness of 30 nm, and a silicon nitride film 6 having a thickness of about 80 nm is grown thereon by the CVD method. 2 (a)].

Next, a photoresist film 7 covering the n-type collector region 3 is formed, and boron is applied to the n-type polycrystalline silicon layer 4 at an energy of, for example, 50 keV and a dose of 1 × 10 4.
Ions are implanted under the condition of ¹⁶ cm ^-2 to form a p-type polycrystalline silicon layer 8. The p-type polycrystalline silicon layer 8 becomes a low-resistance base extraction layer. Here, the photoresist film 7 may be slightly larger or smaller than the size of the single crystal silicon layer (3) [FIG. 2 (b)].

Next, the photoresist film is isotropically etched by exposure to oxygen plasma by about 200 nm, and the exposed silicon nitride film 6 is etched by, for example, a mixed gas of CF ₄ and O ₂ . By isotropically etching the photoresist film, the emitter formed in the subsequent process can be miniaturized, and the distance between the emitter and the base extraction layer is set to prevent the reduction of the emitter-base breakdown voltage of the transistor can do. Here, it is possible not to etch the photoresist film. Alternatively, the silicon nitride film under the photoresist film may be side-etched with a mixed gas of CF ₄ and O ₂ [FIG. 2 (c)].

Next, the photoresist film 7 is removed, and the surfaces of the collector region 3 and the polycrystalline silicon layer 4 are oxidized using the silicon nitride film 6 as a mask to a thickness of 100 to 200 nm.
A silicon oxide film 9 of a degree is formed. At this time, boron in the eight p-type polycrystalline silicon layers diffuses into the single-crystal silicon layer, and a p-type single-crystal silicon region 10 is formed around the single-crystal layer. However, if the size of the above-mentioned photoresist film is slightly smaller than the size of the single-crystal silicon layer, a p-type single-crystal silicon region 10 is formed at the time of ion implantation, and is further diffused in the oxidation step. Next, the silicon nitride film 6 is removed with a hot phosphoric acid solution.
Ion implantation is performed under the condition of × 10 ¹³ cm ⁻² to form the p-type base region 11 (FIG. 2D).

Next, the silicon oxide film 5 on the single crystal silicon layer is removed by wet etching, and a polycrystalline silicon layer is grown to a thickness of about 200 nm.
V, ions are implanted under the conditions of 1 × 10 ¹⁶ cm ⁻² and patterned by a photoresist film to form an n-type polycrystalline silicon layer 12. After that, heat treatment is performed at 1000 ° C. for 20 seconds to diffuse arsenic to the surface of the single crystal silicon layer,
An n-type emitter region 13 is formed. Next, an insulating film 14 is formed, an opening is formed on the n-type polycrystalline silicon layer 12,
An aluminum film is formed by sputtering and patterned to form an emitter electrode 15 [FIG.
(E)].

As is apparent from the above description, in the transistor of this embodiment, the step of the emitter opening is formed by the insulating film 1.
Since the thickness can be formed to be equal to or less than the layer thickness, the distance between the emitter region and the emitter electrode can be formed as thin as the thickness of the n-type polycrystalline silicon layer 12 even when the emitter is miniaturized, and the emitter resistance can be reduced. Further, by performing isotropic etching of the photoresist film or the silicon nitride film, a fine emitter having a resolution equal to or less than the resolution of the photoresist film can be formed, and a certain distance can be provided between the emitter and the base extraction layer. In addition, a reduction in breakdown voltage between the emitter and the base of the transistor can be prevented.

FIGS. 3A to 3E are process sectional views for explaining a second embodiment of the method for manufacturing a bipolar semiconductor device according to the present invention. The process is the same as that of the first embodiment up to the point where the insulating region 2 is formed on the surface of the n-type silicon substrate 1. Next, an n-type collector region 3 and an n-type polycrystalline silicon layer 4 having a thickness of about 300 nm are formed by an epitaxial growth method, and a 30 nm-thick BSG (borosilicate glass) containing about 4 to 6 mol% of boron is formed thereon. 3) A film 16 is formed (FIG. 3A).

Next, the n-type collector region 3 is covered with a photoresist film 7 and boron is ion-implanted at an acceleration energy of 30 keV to about 1 × 10 ¹⁶ cm ⁻² to form a p-type polycrystalline silicon layer 8. . As in the previous embodiment, the photoresist film 7 may be slightly larger or smaller than the size of the single crystal silicon layer (3) [FIG.
(B)]. Next, the surface of the photoresist film is removed by about 200 nm by isotropic etching, and a silicon oxide film 17 is formed on the BSG film 16 by a liquid phase growth method using the photoresist film as a mask. The thickness of the silicon oxide film 17 is suitably about 50 to 200 nm [FIG.
(C)].

Next, the photoresist film 7 is removed, and boron is diffused from the BSG film 16 to the surface of the n-type collector region 3 by, for example, heat treatment at 1000 ° C. for 30 seconds to form the p-type base region 11. At this time, boron is also diffused to the surface of p-type polycrystalline silicon layer 8. At this time, boron in the p-type polycrystalline silicon layer 8 also diffuses, and a p-type single-crystal silicon region 10 is formed around the single-crystal layer. However, if the size of the above-mentioned photoresist film is slightly smaller than the size of the single-crystal silicon layer, a p-type single-crystal silicon region 10 is formed at the time of boron ion implantation, and is further diffused by heat treatment [FIG. d)].

Next, the exposed BSG film is removed by a wet or dry etching method.
After growing a 0 nm polycrystalline silicon layer, arsenic is grown to 50 nm.
Ion implantation is performed under the conditions of keV and 1 × 10 ¹⁶ cm ⁻² , and patterning is performed with a photoresist film to form an n-type polycrystalline silicon layer 12. After that, arsenic is diffused to the surface of the single crystal silicon layer by a heat treatment at 1000 ° C. for 20 seconds,
An n-type emitter region 13 is formed. Next, an insulating film 14 is formed, an opening is formed on the n-type polycrystalline silicon layer 12,
Aluminum is deposited by sputtering and patterned to form an emitter electrode 15 [FIG.
(E)].

According to this embodiment, the same effects as those of the first embodiment can be obtained, and further, the following effects can be obtained. Since thermal oxidation is not performed after the formation of the p-type polycrystalline silicon layer 8, impurities in the p-type polycrystalline silicon layer 8 may be absorbed by the growing thermal oxide film [9 in FIG. 2 (d)]. Therefore, it is possible to draw out the base with low resistance. For the same reason, the impurity in the p-type polycrystalline silicon layer 8 does not largely diffuse into the n-type single-crystal silicon layer (3), so that the transistor can be formed with high accuracy, and the size can be further reduced. Can contribute to.

The preferred embodiment has been described above.
The present invention is not limited to these embodiments, and various changes can be made within the gist of the present invention described in the claims. For example, in the embodiment, the epitaxial growth method was used to form the n-type single-crystal silicon layer serving as the collector region. However, instead of this method, an amorphous silicon layer was formed and then the single-crystal silicon layer was partially formed. You may make it. Also, during the epitaxial growth for forming the collector region, the doping impurity is changed to boron,
The base region may be formed by an epitaxial method. Further, as the substrate, a p-type silicon substrate having an n ⁺ -type buried layer and an n-type epitaxial layer formed on the surface can be used instead of the embodiment. Also,
In the embodiment, a single transistor has been described.
The present invention is applicable not only to a single device but also to a bipolar integrated circuit or a Bi-type integrated circuit.
The present invention can be applied to a semiconductor integrated circuit such as a CMOS integrated circuit and the like, and can also be applied to a pnp transistor in which all conductivity types are reversed.

[0025]

As described above, in the method of manufacturing a bipolar semiconductor device according to the present invention, an n-type single-crystal silicon layer serving as a transistor formation region and a polycrystalline silicon layer serving as a base extraction layer are formed of the same silicon layer. According to the present invention, the step at the emitter opening can be significantly reduced. Therefore, according to the present invention, it is possible to reduce the thickness of the polycrystalline silicon layer for extracting the emitter, and it is possible to extract the emitter with a low resistance even to a miniaturized emitter.
Further, since the polycrystalline silicon for extracting the emitter is not formed by burying the opening, it is possible to avoid a situation in which the transistor cannot be formed because the opening cannot be buried. Therefore, according to the present invention, it is possible to stably form all the transistors even in a semiconductor integrated circuit in which large-sized transistors are mixedly present.

Further, according to the present invention, since the entire region of the transistor can be formed by only one photoresist process, there is no need to provide a margin for misalignment, which contributes to miniaturization of the device. be able to. In the conventional example in which the emitter is formed by the self-alignment method, a step that requires strict process control of filling the cavity with polycrystalline silicon is required. However, such a step is not used in the present invention. However, since the manufacturing method is a combination of relatively easy steps, manufacturing with a high yield is possible.

Further, by etching away the surface of the photoresist film by a predetermined thickness or by side-etching the silicon nitride film by a predetermined amount, an emitter having a width smaller than the resolution limit of the photoresist can be formed. it can. Further, since a certain distance can be provided between the emitter and the base extraction layer, a required emitter-base breakdown voltage can be ensured even in a miniaturized transistor.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a bipolar semiconductor device formed according to an embodiment of the present invention.

FIG. 2 is a process sectional view for explaining the first embodiment of the method of manufacturing the bipolar semiconductor device according to the present invention.

FIG. 3 is a process sectional view for describing a second embodiment of the method of manufacturing the bipolar semiconductor device according to the present invention.

FIG. 4 is a process cross-sectional view for explaining a conventional manufacturing method.

[Explanation of symbols]

 Reference Signs List 1 n-type silicon substrate 2 insulating region 3 n-type collector region 4 n-type polycrystalline silicon layer 5 silicon oxide film 6 silicon nitride film 7 photoresist film 8 p-type polycrystalline silicon layer 9 silicon oxide film 10 p-type single crystal silicon region Reference Signs List 11 p-type base region 12 n-type polycrystalline silicon layer 13 n-type emitter region 14 insulating film 15 emitter electrode 16 BSG film 17 silicon oxide film 101 n-type silicon substrate 102 insulating region 103 first silicon oxide film 104 silicon nitride film 105 First polycrystalline silicon layer 106 Second silicon oxide film 107 Third silicon oxide film 108 Second polycrystalline silicon layer 109 Fourth silicon oxide film 110 External base region 111 Internal base region 112 Third polycrystalline Silicon layer 113 Emitter region 114 Emitter electrode

Claims (7)

(57) [Claims] 1. A semiconductor substrate having a substantially flat surface and a first semiconductor region of a first conductivity type formed in a region surrounded by the insulating region and a region surrounded by the insulating region. Is grown to form a first polycrystalline silicon film on the insulating region and a first polycrystalline silicon film is formed on the first semiconductor region.
Forming a second semiconductor region of a conductivity type single crystal; and doping the first polysilicon film with a second conductivity type impurity to convert the first polysilicon film to a second conductivity type. Forming an insulating film having an opening at a central portion of the second semiconductor region covering the first polycrystalline silicon film and the second semiconductor region; and forming an insulating film on the second semiconductor region. Forming a first diffusion layer of a second conductivity type in a surface region of the second semiconductor region by doping an impurity of a second conductivity type; and forming the first diffusion layer in the first diffusion layer through the opening. A first conductivity type impurity is doped into the surface region of the first diffusion layer to form the first diffusion layer.
Forming a conductive type second diffusion layer; and a method for manufacturing a bipolar semiconductor device. 2. A semiconductor substrate having a substantially flat surface and an insulating region formed on the surface and a first semiconductor region of the first conductivity type formed in a region surrounded by the insulating region. Is grown to form a first polycrystalline silicon film on the insulating region and a first polycrystalline silicon film is formed on the first semiconductor region.
Forming a second semiconductor region of a conductivity type single crystal; and forming a first silicon oxide film and a silicon nitride film on the first polycrystalline silicon film and on the second semiconductor region. Forming a photoresist film on the silicon nitride film to cover the second semiconductor region; doping the first polysilicon film with a second conductivity type impurity using the photoresist film as a mask; Converting the first polycrystalline silicon film to the second conductivity type by using the photoresist film as a mask, and selectively removing the silicon nitride film. Forming a second silicon oxide film on the uncovered region; and doping impurities of a second conductivity type using the second silicon oxide film as a mask to form a surface region of the second semiconductor region. Forming a first diffusion layer of a second conductivity type on the first silicon oxide film; etching a first silicon oxide film on a region where the second silicon oxide film is not formed; Forming a second polycrystalline silicon film of the first conductivity type in contact with the first diffusion layer in a region where the film has been removed; and performing a heat treatment to remove impurities in the second polycrystalline silicon film. Forming a second diffusion layer of the first conductivity type in the surface region of the first diffusion layer by diffusing the first diffusion layer into the first diffusion layer. 3. After the first polysilicon film is doped with a second conductivity type impurity using the photoresist film as a mask, before the silicon nitride film is selectively removed using the photoresist film as a mask. 3. The method of manufacturing a bipolar semiconductor device according to claim 2, wherein a surface of said photoresist film is removed by a predetermined thickness. 4. The bipolar semiconductor device according to claim 2, wherein the silicon nitride film is side-etched by a predetermined amount when the silicon nitride film is selectively removed using the photoresist film as a mask. Production method. 5. A semiconductor substrate having a substantially flat surface and an insulating region formed on the surface and a first semiconductor region of the first conductivity type formed in a region surrounded by the insulating region. Is grown to form a first polycrystalline silicon film on the insulating region and a first polycrystalline silicon film is formed on the first semiconductor region.
Forming a second semiconductor region of a conductivity type single crystal; forming a first silicon oxide film on the first polycrystalline silicon film and on the second semiconductor region; Forming a photoresist film on the silicon oxide film to cover the second semiconductor region; and doping the first polysilicon film with a second conductivity type impurity using the photoresist film as a mask. Converting the first polycrystalline silicon film to the second conductivity type, growing silicon oxide using the photoresist film as a mask to form a second silicon oxide film, and forming a second silicon oxide film in the second semiconductor region. A second conductivity type first is doped in a surface region of the second semiconductor region by doping with a second conductivity type impurity.
Forming a diffusion layer of the following; etching a first silicon oxide film on a region where the second silicon oxide film is not formed; and removing the first silicon oxide film in a region where the first silicon oxide film is removed. Forming a second polycrystalline silicon film of the first conductivity type in contact with the first diffusion layer; and performing heat treatment to diffuse impurities in the second polycrystalline silicon film into the first diffusion layer. Forming a second diffusion layer of the first conductivity type in the surface region of the first diffusion layer. 6. The method according to claim 1, wherein the first polycrystalline silicon film is doped with a second conductivity type impurity using the photoresist film as a mask, and before the silicon oxide is grown using the photoresist film as a mask. 6. The method for manufacturing a bipolar semiconductor device according to claim 5, wherein the surface of the semiconductor device is removed by a predetermined thickness. 7. The method according to claim 1, wherein the first silicon oxide film contains a second conductivity type impurity, and the formation of the first diffusion layer comprises:
6. The method for manufacturing a bipolar semiconductor device according to claim 5, wherein the heat treatment is performed by diffusing impurities of the first silicon oxide film into the second semiconductor region.