JP2580311B2 - Mutual monitoring processing method of multiplex system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a mutual monitoring processing method of a multiplexing system for mutually monitoring the normality of each processor of a multiprocessor. In a multiplex system in which a plurality of processors (1) are combined, at least two common memories (2) provided so as to be connected to the plurality of processors (1) are provided. And an interrupt for sending an interrupt signal with an identification number to each of the plurality of processors (1) at predetermined time intervals to the other processors (1) via the plurality of common memories (2). An abnormality monitor that receives an interrupt signal with the identification number from the other processor (1) via a generating unit (3) and each of the plurality of common memories (2); A monitoring unit (4), wherein the abnormality monitoring unit (4) cannot receive the interrupt signal with the identification number from the same processor (1) from each of the plurality of common memories (2). In the first receiving mode, it is determined that an abnormality has occurred in the processor (1) corresponding to the identification number, and the interrupt signal with the identification number from each of the plurality of processors (1) is transmitted to the plurality of common memories. At the time of the second reception mode in which all of the interrupt signals cannot be received via any one of (2), it is determined that an abnormality has occurred in the common memory (2) that has not been able to be received, and all interrupt signals with identification numbers have In the case where any one of them is not received and the receiving mode is other than both the first receiving mode and the second receiving mode, the respective processors and the respective common memos are used. It is characterized in that it is determined that an abnormality has occurred in the connection line to the connection.

[Industrial applications]

The present invention relates to a mutual monitoring processing method of a multiplex system,
More specifically, the present invention relates to a mutual monitoring processing method of a multiplexing system for mutually monitoring the normality of each processor of a multiprocessor.

In order to realize a highly reliable system, a plurality of processors are combined to form a multiprocessor system, that is, a multiplex system. In this case, it is necessary to monitor whether each of the multiplexed processors is operating normally (normality).

[Conventional technology]

FIG. 8 is an explanatory diagram of a conventional technique, and shows a conventional mutual monitoring method.

In FIG. 8, 1 or CPU0 and CPU1 are processors or central processing units (CPUs), 6 is a mutual monitoring dedicated device, and 7 is communication means between CPUs.

A mutual monitoring dedicated device 6 is provided separately from the processors CPU0 and CPU1 for monitoring the processors CPU0 and CPU1. The processors CPU0 and CPU1 periodically generate an interrupt or transmit / receive a message to / from each other via the mutual monitoring dedicated device 6. If this interrupt is not generated or the message transmission / reception is not performed at a predetermined time, each of the processors CPU0 and CPU1 determines that an abnormality has occurred in the other, and performs a predetermined abnormality detection process.

[Problems to be solved by the invention]

According to the prior art described above, each processor CPU0 and CPU1
However, if an error occurs in the mutual monitoring device 6 even if the status is normal, there is a problem that it is erroneously recognized that an error has occurred in the processor CPU0 or CPU1.

In order to prevent this, between the processors CPU0 and CPU1, in addition to the mutual monitoring device 6 and the normal bus, a separate inter-CPU communication means 7 must be provided to identify the abnormal point. However, there is a problem that the system becomes complicated and multiplexing is restricted.

SUMMARY OF THE INVENTION An object of the present invention is to provide a mutual monitoring processing method for a multiplexing system in which the normality of a processor is accurately monitored and restrictions on multiplexing are eliminated.

[Means for solving the problem]

FIG. 1 is a block diagram showing the principle of the present invention, and shows a multiplexing system according to the present invention.

In FIG. 1, 1 or CPU0 to CPU13 are processors or central processing units (CPU), 2 or M0 and M1 are common memories,
3 is an interrupt generation unit, 4 is an abnormality monitoring unit, 20 is a storage unit, and 21 or EF0
Or EF3 is an error flag.

The plurality of processors CPU0 to CPU3 are combined to form a multiprocessor system, that is, a multiplex system. One or more common memories M0 and M1 are provided as memories common to the processors CPU0 to CPU3. The common memories M0 and M1 are connected to the processor via each of them.
CPU0 to CPU3 are provided so as to be connected to each other.

Each of the processors CPU0 to CPU3 is provided with an interrupt generation unit 3 and an abnormality monitoring unit 4.

The interrupt generation unit 3 forms an interrupt signal with an identification number at a predetermined time interval and sends it to each of the processors CPU0 to CPU3 via the common memory M0 or M1 at the interval.
At this time, the interrupt signal is sent to at least another processor 1 (a processor 1 other than the processor 1 to which the interrupt generating unit 3 belongs) so that the processors 1 mutually monitor. The identification number is uniquely determined depending on which of the processor 1 sends the interrupt signal, the processor 1 that receives the interrupt signal, and the common memory 2 that passes through the processor. Assuming that the numbers of the processors 1 and the common memory 2 are n and m, respectively, n × m identification numbers are required. In FIG. 1, n = 4 and m = 2, and eight interrupt signals with identification numbers It is represented by For example, the interrupt generation unit 3 of the processor CPU0 is connected via the common memory M0. Via common memory M1 It is sent to each processor CPU0 or CPU3. That is, m = 2 interrupt signals are transmitted.

The abnormality monitoring unit 4 is an interrupt signal with an identification number transmitted from the interrupt generation unit 3 of the processors CPU0 to CPU3 via the common memories M0 and M1. Receive. At this time, in order for the processors 1 to monitor each other, the interrupt signal is received from at least another processor 1 (processor 1 other than the processor 1 to which the abnormality monitoring unit 4 belongs). Then, the abnormality monitoring unit 4 outputs a signal The presence or absence of an error is used to determine whether an abnormality has occurred.

In the common memory M0, the signal The data is written into a predetermined storage unit 20 corresponding to each of them, read out immediately and sent to the processors CPU0 to CPU3. Therefore, it can be said that the common memory M0 has a function of generating an interrupt with an identification number for the processors CPU0 to CPU3 sharing the same. The same applies to the common memory M1.

The error flags EF0 to EF3 are for recording the result of the abnormality monitoring unit 4 determining that an abnormality has occurred.
It is provided corresponding to each of U0 to CPU3.

Processors CPU0 to CPU3 and common memories M0 and M1 are
Each has the same configuration.

(Operation)

FIG. 2 is a diagram for explaining the operation of the present invention, and shows how an interrupt signal with an identification number is transmitted and received.

For example, when focusing on the processor CPU2, the interrupt generation unit 3 sends the signals via the common memories M0 and M1, respectively. Send to processor CPU0 or CPU3. On the other hand, the abnormality monitoring unit 4 of the processor CPU2 sends a signal via the common memory M0. Signal via common memory M1 To receive.

Now, for example, a signal Are not received (there is no interruption of identification numbers “0” and “4”), the abnormality monitoring unit 4 determines that an abnormality has occurred in the processor CPU0 corresponding to the identification number. The identification number “0” is the processor CPU0 or the common memory M0
And the identification number "4" corresponds to the processor CPU0 or the common memory M1, so that the processor CPU0 is uniquely obtained. After that, the abnormality monitoring unit 4 starts
Error flag EF in common memory M0 and M1 corresponding to U2)
In step 2, the error bit indicating the abnormality of the processor CPU0 is set to "1" (recorded).

Similarly, for example, the signal Are not received, the abnormality monitoring unit 4 determines that an abnormality has occurred in the common memory M1 corresponding to the identification number. And the correct error flag EF2 of the common memory M0
, The error bit indicating the abnormality of the common memory M1 is set to “1”.

The signal Either of the signal Is not received, but it cannot be determined that an abnormality has occurred in the processor CPU0 or the common memory M0, it can be determined that an abnormality has occurred in the connection line (cable or the like). Furthermore,
In this case, the signals are also sent to the other processors CPU1 and CPU3. If the signal cannot be received, the connection between the processor CPU0 and the common memory M0 is abnormal. Can not be received, it can be known that the connection line between the common memory M0 and the processor CPU2 is abnormal. This is recorded in the error flag EF2.

In the other processors CPU0, CPU1 and CPU3, the presence / absence of an abnormality is also detected, and the result is output to the common memory M0.
And / or recorded in error flags EF0, EF1 and EF3 in M1.

〔Example〕

FIG. 3 is a block diagram of the embodiment.
2 shows the configuration of CPU0.

In FIG. 3, 30 to 33 are CPU0 to CPU3 interrupt units, 40 is a CPU abnormality detection processing unit, 41 is a common memory abnormality detection processing unit, and 5 is a system state monitoring unit.

Hereinafter, the processing performed by each unit will be described with reference to FIGS. 4 to 7.

FIG. 4 shows an interrupt generation processing flow.
0 shows the processing to be performed.

 It waits for a predetermined time to elapse.

After a lapse of a predetermined time, an interrupt of identification number 0 is generated for the processor CPU0 via the common memory M0. Next, an interrupt of identification number 4 is generated for the processor CPU0 via the common memory M1. Thereafter, the process returns.

As described above, the CPU0 interrupt unit 30 sends a signal to the processor CPU0 at predetermined time intervals. Is sent.

Similarly, CPU1 to CPU3 interrupt units 31 to 33 send signals to processors CPU1 to CPU3 at predetermined time intervals, respectively. Is sent. Therefore, in this example, the signal There are four each.

In the other processors CPU1 to CPU3, CPU0 to CPU3 interrupt units 31 to 33 are provided, and transmit predetermined signals.

FIG. 5 is a flowchart of the abnormality monitoring process, in which the abnormality monitoring unit 4
Shows the processing to be performed.

signal Is transmitted at predetermined time intervals, Is waited for a predetermined time to elapse.

After a predetermined time, a signal , That is, whether all interrupts with identification numbers 0 to 7 have occurred.

If all the interrupts have occurred, it is determined that it is normal, and the process returns.

If there is an interrupt that has not occurred, it is determined that an error has occurred, and the processor 1
Is determined for abnormalities.

If the interrupts of the identification numbers 0 and 4 have not occurred, it is determined that an abnormality has occurred in the processor CPU0, and the abnormality detection processing for this is performed by the CPL abnormality detection processing unit 40 (described later). Still other processors CPU1 to CPU3
For, the presence or absence of an abnormality is similarly checked, and if there is an abnormality, an abnormality detection process is performed.

After determining the abnormality of the processor 1, the abnormality of the common memory 2 is determined.

If all of the interrupts with identification numbers 0 to 3 have not occurred, it is determined that an abnormality has occurred in the common memory M0, and an abnormality detection process for this is performed by the common memory abnormality detection processing unit 41 (described later). The same processing is performed for the common memory M1.

In cases other than the above, it is determined that the connection line connecting the processor 1 and the common memory 2 is abnormal, the abnormal part is specified as described above, and the abnormality monitoring unit 4 performs abnormality detection processing.

 Thereafter, the process returns.

As described above, in the processors CPU0 to CPU3, abnormality monitoring of each element of the system is performed.

FIG. 6 is a flowchart of the CPU abnormality detection processing, showing the processing performed by the CPU abnormality detection processing unit 40 of one processor CPUm (m is any one of 0 to 3).

Processor detected according to the result of error monitoring processing
CPUn (n is any of 0 to 3 other than m)
It is recorded in the corresponding error flag EFm of the common memories M0 and M1.

The other processors other than the processor CPUn check whether or not the processor CPUn is abnormal by referring to the error flag EF corresponding to the other processor.

If another processor also records an abnormality in the processor CPUn, it is determined that an abnormality has actually occurred in the processor CPUn.

If another processor has not recorded an abnormality in the processor CPUn, it is determined that an abnormality has occurred in the interrupt section of the processor CPUn that generates an interrupt with an identification number for the processor CPUm.

FIG. 7 is a flowchart of the common memory abnormality detection processing flow, showing the processing performed by the common memory abnormality detection processing unit 41 of one processor CPU _α (α is any of 0 to 3). Β represents any of 0 to 3 other than α.

Common memory detected according to the result of the error monitoring process
Mn abnormality of (n is 0 or 1), and records the error flag EF _alpha corresponding common memory other than the common memory Mn.

The other processors also check whether the abnormality of the common memory Mn is recorded by referring to the error flag EF corresponding to the other processor.

If another processor records an abnormality in the common memory Mn, it is determined that an abnormality has actually occurred in the common memory Mn.

If another processor has not recorded an abnormality in the common memory Mn, it is determined that an abnormality has occurred in the interrupt section of the processor that generates an interrupt with an identification number for the processor CPU _α .

The results of the abnormality detection processing are all stored in the common memory M0 and / or
Recorded in M1. The system status monitoring unit 5 of each of the processors CPU0 to CPU3 refers to the result at a predetermined cycle, and
Monitor system status.

〔The invention's effect〕

As described above, according to the present invention, in the mutual monitoring processing of the multiplexing system, an interrupt signal with an identification number is transmitted to at least another processor via the common memory at a predetermined time interval, whereby an abnormality is detected. The occurrence can be known accurately and its location can be specified correctly. In addition, since the system does not become particularly complicated, the number of processors and the number of common memories (multiplexing number) can be eliminated, and the number of multiplexing can be reduced. And an extremely reliable system can be constructed.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention, FIG. 2 is a diagram illustrating the operation of the present invention, FIG. 3 is a diagram illustrating the configuration of the embodiment, FIG. 4 is an interrupt generation processing flow, FIG. FIG. 6 is a flowchart of a CPU abnormality detection process, FIG. 7 is a flowchart of a common memory abnormality detection process, and FIG. 1 or CPU0 to CPU3 is a processor or central processing unit (CPU), 2 or M0 and M1 is a common memory, 3 is an interrupt generator,
4 is an abnormality monitoring unit, 20 is a storage unit, 21 or EF0 to EF3 are error flags.

Claims (1)

(57) [Claims] 1. A multiplexing system comprising a plurality of processors (1), comprising at least two common memories (2) provided to be connected to the plurality of processors (1), respectively. An interrupt generation unit that sends an interrupt signal with an identification number to each of the plurality of processors (1) at predetermined time intervals to another processor (1) via each of the plurality of common memories (2); (3) the plurality of common memories (2)
And an abnormality monitoring unit (4) for receiving the interrupt signal with the identification number from the other processor (1) via each of the above-mentioned processors, wherein the abnormality monitoring unit (4) is provided from the same processor (1). It is determined that an abnormality has occurred in the processor (1) corresponding to the identification number in the first reception mode in which the interrupt signal with the identification number cannot be received from each of the plurality of common memories (2). And the interruption signal with the identification number from each of the plurality of processors (1) cannot be received in the second reception mode in which all of the interruption signals with the identification number cannot be received via any one of the plurality of common memories (2). It is determined that an abnormality has occurred in the common memory (2), and at least one of the interrupt signals with identification numbers has not been received. When the receiving mode is other than the second receiving mode, it is determined that an abnormality has occurred in a connection line between each of the processors and each of the common memories. Mutual monitoring processing method of the system.