JP2545815B2 - How to identify good / defective semiconductor integrated circuits - Google Patents
How to identify good / defective semiconductor integrated circuitsInfo
- Publication number
- JP2545815B2 JP2545815B2 JP61300775A JP30077586A JP2545815B2 JP 2545815 B2 JP2545815 B2 JP 2545815B2 JP 61300775 A JP61300775 A JP 61300775A JP 30077586 A JP30077586 A JP 30077586A JP 2545815 B2 JP2545815 B2 JP 2545815B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- pad
- semiconductor integrated
- chip
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路の良品・不良品判別方法に関
し、特に半導体集積回路の電源パッド、特に電源パッド
が改良されたＣ−MOS半導体集積回路を用いた良品・不
良品判別方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for determining whether a semiconductor integrated circuit is a good product or a defective product, and more particularly to a power supply pad of the semiconductor integrated circuit, particularly a C-MOS semiconductor integrated circuit having an improved power supply pad. The present invention relates to a non-defective / defective product discriminating method.
LSIが良品か不良品かを判別する工程は大きく２種類
に分けられ、拡散工程完了直後の判別（以後ウェハーチ
ェックと記す）と、ウェハーを一つ一つのチップに分離
し組み立て完了後の判別（以後選別と記す）とがある。
一般に、チップ設計において電源パッドの設置は、組み
立て後、容器の電源端子につながる数だけしか行われ
ず、ウェハーチェックと選別で使用される電源パッドの
数は同じであった。The process of determining whether the LSI is a good product or a defective product is roughly divided into two types, a determination immediately after the completion of the diffusion process (hereinafter referred to as a wafer check) and a determination after the completion of assembly by separating the wafer into individual chips ( Hereinafter referred to as selection).
Generally, in the chip design, only the number of power supply pads installed after assembly is connected to the power supply terminals of the container, and the number of power supply pads used for wafer check and screening is the same.
第４図は従来のウェハーチェックにおける、チップと
チップに電源を供給する様子を示す概略図であり、１は
チップ、２はチップ内のGNDライン、３はチップ内のVDD
ラインを示している。５と６はウェハーチェックにおい
てチップに低レベル（例えばON）、高レベル（例えば5
V）を供給するための電源である。７は信号パッド、８
はGNDパッド、９はVDDパッド、10は空パッドを示してい
る。ウェハーチェック時と選別時での測定条件の違い
は、選別時には電源５及び６とGNDライン２及びVDDライ
ン３に直列に形成される寄生インパーダンス４がほとん
ど無視できるが、ウェハーチェック時には、チップ１に
電源を供給するためにパッドに接触する探針との間に接
触抵抗が現れるため無視できなくなる事である。FIG. 4 is a schematic diagram showing how chips and chips are supplied with power in a conventional wafer check. 1 is a chip, 2 is a GND line in the chip, and 3 is VDD in the chip.
Shows the line. 5 and 6 are low level (for example, ON) and high level (for example, 5) chips on the wafer check.
V) is the power supply for supplying. 7 is a signal pad, 8
Is a GND pad, 9 is a VDD pad, and 10 is an empty pad. The difference between the measurement conditions at the time of wafer check and that at the time of sorting is that the parasitic impedance 4 formed in series with the power supplies 5 and 6 and the GND line 2 and VDD line 3 can be almost ignored at the time of sorting. This is because contact resistance appears between the probe and the probe that comes into contact with the pad to supply power to No. 1 and cannot be ignored.
上述した半導体集積回路は、出力バッファが高レベル
から低レベルに変化した時、チップ１内のGNDライン２
から電源２に寄生インピーダンス４を通して電流I1が流
れ、その間GNDライン４にはノイズＮが発生する。例え
ば、ウェハーチェックにおけるインピーダンス４の値を
Ｚ（Ω）、電流I1の電流値をi1（Ａ）とすると、GNDラ
イン４に発生するノイズＮはi1・Ｚ（ｖ）で表すことが
できる（第５図）。The semiconductor integrated circuit described above has the GND line 2 in the chip 1 when the output buffer changes from the high level to the low level.
A current I 1 flows from the power source 2 to the power source 2 through the parasitic impedance 4, while noise N is generated in the GND line 4. For example, if the value of the impedance 4 in the wafer check is Z (Ω) and the current value of the current I 1 is i 1 (A), the noise N generated in the GND line 4 can be represented by i 1 · Z (v). Yes (Fig. 5).
特に高駆動能力の出力バッファを有する半導体集積回
路の場合、電流・I1は大きくなり必然的にノイズ・Ｎも
大きくなる。VDD＝５（Ｖ）、GND＝０（Ｖ）、インピー
ダンスＺ＝５（Ω）電流i1＝200（mA）の条件下で、入
力レベルが2.5（Ｖ）（インピーダンスＺ＝０（Ω）
時）の入力レベルを測定すると、GNDライン２がi1・Ｚ
＝１（Ｖ）になっているので、この条件では入力レベル
は3.5（Ｖ）という結果が出てしまう。In particular, in the case of a semiconductor integrated circuit having an output buffer having a high driving capability, the current I 1 becomes large and the noise N becomes large as a result. Input level is 2.5 (V) (impedance Z = 0 (Ω)) under the conditions of VDD = 5 (V), GND = 0 (V), impedance Z = 5 (Ω) current i 1 = 200 (mA)
When the input level is measured, the GND line 2 shows i 1 · Z
Since it is = 1 (V), the input level is 3.5 (V) under this condition.
接触抵抗値が大きい程インピーダンス・Ｚを大きくす
る傾向にあり、従って接触抵抗の発生は入力レベルの測
定を正しく行えなくし、本来良品であるべきチップが不
良と判定されてしまい、ウェハーチェック時の歩留りの
低下をもたらす。The larger the contact resistance value is, the larger the impedance Z tends to be. Therefore, the generation of contact resistance makes it impossible to measure the input level correctly, and the chip that should be a good product is judged to be defective, and the yield at the time of wafer check Bring about a decline.
本発明の目的は、ウェハーチェックにおいてパッドと
探針間に形成される接触抵抗を小さくし、正しくウェハ
ーチェックが行える半導体集積回路の良品・不良品判別
方法を提供する事である。An object of the present invention is to provide a method of discriminating a non-defective product / defective product of a semiconductor integrated circuit which can reduce a contact resistance formed between a pad and a probe in a wafer check and can correctly perform a wafer check.
本発明の半導体集積回路の良品・不良品判別方法は、
半導体基板上に、容器の電源端子に接続される電源パッ
ドに加え上記電源端子に接続されない電源パッドを増設
し、これら容器に電源端子に接続される上記電源パッド
及び増設した上記電源パッドに共通に電源を供給しなが
ら良品・不良品の判別を行うことを特徴としている。The method for discriminating the good / defective product of the semiconductor integrated circuit of the present invention is
On the semiconductor substrate, in addition to the power supply pad connected to the power supply terminal of the container, a power supply pad not connected to the power supply terminal is added, and the power supply pad connected to the power supply terminal and the added power supply pad are commonly connected to these containers. The feature is that it determines whether the product is good or bad while supplying power.
次に、本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.
第１図は本発明の第１の実施例を示す半導体集積回路
のウェハーチェックにおける、チップとチップに電源を
供給する様子を示す概略図である。11は増設したGNDパ
ッド、12は増設したVDDパッドであり、両者共にウェハ
ーチェック専用電源パッドである。尚、第４図と同じ機
能を示す部分は同じ番号を付して説明を省略する。増設
した電源パッド11,12は空パッドを利用している。FIG. 1 is a schematic diagram showing a chip and a state of supplying power to the chip in a wafer check of a semiconductor integrated circuit showing a first embodiment of the present invention. Reference numeral 11 is an expanded GND pad, and 12 is an expanded VDD pad, both of which are dedicated power pads for wafer check. Incidentally, the parts having the same functions as those in FIG. The additional power supply pads 11 and 12 use empty pads.
ここでGNDライン２から一つのGNDパッド８又は11を経
由して電源間に形成されるインピーダンス・４の値をＺ
（Ω）出力バッファ動作時にGNDライン２から電源５に
流れる全電流値をi1（Ａ）とすると従来のGNDパッド８
の他に増設したGNDパッド11が２ケ存在するのでGNDライ
ン２に発生するノイズ・Ｎ′はi1・Z/3（Ｖ）で表す事
ができる（第３図）。Here, let Z be the value of the impedance 4 formed between the GND line 2 and the power supply via one GND pad 8 or 11.
(Ω) If the total current value flowing from GND line 2 to power supply 5 during output buffer operation is i 1 (A), conventional GND pad 8
In addition to this, there are two additional GND pads 11, so the noise N'generated on the GND line 2 can be expressed by i 1 · Z / 3 (V) (Fig. 3).
第２図は本発明の２の実施例を示す、増設する電源パ
ッド周辺の概略図である。13は増設した電源パッド、14
は高駆動能力の出力バッファ、15は駆動能力の小さい出
力バッファ（あるいは入力バッファ）、16はチップ内の
最外殻の電源ライン、７は14,15に接続される信号パッ
ドである。FIG. 2 is a schematic view of the periphery of a power pad to be added, showing a second embodiment of the present invention. 13 is an additional power pad, 14
Is an output buffer having a high driving capability, 15 is an output buffer (or an input buffer) having a small driving capability, 16 is an outermost power source line in the chip, and 7 is a signal pad connected to 14, 15.
高駆動能力の出力バッファ14は、駆動能力の小さい出
力バッファや入力バッファに比べて比較的大きな面積を
必要とする。従って隣接する信号パッドとの距離も大き
くなりバッファ15のパッドの隣接する信号パッドとの間
に形成される空領域に電源パッドを増設する事ができ
る。増設した電源パッド13はチップ内の最外殻電源ライ
ン16に接続する事ができる。The high drive capacity output buffer 14 requires a relatively large area as compared with an output buffer and an input buffer having a low drive capacity. Therefore, the distance from the adjacent signal pad becomes large, and the power supply pad can be added to the empty area formed between the pad of the buffer 15 and the adjacent signal pad. The additional power supply pad 13 can be connected to the outermost shell power supply line 16 in the chip.
以上説明したように本発明は、ウェハーチェック専用
電源パッドを増設する事により、電源パッドと電源間に
形成される抵抗値を小さくする事ができる。従ってチッ
プ内の電源ラインに発生するノイズが小さくなるので、
入力レベルの測定を正しく行え、ウェハーチェックの歩
留り低下を防止できる効果がある。As described above, the present invention can reduce the resistance value formed between the power supply pad and the power supply by adding the wafer check dedicated power supply pad. Therefore, the noise generated in the power supply line in the chip is reduced,
There is an effect that the input level can be measured correctly and the reduction in the yield of wafer check can be prevented.
第１図は本発明による第１の実施例を示す半導体チップ
の平面図、第２図は本発明の第２の実施例を示す電源パ
ッド部の平面図、第３図は本発明によるチップの電源ラ
インにノイズが発生する様子を示したグラフ、第４図は
従来のチップと、チップに電源を供給する様子を示す半
導体チップの平面図、第５図は従来のチップの電源ライ
ンにノイズが発生する様子を示したグラフである。 １……半導体チップ、2,3……チップ内電源ライン、４
……寄生インピーダンス、5,6……電源、７……信号パ
ッド、8,9……電源パッド、10……空パッド、11,12,13
……ウェハーチェック専用電源パッド、14……高駆動能
力出力バッファ、15……低駆動能力出力バッファ（又は
入力バッファ）、16……チップ内最外殻電源ライン。1 is a plan view of a semiconductor chip showing a first embodiment of the present invention, FIG. 2 is a plan view of a power supply pad section showing a second embodiment of the present invention, and FIG. 3 is a view of a chip according to the present invention. A graph showing how noise is generated in a power supply line, FIG. 4 is a plan view of a conventional chip and a semiconductor chip showing how power is supplied to the chip, and FIG. 5 is a graph showing noise in the power supply line of the conventional chip. It is a graph showing how it occurs. 1 ... Semiconductor chip, 2,3 ... In-chip power supply line, 4
...... Parasitic impedance, 5,6 …… Power supply, 7 …… Signal pad, 8,9 …… Power supply pad, 10 …… Empty pad, 11,12,13
...... Wafer check dedicated power supply pad, 14 …… High drive capacity output buffer, 15 …… Low drive capacity output buffer (or input buffer), 16 …… Outermost shell power line in the chip.
Claims (1)
れる電源パッドに加え前記電源端子に接続されない電源
パッドを増設し、これら容器の電源端子に接続される前
記電源パッド及び増設した前記電源パッドに共通に電源
を供給しながら良品・不良品の判別を行うことを特徴と
する半導体集積回路の良品・不良品判別方法。1. On a semiconductor substrate, in addition to a power supply pad connected to a power supply terminal of a container, a power supply pad not connected to the power supply terminal is added, and the power supply pad connected to the power supply terminal of these containers and the added power supply pad. A method for discriminating a non-defective / defective product of a semiconductor integrated circuit, which is characterized in that a non-defective / defective product is discriminated while supplying a common power to a power pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61300775A JP2545815B2 (en) | 1986-12-16 | 1986-12-16 | How to identify good / defective semiconductor integrated circuits |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61300775A JP2545815B2 (en) | 1986-12-16 | 1986-12-16 | How to identify good / defective semiconductor integrated circuits |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63152142A JPS63152142A (en) | 1988-06-24 |
| JP2545815B2 true JP2545815B2 (en) | 1996-10-23 |
Family
ID=17888938
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61300775A Expired - Fee Related JP2545815B2 (en) | 1986-12-16 | 1986-12-16 | How to identify good / defective semiconductor integrated circuits |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2545815B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63221636A (en) * | 1987-03-10 | 1988-09-14 | Nec Corp | Semiconductor integrated circuit device |
| KR102625726B1 (en) * | 2018-12-31 | 2024-01-15 | 엘지디스플레이 주식회사 | Light emitting display apparatus |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS615539A (en) * | 1984-06-20 | 1986-01-11 | Hitachi Ltd | Semiconductor device |
| JPS6099539U (en) * | 1984-10-11 | 1985-07-06 | 日本電気株式会社 | Integrated circuit with power supply terminal for testing |
| JPS61269326A (en) * | 1985-05-24 | 1986-11-28 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-12-16 JP JP61300775A patent/JP2545815B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63152142A (en) | 1988-06-24 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19960611 |
|
| LAPS | Cancellation because of no payment of annual fees |