JP2534735B2 - Relief address detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention detects the address of a defective address repaired by replacing a redundant memory cell in a repair address detecting circuit, particularly in a semiconductor memory device having a redundant memory cell. The present invention relates to a relief address detection circuit for.

[Conventional technology]

FIG. 3 is a circuit diagram of a typical conventional relief address detection circuit provided in a semiconductor memory device having a redundant memory and its surroundings. This drawing shows the case of a semiconductor memory device having two redundant word lines, and P1i (i is each bit of 0 to n) is n + 1 output signals from a relief address program circuit (not shown), The logical value of each P1i is the respective logical value of the n + 1-bit signal Rli indicating the address of the defective word line replaced with the first redundant word line,
The fuses are programmed by fuse cutting or the like so that "1" is output when the logic values of the n + 1-bit signal AXi indicating the external X address input match, and "0" is output when the logic values do not match. EN1 is a redundant memory cell activation signal that specifies whether to repair a specific defective word line using the first redundant word line, and is "1" when used by the repair address program circuit as in P1i. If not, "0" is output. In addition, P2i, EN2 is the above P1i, E
This signal is similar to N1 and controls the second redundant word line. RD1 is an output signal of the relief address decoder 4 for driving the first redundant word line, and includes an n + 1 bit signal AXi indicating an X address input externally input and an n + 1 bit signal R1i indicating a first relief address. Outputs "1" when the logical values of the two match and EN1 is programmed to be "1". RD2 is the second
The output signal of the repair address decoder 5 for driving the redundant word of the operation is described in the same manner as RD1.

The repair address detection circuit 3 shown in FIG. 3 is composed of a load circuit section 31 composed of two Pch MOSFETs connected in series and a drive circuit section 32 composed of two Nch MOSFETs connected in parallel. One end of the Pch MOSFETs connected in series has a power supply potential, the other end is connected to the drive circuit section 32, and a chip enable signal () and a specific internal Y address signal Yn are given as gate input signals. Further, the Nch MOSFETs connected in parallel have their respective soles connected to GND and their drains connected to the load circuit section 31, and are given the aforementioned RD1 and RD2 respectively as gate input signals. In this circuit, ▲ ▼,
When both Yn are “0”, the two Pch MOs of the load circuit section 31
Both SFETs are turned on, and RD1 or RD2 is "1".
When one of the Nch MOSFETs in the drive circuit section 32 is turned on, a through current flows. In other words, the semiconductor memory device is in the active state and the external Y address input signal AYn corresponding to the internal address signal Yn is set to "0".
Then, if the external X address input signal AXi and the first
Alternatively, a through current flows through this circuit when all the bits of the second relief address match. However, when AYn is set to "1", the load circuit unit 31 is turned off, and this through current does not flow. From the above, the word line activated by the X address input from the outside is changed from address 0 to the final address, and AYn
The address of the relief word line is detected by comparing the operating currents when "0" is set to "0" and when AYn is set to "1", and searching for the X address that causes the above-described through current difference. be able to. In addition, in this circuit, load circuit section 31
By controlling with, the through current is prevented from flowing during standby of the semiconductor memory device. Further, the magnitude of this shoot-through current can be easily optimized by controlling the capacity of the Pch MOSFET of the load circuit section 31.

Although the repair address detection circuit in the semiconductor memory device having two redundant word lines is shown in FIG. 3, when there are two or more redundant word lines, a repair address decoder corresponding to each redundant word line is provided. It is expanded by connecting in parallel the drive circuit unit 32 with an Nch MOSFET having a gate input of the output signal of. When the redundant memory cell is provided on the digit line (Y line), X is used in the above description.
This is achieved by exchanging Y and Y.

FIG. 4 shows a repaired product discriminating circuit provided for judging whether or not the semiconductor memory device is a repaired product using redundant memory cells. The circuit configuration is the same as that of the repair address detection circuit 3 in FIG. 3 described above, and instead of Yn as an input signal,
A specific internal Y address signal Ym different from Yn
EN1 and EN2 are given instead of. By determining the difference in operating current between when the external Y address input AYm corresponding to Ym is "0" and when this circuit is "1" by this circuit, it is possible to immediately determine whether or not the semiconductor device is a repair product. Can be determined. This circuit is essentially unnecessary if it has the rescue address detection circuit 3 described above. However, when it is not necessary to detect the repair address and it is desired to determine only whether the semiconductor memory device is a repair product, the repair address detection circuit 3 searches all the addresses that may be the repair address. Since it is necessary, the time required for the determination becomes long. Therefore,
Normally, in this type of semiconductor memory device, the repair address detecting circuit 3
Along with this, a repaired product discrimination circuit is also provided.

[Problems to be solved by the invention]

In the above-mentioned conventional repair address detection circuit in the semiconductor memory device, in order to detect the repair address, it is necessary to search all the addresses that may be repaired. Therefore, each time the number of address signal lines involved in the rescue address increases, the time required for the search becomes twice as long as before. In recent years, the memory capacity has increased and the frequency of use of redundant memory cells has increased, while the time required to detect a repair address has doubled.
The increase in the number of times has become a big problem in the evaluation and selection of semiconductor memory devices.

An object of the present invention is whether the repair address detecting circuit of the conventional semiconductor memory device described above is "1" or "0" one by one from the lowest address to the highest address for designating the repair address. By determining, you can finally determine the repair address,
It is an object of the present invention to provide a repair address detection circuit that can significantly reduce the repair address detection time compared to the conventional case.

[Means for solving problems]

The repair address detection circuit of the present invention is a semiconductor memory device configured to replace a defective cell in a normal memory cell array with a redundant memory cell to repair a partially defective product as a nondefective product. A relief address program circuit that outputs a logical value "1" to a bit in which the respective logical values of the bit indicating the address of the address line and the bits indicating the address of the external address signal match, and the relief address program circuit A drive circuit unit that takes the logical sum of the logical products of the output bit and each bit indicating the address of the external address signal, and the first switching that is connected in series with this drive circuit unit and is controlled by the chip enable signal. A load circuit section in which a transistor and a second switching transistor controlled by another signal are connected in series Composed of Te.

By having the above configuration, the number of external address lines
Apply "1" to the book and "0" to other external address lines to turn the load circuit on or off and check the change in operating current by sequentially changing "1" on the external address lines. Thus, the replaced address can be known.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention and shows a case where it is applied to a semiconductor memory device having two redundant word lines. The repair address detecting circuit of the present invention includes a circuit for detecting the address of the repair word line replaced with the first redundant word line and a circuit for detecting the address of the repair word line replaced with the second redundant word line. Two are provided independently. Less than,
The repair address detection circuit 1 related to the first redundant word line will be described. This circuit comprises a load circuit section 11 composed of two Pch MOSFETs connected in series as in the above-mentioned conventional example, to which a chip enable signal ▲ ▼ and a specific internal Y address signal Yk are applied, and one end is supplied with power. The potential and the other end are connected to the drive circuit unit 12. The drive circuit unit 12 is composed of a plurality of Nch MOSFETs connected in parallel, the number of which is the number of bits of the address signal required to specify the first relief address,
In this embodiment, the number of bits of the X address signal is n + 1. The sources of the Nch MOSFETs are respectively connected to GND and the drains thereof are respectively connected to the load circuit section 11. The logic values of the internal X address signal Xi (i indicates each bit of 0 to n) as gate input signals and the corresponding values A signal I1i obtained by ANDing with the logical value of the output signal P1i of the repair address program circuit is given.

Now the operation of this embodiment an explanation will be given, only AX ₀ of the bit signals AX ₀ ~AX _n external address input signal corresponding to each bit signal X ₀ to X _n of the internal address signal "1" And AX ₁ to AX _n are “0”, X _{1 to} X _n are all “0”
Since I1 _{1 to} I1 _n also output "0", the drive circuit unit 12
All Nch MOSFETs are in the OFF state except for the one that inputs I1 ₀ . Therefore, at this time, only signals X ₀ and P ₁₀ contribute to the driving of this circuit. Here, if the signals of each bit forming the address of the first relief word line are R1 ₀ to R1 _n , R1 ₀ and AX ₀ match when the least significant bit R1 ₀ is "1". , P1 ₀ outputs "1". Since X _{0 is} also “1”, “1” is also output to the logical product output I1 ₀ , and the drive circuit unit 12 is turned on. Conversely, when R1 ₀ is “0”, R1 ₀
Since it does not match AX ₀ , P1 ₀ outputs “0”. Therefore
I1 ₀ are "0", and the drive circuit section 12 is turned off. From the above, when the external Y address input signal AY _k corresponding to Y _k is set to “1” and “0” with AX _{0 set} to “1” and AX ₁ to AX _{n set} to “0” It can be inferred from the circuit operation of the conventional example that it is possible to determine whether R1 ₀ is "1" or "0" by comparing the operating currents of and. That is, when the operating current when AY _k is “0” is larger than the operating current when AY _k is “1” by the amount of through current flowing through this circuit, R1 ₀ can be determined as “1”. , If there is no difference in these operating currents,
R1 ₀ can be determined to be “0”. In other words Generally, when the relief address detection circuit 1 of the present embodiment want to determine R1i is "1" or "0", out of the signals AX ₀ ~AX _n of each bit of the external X address input signal AXi If only 1 is set to “1”, the operating currents when AY _k is “1” and “0” are compared, and if there is a difference of shoot-through current, R1i is “1”, there is no difference in operating current. For example, R1i can be determined to be "0".

The circuit operation of the repair address detection circuit 2 related to the second redundant word line is similar to that of the repair address detection circuit 1, but the internal Y address signal input to the load circuit section 21 is Y _k. You need to input another signal Y _l . This is because when detecting the first relief address, in order to prevent a through current from flowing through the relief address detection circuit 2, AY _{1 is set} to “1” and the load circuit unit 21 of the relief address detection circuit 2 is turned off. It depends on what you need. Similarly, when detecting the second relief address, it is necessary to keep the load circuit 11 of the relief address detecting circuit 1 and the off-state as "1" to AY _k.

In the semiconductor memory device to which the repair address detecting circuit according to the present invention is applied, the repair item discriminating circuit of FIG. 4 described in the conventional example is indispensable. The reason will be described below. Usually, in this type of semiconductor memory device, an output signal of "1" or "0" is output as an initial value as an output of the repair address program circuit regardless of whether the semiconductor memory device is a repair product. Therefore, the repair address detection circuit of the present invention detects an address corresponding to the initial value of the output of the repair address program circuit even when the semiconductor memory device is not a repair product. Therefore, when detecting a repair address in the semiconductor memory device of the present invention,
First, it is necessary to confirm that the device is a repaired product by the repaired product determination circuit. However,
As described above, the conventional semiconductor memory device also has the repair item determination circuit, and since the time required to determine the repair item is short, the indispensability of the repair item determination circuit in the present invention does not impair the effectiveness. it is conceivable that.

Furthermore, in the embodiment of the present invention described above, the internal X
A similar relief address detection circuit can be realized by using the inverted bit signal ▲ ▼ of the internal X address signal instead of the bit signal Xi of the address signal. Even if the logic of the internal X address signal and the output signal of the repair address program circuit is changed from AND to NOR, the Pch MOSFET and the Nch MOSFET, the power source and the GND are further changed in the above embodiment.
The rescue address detection circuit of the present invention can be realized by replacing ∘ with CS by changing to NAND or OR logic.
However, in this case, the conditions for determination differ depending on the circuit. That is, depending on the circuit, only one of the external X address lines may be set to “0” as a measurement condition at the time of detection, and the rescue address determination criterion is “0” when AY _k is “1”. In some cases, the relief address R1i of the bit of interest when there is a difference in the operating current is "0", and when there is no difference in the operating current, R1i must be set to "1".

Furthermore, in this embodiment, the internal Y address signal is used as the control signal for the load circuit units 11 and 21, but it can be controlled in a direct current manner from the external input terminal, and whether the signal is "1" or "0". It does not matter what kind of signal is used as long as it is an internal signal which does not cause a change in the operating current, such as a Y decoder output signal.

Furthermore, the present embodiment has described the semiconductor memory device having two redundant word lines, but in the semiconductor memory device having two or more redundant word lines, the repair address detecting circuit corresponding to each redundant word line is provided. The present invention can be realized by including the above, and in a semiconductor memory device having redundant memory cells on a digit line (Y line), it can be explained by exchanging X and Y described above.

[Embodiment 2] FIG. 2 is a circuit diagram of another embodiment of the present invention, in which only the portion corresponding to the repair address detection circuit 1 in the embodiment of FIG. 1 is shown. The difference from the embodiment of FIG. 1 lies in the drive circuit section. In the embodiment of FIG. 1, the AND logic of Xi and P1i is taken in advance and the signal is used as the input signal of the Nch MOSFET of the drive circuit section. On the other hand, in this embodiment, two Nchs connected in series
There are n + 1 sets of MOSFETs, one end of each of which is connected to GND and the other end of which is connected to the load circuit section. The bit signal of the internal X address signal is used as the gate input signal of the two Nch MOSFETs.
Xi and the corresponding output signal P1i of the relief address program circuit are connected to each other. First in this circuit
It can be easily inferred from the description of the embodiment of FIG. 1 that the repair address can be detected by the same operation as that of the embodiment of FIG. The present embodiment has an advantage that the repair address detecting circuit of the present invention can be constructed with a smaller number of elements as compared with the embodiment of FIG. 1 and is more practical.

〔The invention's effect〕

As described above, the present invention uses each bit output signal of the relief address program circuit and each bit signal of the internal address signal as input signals of the drive circuit unit of the relief address detection circuit in the semiconductor memory device, and respectively responds. By providing a logic circuit that takes a 2-bit logic (excluding exclusive OR), when detecting a repair address, one from the lowest address to the highest address necessary to configure the address By being able to determine whether it is “0”,
This has the effect of significantly shortening the repair address detection time.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing another embodiment of the present invention, FIG. 3 is a configuration diagram of a conventional relief address detection circuit, and FIG. FIG. 4 is a configuration diagram of a repaired product discrimination circuit. 1,2,3 …… Relief address detection circuit, 4,5 …… Repair address decoder, 11,21,31 …… Load circuit section, 12,22,32 …… Drive circuit section, ▲ ▼ …… Chip enable signal , Y _{k to} Y _n ... internal Y address signal, X _{0 to} X _n ... bit signal of internal X address signal, P1 _{0 to} P1 _n , P2 _{0 to} P2 _n ... output signal of relief address program circuit, EN1 , EN2 ... Redundant memory cell activation signal.

Claims (1)

(57) [Claims] 1. A repair address detection circuit configured to replace a defective cell in a normal memory cell array with a redundant memory cell to repair a partially defective product as a non-defective product. Each bit indicating the address is compared with each bit indicating the address of the external address signal, and the bit whose logic value matches is one logic level, and the bit that does not match outputs a detection signal consisting of multiple bits that are the opposite logic level. The detection circuit is provided in parallel between the node and the first power supply terminal, and each bit of the detection signal has a first input, and each bit of a bit designation signal in which only one bit has one logic level has a second bit. A plurality of drive circuits to be input, the drive circuits of which conduction is controlled according to the logic levels of the first and second inputs; A first switching transistor whose conduction is controlled by a chip enable signal provided between two power supply terminals, and a first logic level after the conduction of the plurality of drive circuits input from outside is determined A rescue address detection circuit, comprising: a second switching transistor whose conduction and non-conduction are controlled by a control signal which becomes a second logic level after the conduction of the drive circuit is determined.