JP2531269B2 - Sync detection method - Google Patents

Description

The present invention relates to a synchronization detection method, and more particularly to a synchronization detection method for a phase locked loop.

[Conventional technology]

Sync detection occurs to trigger an alarm when the phase-locked loop goes out of sync, or to signal that sync has been established for the next operation after synchronization is established. .

FIG. 3 is a block diagram of a first example of the conventional synchronization detection system, and FIG. 4 is a timing chart for explaining the operation of the first conventional example.

A signal S11 obtained by dividing the VCO output S1 output from the voltage controlled oscillator (hereinafter referred to as VCO) 1 by M by the M dividing circuit 2 and a signal S12 obtained by dividing the reference frequency signal S2 by N by the N dividing circuit 3 are excluded. The phase comparison circuit 4 which is a logical OR circuit compares the phases, the comparison result S3 is smoothed by the loop filter 5 to generate the control signal S8, and the control signal S8 controls the VCO1 to form a phase locked loop. As shown in FIG. 4, the comparison result S3 becomes a rectangular wave signal having a frequency twice that of the signals S11 and S12. If the high-level voltage of this rectangular wave signal is V _H and the low-level voltage is V _L , the voltage of the control signal S8 is (V _H + V _L ).
VCO1 is controlled to be / 2. Therefore, the comparison result S3
The state in which the duty ratio of the rectangular wave signal is 50%, in other words, the state in which the phase difference θ between the signals S11 and S12 is π / 2 is the normal phase synchronization state.

The signal S11 is input to the block terminal C of the D flip-flop 12, the signal S12 is input to the data input terminal D, and the Q terminal output is used as the determination signal S9. Since the D flip-flop 12 samples and outputs the signal S12 at the timing of rising of the signal S11 (illustrated by an arrow in FIG. 4), the determination signal S9 becomes "1" continuously in the phase locked state. If the out-of-sync state continues for a long time, "1" and "0" are output with almost the same probability. Since the determination signal S9 is obtained in each cycle of the signal S11, the determination signal S9 can be input to a protection circuit (not shown) such as a majority circuit to prevent erroneous determination due to disturbance.

FIG. 5 is a block diagram of a second example of the conventional synchronization detection system, and FIG. 6 is a timing chart for explaining the operation of the second conventional example.

The configuration and operation of the phase-locked loop in which synchronization is determined in the conventional example shown in FIG. 5 are exactly the same as the configuration and operation of the phase-locked loop in the conventional example shown in FIG.

In the normal phase locked state, as shown in FIG. 6, the voltage of the control signal S8 is near (V _H + V _L ) / 2, so the control signal S8 is near (V _H + V _L ) / 2. For example, whether or not it is within the range of V _{L to} V _H is determined by the threshold value determination circuit 13 in an analog manner, and the determination result is used as the determination signal S10.

[Problems to be Solved by the Invention]

In the conventional example shown in FIG. 3 described above, the phase difference θ (see FIG. 4) between the signals S11 and S12 deviates from the value π / 2 in the correct synchronization state, and becomes a steady state at the end in the range of 0 to π. When (in this case, the synchronization is lost by a slight disturbance), or 0 to π
There is a drawback in that it cannot detect cases that fluctuate within the range.

On the other hand, the conventional example shown in FIG. 5 has a drawback that synchronization determination is made by the output of the loop filter 5 and therefore the determination is time-consuming and is not suitable for using a protection circuit. Moreover, since analog amounts are handled, fluctuations in constituent elements are caused. It is easily affected by fluctuations in power supply voltage, requires adjustment, and is not suitable for use in ICs.
If the control signal S8 is digitized by the A / D converter and the threshold value is digitally judged, the drawbacks caused by the analog operation can be considerably eliminated, but the A / D converter also needs to be incorporated into the IC, and as an IC, Larger scale makes it difficult to configure easily.

The object of the present invention is to be easily processed digitally, to avoid the drawbacks caused by analog processing, to be suitable for IC, and
An object of the present invention is to provide a synchronization detection method that can improve accuracy and that has few misjudgments.

[Means for solving the problem]

The synchronization detection method of the present invention inputs a voltage-controlled oscillator, a signal whose frequency and phase are determined by the output signal of the voltage-controlled oscillator, and a reference frequency signal, compares the phases, and outputs the comparison result as a duty of a rectangular wave signal. Phase-locked-loop synchronization detection system including a phase comparator including an exclusive OR circuit for generating a signal for controlling the voltage-controlled oscillator based on the rectangular wave signal output from the phase comparator In the above, the rectangular wave signal is sampled at a sampling frequency that is at least twice the repetition frequency of the rectangular wave signal, and the sampling frequency is obtained within each counting cycle of a predetermined integer multiple of the repeating cycle of the rectangular wave signal. Count the number of high level samples or at least one of the low level samples of the square wave signal to obtain a count value. First means for outputting a first second comprising an overflow signal below the threshold that defines whether or advance equal to or greater than the threshold value that defines troduction, the first
Second means for determining the synchronization / asynchronization of the phase locked loop based on the generation pattern or the generation probability of the overflow signal output by the means.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation of this embodiment.

The VCO output S1 output from VCO1 is divided by M by the M dividing circuit 2, and the reference frequency signal S2 is divided by N by the N dividing circuit 3. The phase comparison circuit 4 is an exclusive OR circuit. The phase comparison is performed by using the loop filter 5, the control result is smoothed by the loop filter 5, and VCO1 is controlled by this control signal to form a phase locked loop. Is the same.

The high level of the rectangular wave signal of the comparison result S3 is "1", the low level is "0", and the cycle is T.

The timing generation circuit 6 operates from the sampling clock S4 having a cycle much shorter than the cycle T to the reset signal S5 having a cycle T.
Create The input signal is sampled at the timing of the sampling clock S4, the samples having a value of "1" are counted, and an overflow signal is generated when the count value reaches, for example, 55% of the number of sampling clocks S4 in the cycle T. , Counting circuit 7 reset by reset signal S5
A comparison result S3 and a signal obtained by inverting the comparison result S3 by the NOT circuit 9 are input to and 8. Comparison result S3 duty ratio is 55%
With the above, the counting circuit 7 generates the overflow signal S6 via the OR circuit 10. When the duty ratio is 45% or less, the counting circuit 8 generates the overflow signal S6. If the duty ratio is within the range of 50 ± 5%, the overflow signal S6 is not generated. The protection circuit 11 monitors the occurrence of the overflow signal S6 at the cycle of the reset signal S5 and continuously outputs n ₁
If the overflow signal S6 occurs once, it is determined to be in the asynchronous state, and if the overflow signal S6 is not generated even once in the continuous monitoring of n ₂ times, it is determined to be the synchronous state, and the determination result is the determination signal.
Output as S7.

In the embodiment shown in FIG. 1, the duty ratio of the comparison result S3 is
If it is inside the range of 50 ± 5%, it is judged as the synchronous state, and if it is outside the range, it is judged as the asynchronous state.

Sampling clock compared with the frequency of comparison result S3
The higher the frequency of S4, the higher the accuracy of judgment,
It cannot be judged unless it is at least twice as high.

If the division ratio M of the M division circuit 2 is 2 or more, VCO output S1
Can be used as the sampling clock S4, and N
If the frequency dividing ratio N of the frequency dividing circuit 3 is 2 or more, the reference frequency signal
S2 can be used as the sampling clock S4. Further, the sampling clock S4 may be asynchronous with the VCO output S1 and the reference frequency signal S2.

The cycle of the reset signal S5 may be an integral multiple of the cycle T. Also, instead of the protection circuit 11, a protection circuit using majority decision can be used.

Further, the counting circuit 7, the counting circuit 8, the NOT circuit 9, and the OR circuit 10
Instead of getting the overflow signal S6 by
S3 is sampled at the timing of the sampling clock S4, and the sample of the value "1" (or "0") generated in the cycle of the reset signal S5 is counted. It is also possible to use a circuit for generating the overflow signal S6.

In addition, the phase-locked loop is composed of the M divider circuit 2 and the N divider circuit 3.
The present invention can be applied to the case where is not used.

〔The invention's effect〕

As described above, the present invention samples the rectangular wave signal output by the phase comparator of the phase locked loop at high speed,
By determining synchronization / asynchronization based on the ratio of the number of samples with the value “1” to the number of samples with the value “0”, it is possible to configure with a digital circuit, so there is no effect due to fluctuations in the constituent elements or fluctuations in the power supply voltage. There are few, no adjustment is required, there is an effect suitable for IC, and there is an effect that the sampling frequency can be increased to improve the judgment accuracy. Furthermore, the number of samples with the value "1" and the value "0" A large number of signals corresponding to the ratio to the number of samples of "can be obtained in a short time, and since a protection circuit is provided, an erroneous determination can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG.
FIG. 3 is a timing chart for explaining the operation of the embodiment shown in the figure, FIG. 3 is a block diagram of the first example of the conventional synchronization detection system, and FIG. 4 is for explaining the operation of the conventional example shown in FIG. 5 is a timing chart of the synchronization detection method
FIG. 6 is a block diagram of the example of FIG. 5, and FIG. 6 is a timing chart for explaining the operation of the conventional example shown in FIG. 1 ... VCO, 2 ... M divider, 3 ... N divider, 4
...... Phase comparison circuit, 5 …… Loop filter, 6 …… Timing generation circuit, 7,8 …… Counting circuit, 9 …… NOT circuit, 10
…… OR circuit, 11 …… Protection circuit.

Claims (1)

(57) [Claims] 1. An exclusive circuit for inputting a voltage-controlled oscillator, a signal whose frequency and phase are determined by an output signal of the voltage-controlled oscillator, and a reference frequency signal, comparing the phases, and outputting a comparison result as a duty ratio of a rectangular wave signal. In a phase detection loop synchronization detection method, comprising a phase comparator formed of a logical sum circuit and a loop filter that forms a signal for controlling the voltage controlled oscillator based on the rectangular wave signal output by the phase comparator, The rectangular wave signal obtained by sampling the rectangular wave signal at a sampling frequency that is at least twice the repetition frequency of the rectangular wave signal and obtaining within this counting cycle every counting cycle that is a predetermined integer multiple of the repeating cycle of the rectangular wave signal. The number of high-level samples or at least one of the low-level samples of the A first means for outputting an overflow signal when the threshold value is equal to or greater than a threshold value of 1 or equal to or lower than a second predetermined threshold value, and a generation pattern or a generation probability of the overflow signal output by the first means. And a second means for determining whether the phase locked loop is synchronous or asynchronous based on the above.