JP2012199301A - Solid-state imaging device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state imaging device allowing enhancement of an aperture ratio and improvement of sensitivity.SOLUTION: A solid-state imaging device comprises a semiconductor substrate 103 in which an imaging region having a plurality of pixels arranged in a matrix are formed, and a first wiring layer (at the imaging region side) 105a and a second wiring layer 105b that are formed on the imaging region. Photodiodes PD, transfer transistors TG, floating diffusions FD, reset transistors RS, and amplifier transistors SF are formed in the imaging region. Row-direction wiring extending in the row direction between the adjacent pixels and column-direction wiring extending in the column direction between the adjacent pixels are one or less at the center of the pixels in the second wiring layer 105b.

Description

  The present invention relates to a solid-state imaging device, and more particularly to a technique for improving sensitivity by increasing the amount of light incident on a photodiode by enlarging a wiring opening.

  The MOS type image sensor which is one of the solid-state imaging devices has responded to the demand for a higher number of pixels such as a digital still camera by reducing the unit cell size. However, when the unit cell size is reduced, the metal wiring arranged around the photodiode blocks the optical path of the incident light to the photodiode, which causes a decrease in sensitivity, color mixing, and the like.

In order to prevent such a decrease in sensitivity and color mixing, various efforts have been made.
For example, technologies such as condensing with an on-chip lens, enlargement of the photodiode area by sharing multiple pixels, reduction of the number of wiring layers and expansion of wiring openings, and use of waveguides by devising the layout have been developed to improve sensitivity and prevent color mixing. (See, for example, Patent Document 1).

Hereinafter, a conventional solid-state imaging device (photoelectric conversion device) described in Patent Document 1 will be described with reference to FIG. Here, the photoelectric conversion device will be described.
FIG. 23 is an equivalent circuit diagram of the pixel region and the vertical scanning circuit of the photoelectric conversion device.

  The photoelectric conversion device includes a large number of unit cells in the pixel region (1). The unit cell includes a photodiode (PD2-1, PD2-2), a transfer transistor (M1, M2), a reset transistor (M3, M5), and an amplification transistor (M4). Here, one cell is composed of two pixels (photodiodes).

  The photodiodes (PD2-1, PD2-2) accumulate electric charges by photoelectric conversion according to the received light, and the transfer transistors (M1, M2) are accumulated in the photodiodes (PD2-1, PD2-2). The transferred charges are transferred to the charge storage unit (floating diffusion) in accordance with the transfer control signal. The reset transistors (M3, M5) initialize the charge storage unit FD according to the reset signal, and the amplification transistor (M4) outputs a signal (voltage) according to the level of the charge stored in the charge storage unit to the output signal line. Output to (2).

  The gates of the transfer transistors (M1, M2) are connected to the transfer gate lines (43, 44), and the gates of the reset transistors (M3, M5) are connected to the reset line (46). The source of the amplification transistor (M4) is connected to the signal line (2).

  The drain of the amplification transistor (M4) and the drain of the reset transistor (M5) are connected in the active region, and are connected to the power supply line (4) in the adjacent column via the bridge line (45). Note that the drain of the reset transistor (M5) arranged in the adjacent column is connected to the power supply line (4) of the column.

  Here, the transfer gate lines (43, 44), the bridge line (45), and the reset line (46) are configured by the first layer wiring close to the semiconductor substrate, and the signal line (2) and the power supply line (4) are The second layer wiring is formed above the first layer wiring.

Next, wiring will be described.
The transfer gate lines (43, 44) as the first layer wiring extend in the row (lateral direction in the drawing) direction between the photodiodes that are adjacent cells in the vertical direction, and the bridge line (45). The reset line (46) extends in the row direction between the photodiodes in the cell.

  The signal line (2) as the second layer wiring extends in the column direction between the photodiodes adjacent in the row direction. The power supply line (4) extends in the column direction between adjacent photodiodes every other column in the row direction.

  In the above configuration, the second layer wiring is a total of one signal line (2), one signal line (2), and one power supply line (4) between photodiodes adjacent in the row direction. Two wirings are arranged, and the aperture ratio can be made larger than that of a photoelectric conversion device in which two wirings are arranged between adjacent photodiodes.

JP 2010-16056 A

  However, in the photoelectric conversion device described in Patent Document 1, the average number of wirings between photodiodes is 1.5, and the aperture ratio can be improved as compared with the conventional wiring between two photodiodes. However, it is necessary to reduce the pixel size in order to meet the demand for further increase in the number of pixels, and further improvement of the aperture ratio is required.

  In addition, when there are two wirings in the second layer between adjacent photodiodes, when the pixel size is reduced, the light collected by the on-chip lens interferes with the wiring, resulting in a decrease in sensitivity.

  In view of the above problems, an object of the present invention is to provide a solid-state imaging device capable of increasing the aperture ratio and improving the sensitivity.

  In order to solve the above problems, a solid-state imaging device according to the present invention includes a semiconductor substrate having an imaging region including a plurality of pixels arranged in a matrix direction, and a peripheral circuit region including a peripheral circuit around the imaging region, A wiring layer disposed above the imaging region and for connecting the pixel and the peripheral circuit, the wiring layer including a first wiring layer and a second wiring layer from the semiconductor substrate side; In order, the first wiring layer includes two wirings extending in a second direction orthogonal to the first direction between pixels adjacent to each other in the first direction, and the second wiring layer Includes two wirings extending in the first direction between pixels adjacent in the second direction, and at least one of the two wirings of the second wiring layer is the first wiring. That the first wiring layer has entered the central region of pixels adjacent in the direction of It is a symptom.

  According to the above configuration, at least one of the two wirings of the second wiring layer enters the first wiring layer in the central region of the pixel adjacent in the first direction. The number of wirings is one or less in the central region of pixels adjacent in the first direction, and the aperture ratio and sensitivity can be improved.

2 is a layout diagram showing a diffusion layer, polysilicon, and contacts in a unit cell of the solid-state imaging device according to the first embodiment. FIG. 1 is a circuit diagram schematically showing a unit cell of a solid-state imaging device according to a first embodiment. FIG. 2 is a layout diagram showing a first wiring layer and vias connecting the first wiring layer and the second wiring layer in addition to FIG. 1. FIG. 4 is a layout diagram showing a second wiring layer in addition to FIG. 3. It is sectional drawing in the broken line a in FIG. It is sectional drawing in the broken line b in FIG. FIG. 3 is a layout diagram according to a second embodiment showing a first wiring layer and vias connecting the first wiring layer and the second wiring layer in addition to FIG. 1. FIG. 8 is a layout diagram showing a second wiring layer in addition to FIG. 7. It is sectional drawing in the broken line c in FIG. It is sectional drawing in the broken line d in FIG. FIG. 5 is a layout diagram according to a third embodiment showing a first wiring layer and vias connecting the first wiring layer and the second wiring layer in addition to FIG. 1. FIG. 12 is a layout diagram showing a second wiring layer in addition to FIG. 11. It is sectional drawing in the broken line e in FIG. It is sectional drawing in the broken line f in FIG. FIG. 5 is a layout diagram according to a third embodiment showing a first wiring layer and vias connecting the first wiring layer and the second wiring layer in addition to FIG. 1. FIG. 16 is a layout diagram showing a second wiring layer in addition to FIG. 15. It is sectional drawing in the broken line g in FIG. It is sectional drawing in the broken line h in FIG. It is the layout figure which showed the diffused layer, the polysilicon, and the contact in the unit cell of the solid-state imaging device which concerns on 5th Embodiment. It is a circuit diagram which shows typically the unit cell of the solid-state imaging device which concerns on 5th Embodiment. FIG. 20 is a layout diagram showing a first wiring layer and vias connecting the first wiring layer and the second wiring layer in addition to FIG. 19. FIG. 22 is a layout diagram showing a second wiring layer in addition to FIG. 21. It is an equivalent circuit diagram of a pixel region and a vertical scanning circuit of a photoelectric conversion device in the prior art.

  The shapes, materials, numerical values, and the like described in the embodiments are merely preferred examples, and the present invention is not limited to these embodiments. In addition, modifications can be made as appropriate without departing from the scope of the technical idea of the present invention, and combinations of other embodiments, modifications, and the like can be made within a range where no contradiction occurs.

In the solid-state imaging device according to the present invention, the number of metal wirings between the photodiodes in the row direction and the column direction is two, and one is arranged in the first wiring layer and one in the second wiring layer, or By laying out two lines in the first wiring layer, the opening is enlarged, and the opening ratio and high sensitivity are realized.
<First Embodiment>
The solid-state imaging device according to the first embodiment has one wiring in the first wiring layer and wiring in the second wiring layer in a cross section at a virtual plane passing through the center of the photodiodes adjacent in the row direction and extending in the row direction. Each one is arranged. In addition, one wiring is arranged in the first wiring layer and one wiring is arranged in the second wiring layer in a cross section of a virtual plane extending in the column direction through the center of the photodiodes adjacent in the column direction.

  That is, in the first wiring layer 105a, two wirings (here, extending in the row direction, which is a second direction orthogonal to the first direction), between pixels adjacent to each other in the column direction, which is the first direction. , Two transfer control signal lines T1 and T2, two transfer control signal lines T3 and T4, and two lines of the first power supply line VDD1 and the reset signal line Rx) are arranged in the second wiring layer 105b. , Two wirings extending in the column direction, which is the first direction, between pixels adjacent in the row direction, which is the second direction (here, two of the signal line SIG and the ground line VSS, the signal line SIG and the first line) 3 power supply lines VDD3) and one of the two wirings of the second wiring layer 105b (here, the signal line SIG or the signal line SIG of the two signal lines SIG and the ground line VSS) One ground line VSS or two wiring signal lines SIG and the third The source line VDD3 is one of the signal line SIG and the third power supply line VDD3.) Enters the first wiring layer 105a in the central region of the pixel adjacent in the column direction, which is the first direction, One of the two wirings of the wiring layer 105a (here, any one of the transfer control signal lines T1 and T2, one of the transfer control signal lines T3 and T4, or the first power supply line) One of the reset signal lines Rx out of two of the VDD1 and the reset signal line Rx) enters the second wiring layer 105b in the central region of the pixel adjacent in the row direction which is the second direction. Yes.

Hereinafter, the first embodiment will be described in detail with reference to FIGS.
FIG. 1 is a layout diagram showing diffusion layers, polysilicon, and contacts in a unit cell of the solid-state imaging device according to the first embodiment.

FIG. 2 is a circuit diagram schematically showing a unit cell of the solid-state imaging device according to the first embodiment.
3 is a layout diagram showing the first wiring layer and vias connecting the first wiring layer and the second wiring layer in addition to FIG. 1, and FIG. 4 is a layout diagram showing the second wiring layer in addition to FIG. .

5 is a cross-sectional view taken along the broken line a in FIG. 4, and FIG. 6 is a cross-sectional view taken along the broken line b in FIG.
1. Overall Configuration As shown in FIGS. 5 and 6, the solid-state imaging device 101 includes a semiconductor substrate 103 having an imaging region and a peripheral circuit region on the main surface side, and a wiring layer 105 formed on the imaging region of the semiconductor substrate 103. And a waveguide 107 provided in the wiring layer 105, a color filter 109 provided on at least an imaging region of the semiconductor substrate 103, and a lens 111 provided on the color filter 109.

  As shown in FIG. 1, the imaging region includes a plurality of pixels arranged in the matrix direction. The peripheral circuit region includes a circuit for outputting a pixel signal from the pixel region to an external device and supplying power to each transistor (not shown). Note that the peripheral circuit region is provided in a partial range or the entire range around the pixel region.

The wiring layer 105 is provided with wiring for electrically connecting the peripheral circuit and each pixel, and has two layers of the first wiring layer 105a and the second wiring layer 105b from the semiconductor substrate 103 side. That is, it has a two-layer structure. Specifically, each of the first wiring layer 105a and the second wiring layer 105b is configured by forming a metal wire (eg, aluminum wire) in an insulating material (eg, SiO ₂ ). ing.

  For example, the waveguide 107 is formed between wirings arranged in the wiring layer 105. The waveguide 107 is made of a material (for example, SiN: having a refractive index of 2.0) having a higher refractive index than the periphery (for example, the wiring layer 105). When the diameter of the waveguide 107 is increased, more light collected by the lens 111 can be incident on the light receiving unit (photodiode), and high sensitivity can be realized.

  As shown in FIG. 1, each pixel includes a photodiode PD and a transfer transistor TG. Here, one unit cell is composed of a plurality of pixels, and in this embodiment, one unit cell is composed of four pixels (a so-called four-pixel one-cell structure).

  That is, the unit cell includes four photodiodes PD (for example, PD11, PD21, PD31, PD41), four transfer transistors TG (for example, TG1, TG2, TG3, TG4), one reset transistor RS, Two amplification transistors SF (for example, SF1 and SF2) are provided.

  Note that the photodiode, the transfer transistor, and the reset transistor are generally referred to as “PD” for the photodiode, and “PD” for the transfer transistor when describing the photodiode, transfer transistor, and amplification transistor as a whole, regardless of their positions. “TG” is used for the amplification transistor “SF”.

  The column direction here is a direction (arrangement direction) in which a plurality (four in this case) of photodiodes constituting one unit cell are arranged, and the row direction is an arrangement of photodiodes. It is a direction orthogonal to the direction.

The photodiode PD accumulates charges by photoelectric conversion according to the received light, and the transfer transistor TG transfers the charges accumulated in the photodiode PD to the charge accumulation unit (floating diffusion) FD according to the transfer control signal. . The reset transistor RS initializes the charge storage unit FD according to the reset signal, and the amplification transistor SF outputs a signal according to the level of the charge stored in the charge storage unit FD.
2. Layout The layout of photodiodes and the like will be described with reference to FIG.

  As described above, the unit cell according to the present embodiment includes four photodiodes PD11, PD21, PD31, PD41, four transfer transistors TG1, TG2, TG3, TG4, two amplification transistors SF1, SF2 and one reset transistor RS are provided.

  Four photodiodes PD11, PD21, PD31, PD41 are arranged at equal intervals in the column direction, and four transfer transistors TG1, TG2, TG3, TG4, etc. are arranged corresponding to each photodiode PD. .

  Note that in the symbol “PDnk” of the photodiode, “n” indicates the number of rows, “k” indicates the number of columns, and “n”, “k”, “k + 1”, or the like is used depending on the case. For example, “PD23” is shown when a photodiode arranged in the second row and the third column in the drawing is shown. “N” and “k” are both natural numbers.

  The symbol “TGn” of the transfer transistor corresponds to “n” indicating the row of the photodiode PDnk. That is, the transfer transistor TG3 indicates the transfer transistor TG provided corresponding to the photodiode PD3k in the third row in the unit cell in which the transfer transistor is arranged.

  The transfer transistors TG1, TG2, TG3, TG4 are arranged corresponding to the photodiodes PD11, PD21, PD31, PD41. For example, the transfer transistors TG1 and TG3 are disposed obliquely below the photodiodes PD11 and PD31, and the transfer transistors TG2 and TG4 are disposed obliquely above the photodiodes PD21 and PD41.

  Specifically, among the four photodiodes PD constituting the unit cell, the transfer transistors TG1 and TG2 corresponding to the photodiodes PD1k and PD2k located in the upper half are on the side where the photodiodes PD1k and PD2k face each other. They are arranged in a state of facing each other in a region corresponding to one corner. The transfer transistors TG3 and TG4 corresponding to the photodiodes PD3k and PD4k located in the lower half of the unit cell are arranged in a state in which the photodiodes PD3k and PD4k face each other in a region corresponding to one corner existing on the side facing each other. ing.

Needless to say, the positional relationship between the photodiode PD and the transfer transistor TG is not limited to this example, and may be another positional relationship.
The amplification transistors SF1 and SF2 are arranged around the center of the unit cell in the column direction. That is, the amplification transistors SF1 and SF2 are arranged in a region between the photodiodes PD2k in the second row and the photodiodes PD3k in the third row and around the regions among the four photodiodes PD constituting the unit cell. ing. That is, it is arranged in a region between the transfer transistors TG2 and TG3 in each unit cell.

The reset transistor RS is between photodiodes adjacent in the row direction (also between unit cells adjacent in the row direction), and is an end region in the column direction of the unit cells (here, an upper end region). There is.) That is, the reset transistor RS of the unit cell including the photodiode PD1k is arranged in a region on the opposite side of the photodiode PD1k from the side where the transfer transistor TG1 corresponding to the photodiode PD1k is arranged.
3. Circuit Configuration Connection of photodiodes and the like will be described with reference to FIG.

The connection between each transistor and the wiring will be described later.
Each transfer transistor TG1, TG2, TG3, TG4 has its source connected to the N-side electrode of the corresponding photodiode PD1k, PD2k, PD3k, PD4k, and its gate connected to the corresponding transfer control signal line T1, T2, T3, T4. It is connected to the.

  The drains of the transfer transistors TG1, TG2, TG3, and TG4 are connected to the gates of the two amplification transistors SF1 and SF2 and to the source of the reset transistor RS. Thereby, the charge storage unit FD is configured.

The drains of the amplification transistors SF1 and SF2 are connected to the second power supply line VDD2, and the sources are connected to the signal line SIG.
The reset transistor RS has a gate connected to the reset signal line Rx and a drain connected to the first power supply line VDD1.

A ground line VSS that secures the substrate potential (ground) of the semiconductor substrate 103 is connected to a substrate contact C6 described later.
4). Wiring The solid-state imaging device 101 includes a row direction wiring group and a column direction wiring group in the wiring layer 105 as shown in FIGS. 1 and 2. The row direction wiring group is a wiring that extends in the row direction between adjacent pixels in the column direction. The row direction wiring group includes a first power supply line VDD1, a reset signal line Rx, transfer control signal lines T1, T2, T3, T4, and a second power supply line 2VDD2.

The column direction wiring group is a wiring extending in the row direction between pixels adjacent in the column direction. The column-direction wiring group includes a ground line VSS, a signal line SIG, and a third power supply line VDD3.
(1) Transfer control signal line (T)
The transfer control signal lines T1, T2, T3, and T4 are arranged in a state extending between the rows of photodiodes (PD) arranged in a matrix in the row direction.

  The transfer control signal lines T1 and T2 extend in the row direction between the photodiode PD1k in the first row and the photodiode PD2k in the second row in each unit cell. The transfer control signal lines T3 and T4 extend in the row direction between the photodiode PD3k in the third row and the photodiode PD4k in the fourth row in each unit cell. Needless to say, the arrangement positions of the transfer control signal lines T1, T2, T3, and T4 are not limited to this example, and may be other positions.

  The transfer control signal line T1 includes a wiring T1a of the first wiring layer 105a and a wiring T1b of the second wiring layer 105b. Similarly, the transfer control signal line T2 includes the wiring T2a of the first wiring layer 105a and the wiring T2b of the second wiring layer 105b, and the transfer control signal line T3 includes the wiring T3a and the second wiring layer of the first wiring layer 105a. From the wiring T3b of 105b, the transfer control signal line T4 includes the wiring T4a of the first wiring layer 105a and the wiring T4b of the second wiring layer 105b.

It should be noted that the transfer control signal line T1 and the transfer control signal line T3 have the same configuration only in the arrangement location, and the transfer control signal line T2 and the transfer control signal line T4 have the same configuration only in the arrangement location. is doing. Therefore, the transfer control signal lines T1 and T2 will be described below.
(I) Wiring in the first wiring layer (T1a, T2a, etc.)
As shown in FIG. 3, the wiring T1a of the transfer control signal line T1 is formed along the second row end (the photodiode PD2k side) of the photodiode PD1k in the first row, and is arranged in the row direction. Each of the photodiodes PD1k thus formed is extended in the row direction while alternately having removal portions and overhang portions formed corresponding to the photodiodes PD1k.

  That is, with reference to the photodiode PD11, the wiring T1a of the transfer control signal line T1 serves as a removal portion having no wiring in the photodiodes PD11 and PD13 in the first row and the even columns in the first row. The photodiodes PD12, 14 and the like are overhanging portions projecting toward the photodiodes PD22, PD24 in the second row.

  Similarly, the wiring T2a of the transfer control signal line T2 is formed along the end of the first column side (the photodiode PD1k side) of the photodiode PD2k in the second row, as shown in FIG. It extends in the row direction while alternately having removal portions and overhang portions formed corresponding to the photodiodes PD2k arranged in the direction.

  In other words, the wiring T2a of the transfer control signal line T2 is a removed portion having no wiring in the photodiodes PD22, PD24, etc. in the even-numbered columns in the second row, with reference to the photodiode PD21, and the even-numbered columns in the second row. In the photodiodes PD21, PD23, etc., the projecting portion is projected to the photodiodes PD11, PD13 side of the first row.

  As described above, the wirings T1a and T2a have a shape in which the removal portion and the overhang portion are alternately inverted in each column while having the removal portion and the overhang portion as a set between the photodiodes adjacent in the column direction. I am doing.

  The position of the overhang portion in the column direction is a central region located between the photodiode PD1k in the first row and the photodiode PD2k in the second row and in the center thereof. The positions in the row direction of the overhang portions and the removal portions in the respective wirings T1a and T2a are intermediate regions including the centers of the respective photodiodes PD1k and PD2k.

Note that the protruding portions of the wirings T1a and T2a may be linearly bent or projecting as shown in FIG. 3, or may be curved and projecting in an arc shape.
(Ii) wiring of the second wiring layer (T1b, T2b, etc.)
As shown in FIG. 4, the wiring T1b of the transfer control signal line T1 is formed in a region between the first row and the second row and corresponding to the removed portion of the wiring T1a of the first wiring layer 105a. The wiring T1b has a shape that is line symmetric with respect to an imaginary line that extends in the row direction and passes through the center between adjacent photodiodes PD in the column direction, and has an “H” shape here.

  The wiring T1b is in an independent state between the photodiodes PD1k and PD2k in odd columns in the first row and the second row (here, “k” is an odd natural number) with reference to the photodiode PD11. It is arranged with. Here, the “independent state” means that the second wiring layer 105b is not in contact with other wiring, and is connected to the first wiring layer 105a across the layers, for example, vias. Including cases.

  Similarly, the wiring T2b of the transfer control signal line T2 is formed in a region between the first row and the second row and corresponding to the removed portion of the wiring T2a of the first wiring layer 105a as shown in FIG. Has been. The wiring T <b> 2 b has a shape that is line-symmetric with respect to an imaginary line that extends in the row direction and passes through the center between the photodiodes PD adjacent in the column direction, and has an “H” shape here. That is, the wiring T2a has the same shape as the wiring T1a.

  The wiring T2b is in an independent state between the photodiodes PD1k and PD2k in the even-numbered columns in the first row and the second row (here, “k” is an even natural number) with reference to the photodiode PD11. It is arranged with. The “independent state” here is as described above.

In this way, the wirings T1b and T2b are arranged in the row direction while being replaced in units of columns.
A portion extending in the horizontal direction of the “H” -shaped wirings T1b and T2b is located between the photodiode PD1k in the first row and the photodiode PD2k in the second row and in the central region thereof.
(Iii) Summary The wiring T1a and the wiring T1b are connected by vias (see FIG. 3), thereby configuring the transfer control signal line T1 extending in the row direction. Similarly, the wiring T2a and the wiring T2b are connected by vias, thereby configuring the transfer control signal line T2 extending in the row direction.

  The connection between the wiring T1a and the wiring T1b includes a portion sandwiching the removal portion in the wiring T1a and an upper end portion or a lower end portion of a pair of vertically extending portions constituting the “H” shape of the wiring T1b. Done in Similarly, the via connection between the wiring T2a and the wiring T2b is made between the portion sandwiching the removal portion in the wiring T2a and the portion extending in the pair of vertical (column) directions constituting the “H” shape of the wiring T2b. It is performed at the upper end portion or the lower end portion.

  As described above, the wiring between the wiring T1a and the wiring T1b and the wiring between the wiring T2a and the wiring T2b are alternately performed in units of columns in the row direction as shown in FIGS. That is, the wiring between the wiring T1a and the wiring T1b and the wiring between the wiring T2a and the wiring T2b are arranged while changing the positional relationship and the wiring layer to be wired for each column.

  As described above, the transfer control signal lines T3 and T4 have the same configuration as the transfer control signal lines T1 and T2 except that the transfer control signal lines T1 and T2 are formed at different locations (arrangement locations). The positional relationship between T3 and T4 is the same as that of the transfer control signal lines T1 and T2.

As a result, the transfer control signal lines T1, T2, T3, and T4 have the same configuration, and the load of the signal lines can be made equal. Further, the transfer control signal lines T1 and T2 and the transfer control signal lines T3 and T4 have the same shape (configuration) at the top and bottom with respect to the approximate center of the unit cell, and are caused by variations in the wiring shape. Variations in optical characteristics can be reduced.
(2) Reset signal line (Rx)
The reset signal line Rx is arranged in a state extending between the rows of photodiodes PD arranged in a matrix in the row direction. Here, it is arranged on the upper end side of the photodiode PD1k arranged in the first row (the first row of the unit cell) in each unit cell. That is, in the photodiode PD1k in the first row of the unit cell, the photodiode PD1k is arranged at the end on the side where the photodiode PD4k in the last row (four rows) of another adjacent unit cell is located. Needless to say, the wiring position of the reset signal line SIG is not limited to this example, and may be another position, for example, the lower end side of the photodiode PD4k in the fourth row.

The reset signal line Rx includes a wiring Rxa of the first wiring layer 105a and a wiring Rxb of the second wiring layer 105b.
(I) First wiring layer wiring (Rxa)
As shown in FIG. 3, the reset signal line Rx wiring Rxa is formed along the other unit cell side end of the photodiode PD1k in the first row (in the figure, the upper end of each photodiode PD1k). The photodiode PD1k and the photodiode PD1k + 1 adjacent to each other in the row direction are formed so as to straddle the adjacent photodiode PD1k + 1.

  More specifically, it is formed between the photodiode PD11 and the photodiode PD12 so as to straddle the photodiode PD11 and the photodiode PD12 (so as to overlap in a plan view).

That is, the reset signal line Rxa has a shape in which the protruding portion of the wiring T1a of the transfer control signal line T1 and the wiring T2a of the transfer control signal line T2 is a removed portion, and the portion where the photodiode PD1k of each column is located It has the removal part corresponding to.
(Ii) Wiring of second wiring layer (Rxb)
As shown in FIG. 4, the wiring Rxb of the reset signal line Rx is formed in units of columns along the upper end of the photodiode PD1k in the first row. In other words, the upper end is another unit cell adjacent in the column direction, which is the end on the side where the unit cell and the other unit cell face each other.

  The wiring Rxb has a shape that is line symmetric with respect to an imaginary line extending in the row direction and passing through the center between adjacent photodiodes PD in the column direction, in this case, an “H” shape. That is, the wiring Rxa has the same shape as the wiring T1b of the second wiring layer 105b such as the transfer control signal line T1.

The portion extending in the horizontal direction of the “H” -shaped wiring RXb is the photodiode PD1k in the first row and the photodiode in the fourth row which is the last row of other unit cells adjacent to the photodiode PD1k in the column direction. It is located in the center area between PD4k.
(Iii) Summary The wiring Rxa and the wiring Rxb are connected by vias (see FIG. 3), and thereby, one reset signal line Rx extending in the row direction is configured. The vias of the wiring Rxa and the wiring Rxb are connected to a pair of upper and lower portions constituting the “H” shape of the wiring Rxb of the second wiring layer 105b and a portion sandwiching the removal portion of the wiring Rxa of the first wiring layer 105a. It is performed at the lower end portion of the portion extending in the (row) direction.
(3) First power supply line (VDD1)
The first power supply line VDD1 is arranged in a state extending between the rows of photodiodes arranged in a matrix in the row direction. Here, it is arranged on the lower end side of the photodiode PD4k arranged in the last row in each unit cell. That is, it is arranged on the side facing the other unit cell adjacent in the column direction in the photodiode PD4k arranged in the last row in each unit cell. Needless to say, the wiring position of the first power supply line VDD1 is not limited to this example, and may be another position.

  The first power supply line VDD1 is composed of the wiring VDD1a of the first wiring layer 105a. As shown in FIG. 3, the wiring VDD1a is formed along the other end on the unit cell side adjacent to the column direction in the photodiode PD4k in the fourth row (in the figure, the lower end of each photodiode PD4k). ing.

  In the wiring VDD1a, a bridging portion that bridges adjacent photodiodes PD4k + 1 between the adjacent photodiodes PD4k in the row direction, and an intermediate portion including the center in the row direction of each photodiode PD4k protrudes to the other unit cell side. Overhangs are alternately provided in the row direction.

That is, the wiring VDD1a has a shape such that the removed portion of the wiring T1a of the transfer control signal line T1 and the wiring T2a of the transfer control signal line T2 is an overhanging portion.
The position of the protruding portion in the column direction is between the photodiode PD4k in the fourth row, which is the last row of the unit cells, and the photodiode PD1k in the first row, which is the first row of unit cells adjacent in the column direction. And the central area.
(4) Second power line (VDD2)
The second power supply line VDD2 is arranged in a state extending between the rows of photodiodes arranged in a matrix in the row direction. Here, it is arranged between the photodiode PD2k and the photodiode PD3k arranged in a row at an intermediate position in each unit cell.

  That is, the four photodiodes PD constituting the unit cell are arranged between the photodiode PD2k and the photodiode PD3k facing the boundary portion that is divided in half. Needless to say, the wiring position of the second power supply line VDD2 is not limited to this example, and may be another position.

  The second power supply line VDD2 includes the wiring VDD2a of the first wiring layer 105a. As shown in FIG. 3, the wiring VDD2a bridges the photodiodes PD adjacent to each other in the row direction in the photodiode PD2k on the second row side (the upper half side) between the photodiodes PD adjacent in the row direction. The photodiode PD3k on the third row side (lower half side) has a bridge portion that bridges the photodiodes PD adjacent in the row direction, and the bridge portions form a pair. Stretched in the row direction.

In addition, a pair of bridge | crosslinking part is connected by the connection part extended | stretched in the column direction in the center area | region between the photodiodes adjacent to a row direction.
As shown in FIG. 3, the wiring VDD2a is connected between the photodiodes PD (for example, the photodiode PD2k and the photodiode PD3k) in each column, and the photodiode PD (for example, the photodiode) on the other side from each photodiode PD. In PD2k, the photodiode PD on the other side corresponds to the photodiode PD3k).

That is, the wiring VDD2a has a shape such that the wirings T1a and T2a of the first wiring layer 105a in the transfer control signal lines T1 and T2 are combined, and the removal part in each of the wirings T1a and T2a is replaced with an overhanging part.
(5) Signal line (SIG)
The signal lines SIG are arranged in a state extending between the columns of the photodiodes PD arranged in a matrix in the column direction. Here, the signal line SIG of the photodiode PDn1 in the first column in each unit cell is arranged between the photodiode PDn1 in the first column and the photodiode PDn2 in the second column. Needless to say, the wiring position of the signal line SIG is not limited to this example, and other positions (for example, the signal line SIG of the photodiode PDn2 in the second column and the photodiode PDn1 in the first column) Yes.)

The signal line SIG includes a wiring SIGa of the first wiring layer 105a and a wiring SIGb of the second wiring layer 105b, and the wiring SIGa of the first wiring layer 105a and the wiring SIGb of the second wiring layer 105b are connected via vias, for example. It is connected.
(I) First wiring layer wiring (SIGa)
As shown in FIG. 3, the wiring line SIGa of the signal line SIG is formed between the photodiode PDnk and the photodiode PDnk + 1 adjacent in the row direction. Further, the wiring SIGa is connected between other wirings extending in the row direction (for example, the wiring SIGa between the photodiode PD11 in the first row and the first column and the photodiode PD12 in the second column is the wiring Rxa of the reset signal line Rx). And the wiring T1a of the transfer control signal line T1).

In other words, the wiring SIGa is a removed portion that extends in the column direction and from which the inter-row portion is removed.
The wiring SIGa has a shape extending in the column direction and extending toward two adjacent photodiodes PD in the row direction at both ends (upper and lower ends), that is, in an “I” shape. The portion extending in the column direction is located in the central region between the photodiodes PDnk and PDnk + 1 adjacent in the column direction.

The wiring SIGa has a ground line VSSa between the photodiodes PD4k and PD4k + 1 located in the fourth row, which is the last row of the unit cell, and therefore, between the photodiodes PD4k and PD4k + 1 in the fourth row. (This portion can also be regarded as a removal portion.)
(Ii) Second wiring layer wiring (SIGb)
As shown in FIG. 4, the wiring SIGb of the signal line SIG is formed between the columns and extends between the photodiodes PD adjacent in the column direction (for example, between the photodiode PD11 and the photodiode PD21). It is formed in a state of extending in the column direction. In other words, between the photodiodes PD adjacent in the row direction is extended in the column direction, and there is no wiring in the intermediate region including the center of the photodiode, that is, a removal portion from which the conductive path is removed.

  In addition to the signal line SIG, the ground line VSS or the third power supply line VDD3 is also arranged between the columns. Here, the signal line SIG is adjacent to the row direction and the number of columns is increased. Is arranged on the photodiode PD side.

In the photodiodes PD4k, PD4k + 1, etc. in the fourth row, which is the last row in the unit cell, a removal portion is not formed, and a portion corresponding to an intermediate region including the center of the photodiodes PD4k, PD4k + 1, etc. in the fourth row ( In other rows, it is a portion that becomes a removal portion.) Is a protruding portion that protrudes in the row direction and on the opposite side to the other photodiode side adjacent in the direction in which the number of columns increases. This shape is the same as the protruding portion of the wiring T1a such as the transfer control signal line T1. Note that the position of the protruding portion is a central region between photodiodes adjacent in the row direction.
(Iii) Summary The wiring SIGa and the wiring SIGb are connected by vias, thereby forming one signal line SIG extending in the column direction. The via connection between the wiring SIGa and the wiring SIGb is the “I” shape of the wiring SIGa of the first wiring layer 105a and the portion (upper and lower ends) sandwiching the removed portion of the wiring SIGb of the second wiring layer 105b. It is performed at the end portion of the portion extending in the right (row) direction (on the other photodiode side adjacent in the row direction and increasing the number of columns).
(6) Ground line (VSS)
The ground line VSS is arranged in a state extending between the columns of the photodiodes PD arranged in a matrix in the column direction. Here, the photodiode PDnk (k is an odd natural number) located in the odd-numbered column with respect to PD11 is arranged on the right side (the side in the row direction where the number of columns increases).

  Specifically, it is arranged between the photodiode PDn1 in the first column and the photodiode PDn2 in the second column, between the photodiode PDn3 in the third column and the photodiode PDn4 in the fourth column, or the like. Needless to say, the wiring position of the ground line VSS is not limited to this example, and may be another position.

The ground line VSS is composed of the wiring VSSa of the first wiring layer 105a and the wiring VSSb of the second wiring layer 105b. The wiring VSSa of the first wiring layer 105a and the wiring VSSb of the second wiring layer 105b are connected via vias, for example. It is connected.
(I) First wiring layer wiring (VSSa)
As shown in FIG. 3, the wiring VSSa of the ground line VSS is formed in the unit cell corresponding to the row facing the other unit cell adjacent in the column direction, that is, the last row of each unit cell. . Here, it is formed between the photodiode PD41 in the fourth row in the unit cell and the photodiode PD42 adjacent to the photodiode PD41 on the side where the number of columns increases in the row direction (on the right side of the photodiode PD41). Has been.

The wiring VSSa has a shape extending in the column direction and extending toward the two adjacent photodiodes PD in the row direction at both ends (upper and lower ends), that is, in an “I” shape. The portion extending in the column direction is located in a central region between the photodiode PD4k and the photodiode PD4k + 1 (k is an odd natural number) adjacent in the column direction.
(Ii) Second wiring layer wiring (VSSb)
As shown in FIG. 4, the wiring VSSb of the ground line VSS is formed so as to extend between the columns along the column direction. The wiring VSSb is formed continuously in the column direction except for the portion (the fourth row of each unit cell) where the wiring VSSa of the first wiring layer 105a is formed.

  A signal line SIG is also arranged between the columns in addition to the ground line VSS. Here, the ground line VSS is a column on the side where the number of columns is smaller among the columns in which the ground line VSS is arranged. It is arranged in the place near.

  The wiring VSSb corresponds to a central region in the column direction of the photodiodes PD11, PD21, and PD31 in the photodiodes PD11, PD21, and PD31 in all other rows except the fourth row, which is the last row in the unit cell. The portion is in the row direction and has an overhanging portion projecting to the other photodiode (PD12, PD22, PD32) side adjacent to the side where the number of columns increases. This shape is the same as the protruding portion of the wiring T1a such as the transfer control signal line T1. Note that the position of the protruding portion is a central region between the photodiodes PD adjacent in the row direction.

The wiring VSSb has a removal portion in which the central region in the column direction of the photodiode PD4k is removed from the photodiode PD4k (k is an odd number) in the fourth row, which is the last row in the unit cell.
(Iii) Summary The wiring VSSa and the wiring VSSb described above are connected by vias, thereby forming one ground line VSS extending in the column direction. The vias of the wiring VSSa and the wiring VSSb are connected to the portion of the wiring VSSb sandwiching the removed portion (upper and lower ends) and the end of the portion extending in the row direction forming the “I” shape of the wiring VSSa. It is performed in the part (in the row direction and the side where the number of columns increases).
(7) Third power line (VDD3)
The third power supply line VDD3 is arranged in a state extending between the columns of photodiodes arranged in a matrix in the column direction. Here, the photodiode PDnk (k is an even natural number) located in the even-numbered column with respect to PD11 is arranged on the right side (the side in the row direction and the number of columns increases).

  Specifically, it is arranged between the photodiode PDn2 in the second row and the photodiode PDn3 in the third row, between the photodiode PDn4 in the fourth row and the photodiode PDn5 in the fifth row, and the like. Needless to say, the wiring position of the third power supply line VDD3 is not limited to this example, and may be another position.

The third power supply line VDD3 is composed of a wiring VDD3a in the first wiring layer and a wiring VDD3b in the second wiring layer, and the wiring VDD3a in the first wiring layer and the wiring VDDb in the second wiring layer are connected via, for example, vias. ing. Note that the third power supply line VDD3 is the same as the ground line VSS except for the formation location.
(I) First wiring layer wiring (VDD3a)
As shown in FIG. 3, the wiring VDD3a of the third power supply line VDD3 is formed in a unit cell corresponding to a row facing another unit cell adjacent in the column direction, that is, the last row of each unit cell. ing. Here, it is formed between the photodiode PD42 in the fourth row in the unit cell and the photodiode PD43 adjacent to the photodiode PD42 on the side where the number of columns increases in the row direction (on the right side of the photodiode PD42). Has been.

The wiring VDD3a has a shape extending in the column direction and extending toward two adjacent photodiodes PD in the row direction at both ends (upper and lower ends), that is, in an “I” shape. The portion extending in the column direction is located in a central region between the photodiode PD4k and the photodiode PD4k + 1 (k is an even natural number) adjacent in the column direction.
(Ii) Second wiring layer wiring (VDD3b)
As shown in FIG. 4, the wiring VDD3b of the third power supply line VDD3 is formed so as to extend between the columns along the column direction. The wiring VDD3b is formed continuously in the column direction except for the portion (the fourth row of each unit cell) where the wiring VDD3a of the first wiring layer 105a is formed.

  A signal line SIG is also arranged between the columns in addition to the third power supply line VDD3. Here, the third power supply line VDD3 is a column among the columns in which the third power supply line VDD3 is arranged. It is placed near the row with the smaller number.

  The wiring VDD3b corresponds to the central region in the column direction of each of the photodiodes PD12, PD22, and PD32 in the photodiodes PD12, PD22, and PD32 in all other rows except the fourth row, which is the last row in the unit cell. The portion is in the row direction and has an overhanging portion projecting to the other photodiode (PD13, PD23, PD33) side adjacent to the side where the number of columns increases. This shape is the same as the protruding portion of the wiring T1a such as the transfer control signal line T1. Note that the position of the protruding portion is a central region between the photodiodes PD adjacent in the row direction.

The wiring VDD3b has a removal portion in which the center region in the column direction of the photodiode PD4k is removed from the photodiode PD4k (k is an even number) in the fourth row, which is the last row in the unit cell.
(Iii) Summary The wiring VDD3a and the wiring VDD3b are connected by vias, thereby forming one third power supply line VDD3 extending in the column direction. Via connection between the wiring VDD3a and the wiring VDD3b is a portion of the wiring VDD3b sandwiching the removed portion (upper and lower ends) and an end of the portion extending in the row direction constituting the “I” shape of the wiring VDD3a This is performed in a portion (in the row direction and on the side where the number of columns decreases).
(8) Others The row direction wiring group and the column direction wiring group described above are electrically connected to the photodiodes PD and the like constituting each pixel, but dummy wirings that are not electrically connected are arranged. May be.

In the present embodiment, as shown in FIG. 4, the wiring DYb of the dummy wiring DY is arranged between the photodiode PD2k in the second row and the photodiode PD3k in the third row of each unit cell in the second wiring layer 105b. Has been. As shown in FIG. 4, the wiring DYb has an “H” shape, like the wirings T1b, T2b, T3b, and T4b of the transfer control signal lines T1, T2, T3, and T4.
5. Connection relationship between semiconductor substrate side and wiring (1) Transfer transistor (TG)
As shown in FIG. 1, the transfer transistor TG1 has a gate between the photodiode PD1k in the first row and the photodiode PD2k in the second row, and a contact C1 and a wiring T1a arranged in the first wiring layer 105a. Connected with. Note that the gate of the transfer transistor TG2 is also connected to the wiring T2a disposed in the first wiring layer 105a by the contact C1.

  The drains of the transfer transistors TG1 and TG2 are connected by the same diffusion layer 121 as the source of the reset transistor RS, and are connected without a metal wiring. Each drain is made of the same material as the gates of amplification transistors SF1 and SF2, which will be described later, and extends in both directions in the column direction (here, the vertical direction is two directions in which the number of rows increases or decreases). Connected with no metal wiring.

  For example, a shared contact C7 is used for connection between the drains of the transfer transistors TG1 and TG2 (the diffusion layer 121) and the polysilicon 123 of the amplification transistors SF1 and SF2.

  As shown in FIG. 1, the transfer transistor TG3 has a gate between the photodiode PD3k in the third row and the photodiode PD4k in the fourth row, and a contact C1 and a wiring T3a arranged in the first wiring layer 105a. Connected with. Note that the gate of the transfer transistor TG4 is also connected to the wiring T4a disposed in the first wiring layer 105a by the contact C1.

The drains (diffusion layers 125) of the transfer transistors TG3 and TG4 are made of the same material as the gates of the amplification transistors SF1 and SF2, and are in both directions in the column direction (here, the vertical direction and the two directions in which the number of rows increases or decreases). For example, it is connected to the polysilicon 123 extending in a shared contact C7 without a metal wiring.
(2) Amplification transistor (SF)
The drains of the amplifying transistors SF1 and SF2 are connected to the connecting portion of the second power supply line VDD2 disposed between the photodiode PD2k in the second row and the photodiode PD3k in the third row and disposed in the first wiring layer 105a with a contact C2. It is connected.

  Each source of the amplification transistors SF1 and SF2 is connected between the photodiode PD2k in the second row and the photodiode PD3k in the third row and connected to the wiring SIGa of the signal line SIG formed in the first wiring layer 105a through the contact C3. Has been.

  That is, the signal line SIG is disposed above the drains of the transfer transistors TG1, TG2, TG3, and TG4 and above the polysilicon wiring connecting the gates of the amplification transistors SF1 and SF2.

  Further, a signal line SIG is arranged above the diffusion layer connecting the drains of the transfer transistors TG1 and TG2 and the source of the reset transistor RS and above the drains of the transfer transistors TG3 and TG4.

In addition, the amplification transistors SF1 and SF2 use as a drain a diffusion layer formed between the gates of the amplification transistors SF1 and SF2. In other words, the amplification transistors SF1 and SF2 are arranged in parallel by sharing the drain diffusion layer.
(3) Reset transistor (RS)
The drain of the reset transistor RS is a first power supply disposed in the first wiring layer 105a between the photodiode PD4k in the fourth row and the photodiode PD1k in the first row of another unit cell adjacent in the column direction. The contact VDD is connected to the wiring VDD1a of the line VDD1.

The gate of the reset transistor RS is the fourth row of the last row of the photodiode PD1k in the first row and another unit cell (becomes the upper unit cell) adjacent in the column direction where the number of rows decreases. The photodiode PD4k is connected to the wiring Rxa of the reset signal line Rx disposed in the first wiring layer 105a through a contact C5.
(4) Ground line (VSS)
The ground line VSS is connected to a contact C6 disposed on the right side of the photodiode PD4k (k is an odd number) in the odd-numbered column in the fourth row.
(5) Others As shown in FIGS. 2 and 3, the second power supply line VDD2 intersects with the third power supply line VDD3, specifically, the photodiode PD2k (k is an even number in the second row even column). ) And the photodiode PD3k in the even-numbered column in the third row (k is an even number).

Thereby, the effect that the power supply from the second power supply line VDD2 of the source follower is stably performed can be obtained.
6). Cross-sectional structure The solid-state imaging device 101 employs the above-described wiring configuration, so that a line segment passing through the center of the upper and lower photodiodes PD (of photodiodes adjacent in the column direction as shown in FIGS. In the cross section at the line connecting the centers, one wiring can be arranged in the first wiring layer 105a and one wiring can be arranged in the second wiring layer 105b. In addition, in a cross section taken along a line passing through the center of the left and right photodiodes PD (a line connecting the centers of the photodiodes PD adjacent in the row direction), one wiring is connected to the first wiring layer 105a. One wiring can be arranged in each of the second wiring layers 105b. Thereby, the high sensitivity of the solid-state imaging device 101 can be realized. This will be specifically described below.
(1) Section a
(I) First Wiring Layer As shown in FIGS. 5 and 3, in the cross section passing through the centers of the photodiodes PD13 and PD14, the wiring in the first wiring layer 105a is only the wiring SIGa of the signal line SIG. Even in the cross section passing through the center of the photodiode PD4k in the fourth row, the wiring in the first wiring layer 105a is only one of the wiring VSSa of the ground line VSS and the wiring VDD3a of the third power supply line VDD3.
(Ii) Second Wiring Layer As shown in FIGS. 5 and 4, in the cross section passing through the centers of the photodiodes PD13 and PD14, the wiring in the second wiring layer 105b includes the wiring VDD3b of the third power supply line VDD3 and the ground line. Only one of the VSS wiring VSSb is provided.
(Iii) Others As shown in FIGS. 3 to 5, in the cross section passing through the centers of the photodiodes PD13 and PD14, the third power supply line VDD3 of the second wiring layer 105b is located above the wiring SIGa of the first wiring layer 105a. The wiring VDD3b or the ground line VSSb of the ground line VSS is located.

  In the photodiode PD other than the photodiodes PD13 and PD14, the second wiring layer 105b is disposed above the wiring VSSa of the ground line VSS or the wiring VDD3a of the third power supply line VDD3 of the first wiring layer 105a. Any of the wiring VDD3b of the third power supply line VDD3, the wiring VSSb of the ground line VSS, and the wiring SIGb of the signal line SIG is located.

That is, the wiring of the first wiring layer 105a and the wiring of the second wiring layer 105b overlap in plan view. Thereby, the space | interval of the wiring extended in a column direction, ie, a wiring opening diameter, can be enlarged.
(2) Section b
(I) First Wiring Layer As shown in FIGS. 6 and 3, in the cross section passing through the centers of the photodiodes PD34 and PD44, the wiring in the first wiring layer 105a is the wiring T3a of the transfer control signal line T3, the first power supply. Only one of the wirings VDD1a of the line VDD1 is provided. In the photodiode PD other than the photodiodes PD34 and PD44, the wirings in the first wiring layer 105a are the wirings T1a, T2a, T3a, T4a of the transfer control signal lines T1, T2, T3, T4, the first power source. Only one of the wiring VDD1a of the line VDD1 and the wiring VDD2a of the second power supply line VDD2 is provided.
(Ii) Second Wiring Layer As shown in FIGS. 6 and 4, in the cross section passing through the centers of the photodiodes PD34 and PD44, the wiring in the second wiring layer 105b is the wiring T4b of the transfer control signal line T4, the reset signal line Only one of the Rx lines Rxb is provided. In the photodiode PD other than the photodiodes PD34 and PD44, the wiring in the second wiring layer 105b includes the wirings T1b, T2b, T3b, T4b of the transfer control signal lines T1, T2, T3, T4, and the dummy wiring DY. Only one of the wiring DYb and the wiring Rxb of the reset signal line Rx is provided.
(Iii) Others As shown in FIGS. 3, 4 and 6, in the cross section passing through the centers of the photodiodes PD34 and PD44, the wiring VDD1a and the transfer control signal line T3 of the first power supply line VDD1 of the first wiring layer 105a. One of the wiring T4b of the transfer control signal line T4 and the wiring Rxb of the reset signal line Rx in the second wiring layer 105b is located above the wiring T3a.

  Also in the photodiodes PD other than the photodiodes PD34 and PD44, the wirings T1a, T2a, T3a, T4a of the transfer control signal lines T1, T2, T3, and T4 of the first wiring layer 105a, and the first power supply line VDD1. Above any of the wiring VDD1a and the wiring VDD2a of the second power supply line VDD2, the wirings T1b, T2b, T3b, T4b of the transfer control signal lines T1, T2, T3, T4, the wiring DYb of the dummy wiring DY, and the reset Only one of the wirings Rxb of the signal line Rx is located. That is, the wiring of the first wiring layer 105a and the wiring of the second wiring layer 105b overlap in plan view.

From the above, it is possible to increase the interval between wirings extending in the row direction, that is, the wiring opening diameter.
(3) For both cross sections a and b As described above, when the circular lens 111 is used in plan view, the distance between the wirings sandwiching the photodiode PD positioned below the lens 111 can be increased. In this configuration, the wiring is not positioned below the peripheral edge of each other. For this reason, the aperture ratio as the solid-state imaging device 101 can be increased. Further, the light condensed by the lens 111 (broken line shown in FIGS. 5 and 6) can be prevented from being blocked by the wiring of the first wiring layer 105b, and the sensitivity can be increased.
7). Summary (1) In the transfer control signal lines T1, T2, T3, and T4, the wirings T1a, T2a, T3a, and T4a in the first wiring layer 105a and the wirings T1b, T2b, T3b, and T4b in the second wiring layer 105b are the same. Because of the shape, the transfer control signal lines T1, T2, T3, and T4 can have the same transfer capability, and variations in transfer capability for each row can be reduced.
(2) The signal line SIG, the ground line VSS, and the third power supply line VDD3 included in the column direction wiring group are the wirings SIGa, VSSa, VDD3a in the first wiring layer 105a and the wirings SIGb, VSSb, VDD3b in the second wiring layer 105b. Since each has a similar shape, variation due to wiring between columns can be reduced.
(3) The signal line SIG is arranged above the diffusion layer 121 made of the same material as the drains of the transfer transistors TG1, TG2, TG3, and TG4, and above the polysilicon 123 connected to the gates of the amplification transistors SF1 and SF2. Therefore, when the charge read operation is performed, the potential of the signal line SIG varies following the potential change of the charge storage portion FD by the amplification transistors SF1 and SF2. Thereby, the parasitic capacitance Cfd of the charge storage unit FD apparently shown in FIG. 2 is reduced, and a large potential change of the charge storage unit FD can be obtained, resulting in an effect of improving the S / N. It is done.
(4) The amplification transistors SF1 and SF2 share a drain diffusion layer and are arranged in parallel connection. This facilitates the arrangement of the second power supply line VDD2 arranged in the row direction between the transfer transistors TG2 and TG3. Further, the configuration of the peripheral diffusion layer as seen from each photodiode PD can be made uniform.
(5) The third power supply line VDD3 is arranged so as to skip one column. That is, the third power supply line VDD3 is arranged in one of 22 columns adjacent in the row direction. A ground line VSS is arranged in the vacant row.

  Specifically, with reference to the photodiode PD11, the power supply line VDD3 is on the right side of the even number column (the side on which the number of rows increases), and the ground line VSS is on the right side of the odd number column (the side on which the number of rows increases). )).

  On the ground line VSS side, in the fourth row which is the last row (in particular, between the transfer transistor TG4 and the reset transistor RS), the diffusion layer of the contact C6 to which the ground line VSS and the semiconductor substrate 103 are connected is provided. Is formed.

  The third power supply line VDD3 has a contact C6 between the transfer transistor TG4 and the reset transistor RS in the column in which the third power supply line VDD3 is arranged (that is, in the region where the diffusion layer of the substrate contact C6 is arranged). A dummy diffusion layer 127 similar to that shown in FIG. The dummy diffusion layer 127 is formed by implantation similar to the source and drain of the reset transistor RS, but does not have a connection portion (contact).

Thereby, the difference in layout due to the presence or absence of the contact (C6) due to the difference in the columns can be eliminated, and the variation can be suppressed.
(6) For example, when the reset transistor RS is connected to the power supply line of the amplification transistor SF, it is necessary to turn on / off the drain of the amplification transistor SF. The drain of the column reset transistor RS is connected to the first power line VDD1. For this reason, it is not necessary to turn on / off the drain of the amplification transistor SF, and low power consumption can be realized.
(7) Between each column, a combination of the signal line SIG and the ground line VSS and a combination of the signal line SIG and the third power supply line VDD3 are arranged. Since the ground line VSS and the third power supply line VDD3 have the same shape, as a result, wiring is performed in the same shape between the columns. Thereby, the photodiodes PD can be arranged at an equal pitch in the row direction. Further, the current directions of the amplification transistors SF1 and SF2 can be made the same. As a result, differences in layout and the like are eliminated, and a configuration that is resistant to variations can be obtained.
(8) Since the transfer control signal lines T1, T2, T3, and T4 are interchanged between the first wiring layer 105a and the second wiring layer 105b for each column, that is, periodically, variation in layout, noise generation, etc. Can be adjusted equally.
(9) Since the second power supply line VDD2 which is one of the row direction wiring groups is connected to the third power supply line VDD3 which is one of the column direction wiring groups via, for example, vias, the second power supply line VDD2 The output signal can be stabilized.
(10) The ground line VSS is connected via a contact C6 formed on the semiconductor substrate 103. Thereby, the substrate potential can be stabilized. Further, since the contact C6 is formed for each unit cell in the column direction, a stable substrate potential can be obtained in the entire range in the imaging region of the semiconductor substrate 103.
(11) Since the second power supply line VDD2 is connected to the shared diffusion layer (drain) of the amplification transistors SF1 and SF2, electrical variation between the amplification transistors SF1 and SF2 is reduced, and the amplification transistors SF1 and SF2 The power of can be strengthened. Further, the number of wirings can be reduced, and the degree of freedom of wiring layout can be increased. In addition, since the wiring VDD2a of the first wiring layer 105a of the second power supply line VDD2 is disposed on the above diffusion layer and connected to the diffusion layer via the contact C2, it can be efficiently connected in a space-saving manner. Therefore, the degree of freedom in layout can be increased.
(12) The amplifying transistors SF1 and SF2 have a shared diffusion layer, and a virtual line passing between the photodiode PD2k in the second row corresponding to the center of the unit cell and the photodiode PD3k in the third row. , They are arranged in a symmetrical layout in the vertical direction (in the column direction, the side where the number of rows decreases and the side where the number of rows increases). For this reason, it is possible to eliminate variations in the layout between the upper and lower sides, and to ensure a uniform layout as a whole.
(13) The first power supply line VDD1, which is a power supply line to the reset transistor RS, is formed in the wiring layer 105 and is connected to each reset transistor RS through, for example, vias. can do.
(14) In the reset transistor RS and the transfer transistor TG, the source of the reset transistor RS and the drain of the transfer transistor TG are connected by a diffusion layer. Thereby, it is not necessary to use the metal wiring in the wiring layer 105, the number of wirings can be reduced, and the degree of freedom of layout can be increased by reducing the number of wirings.
(15) The two transfer transistors TG (TG1 and TG2 or TG3 and TG4) have their drains connected by polysilicon (polysilicon wiring), and the polysilicon includes the gate of the amplification transistor SF. Yes (composing the gate). Thereby, it is not necessary to use the metal wiring in the wiring layer 105, the number of wirings can be reduced, and the degree of freedom of layout can be increased by reducing the number of wirings.
(16) Unit cells composed of the photodiode PD, the transfer transistor TG, the reset transistor RS, and the amplification transistor SF are respectively arranged in the column and row directions. That is, the arrangement relationship is not reversed for each column. Can be ensured.
8). Comparative Example Here, a sensor of 14 [M] is used as an example in a 1 / 2.33 type optical system often used in a digital still camera, and the aperture diameters are compared.

  In this case, the pixel size is 1.4 [μm]. The wiring width of the first wiring layer 105a and the second wiring layer 105b is 100 [nm], the distance between two wirings arranged between the pixels is 100 [nm], and the distance between the waveguide 107 and the wiring is 100 [nm]. nm].

When there are two wires in the second wiring layer (105b), the wire opening diameter (the inner dimension between the wires) is 1.1 [μm □], and the waveguide diameter is 0.9 [μm □]. .
In the first embodiment, since the wirings provided in the first wiring layer 105a and the second wiring layer 105b are one by one, the wiring opening diameter is 1.3 [μm □], the waveguide diameter is 1.. 1 [μm □].

Comparing these, in the solid-state imaging device 101 according to the first embodiment, the wiring opening diameter is increased by 18 [%] (40 [%] in area) compared to the solid-state imaging device according to the conventional example. The waveguide diameter is increased by 22 [%] (49 [%] in area), and the effect is great.
<Second Embodiment>
In the solid-state imaging device according to the second embodiment, two wires are arranged in the first wiring layer in a cross section of a virtual plane that passes through the center of the photodiodes adjacent in the row direction and extends in the row direction. In addition, two wires are arranged in the first wiring layer in a cross section of a virtual plane that passes through the center of the photodiodes adjacent in the column direction and extends in the column direction.

  That is, in the first wiring layer 205a, two wirings extending in the row direction, which is a second direction orthogonal to the first direction, between pixels adjacent in the column direction, which is the first direction (here, Two transfer control signal lines 2T1 and 2T2, two transfer control signal lines 2T3 and 2T4, and a first power supply line 2VDD1 and a reset signal line 2Rx) are disposed, and the second wiring layer 205b includes Two wirings extending in the column direction, which is the first direction, between pixels adjacent in the row direction, which is the second direction (here, two of the signal line 2SIG and the ground line 2VSS, the signal line 2SIG, and the third line) And two wirings of the second wiring layer 205b enter the first wiring layer 205a in the central region of the pixels adjacent in the column direction which is the first direction. It is out.

  With the configuration as described above, the wiring around the photodiode is only the first wiring layer, and the wiring opening on the photodiode can be enlarged particularly for light from an oblique direction, thereby realizing high sensitivity. . Further, higher sensitivity can be realized by tapering the waveguide formed in the wiring layer.

Details of the second embodiment will be described below with reference to FIGS.
FIG. 7 is a layout diagram showing the first wiring layer in addition to FIG. 1 and vias connecting the first wiring layer and the second wiring layer. FIG. 8 is a layout diagram showing the second wiring layer in addition to FIG. is there.

9 is a cross-sectional view taken along the broken line c in FIG. 8, and FIG. 10 is a cross-sectional view taken along the broken line d in FIG.
As in the first embodiment, the solid-state imaging device 201 according to the second embodiment includes a semiconductor substrate 203, a wiring layer 205, a waveguide 207, a color filter 209, as shown in FIGS. A lens 211 is provided, and the wiring layer 205 includes a first wiring layer 205a and a second wiring layer 205b. In this embodiment mode, the waveguide 207 in the cross section in the row direction (FIG. 9) and the cross section in the column direction (FIG. 10) is thickened as it approaches the color filter 209 side from the semiconductor substrate 203 side.

The semiconductor substrate 203 of the solid-state imaging device 201 has the same configuration as the semiconductor substrate 103 of the solid-state imaging device 101 according to the first embodiment, and the wiring layer 205 formed on the imaging region of the semiconductor substrate 203 is different. That is, the layout showing the diffusion layers, polysilicon, and contacts in the unit cell is the same as that in FIG. 1, and the number of wirings of the first wiring layer 205a and the second wiring layer 205b formed thereabove are different. For this reason, the wiring layer 205 will be described below.
1. Wiring The wirings in the second embodiment, that is, the types of wirings included in the row direction wiring group and the column direction wiring group, are included in the row direction wiring group and the column direction wiring group according to the first embodiment. It is the same as the type of wiring to be used.

  That is, as shown in FIG. 7 and FIG. 8, the row direction wiring group includes the first power supply line 2VDD1, the reset signal line 2Rx, the transfer control signal lines 2T1, 2T2, 2T3, 2T4, and the second power supply line 2VDD2. The directional wiring group includes a ground line 2VSS, a signal line 2SIG, and a third power supply line 2VDD3.

In addition, the arrangement positions of the row direction wiring group and the column direction wiring group according to the second embodiment are the same as the arrangement positions in the first embodiment, but different from the first embodiment. Also good.
(1) Transfer control signal line (2T)
Similarly to the first embodiment, the transfer control signal lines 2T1, 2T2, 2T3, and 2T4 are arranged in a state extending between the rows of photodiodes 2PD arranged in a matrix in the row direction. Note that the wiring positions of the transfer control signal lines 2T1, 2T2, 2T3, and 2T4 are the same as those of the transfer control signal lines T1, T2, T3, and T4 of the first embodiment as described above.

  The transfer control signal line 2T1 includes the wiring 2T1a of the first wiring layer 205a, and the second wiring layer 205b has no wiring. Similarly, the transfer control signal line 2T2 includes the wiring 2T2a of the first wiring layer 205a, and the second wiring layer 205b has no wiring.

  The transfer control signal line 2T3 includes the wiring 2T3a of the first wiring layer 205a, and the second wiring layer 205b has no wiring. Similarly, the transfer control signal line 2T4 includes the wiring 2T4a of the first wiring layer 205a, and the second wiring layer 205b has no wiring.

  Note that the transfer control signal line 2T1 and the transfer control signal line 2T3 have the same configuration only in the arrangement location, and the transfer control signal line 2T2 and the transfer control signal line 2T4 have the same configuration only in the arrangement location. is doing. Therefore, the transfer control signal lines 2T1 and 2T2 will be described below.

  The wiring 2T1a and the wiring 2T2a extend in the row direction between the photodiodes 2PD1k and 2PD2k adjacent to each other in the column direction as a pair. The wiring 2T1a and the wiring 2T2a have a symmetrical shape in the column direction with respect to a virtual line extending in the row direction at the center between the photodiode 2PD1k and the photodiode 2PD2k. That is, it has a line-symmetric shape with the virtual line as the axis of symmetry.

The wiring 2T1a and the wiring 2T2a have a projecting portion that protrudes so as to approach each other between the photodiode 2PD1k and the photodiode 2PD2k adjacent in the column direction.
(2) Reset signal line (2Rx) and first power supply line (2VDD1)
As shown in FIG. 7, the reset signal line 2Rx is arranged in a state extending between the rows of photodiodes 2PD arranged in a matrix in the row direction. Here, it is arranged on the upper end side of the photodiode 2PD1k arranged in the first row in each unit cell. That is, the reset signal line 2Rx is arranged on the other unit cell side adjacent to the side where the number of rows increases in the column direction. The reset signal line 2Rx includes the wiring 2Rxa of the first wiring layer 205a.

  The first power supply line 2VDD1 is arranged in a state extending between the rows of the photodiodes 2PD arranged in a matrix in the row direction. Here, it is arranged on the lower end side of the photodiode 2PD4k arranged in the fourth row which is the last row in each unit cell. That is, the first power supply line 2VDD1 is arranged on the other unit cell side adjacent to the side where the number of rows increases in the column direction. The first power supply line 2VDD1 includes the wiring 2VDD1a of the first wiring layer.

The wiring 2Rxa of the reset signal line 2Rx and the wiring 2VDD1a of the first power supply line 2VDD1 have the same configuration as the transfer control signal line 2T1 and the transfer control signal line 2T2.
That is, the wiring 2Rxa and the wiring 2VDD1a are arranged between the photodiode 2PD4k adjacent in the column direction and the photodiode 2PD1k in the first row of another unit cell adjacent to the photodiode 2PD4k on the side where the number of rows increases. The pair extends in the row direction.

  The wiring 2Rxa and the wiring 2VDD1a are symmetrical in the column direction with respect to a virtual line extending in the row direction at the center of the photodiode 2PD4k and the photodiode 2PD1k. That is, it has a line-symmetric shape with the virtual line as the axis of symmetry.

The wiring 2Rxa and the wiring 2VDD1a have a protruding portion that protrudes so as to approach each other between the photodiode 2PD4k and the photodiode 2PD1k adjacent in the column direction.
(3) Second power line (2VDD2)
The second power supply line 2VDD2 is arranged in a state extending between the rows of the photodiodes 2PD arranged in a matrix in the row direction. Here, it is arranged between the photodiodes 2PD2k in the second row and the photodiodes 2PD3k in the third row that exist at the center position in each unit cell. That is, the second power supply line 2VDD2 is arranged between the photodiode 2PD2k and the photodiode 2PD3k facing the boundary portion where the four photodiodes 2PD constituting the unit cell are vertically divided into two.

  The second power supply line 2VDD2 includes the wiring 2VDD2a of the first wiring layer 205a. As shown in FIG. 7, the wiring 2VDD2a has a shape that combines the transfer control signal line 2T1 and the transfer control signal line 2T2.

  That is, the wiring 2VDD2a includes a pair of row direction extending portions extending in the row direction and a connecting portion that connects the pair of row direction extending portions at a substantially center between the photodiode 2PD2k and the photodiode 2PD2k + 1 adjacent in the row direction. And have. The connecting portion extends in the column direction.

  The pair of extending portions in the row direction has a symmetrical shape in the column direction with respect to a virtual line extending in the row direction at the center between the photodiodes 2PD2k and 2PD3k. That is, it has a line-symmetric shape with the virtual line as the axis of symmetry.

The pair of row direction extending portions have the same shape as the transfer control signal lines 2T1 and 2T2, the first power supply line 2VDD1, and the reset signal line 2Rx. The pair of row-direction extending portions have projecting portions that protrude so as to approach each other between the photodiodes 2PD adjacent in the column direction.
(4) Signal line (2SIG)
The signal line 2SIG is arranged in a state extending between the columns of photodiodes arranged in a matrix in the column direction. Here, the signal line 2SIG of the photodiode 2PDnk in the k-th column is arranged between the photodiode line 2PDnk + 1 in the (k + 1) th column (in this example, the signal line 2SIG is on the right side of each column, but on the left side of each column). May be.)

As shown in FIGS. 7 and 8, the signal line 2SIG includes a wiring 2SIGa of the first wiring layer 205a and a wiring 2SIGb of the second wiring layer 205b, and the wiring 2SIGa and the second wiring layer 205b of the first wiring layer 205a. The wiring 2SIGb is connected via a via, for example.
(I) First wiring layer wiring (2SIGa)
As shown in FIG. 7, the wiring SIGa of the signal line 2SIG is formed between the photodiodes 2PD adjacent in the row direction (for example, between the photodiode 2PD11 and the photodiode 2PD12).

  The wiring 2SIGa is between other wirings included in the row direction wiring group (for example, in the photodiode 2PD21 in the second row, between the wiring 2T2a of the transfer control signal line 2T2 and the wiring 2VDD2a of the second power supply line 2VDD2). ) In an independent state. That is, the wiring 2SIGa exists only between the photodiodes 2PD adjacent in the row direction.

The wiring 2SIGa is connected between the photodiodes 2PD2k in the second row and the photodiodes 2PD3k in the third row by sorting and contact ("C3" in FIG. 1) of the amplification transistors 2SF1 and SF2. It has a connecting portion protruding to the wiring 2VSSa side of a later-described ground line 2VSS.
(Ii) Second wiring layer wiring (2SIGb)
As shown in FIG. 8, the wiring 2SIGb of the signal line 2SIG is formed between the columns, and extends in the column direction beyond the photodiodes 2PD adjacent in the column direction. That is, the wiring 2SIGb has a shape extending in the column direction and having a removal portion from which the central region in the column direction of each photodiode 2PD is removed.
(Iii) Summary The wiring 2SIGa and the wiring 2SIGb are connected by vias, thereby forming one signal line 2SIG extending in the column direction. Via connection between the wiring 2SIGa and the wiring 2SIGb is performed at a portion (upper and lower ends) of the wiring 2SIGb sandwiching the removed portion and an end portion in the column direction of the wiring 2SIGa.

As a result, the signal line 2SIG arranged in the column direction is switched to the second wiring layer 205b side where it intersects with the wiring included in the row direction wiring group arranged in the first wiring layer 205a.
(5) Ground line (2VSS)
The ground line 2VSS is arranged in a state extending between the columns of the photodiodes 2PD arranged in a matrix in the column direction. Here, it is arranged on the right side (the side on which the number of columns increases) corresponding to odd columns with 2PD11 as a reference. Specifically, it is arranged between the photodiode 2PDn1 in the first column and the photodiode 2PDn2 in the second column, or between the photodiode 2PDn3 in the third column and the photodiode 2PDn4 in the fourth column.

The ground line 2VSS is composed of the wiring 2VSSa of the first wiring layer 205a and the wiring 2VSSb of the second wiring layer 205b. The wiring 2VSSa of the first wiring layer 205a and the wiring 2VSSB of the second wiring layer 205b are, for example, via vias. It is connected. The ground line 2VSS is arranged between each column in a pair with the signal line 2SIG.
(I) First wiring layer wiring (2VSSa)
As shown in FIG. 7, the wiring 2VSSa of the ground line 2VSS is formed between the photodiodes 2PD adjacent in the row direction (for example, between the photodiode 2PD11 and the photodiode 2PD12).

  The wiring 2VSSa is between other wirings included in the row direction wiring group (for example, between the wiring 2T2a of the transfer control signal line 2T2 and the wiring 2VDD2a of the second power supply line 2VDD2 in the photodiode 2PD21 in the second row). ) In an independent state. That is, the wiring 2VSSa exists only between the photodiodes 2PD adjacent in the row direction. The wiring 2VSSa is formed in parallel with the wiring 2SIGa of the signal line 2SIG so as to form a pair.

Note that the wiring 2VSSa arranged between the photodiodes 2PD in the fourth row, which is the last row of each unit cell (for example, between 2PD4k and 2PD4k + 1), is, as shown in FIG. Are connected to the diffusion layer via the contact (C6). For this reason, the wiring 2VSSa has a connection portion protruding to the wiring 2SIGa side of the signal line 2SIG.
(Ii) Wiring of the second wiring layer (2VSSb)
As shown in FIG. 8, the wiring 2VSSb of the ground line 2VSS is formed between the columns, and extends in the column direction across the photodiodes 2PD adjacent in the column direction. That is, the wiring 2VSSb has a shape extending in the column direction and having a removal portion from which the central region in the column direction of each photodiode 2PD is removed.
(Iii) Summary The wiring 2VSSa and the wiring 2VSSb are connected by vias, thereby forming one ground line 2VSS extending in the column direction. Via connection between the wiring 2 VSSa and the wiring 2 VSSb is performed at a portion (upper and lower ends) of the wiring 2 VSSb sandwiching the removed portion and an end portion in the column direction of the wiring 2 VSSa.

As a result, the ground line 2VSS arranged in the column direction is switched to the second wiring layer 205b at the intersection of the wirings included in the row-direction wiring group arranged in the first wiring layer 205a.
(6) Third power line (2VDD3)
The third power supply line 2VDD3 is arranged in a state extending between the columns of the photodiodes 2PD arranged in a matrix in the column direction. Here, with 2PD11 as a reference, it is arranged on the right side (the side on which the number of rows increases) corresponding to even columns. Specifically, it is arranged between the first row photodiode 2PDn1 and the second row photodiode 2PDn1, and between the third row photodiode 2PDn3 and the fourth row photodiode 2PDn4.

  The third power supply line 2VDD3 includes the wiring 2VDD3a of the first wiring layer 205a and the wiring 2VDD3b of the second wiring layer 205b. The wiring 2VDD3a of the first wiring layer 205a and the wiring 2VDD3b of the second wiring layer 205b include, for example, vias. Connected through. As a result, the third power supply line 2VDD3 arranged in the column direction is switched to the second wiring layer 205b where it intersects with the wiring included in the row direction wiring group arranged in the first wiring layer 205a.

The ground line 2VDD3 is paired with the signal line 2SIG and arranged between predetermined columns. The third power supply line 2VDD3 is the same as the ground line 2VSS except for the formation location.
4). Cross-sectional structure The solid-state imaging device 201 employs the above-described configuration, so that a line segment passing through the center of the upper and lower photodiodes 2PD as shown in FIGS. 9 and 10 In the cross-section in FIG. 2, two wirings can be arranged in the first wiring layer 205 a and zero wiring can be arranged in the second wiring layer 205 b.

  Further, in the cross section taken along the line segment passing through the center of the left and right photodiodes PD (the line segment connecting the centers of the photodiodes PD adjacent in the row direction), two wires are connected to the first wiring layer 205a, the second The wiring layer 205b can be arranged with zero wiring.

Thereby, high sensitivity can be realized. This will be specifically described below.
(1) Section c
(I) First Wiring Layer As shown in FIGS. 9 and 7, in the cross section passing through the centers of the photodiodes 2PD13 and 2PD14, the wiring in the first wiring layer 205a is the wiring 2SIGa of the signal line 2SIG and the wiring of the ground line 2VSS. Two lines of 2VSSa, or two lines of wiring 2SIGa of the signal line 2SIG and wiring 2VSS3a of the third power supply line 2VSS3.
(Ii) Second Wiring Layer As shown in FIGS. 9 and 8, in the cross section passing through the centers of the photodiodes 2PD13 and 2PD14, the signal line is connected to the removed portion of the wiring 2SIGb of the signal line 2SIG and the wiring 2VSSb of the ground line 2VSS. In order to correspond to the removed portions of the 2SIG wiring 2SIGb and the wiring 2VDD3b of the third power supply line 2VDD3, the number of wirings of the second wiring layer 205b in the cross section is zero.
(2) Section d
(I) First Wiring Layer As shown in FIGS. 10 and 7, in the cross section passing through the centers of the photodiodes 2PD34 and 2PD44, the wiring in the first wiring layer 205a is the wiring 2T1a and 2T2a of the transfer control signal lines 2T1 and 2T2. (Not shown in FIG. 10), any of the wirings 2T3a and 2T4a of the transfer control signal lines 2T3 and 2T4, the wiring 2VDD1a of the first power supply line 2VDD1, the wiring 2Rxa of the reset signal line 2Rx, and the wiring 2VDD2a of the second power supply line 2VDD2 The number of wirings in the first wiring layer 205a is two.
(Ii) Second Wiring Layer As shown in FIGS. 10 and 8, in the cross section passing through the centers of the photodiodes 2PD34 and 2PD44, the number of wirings in the second wiring layer 205b is zero.
(3) For both cross sections c and d In the second wiring layer 205b, the number of wirings in the cross section passing through the centers of the plurality of photodiodes 2PD is zero, so that the influence of the wiring of the second wiring layer 205b is eliminated, and the opening The rate can be increased. In particular, the aperture ratio on the photodiode 2PD can be increased with respect to light from an oblique direction.

Further, when the circular lens 211 is used, the diameter of the lens 211 can be increased because there is no possibility of being blocked by the wiring of the first wiring layer 205a.
In the second wiring layer 205a, there are two wirings in a cross section passing through the centers of the plurality of photodiodes 2PD. Since the light collected by the lens 211 is collected at the center of the photodiode 2PD, even if there are two wirings between the photodiodes 2PD in the first wiring layer 205a, as shown in FIGS. In addition, there is no possibility that the light condensed by the lens 211 and directed toward the center of the photodiode 2PD (broken line in the figure) is blocked by the wiring of the first wiring layer 205a, and the sensitivity can be increased.

  From the above, even if there are two wirings in the second wiring layer 205b, the light collected by the lens 211 and directed to the center of the photodiode 2PD is not shielded, and as a result, on the photodiode 2PD. The aperture ratio can be increased.

Further, the cross-sectional shape of the waveguide 207 is made thicker as it approaches the color filter 209 side from the semiconductor substrate 203 side. For this reason, light that has passed through the color filter 209 can be guided to the waveguide 207 more efficiently, and optical characteristics without color mixing can be realized.
<Third Embodiment>
In the solid-state imaging device according to the third embodiment, two wires are arranged in the first wiring layer in a cross section at a virtual plane that passes through the center of the photodiodes adjacent in the row direction and extends in the row direction. Further, one wiring is arranged in the first wiring layer and one wiring is arranged in the second wiring layer in a cross section at a virtual plane extending through the center of the photodiodes adjacent in the column direction in the column direction.

  That is, in the first wiring layer 305a, two wirings extending in the row direction, which is a second direction orthogonal to the first direction, between pixels adjacent to each other in the column direction, which is the first direction (here, Two transfer control signal lines 3T1 and 3T2, two transfer control signal lines 3T3 and 3T4, and two power supply lines 3VDD1 and a reset signal line 3Rx.), And the second wiring layer 305b includes Two wirings extending in the column direction, which is the first direction, between pixels adjacent in the row direction, which is the second direction (here, two of the signal line 3SIG and the ground line 3VSS, the signal line 3SIG and the third line) Power supply line 3VDD3), and the two wirings of the second wiring layer 305b enter the first wiring layer 305a in the central region of the pixel adjacent in the column direction which is the first direction. The two wirings of the first wiring layer 305a One (here, one of the transfer control signal lines 3T1 and 3T2, one of the transfer control signal lines 3T3 and 3T4, and two of the first power supply line 3VDD1 and the reset signal line 3Rx) Among these, the reset signal line 4Rx) enters the second wiring layer 305b in the central region of the pixel adjacent in the row direction, which is the second direction.

  With the above configuration, with respect to the column direction, there is one wiring between the rows in the first wiring layer and one wiring in the second wiring layer, so that the wiring opening on the photodiode between the rows is expanded. And high sensitivity can be realized. Similarly, since the waveguide diameter can be enlarged, higher sensitivity can be realized.

  With respect to the row direction, the wiring between the columns is only the first wiring layer, and the wiring opening on the photodiode can be enlarged particularly for light from an oblique direction, and high sensitivity can be realized. Further, higher sensitivity can be realized by tapering the waveguide shape.

The details of the third embodiment will be described below with reference to FIGS.
FIG. 11 is a layout diagram showing the first wiring layer and vias connecting the first wiring layer and the second wiring layer in addition to FIG. 1, and FIG. 12 is a layout diagram showing the second wiring layer in addition to FIG. is there.

13 is a sectional view taken along the broken line e in FIG. 12, and FIG. 14 is a sectional view taken along the broken line f in FIG.
As in the first embodiment, a solid-state imaging device 301 according to the third embodiment includes a semiconductor substrate 303, a wiring layer 305, a waveguide 307, a color filter 309, as shown in FIGS. The wiring layer 305 includes a first wiring layer 305a and a second wiring layer 305b. In this embodiment, the waveguide 307 in the cross section in the row direction (FIG. 13) has a shape that becomes thicker as it approaches the color filter 309 side from the semiconductor substrate 303 side.

  The semiconductor substrate 303 of the solid-state imaging device 301 has the same configuration as the semiconductor substrate 103 of the solid-state imaging device 101 according to the first embodiment, and the wiring layer 305 formed on the imaging region of the semiconductor substrate 303 is different. That is, the layout showing the diffusion layers, polysilicon, and contacts in the unit cell is the same as that in FIG. 1, and the number of wirings of the first wiring layer 305a and the second wiring layer 305b formed thereabove are different.

For this reason, the wiring layer 305 will be described below.
1. Wiring The wirings in the third embodiment, that is, the types of wirings included in the row direction wiring group and the column direction wiring group, are included in the row direction wiring group and the column direction wiring group according to the first embodiment. It is the same as the type of wiring to be used.

  That is, as shown in FIG. 11 and FIG. 12, the row direction wiring group includes the first power supply line 3VDD1, the reset signal line 3Rx, the transfer control signal lines 3T1, 3T2, 3T3, 3T4, and the second power supply line 3VDD2. The directional wiring group includes a ground line 3VSS, a signal line 3SIG, and a third power supply line 3VDD3.

In addition, the arrangement positions of the row-direction wiring group and the column-direction wiring group according to the third embodiment are the same as those in the first embodiment, but, of course, are different from those in the first and second embodiments. Anyway.
(1) Transfer control signal line (3T)
Similarly to the first embodiment, the transfer control signal lines 3T1, 3T2, 3T3, and 3T4 are arranged in a state of extending in the row direction between the rows of photodiodes 3PD arranged in a matrix.

The wiring positions and configurations of the transfer control signal lines 3T1, 3T2, 3T3, and 3T4 are the same as those of the transfer control signal lines T1, T2, T3, and T4 in the first embodiment described above.
The transfer control signal lines 3T1 and 3T2 extend in the row direction between the first row of photodiodes 3PD1k and the second row of photodiodes 3PD2k in each unit cell. The transfer control signal lines 3T3 and 3T4 extend in the row direction between the photodiodes 3PD3k in the third row and the photodiodes 3PD4k in the fourth row in each unit cell.

  The transfer control signal line 3T1 includes the wiring 3T1a of the first wiring layer 305a having the same configuration as that of the wiring T1a of the first wiring layer 105a described in the first embodiment, and the second described in the first embodiment. It consists of the wiring 3T1b of the second wiring layer 305b having the same configuration as the wiring T1b of the wiring layer 105b.

  The transfer control signal line 3T2 includes the wiring 3T2a of the first wiring layer 305a that has the same configuration as the wiring T2a of the first wiring layer 105a described in the first embodiment, and the second described in the first embodiment. It consists of the wiring 3T2b of the second wiring layer 305b having the same configuration as the wiring T2b of the wiring layer 105b.

  The transfer control signal line 3T3 includes the wiring 3T3a of the first wiring layer 305a that has the same configuration as the wiring T3a of the first wiring layer 105a described in the first embodiment, and the second described in the first embodiment. It consists of the wiring 3T3b of the second wiring layer 305b having the same configuration as the wiring T3b of the wiring layer 105b.

  The transfer control signal line 3T4 includes the wiring 3T4a of the first wiring layer 305a having the same configuration as the wiring T4a of the first wiring layer 105a described in the first embodiment, and the second described in the first embodiment. It consists of the wiring 3T4b of the second wiring layer 305b having the same configuration as the wiring T4b of the wiring layer 105b.

Also, the connection between the wiring 3T1a and the wiring 3T1b in the transfer control signal line 3T1, the connection between the wiring 3T2a and the wiring 3T2b in the transfer control signal line 3T2, the connection between the wiring 3T3a and the wiring 3T3b in the transfer control signal line 3T3, and the transfer control signal The connection between the wiring 3T4a and the wiring 3T4b in the line 3T4 is performed at the same connection location via the via as in the first embodiment.
(2) Reset signal line (3Rx)
The reset signal lines 3Rx are arranged in a state extending between the rows of photodiodes 3PD arranged in a matrix in the row direction, and the wiring positions thereof are the same as the reset signal lines Rx of the first embodiment.

  The reset signal line 3Rx includes the wiring 3Rxa of the first wiring layer 305a having the same configuration as the wiring Rxa of the first wiring layer 105a of the reset signal line Rx of the first embodiment, and the reset signal of the first embodiment. The wiring Rxb includes the wiring 3Rxb of the second wiring layer 305b having the same configuration as the wiring Rxb of the second wiring layer 105b of the line Rx.

The connection between the wiring 3Rxa and the wiring 3Rxb in the reset signal line 3Rx is performed at the same connection location via a via as in the first embodiment.
(3) First power line (3VDD1)
The first power supply line 3VDD1 is arranged in a state extending between the rows of the photodiodes 3PD arranged in a matrix in the row direction, and the wiring position thereof is the same as the first power supply line VDD1 of the first embodiment.

The first power supply line 3VDD1 includes the wiring 3VDD1a of the first wiring layer 305a having the same configuration as the wiring VDD1a of the first wiring layer 105a of the first power supply line VDD1 of the first embodiment. Note that the first power supply line 3VDD1 has no wiring in the second wiring layer 305b.
(4) Second power line (3VDD2)
The second power supply line 3VDD2 is arranged in a state extending between the rows of the photodiodes 3PD arranged in a matrix in the row direction, and the wiring position thereof is the same as the second power supply line VDD2 of the first embodiment.

The second power supply line 3VDD2 includes the wiring 3VDD2a of the first wiring layer 305a having the same configuration as the wiring VDD2a of the first wiring layer 105a of the second power supply line VDD2 of the first embodiment. Note that the first power supply line 3VDD1 has no wiring in the second wiring layer 305b.
(5) Signal line (3SIG)
The signal line 3SIG is arranged in a state extending between the columns of the photodiodes 3PD arranged in a matrix in the column direction, and the wiring position thereof is the same as that of the signal line 2SIG of the second embodiment.

  As shown in FIGS. 11 and 12, the signal line 3SIG includes the wiring 3SIGa of the first wiring layer 305a having the same configuration as the wiring 2SIGa of the first wiring layer 205a of the signal line 2SIG of the second embodiment, And the wiring 3SIGb of the second wiring layer 305b having the same configuration as the wiring 2SIGb of the second wiring layer 205b of the signal line 2SIG of the second embodiment.

In the signal line 3SIG, the wiring 3SIGa of the first wiring layer 305a and the wiring 3SIGb of the second wiring layer 305b are connected at the same connection location via vias as in the second embodiment. As a result, the signal line 3SIG arranged in the column direction is switched to the second wiring layer 305b where it intersects with the wiring included in the row direction wiring group arranged in the first wiring layer 305a.
(6) Ground line (3VSS)
The ground line 3VSS is arranged in a state extending between the columns of the photodiodes 3PD arranged in a matrix in the column direction, and the wiring position thereof is the same as the ground line 2VSS of the second embodiment.

  The ground line 3VSS includes the wiring 3VSSa of the first wiring layer 305a having the same configuration as the wiring 2VSSa of the first wiring layer 205a of the ground line 2VSS of the second embodiment and the ground line 2VSS of the second embodiment. It consists of the wiring 3 VSSb of the second wiring layer 305 b having the same configuration as the wiring 2 VSSb of the second wiring layer 205 b.

The connection between the wiring 3VSSa of the first wiring layer 305a and the wiring 3VSb of the second wiring layer 305b in the ground line 3VSS is performed at the same connection location via vias as in the second embodiment. As a result, the ground line 3VSS arranged in the column direction is switched to the second wiring layer 305b where it intersects with the wiring included in the row direction wiring group arranged in the first wiring layer 305a.
(7) Third power line (3VDD3)
The third power supply line 3VDD3 is arranged in a state extending between the columns of the photodiodes 3PD arranged in a matrix in the column direction, and the wiring position thereof is the same as the third power supply line 2VDD3 of the second embodiment. .

  The third power supply line 3VDD3 includes the wiring 3VDD3a of the first wiring layer 305a having the same configuration as the wiring 2VDD3a of the first wiring layer 205a of the third power supply line 2VDD3 of the second embodiment, and the second power supply line 2VDD3 of the second embodiment. The wiring 3VDD3b of the second wiring layer 305b has the same configuration as the wiring 2VDD3b of the second wiring layer 205b of the third power supply line 2VDD3.

In the third power supply line 3VDD3, the wiring 3VDD3a of the first wiring layer 305a and the wiring 3VDD3b of the second wiring layer 305b are connected at the same connection location via vias as in the second embodiment. As a result, the third power supply line 3VDD3 arranged in the column direction is switched to the second wiring layer 305b at the intersection with the row direction wiring group arranged in the first wiring layer 305a.
2. Cross-sectional structure The solid-state imaging device 301 employs the above-described configuration, so that a line segment passing through the center of the upper and lower photodiodes 3PD (the center of the photodiode 3PD adjacent in the column direction) as shown in FIGS. In the cross-section of the first wiring layer 305a, one wiring and the second wiring layer 305b can have one wiring.

  Two wires are connected to the first wiring layer 305a and the second wiring layer in a section taken along a line passing through the center of the left and right photodiodes 3PD (a line connecting the centers of the photodiodes 3PD adjacent in the row direction). 305b can be arranged with zero wiring.

Thereby, high sensitivity can be realized. This will be specifically described below.
(1) Section e
(I) First Wiring Layer As shown in FIGS. 13 and 11, in the cross section passing through the centers of the photodiodes 3PD13 and 3PD14, the wiring in the first wiring layer 305a is the wiring of the signal line 3SIG, the wiring 3SIGa, and the ground line 3VSS. Two of 3VSSa, or two of wiring 3SIGa of the signal line 3SIG and wiring 3VDD3a of the third power supply line 3VDD3.
(Ii) Second Wiring Layer As shown in FIGS. 13 and 12, in the cross section passing through the centers of the photodiodes 3PD13 and 3PD14, the wiring 3SIGb of the signal line 3SIG and the ground line 3VSSb are removed at the removed portion of the signal line 3SIG and the ground line 3VSb. And the third power supply line 3VDD3 correspond to the removed portions of the wiring 3VDD3b, respectively, so that the number of wirings in the second wiring layer 305b in the cross section is zero.
(2) Section f
(I) First Wiring Layer As shown in FIGS. 14 and 11, in the cross section passing through the centers of the photodiodes 3PD34 and 3PD44, the wiring in the first wiring layer 305a is the wiring 3T3a of the transfer control signal line 3T3, the first power supply Only one of the wirings 3VDD1a of the line 3VDD1 is provided.

Also in the other photodiode 3PD, in the center in the row direction, the wiring in the first wiring layer 305a is the wiring 3T1a, 3T2a, 3T3a, 3T4a of the transfer control signal lines 3T1, 3T2, 3T3, 3T4, the first power supply line. Only one of the wiring 3VDD1a of the 3VDD1 and the wiring 3VDD2a of the second power supply line 3VDD2 is provided.
(Ii) Second Wiring Layer As shown in FIGS. 14 and 12, in the cross section passing through the centers of the photodiodes 3PD34 and 3PD44, the wiring in the second wiring layer 305b is the wiring 3DYb of the dummy wiring 3DY and the transfer control signal line 3T4. Only one of the wiring 3T4b and the wiring 3Rxb of the reset signal line 3Rx is provided.

In the other photodiode 3PD, in the cross section passing through the center thereof, the wiring in the second wiring layer 305b includes the wiring 3T1b, 3T2b, 3T3b, 3T4b of the transfer control signal lines 3T1, 3T2, 3T3, 3T4, and the dummy wiring 3DY. Only one of the wiring 3DYb and the wiring 3Rxb of the reset signal line 3Rx is provided.
(3) About both cross sections e and f As described above, in the cross section passing through the center of the photodiode 3PD arranged in the row direction, the number of wirings in the second wiring layer 305b is zero. The influence of wiring is eliminated, and the aperture ratio in the row direction can be increased. In particular, the aperture ratio on the photodiode 3PD can be increased with respect to light from an oblique direction.

  In the cross section passing through the center of the photodiodes 3PD arranged in the column direction, the second wiring layer 305a has two wires. Since the light collected by the lens 311 is collected at the center of the photodiode 3PD, even if there are two wirings between the photodiodes 3PD in the first wiring layer 305a, as shown in FIG. There is no possibility that the light collected by 311 and directed toward the center of the photodiode 3PD (broken line in the figure) is blocked by the wiring of the first wiring layer 305a, and the sensitivity can be increased.

The cross-sectional shape of the waveguide 307 is made thicker as it approaches the color filter 309 side from the semiconductor substrate 303 side. For this reason, light that has passed through the color filter 309 can be guided to the waveguide 307 more efficiently, and optical characteristics without color mixing can be realized.
<Fourth embodiment>
In the solid-state imaging device according to the fourth embodiment, one wiring is wired to the first wiring layer in the cross section in the virtual plane that passes through the center of the photodiode adjacent in the row direction and extends in the row direction. One is arranged. In addition, two wires are arranged in the first wiring layer in a cross section of a virtual plane that passes through the center of the photodiodes adjacent in the column direction and extends in the column direction.

  That is, in the first wiring layer 405a, two wirings (here, extending in the row direction, which is a second direction orthogonal to the first direction), between pixels adjacent to each other in the column direction, which is the first direction. , Two transfer control signal lines 4T1 and 4T2, two transfer control signal lines 4T3 and 4T4, and two power supply lines 4VDD1 and a reset signal line 4Rx.) Are arranged in the second wiring layer 405b. , Two wirings extending in the column direction, which is the first direction, between pixels adjacent in the row direction, which is the second direction (here, two of the signal line 4SIG and the ground line 4VSS, the signal line 4SIG, and the first line) 3 power supply lines 4VDD3), one of the two wirings of the second wiring layer 405b (here, the signal line 4SIG of the two signal lines 4SIG and the ground line 4VSS) One ground line 4VSS or 2 Of the wiring signal line 4SIG and the third power supply line 4VDD3 is one of the signal line 4SIG or the third power supply line 4VDD3) in the central region of the pixels adjacent to each other in the column direction which is the first direction. It enters the layer 405a.

  With the configuration as described above, in the column direction, the wiring between the rows is only the first wiring layer, and the wiring opening on the photodiode can be enlarged particularly with respect to the light from the oblique direction, thereby increasing the sensitivity. Can be realized. Further, higher sensitivity can be realized by tapering the waveguide shape.

  Regarding the row direction, there is one wiring between the columns in the first wiring layer and one wiring in the second wiring layer, so that the wiring opening on the photodiode between the columns can be enlarged, and high sensitivity is achieved. Can be realized. Similarly, since the waveguide diameter can be enlarged, higher sensitivity can be realized.

The details of the fourth embodiment will be described below with reference to FIGS.
FIG. 15 is a layout diagram showing the first wiring layer in addition to FIG. 1 and vias connecting the first wiring layer and the second wiring layer. FIG. 16 is a layout diagram showing the second wiring layer in addition to FIG. is there.

17 is a sectional view taken along the broken line g in FIG. 16, and FIG. 18 is a sectional view taken along the broken line h in FIG.
As in the first embodiment, the solid-state imaging device 401 according to the fourth embodiment includes a semiconductor substrate 403, a wiring layer 405, a waveguide 407, a color filter 409, as shown in FIGS. The lens 411 is provided, and the wiring layer 405 includes a first wiring layer 405a and a second wiring layer 405b. In this embodiment mode, the waveguide 407 in the cross section in the column direction (FIG. 18) is formed to become thicker as it approaches the color filter 409 side from the semiconductor substrate 403 side.

The semiconductor substrate 403 of the solid-state imaging device 401 has the same configuration as the semiconductor substrate 103 of the solid-state imaging device 101 according to the first embodiment, and the wiring layer 405 formed on the imaging region of the semiconductor substrate 403 is different. That is, the layout showing the diffusion layer, polysilicon, and contact in the unit cell is the same as that in FIG. 1, and the number of wirings of the first wiring layer 405a and the second wiring layer 405b formed above is different. For this reason, the wiring layer 405 will be described below.
1. Wiring The types of wirings in the fourth embodiment, that is, the wirings included in the row direction wiring group and the column direction wiring group are the same as the types of wiring described in the first embodiment.

  That is, as shown in FIGS. 15 and 16, the row direction wiring group includes the first power supply line 4VDD1, the reset signal line 4Rx, the transfer control signal lines 4T1, 4T2, 4T3, and 4T4, and the second power supply line 4VDD2. The directional wiring group includes a ground line 4VSS, a signal line 4SIG, and a third power supply line 4VDD3.

The arrangement positions of the row-direction wiring group and the column-direction wiring group according to the fourth embodiment are the same as those in the first to third embodiments, but of course the first to third embodiments. And may be different.
(1) Transfer control signal line (4T)
As shown in FIG. 15, the transfer control signal lines 4T1, 4T2, 4T3, and 4T4 are arranged in a state of extending in the row direction between rows of photodiodes 4PD arranged in a matrix, as in the second embodiment. Has been.

The wiring positions and configurations of the transfer control signal lines 4T1, 4T2, 4T3, and 4T4 are the same as those of the transfer control signal lines 2T1, 2T2, 2T3, and 2T4 of the second embodiment described above.
The transfer control signal lines 4T1 and 4T2 extend in the row direction between the first row of photodiodes 4PD1k and the second row of photodiodes 4PD2k in each unit cell. The transfer control signal lines 4T3 and 4T4 extend in the row direction between the photodiodes 4PD3k in the third row and the photodiodes 4PD4k in the fourth row in each unit cell.

  The transfer control signal line 4T1 includes the wiring 4T1a of the first wiring layer 405a having the same configuration as the wiring 2T1a of the first wiring layer 205a described in the second embodiment, and the second wiring layer 405b has wiring. Not done.

  Similarly, the transfer control signal line 4T2 includes the wiring 4T2a of the first wiring layer 405a having the same configuration as the wiring 2T2a of the first wiring layer 205a described in the second embodiment, and the second wiring layer 405b includes Does not have wiring.

  The transfer control signal line 4T3 includes the wiring 4T3a of the first wiring layer 405a having the same configuration as the wiring 2T3a of the first wiring layer 205a described in the second embodiment, and the second wiring layer 405b has wiring. Not done. Similarly, the transfer control signal line 4T4 includes the wiring 4T4a of the first wiring layer 405a having the same configuration as the wiring 2T4a of the first wiring layer 205a described in the second embodiment, and the second wiring layer 405b includes Does not have wiring.

Also in the fourth embodiment, the transfer control signal line 4T1 and the transfer control signal line 4T3 have the same configuration except for the arrangement location, and the transfer control signal line 4T2 and the transfer control signal line 4T4 have the arrangement location. It has the same configuration just by being different.
(2) Reset signal line (4Rx) and first power supply line (4VDD1)
As shown in FIG. 15, the reset signal line 4Rx is arranged in a state extending between the rows of photodiodes 4PD arranged in a matrix in the row direction, and the wiring position is the reset signal line 2Rx of the second embodiment. Is the same.

  The reset signal line 4Rx is composed of the wiring 4Rxa of the first wiring layer 405a having the same configuration as the wiring 2Rxa of the first wiring layer 205a of the reset signal line 2Rx of the second embodiment. The reset signal line 4Rx has no wiring in the second wiring layer 405b.

  As shown in FIG. 15, the first power supply line 4VDD1 is arranged in a state extending between the rows of photodiodes 4PD arranged in a matrix in the row direction, and the wiring position thereof is the same as that of the first embodiment. This is the same as the power supply line 2VDD1.

  The first power supply line 4VDD1 includes the wiring 4VDD1a of the first wiring layer 405a having the same configuration as the wiring 2VDD1a of the first wiring layer 205a of the first power supply line 2VDD1 of the second embodiment. Note that the first power supply line 4VDD1 has no wiring in the second wiring layer 405b.

Also in the fourth embodiment, the reset signal line 4Rx and the first power supply line 4VDD1 are arranged in the row direction at a predetermined interval.
(3) Second power line (4VDD2)
As shown in FIG. 15, the second power supply line 4VDD2 is arranged in a state extending between the rows of photodiodes 4PD arranged in a matrix in the row direction, and the wiring position thereof is the second in the second embodiment. This is the same as the power supply line 2VDD2.

The second power supply line 4VDD2 is composed of the first wiring layer wiring 4VDD2a having the same configuration as the wiring 2VDD2a of the first wiring layer 205a of the second power supply line 2VDD2 of the second embodiment. Note that the second power supply line 4VDD2 has no wiring in the second wiring layer 405b.
(4) Signal line (4SIG)
The signal lines 4SIG are arranged in a state extending between the columns of the photodiodes 4PD arranged in a matrix in the column direction, and the wiring positions thereof are the same as the signal lines SIG of the first embodiment.

  As shown in FIGS. 16 and 17, the signal line 4SIG includes the wiring 4SIGa of the first wiring layer 405a having the same configuration as the wiring SIGa of the first wiring layer 105a of the signal line SIG of the first embodiment, The wiring 4SIGb of the second wiring layer 405b having the same configuration as the wiring SIGb of the second wiring layer 105b of the signal line SIG of the first embodiment.

The connection between the wiring 4SIGa of the first wiring layer 405a and the wiring 4SIGb of the second wiring layer 405b in the signal line 4SIG is performed at the same connection location via vias as in the first embodiment.
(5) Ground line (4VSS)
The ground line 4VSS is arranged in a state extending between the columns of the photodiodes 4PD arranged in a matrix in the column direction, and the wiring position thereof is the same as the ground line VSS of the first embodiment.

  The ground line 4VSS includes the wiring 4VSSa of the first wiring layer 405a having the same configuration as the wiring VSSa of the first wiring layer 105a of the ground line VSS of the first embodiment and the ground line VSS of the first embodiment. The wiring 4 VSSb of the second wiring layer 405b has the same configuration as the wiring VSSb of the second wiring layer 105b.

The connection between the wiring 4VSSa of the first wiring layer 405a and the wiring 4VSbb of the second wiring layer 405b in the ground line 4VSS is performed at the same connection location via vias as in the second embodiment.
(6) Third power line (4VDD3)
The third power supply line 4VDD3 is arranged in a state extending between the columns of the photodiodes 4PD arranged in a matrix in the column direction, and the wiring position is the same as the third power supply line VDD3 of the first embodiment. .

  The third power supply line 4VDD3 includes the wiring 4VDD3a of the first wiring layer 405a having the same configuration as the wiring VDD3a of the first wiring layer 105a of the third power supply line VDD3 of the first embodiment, and the first power supply line VDD3 of the first embodiment. The wiring 4 VDD 3 b of the second wiring layer 405 b has the same configuration as the wiring VDD 3 b of the second wiring layer 105 b of the third power supply line VDD 3.

In the third power supply line 4VDD3, the wiring 4VDD3a of the first wiring layer 405a and the wiring 4VDD3b of the second wiring layer 405b are connected at the same connection location via vias as in the second embodiment.
2. Cross-sectional structure The solid-state imaging device 401 adopts the above-described configuration, so that a line segment passing through the center of the upper and lower photodiodes 4PD as shown in FIGS. 17 and 18 (the center of the photodiode 4PD adjacent in the column direction). In the cross-section at (), two wirings can be arranged in the first wiring layer 405a.

  In the cross section at the line segment passing through the center of the left and right photodiodes 4PD (the line segment connecting the centers of the photodiodes 4PD adjacent in the row direction), one line is connected to the first wiring layer 405a, and the second wiring layer One wiring can be arranged at 405b.

Thereby, high sensitivity can be realized. This will be specifically described below.
(1) Section g
(I) First Wiring Layer As shown in FIGS. 17 and 15, in the cross section passing through the centers of the photodiodes 4PD13 and 4PD14, the wiring in the first wiring layer 405a is one of the wirings 4SIGa of the signal line 4SIG. In the cross section passing through the center of the other photodiode 4PD, any one of the wiring 4SIGa of the signal line 4SIG, the wiring 4VDD3a of the third power supply line 4VDD3, and the wiring 4VSSa of the ground line 4VSS is provided.
(Ii) Second Wiring Layer As shown in FIGS. 17 and 16, the cross section passing through the centers of the photodiodes 4PD13 and 4PD14 corresponds to the removed portion of the wiring 4SIGb of the signal line 4SIG, and consequently the ground line 4VSS. One of the wiring 4VSSb and the wiring 4VDD3b of the third power supply line 4VDD3.
(2) Section h
(I) First Wiring Layer As shown in FIGS. 18 and 15, in the cross section passing through the centers of the photodiodes 4PD34 and 4PD44, the wiring in the first wiring layer 405a is the same as the wiring 4T3a of the transfer control signal line 4T3 and the transfer control signal. The combination of the wiring 4T4a of the line 4T4, the combination of the wiring 4VDD1a of the first power supply line 4VDD1 and the wiring 4Rxa of the reset signal line 4Rx, or the wiring 4VDD2a of the second power supply line 4VDD2 is configured. There are only two extending portions (for example, corresponding to two transfer control signal lines 4T3 and 4T4).

In the cross section passing through the center of the other photodiode 4PD, the number of wirings in the first wiring layer 405a is two in combination of the transfer control signal lines 4T1 and 4T2.
(Ii) Second Wiring Layer As shown in FIGS. 18 and 16, in the cross section passing through the centers of the photodiodes 4PD34 and 4PD44, the number of wirings in the second wiring layer 405b is zero.
(3) About both sections g and h As described above, in the section passing through the center of the photodiode 4PD arranged in the row direction, the first wiring layer 405a has two wirings. Since the light collected by the lens 411 is collected at the center of the photodiode 4PD, even if there are two wirings between the photodiodes 4PD in the first wiring layer 405a, as shown in FIG. There is no possibility that the light collected by 411 and directed toward the center of the photodiode 4PD (broken line in the figure) is blocked by the wiring of the first wiring layer 405a, and the sensitivity can be increased.

  In the cross section passing through the center of the photodiodes 4PD arranged in the column direction, since the number of wirings is one in the first wiring layer 405a and the second wiring layer, the distance between the wirings sandwiching the photodiode 4PD located below the lens 411 is set. It is possible to increase the size, and the configuration is such that the wiring is not located below the periphery of the lens 411. For this reason, the aperture ratio as the solid-state imaging device 401 can be increased.

Further, the cross-sectional shape of the waveguide 407 is made thicker as it approaches the color filter 409 side from the semiconductor substrate 403 side. Therefore, the light that has passed through the color filter 409 can be guided to the waveguide 407 more efficiently, and optical characteristics without color mixing can be realized.
<Fifth embodiment>
The solid-state imaging device according to the fifth embodiment employs a so-called two-pixel one-cell structure in which a unit cell is composed of two pixels.

  Also in this case, one wiring is arranged in the first wiring layer and one wiring is arranged in the second wiring layer in a cross section at a virtual plane passing through the center of the photodiode adjacent in the row direction and extending in the row direction. . In addition, one wiring is arranged in the first wiring layer and one wiring is arranged in the second wiring layer in a cross section of a virtual plane extending in the column direction through the center of the photodiodes adjacent in the column direction. This wiring configuration (in each direction, one first wiring layer and one second wiring layer) is basically the same as the wiring configuration in the first embodiment. Note that the wiring configuration of the wiring layer 105 in the first embodiment is applied to the two-pixel one-cell structure (this is the fifth embodiment), but the second to fourth embodiments. The wiring configuration of the wiring layer in the form can also be applied.

Hereinafter, the fifth embodiment will be described in detail with reference to FIGS.
FIG. 19 is a layout diagram showing diffusion layers, polysilicon, and contacts in a unit cell of a solid-state imaging device according to the fifth embodiment.

FIG. 20 is a circuit diagram schematically showing a unit cell of the solid-state imaging device according to the fifth embodiment.
21 is a layout diagram showing the first wiring layer and vias connecting the first wiring layer and the second wiring layer in addition to FIG. 19, and FIG. 22 is a layout diagram showing the second wiring layer in addition to FIG. .
1. Configuration The solid-state imaging device according to the fifth embodiment includes a semiconductor substrate, a wiring layer, a color filter, and a lens, and has a waveguide as necessary. Also in the fifth embodiment, the wiring layer has a two-layer structure of a first wiring layer and a second wiring layer.

The semiconductor substrate has an imaging area composed of a plurality of pixels arranged in a matrix direction on the main surface side, and also has a peripheral circuit area.
As shown in FIG. 19, each pixel includes a photodiode 5PD, a transfer transistor 5TG, an amplification transistor 5SF, and a reset transistor 5RS. Here, as described above, one unit cell is constituted by two photodiodes (for example, 5PD11 and 5PD21). That is, the unit cell includes two photodiodes 5PD, two transfer transistors 5TG, one reset transistor 5RS, and amplification transistor 5SF.

  In the fifth embodiment, the drain of the amplification transistor 5SF is connected to the first power supply line 5VDD1 to which the drain of the reset transistor 5RS is connected. For this reason, the wiring of the second power supply line VDD2 that existed in the first embodiment is not the present embodiment.

In the fifth embodiment, since the substrate potential is secured from the peripheral circuit, the wiring of the ground line VSS existing in the first embodiment is not arranged in the present embodiment. .
2. Layout The layout of photodiodes and the like will be described with reference to FIG.

  Two photodiodes 5PD11 and 5PD21 constituting one unit cell are arranged adjacent to each other in the column direction. The arrangement position of the plurality of photodiodes 5PD is the same as the arrangement of the plurality of photodiodes PD in the first embodiment.

  The two transfer transistors 5TG1 and 5TG2 are arranged around the corresponding photodiode 5PD. For example, the transfer transistor 5TG1 is located obliquely below (second row side) the photodiode 5PD11 located on the upper side (positioned on the first row), and the transfer transistor 5TG2 is located on the lower side (located on the second row). ) The photodiodes 5PD12 are disposed obliquely above (first row). That is, the transfer transistor 5TG is arranged in a state of facing each other in a region corresponding to a corner on the side adjacent (opposed) to each other among the two photodiodes 5PD constituting the unit cell.

Needless to say, the positional relationship between the photodiode 5PD and the transfer transistor 5TG is not limited to this example, and may be another positional relationship.
The amplification transistor 5SF and the reset transistor 5RS are arranged between the columns of the photodiodes 5PD arranged in a matrix, and the virtual transistors in the row direction passing through the center between the photodiodes 5PD11 and 5PD12 adjacent in the column direction. They are arranged to be opposite to each other with respect to the line. That is, the amplification transistor 5SF and the reset transistor 5SF are arranged so as to sandwich the two transfer transistors 5TG1 and 5TG2 from both sides in the column direction.

Here, the amplification transistor 5SF is disposed on the lower end side of the unit cell, and the reset transistor 5RS is disposed on the upper end side of the unit cell.
3. Circuit Configuration Connection of photodiodes and the like will be described with reference to FIGS. 19 and 20.

  The connection between the photodiode 5PD and the transfer transistor 5TG and the connection between the transfer transistor 5TG and the reset transistor 5RS are performed by sharing a diffusion layer, as in the first embodiment.

In the fifth embodiment, as shown in FIG. 19, the drain of the reset transistor 5RS and the drain of the amplification transistor 5SF are shared.
4). Wiring The row direction wiring group according to the fifth embodiment includes a first power supply line 5VDD1, a reset signal line 5Rx, and transfer control signal lines 5T1 and 5T2. The column direction wiring group includes a signal line 5SIG and a second power supply line 5VDD2. Hereinafter, a description will be given with reference to FIGS. 21 and 22 in particular.
(1) Transfer control signal line (5T1, 5T2)
The transfer control signal lines 5T1 and 5T2 extend in the row direction between two photodiodes 5PD11 and 5PD21 adjacent to each other in the column direction constituting each unit cell.

Similarly to the transfer control signal lines T1 and T2 of the first embodiment, the transfer control signal lines 5T1 and 5T2 include the wirings 5T1a and 5T2a of the first wiring layer and the wirings 5T1b and 5T2b of the second wiring layer. . Note that the wirings 5T1a and 5T2a in the first wiring layer have the same configuration as the wirings T1a and T2a of the transfer control signal lines T1 and T2 in the first embodiment. The wirings 5T1b and 5T2b in the second wiring layer have the same configuration as the wirings T1b and T2b of the transfer control signal lines T1 and T2 in the first embodiment.
(2) Reset signal line (5Rx)
The reset signal line 5Rx extends between the photodiodes 5PD corresponding to each unit cell in the row direction.

The reset signal line 5Rx includes a wiring 5Rxa in the first wiring layer and a wiring 5Rxb in the second wiring layer, as in the reset signal line Rx in the first embodiment. Note that the wiring 5Rxa of the first wiring layer has the same configuration as the wiring Rxa of the reset signal line Rx of the first embodiment. The wiring 5Rxb of the second wiring layer has the same configuration as the wiring Rxb of the reset signal line Rx of the first embodiment.
(3) First power line (5VDD1)
The first power supply line 5VDD1 extends in the row direction together with the reset signal line 5Rx between the photodiodes 5PD corresponding to each unit cell.

As shown in FIG. 21, the first power supply line 5VDD1 extends substantially in a straight line and includes the wiring 5VDD1a of the first wiring layer. In FIG. 21, the wiring 5VDD1a of the first power supply line 5VDD1 is arranged in the central region between the photodiodes 5PD corresponding to the unit cells.
(4) Signal line (5SIG) and second power supply line (5VDD2)
As shown in FIGS. 21 and 22, the signal line 5SIG and the second power supply line 5VDD2 extend between the photodiodes 5PD11 and 5PD12 adjacent in the row direction in the column direction.

Similarly to the signal line SIG of the first embodiment, the signal line 5SIG includes a wiring 5SIGa in the first wiring layer and a wiring 5SIGb in the second wiring layer.
The wiring 5SIGa has an “I” shape as shown in FIG. That is, it has the same shape as the wiring SIGa of the signal line SIG of the first embodiment. The wiring 5SIGa is arranged between the photodiodes 5PD adjacent in the row direction, for example, between the photodiode 5PD11 and the photodiode 5PD12 in the first row.

  As shown in FIG. 22, the wiring 5SIGb is arranged between the plurality of photodiodes 5PD arranged in the matrix direction and linearly extends between the photodiodes 5PD1k and the photodiodes 5PD2k adjacent to each other in the column direction. It is arranged in.

The wiring 5SIGa and the wiring 5SIGb are connected through, for example, vias, and the first wiring layer and the second wiring layer are interchanged between rows of photodiodes 5PD adjacent in the column direction.
(5) Second power line (5VDD2)
As shown in FIG. 22, the second power supply line 5VDD2 extends in the column direction between the photodiode 5PD11 and the photodiode 5PD12 adjacent in the row direction. That is, the second power supply line 5Vdd2 extends in the column direction between the photodiodes 5PD in a pair with the signal line 5SIG.

As shown in FIGS. 21 and 22, the second power supply line 5VDD2 has a wiring 5VDD2b arranged only in the second wiring layer. As shown in FIG. 22, the wiring 5VDD2b has a central region of the photodiode 5PD extending to a substantially center between the photodiodes 5PD adjacent in the row direction.
(6) Summary With the above configuration, even if the unit cell is composed of two pixels, the center of the photodiodes adjacent in the row direction is arranged as in the first embodiment in which the unit cell is composed of four pixels. In the cross section of the virtual plane extending in the row direction, one wiring is arranged in the first wiring layer and one wiring is arranged in the second wiring layer, and extends in the column direction through the center of the photodiode adjacent in the column direction. In the cross section on the virtual plane, one wiring can be arranged in the first wiring layer and one wiring can be arranged in the second wiring layer.
<Modification>
1. Unit Cell In the first to fourth embodiments described above, a four-pixel one-cell structure in which four photodiodes are arranged for one unit cell is taken as an example, and in the fifth embodiment, one unit cell has a photo Although the two-pixel one-cell structure in which two diodes are arranged is applied as an example, the present invention is not limited to this, and any structure can be applied as long as a unit cell is composed of a plurality of pixels.

For example, a 6-pixel 1-cell structure having 6 photodiodes and 6 transfer transistors per unit cell may be employed.
2. Amplifying Transistor In the first to fourth embodiments, two amplifying transistors are used in a parallel configuration. However, a single configuration can be used, and the same wiring effect can be obtained by using a single configuration.
3. In the dummy embodiment, the layout of the semiconductor substrate is given regularity, has a vertically symmetric configuration within the unit cell, or has a similar wiring configuration in each row and each column. That is, the shape seen from the photodiode is matched in order to reduce variations in layout. For this reason, dummy wirings and dummy contacts are arranged. However, these dummies are not always necessary.
4). Ground line In the first to fourth embodiments, the column-direction wiring group includes the ground line. However, as described in the fifth embodiment, the substrate potential can also be taken from the peripheral circuit. Also in the first to fourth embodiments, the substrate potential may be taken from the peripheral circuit.

In this case, for example, a third power supply line (VDD3 or the like) may be disposed at the ground line (VSS). The arrangement of the third power supply line (VDD3) can reinforce the power supply line in the row direction. Further, the third power supply line (VDD3) in the column direction and the signal line (SIG) are arranged between the photodiodes (PD) adjacent in the row direction, and the number of wirings in the row direction can be reduced.
5. Wiring Shape In the embodiment, the wiring shapes included in each directional wiring group are made the same. For example, in the first embodiment, the wiring VDD1a of the first power supply line VDD1, the wirings T1a, T2a, T3a, and T4a of the transfer control signal lines T1, T2, T3, and T4, the wiring VDD2a of the second power supply line VDD2, and the reset The wiring Rxa of the signal line Rx has the same shape.

Here, the “similar shape” refers to a shape in which one wiring overlaps the other wiring by 50 [%] or more when the target wiring is overlapped. For example, when the wiring VDD1a of the first power supply line VDD1 and the wiring T1a of the transfer control signal line T1 are compared, when these wirings are overlapped, most of the wiring T1a of the transfer control signal line T1 becomes the first power supply line. It can be said that the wiring T1a of the transfer control signal line T1 overlaps with the wiring VDD1a of VDD1, and has the same shape as the wiring VDD1 of the first power supply line VDD1.
6). Waveguide In the above embodiment, a waveguide made of a material higher than the refractive index of the wiring layer is provided on the photodiode. However, the solid-state imaging device may have a structure without a waveguide. good.

  In the second embodiment, the width of the waveguide 207 in the cross section in the row direction (FIG. 9) and the cross section in the column direction (FIG. 10) increases (thickers) as it approaches the color filter 209 side from the semiconductor substrate 203 side. Thus, in the third embodiment, the width of the waveguide 307 in the cross section in the row direction (FIG. 13) becomes larger (thicker) as it approaches the color filter 309 side from the semiconductor substrate 303 side. This requires a space (width) for wiring when there are two wirings in the first wiring layer than when there is one wiring. Thereby, the width of the waveguide of the first wiring layer is narrowed, and the width of the light guide is reduced when there is wiring in the first wiring layer in order to prevent the light condensing property to the photodiode from being lowered. is doing.

  In consideration of the light condensing property to the photodiode, the width of the waveguide may be narrowed from the color filter side to the photodiode side even if the number of wirings in the first wiring layer is one.

  The present invention is useful for realizing a solid-state imaging device that requires a high S / N image as an imaging device such as a digital still camera.

DESCRIPTION OF SYMBOLS 101 Solid-state imaging device 103 Semiconductor substrate 105 Wiring layer 105a 1st wiring layer 105b 2nd wiring layer PD Photodiode TG Transfer transistor SF Amplification transistor RS Reset transistor T Transfer control signal line VDD Power supply line SIG Signal line Rx Reset signal line VSS Ground line

Claims (12)

A semiconductor substrate having an imaging region including a plurality of pixels arranged in a matrix direction, and a peripheral circuit region including a peripheral circuit around the imaging region;
A wiring layer disposed above the imaging region and for connecting the pixel and the peripheral circuit;
The wiring layer includes a first wiring layer and a second wiring layer in this order from the semiconductor substrate side,
In the first wiring layer, two wirings extending in a second direction orthogonal to the first direction between pixels adjacent in the first direction are arranged,
In the second wiring layer, two wirings extending in the first direction between pixels adjacent in the second direction are arranged,
A solid-state imaging device, wherein at least one of the two wirings of the second wiring layer enters the first wiring layer in a central region of pixels adjacent in the first direction. The first direction is the column direction, the second direction is a row direction,
2. The first wiring layer according to claim 1, wherein one of the two wirings of the second wiring layer enters the first wiring layer in a central region of a pixel adjacent in the first direction. Solid-state imaging device. The one of the two wirings of the first wiring layer enters the second wiring layer in a central region of a pixel adjacent in the second direction. Solid-state imaging device. The first direction is the column direction, the second direction is a row direction,
2. The solid-state imaging device according to claim 1, wherein two of the second wiring layers enter the first wiring layer in a central region of pixels adjacent in the first direction. 5. One of the two wirings of the first wiring layer enters the second wiring layer in a central region of pixels adjacent in the second direction. The solid-state imaging device described. In the imaging area,
A photodiode and a transfer transistor provided in each of the plurality of pixels;
A floating diffusion connected to the drains of at least two of the transfer transistors;
A reset transistor having a source connected to the floating diffusion;
An amplification transistor having a gate connected to the floating diffusion, and
The two wires extending in the second direction include a transfer control signal line connected to the gate of the transfer transistor,
The transfer control signal line periodically switches between the first wiring layer and the second wiring layer,
The remaining one of the two wirings of the second wiring layer is located at the center between the photodiodes of the pixels adjacent in the second direction in the central region of the pixels adjacent in the first direction. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is characterized by the following. In the imaging area,
A photodiode and a transfer transistor provided in each of the plurality of pixels;
A floating diffusion connected to the drains of at least two of the transfer transistors;
A reset transistor having a source connected to the floating diffusion;
An amplification transistor having a gate connected to the floating diffusion, and
The two wirings entering the first wiring layer of the second wiring layer include a signal line connected to the source of the amplification transistor, and the signal line includes a poly line including the gate of the amplification transistor. The solid-state imaging device according to claim 4, wherein the solid-state imaging device is located on silicon. In the imaging area,
A photodiode and a transfer transistor provided in each of the plurality of pixels;
A floating diffusion connected to the drains of at least two of the transfer transistors;
A reset transistor having a source connected to the floating diffusion;
An amplification transistor having a gate connected to the floating diffusion, and
An optical waveguide formed in the wiring layer above the photodiode;
The optical waveguide is made of a material having a refractive index higher than that of the insulating film constituting the wiring layer, and the length in the second direction increases as the distance from the semiconductor substrate increases. The solid-state imaging device according to claim 4 or 5, characterized by the above. In the imaging area,
A photodiode and a transfer transistor provided in each of the plurality of pixels;
A floating diffusion connected to the drains of at least two of the transfer transistors;
A reset transistor having a source connected to the floating diffusion;
An amplification transistor having a gate connected to the floating diffusion, and
An optical waveguide formed in the wiring layer above the photodiode;
The optical waveguide is made of a material having a refractive index higher than that of the insulating film constituting the wiring layer, and the length in the first direction increases as the distance from the semiconductor substrate increases. The solid-state imaging device according to claim 2, wherein the solid-state imaging device is characterized by the following. The two wires extending in the second direction arranged in the first wiring layer include a first power supply line connected to the drain of the amplification transistor,
The two wirings extending in the first direction arranged in the second wiring layer include a second power supply line connected to the first power supply line. The solid-state imaging device of any one. The two wirings extending in the second direction arranged in the first wiring layer include a reset wiring connected to the drain of the reset transistor,
The solid-state imaging device according to claim 10, wherein the reset signal line is connected to the second power supply line. The following diffusion is connected to the drains of at least four transfer transistors;
The semiconductor substrate comprises a contact;
12. The wiring according to claim 6, wherein the two wirings extending in the first direction arranged in the second wiring layer include a contact wiring connected to the contact. The solid-state imaging device described.

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