JP2012083992A - Data failure processing apparatus and data failure processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data failure processing apparatus and a data failure processing method that actualize processor relief while avoiding repetitive fault occurrence.SOLUTION: The data failure processing apparatus includes a processor 3 which accesses data stored in a storage device having an error correcting function. The storage device imparts an error correction code to data during data supply. A fault identification unit 302 identifies whether a fault occurs to the data supplied from the storage device based upon the error correction code. A previous evaluation unit 305 issues a previous evaluation request such that an address in which data having an uncorrectable fault is stored is accessed again. A relief propriety determination unit 306 determines whether processor relief can be made according to the issue result of the previous evaluation request. A fault processing unit 307 performs fault handling processing according to a determination of the relief propriety determination unit.

Description

  The present invention relates to a data failure processing apparatus and a data failure processing method.

  In recent information processing apparatuses, functions are improved and a lot of hardware is mounted, so that the number of failure occurrences inevitably increases. Furthermore, there is an increasing demand for improving the reliability of information processing apparatuses.

  For data errors in the memory in the information processing apparatus, the cache memory, and the system bus that connects them, error correction and error detection are performed by ECC (Error Checking and Correcting).

  Patent Document 1 discloses a technique related to a data failure processing apparatus using ECC. The configuration of the data processing apparatus is shown in FIG. When detecting an error that cannot be corrected by the ECC, this data processing apparatus replaces the ECC code with a dedicated code (in the following description, described as poisoning), thereby detecting and reporting an extra failure. A technique is disclosed that suppresses errors and reliably notifies an error to a processor that references illegal data. Specific effects of poisoning by the data processing apparatus include the following matters.

(1) Relief from intermittent failure As a cause of an uncorrectable failure in a DIMM (Dual Inline Memory Module), a cache memory, or the like, there are a case where a memory cell fails in multiple bits and a case where a control system fails. When the control system fails, normal data can be obtained by accessing the DIMM again. In this data failure processing apparatus, since failure processing is entrusted to a request supply source (processor), relief from an intermittent failure is possible depending on control of the request supply source.

(2) Guarantee of data integrity According to the above-mentioned poisoning, the request requester can grasp that the data content is faulty regardless of when and what request source accesses the faulty data. it can.

(3) Identification of failure location According to the poisoning described above, only the location where an uncorrectable failure has occurred reports an error. Thereby, unnecessary trouble reports can be suppressed.

(4) Continuation of operation The above-described data failure processing apparatus is configured to easily continue operation as a system even when an uncorrectable failure occurs. Specifically, since the location of the failure can be identified, even if the data is corrupted, the system operation can be continued without performing an immediate system check unless the corrupted data is used. For example, when work data that is not used again fails, the system operation can be continued as it is. Further, even when the corrupted data is referred to, data integrity is guaranteed, so that failure processing depending on the processing of the request request source may be executed, and there is no need to perform a system check by hardware. Furthermore, the poisoned data can be rewritten to an initial value or the like (cancellation from the poisoned state) as necessary.

  The release from the poisoned state can be released by rewriting all the data to which the ECC code is added. For example, when an ECC code is added to 8-byte data, the poison state can be canceled by updating the 8-byte data.

JP-A-8-263453

  However, in the data failure processing apparatus described in Patent Document 1, there is a possibility that a failure will repeatedly occur. Details of this problem will be described below.

  In the data failure processing device of Patent Document 1, when a processor or the like accesses main memory or cache memory, an uncorrectable failure occurs in the accessed data (or when it is poisoned data), A processor or the like can detect that the data cannot be used. In this case, failure processing such as a predetermined processor check is executed in each device.

  As the failure processing, there is a processor relief processing in which processing after the point of occurrence of the failure is taken over and executed by another processor. In the processor relief process, the processor that has taken over the process re-executes from the process of accessing the data in which the uncorrectable failure has occurred, or the process that can be restarted before that. In this case, even if the processor that has taken over the process accesses the data again, the data remains in the fault state, and the uncorrectable state is detected again. Then, this processor performs the processor relief process again and takes over the process to another processor. As described above, when an uncorrectable failure occurs, processor relief is repeatedly performed, and the processor is exhausted. When the processor is exhausted, it becomes necessary to perform a system check.

  The problem that the above processor is exhausted is shown in FIG. As described above, the data failure processing apparatus described in Patent Document 1 performs processor relief even when an uncorrectable failure occurs. As a result, the processor that has inherited the processing issues a read request for data in which an uncorrectable failure has occurred.

  If it is possible to determine whether or not the data failure can be repaired, the above problem can be avoided. However, in the data failure processing apparatus of Patent Document 1, there is no description about determining whether or not the occurred failure can be relieved (whether it is an uncorrectable failure). In general, the determination of whether or not relief is possible is determined by a combination of cache status, request operation, failure location, failure type (intermittent / fixed), etc., and thus requires a complicated hardware configuration and processing function. Therefore, it is extremely difficult to determine whether or not relief is possible.

  As described above, in the data failure processing apparatus described in Patent Document 1, it is difficult to determine whether or not the data failure can be repaired. Therefore, there is a problem that a failure occurs repeatedly even if processor relief is performed.

  The present invention has been made to solve such a problem, and it is a main object of the present invention to provide a data failure processing apparatus and a data failure processing method for realizing processor relief by avoiding repeated failures. To do.

One aspect of the data failure processing apparatus according to the present invention is as follows.
A data failure processing apparatus comprising a processor for accessing data stored in a storage device having an error correction function,
The storage device gives an error correction code to data at the time of data supply,
The processor is
A failure identification unit for identifying whether or not a failure has occurred in the data supplied from the storage device based on the error correction code;
A pre-evaluation unit that issues a pre-evaluation request to access again the address where the failed data is stored;
A repairability determination unit that determines whether a processor relief can be executed according to a result of issuing the prior evaluation request;
A failure processing unit that performs a failure handling process according to the determination of the repairability determination unit.

One aspect of the data failure handling method according to the present invention is as follows.
A data failure processing method in a data failure processing apparatus comprising a processor for accessing data stored in a storage device having an error correction function,
The storage device gives an error correction code to data at the time of data supply,
The processor is
Identify whether or not a failure has occurred in the data supplied from the storage device based on the error correction code,
Issue a pre-evaluation request to re-access the address where the failed data is stored,
It is determined whether processor relief can be executed according to the issuance result of the prior evaluation request,
A failure handling process is performed according to the determination of whether or not the processor relief can be executed.

  According to the present invention, it is possible to provide a data failure processing apparatus and a data failure processing method that realize processor relief that avoids repeated failures.

1 is a block diagram showing a configuration of a data failure processing apparatus according to a first exemplary embodiment; It is a figure which shows the cache status of the cache unit concerning Embodiment 1. FIG. FIG. 3 is a diagram illustrating a relationship between a failure occurrence location and a failure process of the data failure processing apparatus according to the first exemplary embodiment. FIG. 3 is a diagram illustrating a relationship between a failure occurrence location and a failure process of the data failure processing apparatus according to the first exemplary embodiment. FIG. 3 is a diagram illustrating a relationship between a failure occurrence location and a failure process of the data failure processing apparatus according to the first exemplary embodiment. FIG. 3 is a diagram illustrating a relationship between a failure occurrence location and a failure process of the data failure processing apparatus according to the first exemplary embodiment. FIG. 3 is a diagram illustrating a relationship between a failure occurrence location and a failure process of the data failure processing apparatus according to the first exemplary embodiment. FIG. 3 is a diagram illustrating a processing outline of the data failure processing apparatus according to the first embodiment; 1 is a block diagram showing a configuration of a data failure processing apparatus according to a first exemplary embodiment; 10 is a block diagram illustrating a configuration of a data failure processing apparatus described in Patent Literature 1. FIG. 10 is a diagram showing an outline of processing of a data failure processing apparatus described in Patent Literature 1. FIG.

<Embodiment 1>
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the data failure processing apparatus according to the present embodiment. The data failure processing apparatus includes a main storage unit 1, a cache memory unit 2, and a processor unit 3. In this embodiment, the main storage unit 1 and the cache memory unit 2 are described as a single configuration, but a data failure processing apparatus including a plurality of main storage units and cache memory units may be used. Although not shown, the data failure processing apparatus is configured to include a plurality of processor units 3 so as to enable processor relief.

  The main storage unit 1 includes a main storage unit 101, an access control unit 102, an ECC (Error Check and Correct) check unit 103, and a poisoning processing unit 104. The main storage unit 101 is a so-called main memory, and is a storage device provided in a general information processing apparatus. For the elements constituting the main storage unit 101, those generally used may be used.

  The access control unit 102 is a processing unit that controls data reading from the main storage unit 101 and data writing to the main storage unit 101 in response to a request from the cache memory unit 2 or the processor unit 3. The function of the access control unit 102 is a function of a general information processing apparatus.

  The ECC check unit 103 is a processing unit for realizing a generally known ECC (Error Collection Code). Here, there are no particular restrictions on the ECC (that is, the code) employed by the ECC check unit 103. The ECC check unit 103 receives data read from the main storage unit 101 from the access control unit 102, and performs error detection, data correction, and the like using ECC on the received data. Further, the ECC check unit 103 has a function of reporting the detected error. When the ECC check unit 103 does not detect an error, the ECC check unit 103 does not perform processing such as data correction. On the other hand, when the ECC check unit 103 detects a correctable error, the ECC check unit 103 performs data correction processing. When an uncorrectable error is detected, the ECC check unit 103 adds an ECC code (that is, an error correction code) to the data. The ECC check unit 103 notifies the poisoning unit 104 of the data and the detected failure type after executing error detection, data correction, and the like using the ECC.

  When the poisoning unit 104 receives data indicating that the failure type is “uncorrectable”, the poisoning unit 104 converts the ECC code added to the data into a poisoned code and supplies it to the cache unit 2. When data indicating that the failure type is other than “uncorrectable” is received, the poisoning unit 104 supplies the received data to the cache unit 2 as it is. The code used as the poisoning code may be any code as long as it can be identified as uncorrectable data.

  Next, the configuration of the cache unit 2 will be described. The cache unit 2 includes a store-in cache 201, an access control unit 202, an ECC check unit 203, a poisoning processing unit 204, a request control unit 205, and a cache flushing unit 206.

  The store-in cache 201 is a storage unit that holds cache data in the cache unit 2. There is no special restriction on the logical structure, physical structure, and cache hierarchy structure of the store-in cache 201, and it is sufficient to have a generally used mechanism. A cache storage unit other than the store-in type cache may be employed.

  The access control unit 202 is a processing unit that controls reading and writing of data from the store-in cache 201. The access control unit 202 accesses the access control unit 102 when there is no desired data in the store cache 201. The function of the access control unit 202 is a function of a general cache memory.

  When the access control unit 202 receives a request for cache flushing (hereinafter referred to as a “cache flush request”) from a cache flushing unit 206 (to be described later), the address to be flushed (hereinafter referred to as “cache flushing request”). It is described as a cache flush address). The access control unit 202 determines whether data exists at the cache flush address in the store-in cache 201. If there is no data at the cache flush address, the access control unit 202 ends the process. On the other hand, if there is data at the cache flush address, the access control unit 202 executes processing for discarding the cache contents or reflecting the cache contents in the main storage unit 101 according to the cache status. The cache status employed by the data failure processing apparatus according to this embodiment will be described later with reference to FIG.

  The ECC check unit 203 is a processing unit for realizing a generally known ECC (Error Collection Code). Here, there are no particular restrictions on the ECC code employed by the ECC check unit 203. Further, the ECC code employed by the ECC check unit 203 is independent of the ECC code employed by the ECC check unit 103, and does not need to be related.

  The ECC check unit 203 receives data read from the store-in cache 201 from the access control unit 202, and executes error detection, data correction, and the like using the ECC code for the received data. Further, the ECC check unit 203 has a function of reporting the detected error. When no error is detected, the ECC check unit 203 does not perform processing such as data correction. On the other hand, when a correctable error is detected, the ECC check unit 203 performs a data correction process. When an uncorrectable error is detected, the ECC check unit 203 adds an ECC code to the data. The ECC check unit 203 notifies the poisoning unit 204 of the data and the detected failure type after executing error detection, data correction, and the like using ECC.

  When the poisoning unit 204 receives data indicating that the failure type indicates “uncorrectable”, the poisoning unit 204 converts the ECC code added to the data into a poisoned code and supplies the poisoned code to the request control unit 205. When the data indicating that the failure type is other than “uncorrectable” is received, the poisoning unit 204 supplies the received data to the request control unit 205 as it is. The code used as the poisoning code may be any code as long as it can be identified as uncorrectable data.

  The request control unit 205 is a processing unit that processes a request received from the processor unit 3. The request control unit 205 issues a request to the access control unit 202 in order to access the main storage unit 101 via the access control unit 102 and access to the store-in cache 201. The request control unit 205 uses the data transmitted from the poisoning unit 104 (data read from the main storage unit 101) or the data transmitted from the poisoning unit 204 (data read from the store-in memory 201) as reply data. receive. The request control unit 205 supplies the received reply data to the processor unit 3 that is the request request source. When supplying data to the processor unit 3, the request control unit 205 outputs the ECC code for the data together with the data. The ECC code enables the processor unit 3 to determine whether an uncorrectable failure has occurred in the data.

  When the request control unit 205 receives a cache flush request from the access control unit 301 in the processor unit 3 to be described later, the request control unit 205 transfers the cache flush request to the cache sweep unit 205. The cache flush request includes a cache flush address (that is, an address that reflects data update in the main storage unit 101).

  When the cache flushing unit 206 receives a cache flushing request, the cache flushing unit 206 instructs the access control unit 202 to update the data of the cache flushing address to the main memory 101.

  Next, the configuration of the processor unit 3 will be described. The processor unit 3 includes a processor function unit (not shown), a request control unit 301, a failure processing unit 302, a failure identification unit 302, an FW (FirmWare: firmware) activation unit 303, and a cache flushing instruction unit 304. A pre-evaluation unit 305 and a repairability determination unit 306.

  The processor function unit (not shown) is a processing unit that performs normal calculation processing. This processor function unit (not shown) issues a request to data in the main storage unit 1 or the cache unit 2 as necessary.

  The request control unit 301 generates a request regarding access to the main storage unit 101 requested by the processor function unit, and outputs the request to the cache unit 2. The request control unit 301 receives reply data returned from the cache unit 2. Access to the main storage unit 101 includes a read operation and a write operation. In the case of a read operation, the request control unit 301 receives reply data from the cache unit 2.

  The request control unit 301 performs an ECC check using an ECC code attached to the reply data, and determines whether a failure has occurred in the reply data. When no failure has occurred in the data, the request control unit 301 supplies the data to the processor function unit and ends the process.

  When an uncorrectable failure has occurred in the data, the request control unit 301 does not supply the data to the processor function unit, and notifies the failure identification unit 302 of the occurrence of the failure and the address of the read request (read). The address of the main storage unit 101 to be issued is notified.

  Further, upon receiving a pre-evaluation read request (hereinafter referred to as a previous evaluation request) for evaluating the state of an uncorrectable failure from the pre-evaluation unit 305, the request control unit 301 receives the pre-evaluation request. Issue to cache system 2. When the request control unit 301 receives reply data for the prior evaluation request, the request control unit 301 performs an ECC check in the same manner as normal reply data, and notifies the repairability determination unit 306 of the failure occurrence status.

  In the present embodiment, the request control unit 301 is configured to issue a request to the cache unit 2. However, in a device that does not have the cache unit 2, the request control unit 301 may issue a request directly to the main storage unit 1. Good.

  The failure identification unit 302 receives from the request control unit 301 a notification notifying that a failure has occurred in the reply data and the address of the read request. Upon receipt of this, the failure identification unit 302 detects that an uncorrectable failure has occurred in the reply data. The failure identification unit 302 supplies a start instruction for executing failure processing to the FW activation unit 303 when an uncorrectable failure occurs. Along with this instruction, the failure identification unit 302 also notifies the FW activation unit 303 of the address of the read request.

  The FW activation unit 303 receives an activation instruction and a read request address from the failure identification unit 302. After the reception, the FW activation unit 303 discards the pending processing transaction. Then, the FW activation unit 303 instructs the cache flushing instruction unit 304 to generate a cache flushing request. At this time, the FW activation unit 303 notifies the cache flushing instruction unit 304 of the received read request address as a target address (cache flushing address) flushed from the cache.

  The reason why the cache needs to be flushed is that the uncorrectable data or poisoned data remaining in the cache is purged from the cache or discarded. This is to avoid a cache hit when the pre-evaluation unit 305 described later reads the main memory when these data remain in the cache.

  The FW activation unit 303 waits for processing until a completion notification is issued from the cache flushing instruction unit 304 after the cache flushing instruction unit 304 instructs the cache flushing instruction unit 304 to generate a cache flushing request. When the cache flush completion notification is made, the FW activation unit 303 notifies the pre-evaluation unit 305 of the address of the read request and instructs the pre-evaluation unit 305 to issue the pre-evaluation request. The FW activation unit 303 receives from the repairability determination unit 306 the availability of processor relief determined based on the reply data for the prior evaluation request issued by the prior evaluation unit 305. When receiving a notification that the processor relief is possible, the FW activation unit 303 instructs the failure processing unit 307 to indicate that the processor relief may be started. On the other hand, when the notification that the processor relief is impossible is received, the FW activation unit 303 instructs the failure processing unit 307 to deal with the failure without performing the processor relief.

  The cache flushing instruction unit 304 receives a cache flushing request generation instruction and a cache flushing address from the FW activation unit 303. The cache flushing instruction unit 304 generates a cache flushing request including the cache flushing address information and outputs it to the cache unit 2. The cache flushing instruction unit 304 waits until the completion of the cache flushing request is notified from the cache unit 2, and when the completion notification is made, notifies the FW activation unit 303 of the completion of the cache flushing.

  The pre-evaluation unit 305 receives a pre-evaluation instruction from the FW activation unit 303. The pre-evaluation unit 305 generates a pre-evaluation request using the address of the read request notified together with the pre-evaluation instruction, and issues the pre-evaluation request to the cache unit 2 via the request control unit 301. The purpose of executing this pre-evaluation request is to evaluate whether or not the uncorrectable failure has been resolved. Even when it is determined that the failure cannot be corrected by the ECC code, the failure is solved by shifting the timing depending on the type of the failure.

  The repairability determination unit 306 receives from the request control unit 301 the result of performing an ECC check on the prior evaluation request issued by the prior evaluation unit 305. If the result of the ECC check indicates that no data failure has occurred, the repairability determination unit 306 determines that the processor relief is possible. On the other hand, the repairability determination unit 306 determines that the processor relief is impossible when the result of the ECC check indicates that a data failure has occurred. The repairability determination unit 306 notifies the FW activation unit 303 of the availability of processor relief.

  The failure processing unit 307 is a processing unit that executes failure processing defined by the data failure processing apparatus. The failure processing unit 307 appropriately exchanges information with the firmware and performs failure processing. The failure processing unit 307 receives an activation instruction from the FW activation unit 303. At this time, the failure handling processing is switched based on the determination of whether or not the processor relief is possible by the repairability determination unit 306. When the processor relief cannot be performed, the failure processing unit 307 performs failure processing as a severe failure. When the processor relief is possible, the failure processing unit 307 performs a process for performing the processor relief after the processor check.

  Next, FIG. 2 shows a cache status adopted by the data failure processing apparatus according to this embodiment. Note that the cache status depends on the cache coherency control employed in each information processing apparatus.

  The cache status that the store-in cache 201 according to the present embodiment can take is any one of “I (Invalidate)”, “CE (Clean Exclusive)”, “CS (Clean Shared)”, and “DE (Dirty Exclusive)”. It is. “I” indicates a state in which no data exists on the cache. “CE” indicates a state in which the data registered in the cache matches the data stored in the main memory, and no copy exists in another cache. “CS” indicates a state in which the data registered in the cache matches the data stored in the main memory and a copy exists in another cache. “DE” indicates a state in which the data registered in the cache does not match the data stored in the main memory and does not exist in other caches. In the “DE” state, the latest data exists only in the cache.

  3 to 7 show the relationship between the failure occurrence location and the failure processing of the data failure processing apparatus according to the present embodiment. For example, in FIG. 3 (No. 1), when the processor unit 3 issues a read request and the data read from the cache unit 2 is poisoned at the time of a cache hit (CE / CS), the intermittent failure location Is L2 (cache), the relief from the failure is defined by discarding the L2 cache and then performing processor relief.

  With reference to FIG. 8, the outline of the process of the data failure processing apparatus according to the present embodiment will be described again. In the processor unit 3 according to the present embodiment, after the poisoning process by the cache unit 2 or the main storage unit 1, an uncorrectable failure is detected (failure identification unit 302), a cache is flushed (a cache flushing instruction unit 304, a cache The sweep-out unit 206), issuance of a prior evaluation request (pre-evaluation unit 305), and determination of whether processor relief is possible (reliefability determination unit 306).

  Next, effects of the data failure processing apparatus according to the present embodiment will be described. As described above, when an uncorrectable failure occurs in the data to be read, the processor unit 3 detects the failure and issues a request (pre-evaluation request) again to determine whether the failure has been resolved. Whether or not to perform processor relief is determined according to the determination result. As a result, it is possible to avoid performing the processor relief when the failure is still not resolved, and it is possible to suppress the occurrence of repeated failures.

  Furthermore, since the processes of the prior evaluation unit 306 and the repairability determination unit 306 described above are only data access and processing related to the determination of the access result, the processing load is very small.

  Furthermore, in the data failure processing apparatus according to the present embodiment, the above functions can be added without correcting the processing such as normal processor check and the mechanism of processor relief. For this reason, it is easy to apply the above-described functions (preliminary evaluation function or the like) to various systems.

  The characteristic part of the data processing apparatus according to this embodiment is illustrated in FIG. Even in this configuration, the processor unit 3 detects a failure that has occurred in the storage device, issues a request again, determines whether the failure has been resolved, and performs processor relief according to the determination result. It can be decided whether or not to do so. Thereby, it is possible to avoid the occurrence of a failure again at the time of processor relief.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 1 Main memory unit 101 Main memory part 102 Access control part 103 ECC check part 104 Poisoning part 2 Cache memory unit 201 Store-in cache 202 Access control part 203 ECC check part 204 Poisoning part 205 Request control part 206 Cache flushing part 3 Processor Unit 301 Request control unit 302 Failure identification unit 303 FW activation unit 304 Cache flushing instruction unit 305 Pre-evaluation unit 306 Relief availability determination unit 307 Failure processing unit

Claims (10)

A data failure processing apparatus comprising a processor for accessing data stored in a storage device having an error correction function,
The storage device gives an error correction code to data at the time of data supply,
The processor is
A failure identification unit for identifying whether or not a failure has occurred in the data supplied from the storage device based on the error correction code;
A pre-evaluation unit that issues a pre-evaluation request to access again the address where the failed data is stored;
A repairability determination unit that determines whether a processor relief can be executed according to a result of issuing the prior evaluation request;
A data failure processing apparatus comprising: a failure processing unit that performs a failure handling process according to the determination of the repairability determination unit.   The data failure processing apparatus according to claim 1, further comprising a firmware activation unit that discards a processing transaction in progress when the failure identification unit identifies the failure.   The data failure processing apparatus according to claim 1, further comprising a main storage unit and a cache memory unit as the storage device. The processor is
A cache flushing instruction unit for issuing a cache flush request to the cache memory unit, which is a request for sweeping data corresponding to the address from the cache memory unit before issuing the prior evaluation request; ,
The data failure processing apparatus according to claim 3, wherein the cache memory unit includes a cache flush unit that sweeps data in response to the cache flush request.   The data failure processing apparatus according to claim 4, wherein the pre-evaluation unit issues the pre-evaluation request after processing completion notification from the cache flushing unit is performed. A data failure processing method in a data failure processing apparatus comprising a processor for accessing data stored in a storage device having an error correction function,
The storage device gives an error correction code to data at the time of data supply,
The processor is
Identify whether or not a failure has occurred in the data supplied from the storage device based on the error correction code,
Issue a pre-evaluation request to re-access the address where the failed data is stored,
It is determined whether processor relief can be executed according to the issuance result of the prior evaluation request,
A data failure processing method for performing failure handling processing in accordance with determination of whether or not the processor relief can be executed.   The data failure processing method according to claim 6, wherein when the failure is identified, a processing transaction in progress is discarded.   8. The data failure processing method according to claim 6, further comprising a main storage unit and a cache memory unit as the storage device. The processor is
Before issuing the pre-evaluation request, issue a cache flush request to the cache memory unit, which is a request for sweeping data corresponding to the address from the cache memory unit,
9. The data failure processing apparatus according to claim 8, wherein the cache memory unit sweeps data in response to the cache flush request.   The data failure processing method according to claim 9, wherein the advance evaluation request is issued after the completion of the data sweeping process notification from the cache memory unit.

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