JP2011114568A - Signal sequence producing circuit, signal sequence producing method, signal sequence producing program, and communication system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal sequence producing circuit that can produce a large amount of well-discriminatable signal sequences even if the start of communication from a signal oscillating source is not clear and the circuit is used in a communication system in which a signal is provided thereto randomly. <P>SOLUTION: A signal sequence producing circuit 1A produces a plurality of M-sequences in which all combinations thereof are preferred pairs with each other when taking up two M-sequences from the plurality of M-sequences gives delays to the produced M-sequences respectively, makes exclusive OR on the M-sequences with delays, and outputs the resultant signal sequences. A delay provision means 1B provides delays in such a manner that all combinations of any two signal sequences taken up from the signal sequences have a relation in which at least one of differences between delays given to the identical M-sequences is made different from the other when producing a plurality of signal sequences where combinations of M-sequences are formed from the identical ones. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a signal sequence generation circuit, a signal sequence generation method, a signal sequence generation program and a signal sequence generation program for generating unique individual data (ID) for identification and authentication of articles and individuals, and communication using the generated individual data About the system.

Conventionally, there has been proposed a signal sequence generation circuit capable of generating a large amount of signal sequences having substantially the same characteristics as the M sequence (correlation is small and noise resistance is good) (see, for example, Patent Document 1).
In Patent Document 1, attention is paid to the fact that signal sequences generated by combining M sequences that are preferred pairs with each other become signal sequences having a small correlation with each other, and signal sequences are generated as shown below.
That is, the signal sequence generation circuit described in Patent Document 1 generates a plurality of M sequences that become preferred pairs with each other when viewed two by two. Then, the signal sequence generation circuit gives a delay to each of the plurality of generated M sequences, performs an exclusive OR operation on the plurality of M sequences to which the delay is added, and outputs a signal sequence after the calculation.

JP 2009-141893 A

However, the signal sequence generation circuit described in Patent Document 1 has the following problems.
That is, the value that can be taken by the delay amount when adding the delay is arbitrary (in the case of the order n, any value of 0 to 2 ⁿ −1), and therefore, the combination of a plurality of M sequences is the same. When an arbitrary two of a plurality of signal sequences are taken out and looked at, there are those in which all of the differences in delay amounts given to the same M sequence have the same value (a value other than 0).
Such two signal sequences are signals (signals having different phases only) whose order of signal generation is shifted.
When using the above signal sequence as individual data in a communication system, in a communication system in which the start of communication from a signal oscillation source such as a wireless tag is not clear and a signal is sent randomly, Since the start cannot be specified, the two signal sequences as described above may be determined as the same signal.

  It is an object of the present invention to provide a large number of signal sequences that can be distinguished well even when used in a communication system in which the start of communication from a signal oscillation source is not clear and signals are sent randomly. The present invention provides a signal sequence generation circuit, a signal sequence generation method, a signal sequence generation program, and a communication system using the above-described signal sequence.

The signal sequence generation circuit of the present invention is generated with M sequence generation means for generating a plurality of M sequences in which all combinations are preferred pairs when two M sequences are extracted from a plurality of M sequences and viewed. A delay adding unit that adds a delay amount to each of the plurality of M sequences; and an adding unit that performs an exclusive OR operation on the plurality of M sequences to which the delay amount is added and outputs a signal sequence after the calculation. When the delay adding unit generates a plurality of signal sequences in which a plurality of combinations of M sequences are the same, all combinations of any two signal sequences extracted from the plurality of signal sequences are the same. The delay amount is assigned so that at least one of the differences between the delay amounts assigned to the M series is different from the others.
Here, the relationship described above means a relationship in which not all of the differences between the delay amounts given to the same M series are equal. For this reason, examples of the relationship described above include a relationship in which all the differences are different, a relationship in which any one of the differences is different from the others, and the like.

In the present invention, when the delay providing means generates a plurality of signal sequences composed of the same combination of a plurality of M sequences, all combinations of any two signal sequences extracted from the plurality of signal sequences are all. The delay amount is given so as to satisfy the above-described relationship. For this reason, the signal generation device can generate a plurality of different signal sequences that are not the same signal (not different in phase only) even when the phase is changed.
Therefore, even when used in a communication system in which the start of communication from the signal oscillation source is not clear and signals are sent at random, it is possible to generate a large amount of signal sequences that can be distinguished well.

In the signal sequence generation circuit of the present invention, it is preferable that the delay adding unit applies the same delay amount to a predetermined M sequence in the plurality of signal sequences.
In the present invention, the delay adding means adds the same delay amount to one predetermined M sequence as described above, so that a plurality of combinations of M sequences are extracted from a plurality of signal sequences. All the combinations of arbitrary two signal sequences have the relationship described above.
For this reason, it is possible to generate a plurality of different signal sequences only by giving the same delay amount to one predetermined M sequence. Therefore, for example, as compared with a configuration in which delay amounts are given so that each difference between delay amounts given to the same M series has a different relationship, the processing load when assigning delay amounts can be reduced and simplified. A signal sequence generation circuit can be constructed with a simple configuration.

In the signal sequence generation circuit according to the present invention, the delay adding unit is configured so that all combinations of any two signal sequences extracted from the plurality of signal sequences are all differences between delay amounts added to the same M sequence. It is preferable to give a delay amount so that two of the predetermined relationships are different.
In the present invention, the delay adding means adds a delay amount as described above, whereby a combination of two arbitrary signal sequences extracted from a plurality of signal sequences in which a plurality of combinations of M sequences are the same. Are all in a relationship in which not all of the differences between the delay amounts given to the same M series are equal.
For this reason, it is possible to generate different signal sequences only by paying attention to only two of the differences between the delay amounts given to the same M sequence. Therefore, similarly to the above, it is possible to reduce the processing load when adding the delay amount, and it is possible to construct a signal sequence generation circuit with a simple configuration.

By the way, as described above, in the case of a configuration in which the same delay amount is given to a predetermined one M sequence in a plurality of signal sequences composed of the same combination of a plurality of M sequences, the one M sequence. The possible value of the delay amount given to the sequence is limited. For this reason, the number of signal sequences having substantially the same characteristics as the M sequence is reduced.
On the other hand, the delay amount given to each M sequence can be taken by giving the delay amount so that predetermined two of the differences between the delay amounts given to the same M sequence have different relationships. The value is not limited. For this reason, it is possible to generate a sufficiently large number of signal sequences having substantially the same characteristics as the M sequence.

The signal sequence generation method of the present invention generates a plurality of M sequences in which all combinations are preferred pairs when two M sequences are extracted from a plurality of M sequences and viewed. A signal sequence generation method in which a delay amount is assigned, an exclusive OR operation is performed on a plurality of M sequences to which a delay amount is added, and a signal sequence after the computation is output, and the combinations of the plurality of M sequences are the same When generating a plurality of signal sequences consisting of a plurality of signal sequences, combinations of any two signal sequences extracted from the plurality of signal sequences are all at least of the differences between the delay amounts provided to the same M sequence. It is characterized in that a delay amount is given so that one is different from the other.
In the signal sequence generation method of the present invention, as in the above-described signal sequence generation circuit, when generating a plurality of signal sequences consisting of the same combination of a plurality of M sequences, an arbitrary sequence extracted from the plurality of signal sequences Since all the combinations of the two signal sequences give the delay amount so as to have the relationship described above, the same operations and effects as those of the signal sequence generation circuit described above can be enjoyed.

The signal sequence generation program of the present invention causes a computer to execute the signal sequence generation method described above.
Since the signal sequence generation program of the present invention is used to implement the above-described signal sequence generation method, it can enjoy the same operations and effects as the above-described signal sequence generation method.

The communication system according to the present invention is characterized in that the signal sequence generated by the signal sequence generation circuit described above is used as individual data.
Since the communication system of the present invention uses the signal sequence generated by the signal sequence generation circuit described above as individual data, the start of communication from the signal oscillation source is not clear, so that signals are sent randomly. Even when configured with a simple communication system, it is possible to transmit and receive individual data with good discrimination without overlapping individual data.
That is, in order to clarify the start of communication from the signal oscillation source, it is not necessary to employ a communication system that synchronizes between the signal oscillation source and the reading device that reads individual data, and the configuration of the communication system is simplified. Can be planned.

The block diagram which shows the structure of the separate data writer in 1st Embodiment. The block diagram which shows the structure of the signal series production | generation part in 1st Embodiment. The block diagram which shows the model of the M series production | generation main body and variable delay device in 1st Embodiment. The figure which shows the relationship between the order n of the M series in 1st Embodiment, and the maximum number H of the M series which become a mutually preferred pair. The figure which shows the characteristic polynomial of the maximum number of M series which becomes an M series of order 7 in 1st Embodiment, and becomes a preferred pair mutually. The block diagram which shows the structure of the communication system in 1st Embodiment.

[First embodiment]
DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a first embodiment of the invention will be described with reference to the drawings.
[Configuration of individual data writing device]
FIG. 1 is a block diagram showing a configuration of the individual data writing device 1.
The individual data writing device 1 is a device that generates a signal sequence having substantially the same characteristics as the M-sequence and writes the generated signal sequence to a blank wireless tag as individual data.
As shown in FIG. 1, the individual data writing device 1 includes a management number / delay data conversion unit 2, a signal sequence generation unit 3, an individual data writing unit 4, a data association storage unit 5, And a control unit 6 for controlling the individual data writing device 1 as a whole.

The management number / delay data conversion unit 2 sets a management number given from the control unit 6 to a later-described delay data group R0 when a blank wireless tag in which individual data is not stored is newly written. Are converted into .about.Rr and given to the signal sequence generator 3.
Although specifically described later, the signal sequence generation unit 3 generates a signal sequence having substantially the same characteristics as the M sequence based on the delay data group provided from the management number / delay data conversion unit 2. Is.
The management number / delay data conversion unit 2 and the signal sequence generation unit 3 correspond to the signal sequence generation circuit 1A (FIGS. 1 and 2) according to the present invention.

  The individual data writing unit 4 writes the signal sequence (individual data) generated by the signal sequence generation unit 3 into a blank wireless tag. The individual data writing unit 4 is not specifically shown, but is a first storage unit that stores a blank wireless tag, and a feeding mechanism that feeds out one wireless tag from the first storage unit and sets it to a writing position. , A writing execution unit for writing individual data to a blank wireless tag set at the writing position, a second storage unit for storing the wireless tag to which the individual data is written, and a writing position for the wireless tag to which the individual data is written It is preferable to provide a moving mechanism unit or the like that moves from the first storage unit to the second storage unit.

  The data association storage unit 5 stores the delay data group (or management number) and the generated individual data in association with each other. The stored association data is used for identification or authentication by a data processing system that processes data from a wireless tag, such as a manufacturing process automation system or a distribution system. Note that the system may use the generated individual data as an ID, or may use a delay data group (or management number) as an ID.

[Configuration of signal sequence generator]
FIG. 2 is a block diagram showing a configuration of the signal sequence generation unit 3.
As shown in FIG. 2, the signal sequence generation unit 3 is exclusive of M sequences from r + 1 M sequence generation units 10-0 to 10-r and all M sequence generation units 10-0 to 10-r. And an exclusive OR circuit 11 as addition means for taking an OR (Exclusive OR).

Each M-sequence generation unit 10-0 to 10-r includes an M-sequence generation body 20-0 to 20-r as an M-sequence generation unit, and variable delay devices 21-0 to 21-r.
The management number / delay data converter 2 and the variable delay devices 21-0 to 21-r correspond to the delay applying means 1B (FIGS. 1 and 2) according to the present invention.
The M sequence generation bodies 20-0 to 20-r generate M sequences according to characteristic polynomials f ₀ (x) to f _r (x) having different orders, respectively, and n-stage shift registers SR0 to SRr, It has a well-known configuration including one or a plurality of exclusive OR circuits ExOR01 to ExORr1 that take an exclusive OR of the output of the stage determined by the characteristic polynomial.

  In the present embodiment, the r + 1 M sequences generated by the M sequence generation bodies 20-0 to 20-r are all in a preferred pair relationship. Here, for M sequences, a pair of M sequences in which the maximum value of the cross-correlation function between the M sequences of the same order and the M sequences having different characteristic polynomials is referred to as a preferred pair.

  The variable delay devices 21-0 to 21-r delay the M sequences generated by the corresponding M sequence generation bodies 20-0 to 20-r by the instructed amount and give the delayed delays to the exclusive OR circuit 11, respectively. It is. The delay amounts in the variable delay devices 21-0 to 21-r are not necessarily the same, and the combination of these delay amounts is one parameter that defines the uniqueness of the individual data generated by the signal sequence generation unit 3 It has become.

In the case of this embodiment, the variable delay devices 21-0 to 21-r are respectively associated with the corresponding M-sequence generation bodies 20 so that a delay amount shorter than the M-sequence period 2 ⁿ -1 can be given with a simple configuration. The exclusive OR of the outputs of the multiplier groups D0 to Dr that multiply the values of the respective stages of the shift registers SR0 to SRr in −0 to 20-r by the set values and the outputs of the corresponding multiplier groups D0 to Dr And exclusive OR circuits ExOR02 to EXORr2.

The n pieces of data set in the multiplier groups D0 to Dr are delay data R0 to Rr given from the management number / delay data converter 2. For example, delay data R0 {r _0,0 ,..., R _{0, n−1} } is set in the multiplier group D0.

  The signal sequence generation unit 3 described above may be configured as hardware, or may be configured as software in which functions are realized by a CPU executing a signal sequence generation program. Good.

[Method of delaying M sequence]
FIG. 3 is a block diagram illustrating models of the M-sequence generation main body and the variable delay device.
Next, it will be described with reference to FIG. 3 that the variable delay devices 21-0 to 21-r can be realized by the arithmetic configuration as shown in FIG.
If an M-sequence is given an initial state of the n-stage shift register SR, all subsequent states are determined. Therefore, the M-sequence X ^d delayed by an arbitrary delay amount d is determined at each stage of the shift register SR. It can be seen that the content x ₀ ,..., X _n−1 is given by a linear combination represented by the following expression (1).

The coefficient r _i (i is 0 to (n−1)) is “0” or “1”. If the coefficient r _i is known, it can be determined which stage of the shift register SR should be added.
The delay amount d can take a value in a range shorter than one cycle 2 ⁿ⁻¹ of the M sequence, and can take a value smaller than the number n of stages of the shift register SR, or can take a number n or more.

When the delay amount d is smaller than the number n of stages of the shift register SR, the delayed M series can be extracted from the stage j corresponding to the delay amount d of the shift register SR. In this case, only the coefficients r _j for content x _j of that stage j is "1", it may be set to all of the coefficients for the contents of the other stages "0".
Consider a case where the delay amount d is greater than or equal to the number n of stages of the shift register SR. When the delayed M sequence ^Xd is divided by the characteristic polynomial f (x) related to the M sequence generation main body, the following equation (2) is established. In Equation (2), Q (x) is a quotient and R (x) is a remainder polynomial.

  Pay attention to the right side of the equation (2). Here, the degree of the remainder polynomial R (x) is smaller than n, and the degree part entrusted to the remainder polynomial R (x) in Q (x) f (x) is zero. Here, considering the same order as the right side of the above equation (1), the above equation (2) can be written as the following equation (3).

From the comparison between the above equations (1) and (3), the coefficient of the remainder polynomial R (x) becomes r _{0 to} r _n−1 for forming the M sequence X ^d delayed by the delay amount d. ing. That is, in order to form the M sequence X ^d delayed by the delay amount d, the coefficient of the remainder polynomial R (x) obtained by dividing X ^d by the characteristic polynomial f (x) may be extracted.

[Operation of individual data writing device]
Next, the operation of the individual data writing device 1 described above will be described.
When a new blank wireless tag becomes a write target, the control unit 6 sets initial values in all the shift registers SR0 to SRr of the signal series generation unit 3 and manages the management number related to the write target wireless tag. This is given to the number / delay data converter 2. Then, the management number / delay data conversion unit 2 converts the management number into the delay data groups R0 to Rr and sets them in the multiplier groups D0 to Dr of the signal sequence generation unit 3.

When such initialization processing ends, the control unit 6 causes the signal sequence generation unit 3 to start an operation based on the clock.
The M sequence generation body 20-0 of the M sequence generation unit 10-0 rewrites the contents of the stage of the shift register SR0 for each clock. The multiplier group D0 of the variable delay device 21-0 multiplies the contents of the stage of the shift register SR0 by the set value of the delay data group R0, and the multiplication result is added by the exclusive OR circuit ExOR02 ( And is output as an M series a ₀ (j + d ₀ ) delayed by a delay amount corresponding to the value of the delay data group R0.
The other M sequence generation units 10-1 to 10-r operate in the same manner, and output delayed M sequences a ₁ (j + d ₁ ) to a _r (j + d _r ).

The exclusive OR circuit 11 adds (exclusive OR) the delayed M sequences a ₀ (j + d ₀ ) to a _r (j + d _r ) from all the M sequence generators 10-0 to 10 -r. The signal sequence after the calculation is output.

[Signal generation concept]
FIG. 4 is a diagram showing the relationship between the order n of the M sequence and the maximum number H of M sequences that are preferred pairs.
In FIG. 4, suppose that the largest set (the number of elements is H) of a pair that is a preferred pair with each other is used for signal generation, a larger number of signal sequences can be generated as n × H is larger.
For example, if there are r combinations in which the maximum value of collective elements that are preferred pairs is H, the total number of signal sequences that can be generated is r × 2 ^{n × H.}

FIG. 5 is a diagram illustrating the maximum number of M-sequence characteristic polynomials that are preferred pairs in the M-sequence of order 7.
In the following, a method for generating a signal sequence will be described by taking the order 7 as an example where the number of signal sequences that can be generated is large (n × H is large).
For degree 7, the total number of characteristic polynomials is 18, and when 6 (maximum value H) are selected from these, the combinations in which any of them is a preferred pair are 18 as shown in FIG. I know.

In addition, the value which prescribes | regulates the characteristic polynomial in FIG. 5 is octal display, and represents the following. The order is not 7, but the case of characteristic polynomial f (x) = 1 + x ⁴ + x ⁵ + x ⁶ + x ⁸ is taken as an example. In this case, if each power coefficient is expressed by 0 and 1, and only the coefficient is extracted and expressed, the characteristic polynomial f (x) can be expressed as f (x) = 1000011101 (binary number). When such binary display is changed to octal display, the characteristic polynomial f (x) can be expressed as f (x) = 435 (octal number). FIG. 5 applies such octal display.

6 are configured in the signal sequence generation unit 3 of FIG. 2 so as to select one of the 18 sets of FIG. 5 and follow the six characteristic polynomials f ₀ (x) to f ₅ (x) of the set. 7th-order M-sequence generators 10-0 to 10-5 are formed. The delay data groups R0 to R5 are also obtained by using the selected set of six characteristic polynomials f ₀ (x) to f ₅ (x).
Since the number of M sequence generation units 10-0 to 10-5 is 6, the signal sequence C _k (j) generated when the 7th order M sequence is used is expressed by the following equation (4). become.
In Expression (4), a _{0 to} a ₅ indicate M series according to the characteristic polynomial f ₀ (x) to f ₅ (x), and d _{0 to} d ₅ correspond to the values of the delay data groups R0 to R5. Shows the amount of delay.

Further, by performing the same processing as described above for the other 17 groups in 18 groups in FIG. 5, it is possible to generate a large number of signal sequences with less interference and good noise resistance.
For example, in the case of degree 7 as in the above example, there are 18 combinations of 6 M-sequences in which any pair among them is selected from 18 characteristic polynomials, and any of them is a preferred pair, and , in the case where the possible values of delay _d 0 to d ₅ and ^{2 seven} 0-127, respectively, so that the signal sequences 18 × 2 ^{7 ×} be ^six product.

[Method of giving delay amount]
By the way, if the values that each delay amount can take are arbitrary (in the case of order n, any value from 0 to 2 ⁿ −1), a plurality of signal sequences composed of the same combination of a plurality of M sequences. When any two of them are taken out and looked at, there are those in which all the differences in the delay amounts given to the same M-sequence have the same value (a value other than 0).
Specifically, for example, when order 7 is described as an example, one signal sequence of the two extracted signal sequences is a signal sequence C _k (j) given by the above equation (4), and the other signal sequences are When the signal sequence C _k ′ (j) given by the following equation (5) is used, the signal sequences C _k (j) and C _k ′ (j) satisfy the relationship of the following equation (6). Exists.
In equations (5) and (6), d ₀ ′ to d ₅ ′ indicate delay amounts to be assigned to the M sequences of a _{0 to} a ₅ in the signal sequence C _k ′ (j), respectively. In Expression (6), δ represents a value that does not include 0 (in the case of 0, C _k (j) and C _k ′ (j) are the same signal sequence).

Thus, the signal sequences C _k (j) and C _k ′ (j) satisfying the relationship of the above expression (6) are C _k (0) = C _k ′ (δ) and C _k (1) = C _k ′. (1 + δ), C _k (2) = C _k ′ (2 + δ).
When using a signal sequence as described above as individual data in a communication system, the start of communication from the wireless tag is not clear, and in a communication system in which signals are sent randomly, the start of the signal is specified. Can not. For this reason, the signal sequences C _k (j) and C _k ′ (j) may be determined as the same signal.

Therefore, in the present embodiment, when the delay adding unit 1B generates a plurality of signal sequences in which a combination of a plurality of M sequences is the same, from the two arbitrary signal sequences extracted from the plurality of signal sequences. All the combinations are assigned delay amounts so that at least one of the differences between the delay amounts assigned to the same M-sequence is different from the others. In other words, for example, in the case of degree 7, the delay providing means 1B uses the same signal sequence C _k (j), C that is composed of the same combination of the six M sequences given by the equations (4) and (5). _{When k} ′ (j) is generated, a delay amount is given so as not to satisfy the relationship of the above formula (6).

Specifically, the delay adding unit 1B applies the same delay amount to a predetermined M sequence in a plurality of signal sequences in which a plurality of combinations of M sequences are the same.
That is, for example, in the case of the degree 7, the delay providing unit 1B generates one M of the M sequences a _{0 to} a ₅ when generating the signal sequences C _k (j) and C _k ′ (j) described above. By assigning the same delay amount to the sequence a ₀ and setting d ₀ = d ₀ ′, the above equation (6) is not satisfied. At the same time, the delay applying means 1B provides each difference between the delay amounts to be applied to the other M sequences a _{1 to} a ₅ so that the signal sequences C _k (j) and C _k ′ (j) do not become the same signal sequence. Gives a delay amount so as not to satisfy the relationship of the following equation (7).
As the one M-sequence to impart the same delay amount is not limited to a _0, it may be a a ₁ ~a _5.

A specific delay amount assigning method is implemented by the management number / delay data conversion unit 2 and the variable delay units 21-0 to 21-r constituting the delay assigning means 1B described above. .
That is, the management number / delay data converter generates d ₀ = d ₀ ′ when the signal sequences C _k (j) and C _k ′ (j) having the same combination of the six M sequences are generated, and The delay data groups R0 to R5 are respectively calculated using the characteristic polynomials f ₀ (x) to f ₅ (x) so as not to satisfy the relationship of the above expression (7) (the above [Method of delaying M-sequence] ]).
The variable delay 21-0～21-5 the delay amount _d 0 _{to d} of the M-sequence _a 0 ~a ₅ corresponding to the value of the delay data group R0~R5 _5, d 0'~d 5 ' Just delay.

[Configuration of communication system]
FIG. 6 is a block diagram illustrating a configuration of a communication system that performs communication with the wireless tag in which the individual data is written by the individual data writing device 1.
The communication system 30 includes a wireless tag 31, a wireless tag reader 32, and a host device 33.

  The wireless tag 31 is written with individual data by the individual data writing device 1 described above, and is attached to an article or an individual for management of identification or authentication of the article or an individual, or possessed by an individual. It is something to do. The wireless tag 31 receives a query signal from the loop-shaped transmitting / receiving antenna 40, an individual data memory 41 that records individual data, a control unit 42 that controls the operation of the wireless tag 31, and the wireless tag reader 32. And a transmission / reception unit 43 for transmitting the individual data read from the individual data memory 41 by the control unit 42.

  For example, a resonance circuit (for example, an LC resonance circuit) that resonates with the carrier frequency of the interrogation signal is configured by the loop-shaped transmission / reception antenna 40 and a part of the constituent elements of the transmission / reception unit 43 or the control unit 42. An operating power supply for the tag 31 is obtained. The individual data memory 41 is preferably a nonvolatile memory. The digital modulation method between the wireless tag 31 and the wireless tag reader 32 is not limited. For example, an ASK (amplitude shift keying) modulation method, an FSK (frequency shift keying) modulation method, and a PSK (phase shift keying) modulation method are used. Applicable.

The wireless tag reader 32 radiates a question signal to its surroundings under the control of the host device 33 and acquires individual data of the wireless tag 31 existing in the vicinity of the wireless tag reader 32. The wireless tag reader 32 digitally modulates the non-directional or directional transmission / reception antenna 50, the duplex unit 51 that separates the transmission system and the reception system, and the baseband interrogation signal given from the control unit 54 to the duplex unit 51. A transmitting unit 52 for giving, a receiving unit 53 for converting a received signal from the duplex unit 51 to a baseband signal, and further converting to a binary (digital value) signal; A control unit 54 for identifying individual data assigned to the wireless tag 31 existing in the vicinity, a delay data group (or management number) similar to the data association storage unit 5 described above, and individual data And a reference database 55 that stores association information.
The wireless tag reader 32 may include at least the transmission / reception antenna 50, the transmission unit 52, the reception unit 53, and the control unit 54.

With the above configuration, the control unit 54 acquires the individual data assigned to the wireless tag 31 existing in the vicinity via the receiving unit 53, and then stores the individual data and the reference database 55. The individual data is identified by obtaining a correlation value with the individual data.
Then, after completing the identification process, the control unit 54 sends the identified individual data (having a correlation value equal to or greater than a threshold value) to the host device 33.
In the above, the wireless tag reader 32 executes the process of identifying individual data from the received baseband signal. However, the host apparatus 33 may execute the process of identifying individual data. .

The first embodiment described above has the following effects.
In the present embodiment, for example, in the case of degree 7, the delay adding unit 1B generates a plurality of signal sequences having the same combination of six M sequences, and any two of the plurality of signal sequences are generated. When C _k (j) and C _k ′ (j) are extracted and viewed, a delay amount is given so as not to satisfy the relationship of the above expression (6). For this reason, a plurality of signal sequences having the same combination of the six M sequences can be signal sequences that do not become the same signal even if the phase is changed (the signals are not different only in phase). it can.
Therefore, even when used in the communication system 30 in which the start of communication from the wireless tag 31 is not clear and signals are sent at random, it is possible to generate a large amount of signal sequences that can be distinguished well.

The delay imparting section 1B, for example, in the case of order 7, by giving the same delay amount to a single M-sequence a _0, a plurality of signal series combination of a plurality of M sequences of the same thing When two arbitrary C _k (j) and C _k ′ (j) are taken out and viewed, the relationship of the above formula (6) is not satisfied.
For this reason, it is possible to generate a plurality of different signal sequences only by giving the same delay amount to one predetermined M sequence. Therefore, for example, compared with the configuration in which the delay amount is given so that the differences between the delay amounts given to the same M series are all different, the management number / delay for calculating the delay data group The processing load on the data converter 2 can be reduced, and the signal sequence generation circuit 1A can be constructed with a simple configuration.

In addition, since the communication system 30 uses the signal sequence generated by the signal sequence generation circuit 1A as individual data, the start of communication from the wireless tag 31 is not clear and signals are sent randomly. Even when the communication system is configured, it is possible to transmit / receive individual data with good discrimination without overlapping individual data.
That is, in order to clarify the start of communication from the wireless tag, it is not necessary to employ a communication system that synchronizes between the wireless tag and the wireless tag reader, and the configuration of the communication system can be simplified.

[Second Embodiment]
Next, a second embodiment of the present invention will be described.
In the following description, the same structure and the same member as those in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted or simplified.
The present embodiment is different from the first embodiment only in the delay amount providing method by the delay providing means 1B.

Specifically, when the delay adding unit 1B of the present embodiment generates a plurality of signal sequences in which a plurality of combinations of M sequences are the same, any two signal sequences extracted from the plurality of signal sequences Delay amounts are assigned so that a predetermined two of the differences between the delay amounts assigned to the same M series are different from each other.
In other words, for example, in the case of degree 7, the delay providing means 1B uses the same signal sequence C _k (j), C that is composed of the same combination of the six M sequences given by the equations (4) and (5). when generating _k 'a (j), a delay amount to impart the difference in delay amount between given to the M-sequence _a 0 ~a 1 single M sequence _{a 0} predetermined _five, the one of the other M-sequences _{a 1} It is assumed that the relationship of the above formula (6) is not satisfied by giving a delay amount so that the difference between them is different and d ₀ −d ₀ ′ ≠ d ₁ −d ₁ ′.
The predetermined two combinations are not limited to d ₀ -d ₀ ′ and d ₁ -d ₁ ′, but are d ₀ -d ₀ ′, d ₁ -d ₁ ′, d ₂ -d ₂ ′, d _3. A combination of any two of −d ₃ ′, d ₄ −d ₄ ′, and d ₅ −d ₅ ′ may be adopted.

According to the second embodiment described above, there are the following effects in addition to the same effects as in the first embodiment.
In the above configuration of the first embodiment, for example, if the order is 7, since the possible value of the delay amount to be added to the M-sequence a ₀ of the M sequence a ₀ ~a ₅ is limited, the conventional configuration Then, when 18 × ^{27 × 6} signal sequences having substantially the same characteristics as the M sequence have been generated, the number of generations is limited to 18 × ^{27 × 5} .
On the other hand, in the present embodiment, the delay providing unit 1B provides the delay amount so that the predetermined two of the differences between the delay amounts to be applied to the same M series are different from each other. The possible value of the delay amount given to the M series is not limited. For this reason, it is possible to generate a sufficiently large number of signal sequences having substantially the same characteristics as the M sequence.

It should be noted that the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.
In each of the embodiments described above, the method of assigning the delay amount when generating a plurality of signal sequences having the same combination of a plurality of M sequences is not limited to the method described in the above embodiments. Other methods such as, for example, a method of granting the differences so that all the differences are different from each other, if all the differences between the delay amounts given to the same M series are not equal. May be adopted.

  In each of the above-described embodiments, the signal series generation circuit 1A of the present invention is applied to the individual data writing device 1 of the wireless tag. However, the application is not limited to this. For example, the signal sequence generation circuit 1A of the present invention can be applied to a device on the authentication side. For example, authentication or identification is performed by inputting a password or ID consisting of a delay data group from a keyboard or the like, and comparing a signal sequence generated from the input delay data group with a signal sequence read from a wireless tag. It may be. Further, for example, a signal sequence to be described as a barcode may be generated by the signal sequence generation circuit 1A of the present invention.

  In each of the above-described embodiments, the variable delay units 21-0 to 21-r include the multiplier groups D0 to Dr and the exclusive OR circuits ExOR02 to EXORr2, but other variable delay configurations are applied. It may be. For example, if the range of the delay amount is narrow, a configuration in which a delay shift register and an output of an arbitrary stage of the delay shift register are taken out may be a variable delay configuration.

In each of the above embodiments, the maximum number (H) of M sequences that are preferred pairs with each other is generated and added with a delay, but the number of M sequences generated is determined from the maximum number (H). The number of occurrences may be reduced, and the number of occurrences may be variable.
The wireless tag used in the present invention is not particularly limited, and a tag that incorporates a battery and transmits radio waves by itself, or a tag that exchanges data by using external radio waves can be used. Furthermore, the thing using electromagnetic induction, the thing using a radiated electromagnetic field, etc. can be used. Examples of the electric circuit (antenna circuit) in the wireless tag include a coil shape and a dipole type.
The communication system of the present invention is not limited to the communication system 30. For example, the present invention can be applied to a communication system that reads and processes a signal sequence from a barcode.

  The present invention can be used in a signal sequence generation circuit that generates individual data with good discrimination for identification and authentication of articles and individuals.

  DESCRIPTION OF SYMBOLS 1A ... Signal sequence generation circuit, 1B ... Delay imparting means, 11 ... Exclusive OR circuit (adding means), 20-0 to 20-r ... M sequence generation body (M sequence generation means) ), 30... Communication system.

Claims (6)

M sequence generation means for generating a plurality of M sequences in which all combinations are preferred pairs when two M sequences are taken out from a plurality of M sequences,
A delay adding means for adding a delay amount to each of the plurality of generated M sequences;
An addition means for performing an exclusive OR operation on a plurality of M sequences to which a delay amount is given and outputting a signal sequence after the operation;
The delay giving means is
When generating a plurality of signal sequences composed of the same combination of a plurality of M sequences, all of the combinations composed of any two signal sequences extracted from the plurality of signal sequences are given to the same M sequence. A signal sequence generation circuit, characterized in that a delay amount is provided so that at least one of the differences between the amounts is different from the others. The signal sequence generation circuit according to claim 1,
The delay giving means is
In the plurality of signal sequences, the same delay amount is given to one predetermined M sequence. The signal sequence generation circuit according to claim 1,
The delay giving means is
All combinations of two arbitrary signal sequences extracted from the plurality of signal sequences are given delay amounts so that two of the differences between the delay amounts given to the same M sequence are different from each other. A signal sequence generation circuit characterized by: When two M-sequences are extracted from a plurality of M-sequences, a plurality of M-sequences in which all combinations are preferred pairs are generated, and a delay amount is assigned to each of the generated M-sequences. A signal sequence generation method for performing an exclusive OR operation on a plurality of M sequences to which a quantity is added and outputting a signal sequence after the operation,
When generating a plurality of signal sequences composed of the same combination of a plurality of M sequences, all of the combinations composed of any two signal sequences extracted from the plurality of signal sequences are given to the same M sequence. A signal sequence generation method characterized by assigning a delay amount so that at least one of the differences between the amounts is different from the others. A signal sequence generation program causing a computer to execute the signal sequence generation method according to claim 4. A communication system using the signal series generated by the signal series generation circuit according to any one of claims 1 to 3 as individual data.