JP2010272593A - Nitride semiconductor light emitting element and manufacturing method of the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor light emitting element sufficiently suppressing overflow of electrons from an active layer to a clad layer, and also to provide a method for manufacturing the element. <P>SOLUTION: The nitride semiconductor light emitting element 1 is provided with an active layer I, a p-type clad layer L prepared at one side of the active layer I, a p-type electron block layer K prepared between the p-type clad layer L and the active layer I, and a second guide layer J prepared between the active layer I and the p-type electron block layer K. The active layer I, the p-type clad layer L, the p-type electron block layer K, and the second guide layer J contain a group III nitride system semiconductor. While a part of the second guide layer J located on the side of the p-type electron block layer K includes p-type impurity, it forms hetero junction with the p-type electron block layer K. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a nitride semiconductor light emitting device and a method for manufacturing the same.

  In order to improve the characteristics and reliability of semiconductor laser diodes (LDs) and light-emitting diodes (LEDs) using group III nitride semiconductors (GaN, AlN, InN or mixed crystals thereof), the active layer is changed to a cladding layer. It is important to suppress the overflow of electrons. As a method of suppressing overflow of electrons from the active layer to the cladding layer, a method of providing an electron block layer having a relatively large band gap between the guide layer and the cladding layer on the active layer is used. However, in Group III nitride semiconductors, a large internal electric field due to piezoelectric polarization and spontaneous polarization occurs at the boundary between the guide layer and the electron blocking layer, and the barrier against electrons, that is, the effective height of the barrier due to the electron blocking layer. Cannot be obtained.

  In order to solve this problem, in the invention described in the cited document 1, an intermediate layer made of AlGaInN is provided between the guide layer and the electron blocking layer.

  In the invention described in the cited document 1, by providing an intermediate layer made of AlGaInN, lattice mismatch at the interface between the electron block layer and the intermediate layer is alleviated, and a decrease in the barrier height due to the electron block layer is suppressed.

JP 2007-142038 A

  However, spontaneous polarization that lowers the height of the barrier due to the electron block layer occurs inside the AlGaInN intermediate layer, and the decrease in the height of the barrier due to the electron block layer cannot be sufficiently suppressed. Therefore, the overflow of electrons from the active layer to the cladding layer cannot be sufficiently suppressed.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a nitride semiconductor light emitting device capable of sufficiently suppressing an overflow of electrons from an active layer to a cladding layer and a method for manufacturing the same. To do.

  The nitride semiconductor light emitting device according to the present invention includes an active layer, a p-type cladding layer provided on one side of the active layer, a p-type electron blocking layer provided between the p-type cladding layer and the active layer, A guide layer provided between the active layer and the p-type electron block layer, the active layer, the p-type cladding layer, the p-type electron block layer, and the guide layer including a group III nitride semiconductor, A portion of the layer located on the p-type electron block layer side includes a p-type impurity and forms a heterojunction with the p-type electron block layer.

  In the nitride semiconductor light emitting device according to the present invention, a portion of the guide layer located on the p-type electron block layer side includes a p-type impurity and forms a heterojunction with the p-type electron block layer. With this configuration, an internal electric field in which piezo polarization and spontaneous polarization are synthesized in the guide layer and the p-type electron block layer can be relaxed. Therefore, the height of the barrier due to the p-type electron blocking layer caused by the spontaneous polarization in the crystal of the guide layer and the p-type electron blocking layer as well as the piezo polarization generated at the heterointerface between the guide layer and the p-type electron blocking layer. Can also be suppressed. Therefore, the overflow of electrons from the active layer to the p-type cladding layer can be sufficiently suppressed.

  In addition, it is preferable that a p-type impurity is not intentionally added to a portion of the guide layer located on the active layer side. Thereby, absorption of light by the impurity level in the guide layer on the active layer side can be avoided. Further, since the diffusion of the p-type impurity into the active layer can be suppressed, the generation of crystal defects in the active layer due to the p-type impurity is suppressed. As a result, a decrease in light emission characteristics is suppressed.

  The nitride semiconductor light emitting device of the present invention preferably further includes a p-type contact layer provided on the p-type cladding layer and an n-type contact layer provided on the other side of the active layer. . Thereby, since a contact resistance with the electrode layer provided on each can be reduced, a bias voltage can be applied effectively.

  The method for manufacturing a nitride semiconductor light emitting device according to the present invention includes a step of forming a guide layer on a substrate, a step of forming a p-type electron block layer on the guide layer, and a p-type cladding on the p-type electron block layer. Forming a layer, wherein the guide layer, the p-type electron blocking layer, and the p-type cladding layer include a group III nitride semiconductor, and in the guide layer forming step, no p-type impurity is supplied at an initial stage. In the final stage, crystal growth is performed while supplying a p-type impurity, and a heterojunction is formed between the p-type electron blocking layer and a portion where the crystal is grown while supplying the p-type impurity in the guide layer forming step. .

  In the method for manufacturing a nitride semiconductor light emitting device according to the present invention, in the guide layer forming step, crystal growth is performed without supplying p-type impurities in the initial stage, and crystal growth is performed while supplying p-type impurities in the final stage. Do. Further, in the guide layer forming step, a portion where the crystal has grown while supplying the p-type impurity and the p-type electron block layer form a heterojunction. Therefore, it is possible to easily manufacture a nitride semiconductor light emitting device that can sufficiently suppress the overflow of electrons from the active layer to the cladding layer.

  The nitride semiconductor light emitting device of the present invention can sufficiently suppress the overflow of electrons from the active layer to the cladding layer, and the manufacturing method of the present invention can sufficiently suppress the overflow of electrons from the active layer to the cladding layer. A simple nitride semiconductor light emitting device can be easily manufactured.

1 is a cross-sectional view of a nitride semiconductor light emitting device according to a first embodiment. It is a figure which shows the process of manufacturing the nitride semiconductor light-emitting device concerning 1st Embodiment. It is a figure which shows the process of manufacturing the nitride semiconductor light-emitting device concerning 1st Embodiment. It is a figure which shows the process of manufacturing the nitride semiconductor light-emitting device concerning 1st Embodiment. It is sectional drawing of the conventional nitride semiconductor light-emitting device. It is a figure for demonstrating the effect of the nitride semiconductor light-emitting device concerning 1st Embodiment. It is a figure for demonstrating the effect of the nitride semiconductor light-emitting device concerning 1st Embodiment. It is a graph for demonstrating the relationship between the doping concentration of a p-type impurity, and luminous efficiency. 6 is a cross-sectional view illustrating a nitride semiconductor light emitting device according to a second embodiment. 7 is a cross-sectional view showing a modification of the nitride semiconductor light emitting device according to the second embodiment. It is a figure for demonstrating the effect of the nitride semiconductor light-emitting device concerning 2nd Embodiment, and its modification.

  Hereinafter, the nitride semiconductor light emitting device and the manufacturing method thereof according to the embodiment will be described. Note that the same reference numerals are used for the same elements, and redundant description is omitted.

  In the following embodiments, a metal organic chemical vapor deposition (MOCVD) method is used as a method for growing a crystal. However, the present invention is not limited to this, and a molecular beam growth (MBE) method, a hydride vapor phase growth ( Other growth methods such as the HVPE method may be used.

In the following embodiments, the gas containing ammonia (NH ₃ ) as the nitrogen source gas, the gas containing trimethylgallium (TMG) or trimethylaluminum (TMA) as the group III source gas, and silane as the n-type doping source gas The gas containing (SiH ₄ ) is a gas containing dicyclopentadienyl magnesium (Cp ₂ Mg) as the p-type doping source gas, but the present invention is not limited to this. The details will be described below.

(First embodiment)
FIG. 1 is a cross-sectional view of a nitride semiconductor light emitting device 1 according to the first embodiment. The nitride semiconductor light emitting device 1 according to the first embodiment is, for example, a semiconductor laser. When the three-dimensional orthogonal coordinate system X, Y, Z is set, the thickness direction of the substrate coincides with the Z axis, the width direction of the substrate coincides with the X axis, and the depth direction of the paper surface perpendicular to both the X axis and the Z axis Coincides with the Y-axis.

  The nitride semiconductor light emitting device 1 includes a base substrate 3, an n-type contact layer F, a semiconductor mesa portion W, an electrode layer P, and an electrode layer Q.

The base substrate 3 is laminated on the substrate A having a main surface including the first region 10 and the second region 20 and the first region 10 and the second region 20 of the substrate A in order along the positive direction of the Z axis. The buffer layer B, the base layer D1, the crystal growth limiting portion C, the concavo-convex layer D2, and the planarization layer E, and examples of these materials are as follows.
-Planarization layer E: Al _0.2 Ga _0.8 N
・ Uneven layer D2: GaN
-Crystal growth limiting part C: SiO ₂
・ Underlayer D1: GaN
Buffer layer B: GaN
・ Substrate A: Sapphire

  The crystal growth limiting portion C is made of an insulating stripe mask, and each stripe extends in the Y-axis direction and is spaced apart from each other along the X-axis direction. Further, the exposed surface of the concavo-convex layer D2 has a triangular wave shape in the XZ cross section, and the stripe of the crystal growth limiting portion C is located immediately below the trough of the triangular wave. In addition, the uneven layer D2 of this example has a plurality of triangular prism-shaped portions with the Y axis as the central axis. The planarizing layer E is provided so as to embed the polygonal structure in the uneven layer D2, and the upper surface is planarized.

An n-type contact layer F is provided on the planarization layer E in the first and second regions 10 and 20. On the n-type contact layer F in the first region 10, a semiconductor mesa portion W composed of layers G, H, I, J, K, L, and M is provided in order. An example of the n-type contact layer F and the materials of the layers G, H, I, J, K, L, and M constituting the semiconductor mesa portion W are as follows.
P-type contact layer M: Al _0.2 Ga _0.8 N
P-type cladding layer L: Al _0.2 Ga _0.8 N
-P-type electron block layer K: Al _0.5 Ga _0.5 N
Second guide layer J: Al _0.1 Ga _0.9 N
Active layer I: GaN well layer / AlGaN barrier layer First guide layer H: Al _0.1 Ga _0.9 N
N-type cladding layer G: Al _0.2 Ga _0.8 N
N-type contact layer F: Al _0.2 Ga _0.8 N

The first guide layer H is an undoped layer. The second guide layer J has an undoped lower layer J _i on the active layer I side and an upper layer J _p on the p-type electron block layer K side to which a p-type impurity is added. The upper layer _Jp and the p-type electron block layer K have different compositions and form a heterojunction. The energy band gap of the upper layer _{J p} 3.66 eV, i.e., about 3.7 eV, the energy band gap of the p-type electron blocking layer K is 4.67EV, or about 4.7 eV.

  The p-type cladding layer L and the p-type contact layer M constitute a ridge structure R. On the ridge structure R, an insulator layer N having an opening 30 at the top of the ridge structure R is provided. An electrode layer P is provided on the ridge structure R and the insulator layer N, and the electrode layer P is in contact with the p-type contact layer M exposed through the opening 30 of the insulator layer N. An electrode layer Q is provided on the n-type contact layer F in the second region 20 so as to be separated from the semiconductor mesa portion W.

  A method for manufacturing the nitride semiconductor light emitting device 1 according to the present embodiment will be described with reference to FIGS. 2-4 is a figure which shows typically each process of the manufacturing method of the nitride semiconductor light-emitting device 1 which concerns on this embodiment. In order to manufacture the nitride semiconductor light emitting device 1, for example, the following steps are sequentially performed.

Step (1) First GaN Layer Growth Step A sapphire substrate (substrate A) is introduced and fixed in a space (MOCVD chamber) where crystal growth can be performed by MOCVD, and the MOCVD chamber is made a hydrogen atmosphere. Next, the substrate A is heat-treated at 1050 ° C. for 5 minutes to clean the surface of the substrate A. By performing the heat treatment under such appropriate conditions, contaminants on the surface of the substrate A are removed and the flatness of the surface is improved.

Next, the temperature of the substrate A is lowered to 475 ° C., a group III source gas containing trimethylgallium (TMG), a nitrogen source gas containing ammonia (NH ₃ ), and the like are supplied, as shown in FIG. Thus, a GaN layer (buffer layer B) having a thickness of 25 nm is grown on the first and second regions of the substrate A. Then, the temperature is raised to 1075 ° C., a group III source gas containing trimethylgallium, a nitrogen source gas containing ammonia, and the like are supplied, and a 2.5 μm thick GaN layer on the buffer layer B is thicker than the buffer layer B (Underlayer D1) is grown.

Step (2) Mask Formation of SiO ₂ Stripe The substrate obtained in step (1) is taken out of the MOCVD chamber and introduced into a space (plasma CVD chamber) where film formation by plasma CVD or the like is possible and fixed. Next, a SiO ₂ film having a thickness of about 300 nm is deposited on the base layer D1. Next, the SiO ₂ film is processed by a normal photolithography technique and etching technique to form a SiO ₂ stripe (crystal growth limiting portion C) having a width of 3 μm and a pitch of 6 μm. The stripe direction is the GaN [1-100] direction.

Step (3) Formation of GaN layer facets Next, the substrate obtained in step (2) is again introduced into the MOCVD growth chamber, and the same source gas as that used to form the base layer D1 is used to form a triangular wave cross section, that is, an inclined shape. A GaN layer (uneven layer D2) having a facet structure is formed. Specifically, the growth pressure range is set to 76 to 760 Torr (1.0 × 10 ^{4 to} 1.0 × 10 ⁵ Pa), the substrate temperature is set to the range of 850 to 1000 ° C., and each gas flow rate is controlled. Thus, an inclined facet structure is formed. The GaN crystal constituting the concavo-convex layer D2 starts growing from the portion where the buffer layer B between the stripes of the crystal growth limiting portion C is exposed, and continues to grow by bending in the horizontal direction (X-axis direction) on the stripe. Then, they are united with each other at the central portion in the width direction of the stripe. And since the growth rate of the thickness direction (Z-axis direction) of the center part between the stripes of the crystal growth restriction part C is large, it becomes an inclined facet having a substantially triangular cross section.

Step (4) Growth Step of Planarization Layer E The substrate obtained in Step (3) is heated to 1125 ° C., and an Al _0.2 Ga _0.8 N layer (planarization layer E) having a thickness of 6.9 μm. ) Grow. Thus, the nitride semiconductor base substrate 3 in which the inclined facet structure of the uneven layer D2 is embedded and the surface of the substrate is flattened is obtained. In addition, this film thickness is a value converted into a film thickness when grown on a flat substrate. The growth pressure was 54 Torr (7.2 × 10 ³ Pa).

Step (5) Device Layer Growth Step Next, on the nitride semiconductor base substrate 3 obtained through the steps (1) to (4) described above, the impurity concentration of Si doped is about 3 × 10 18 cm −. n-type Al 0.2 Ga 0.8 n layer of 3 (n-type contact layer F) 2.8 .mu.m, likewise Al 0.2 Ga 0 n-type of impurity concentration of about 4 × 10 18 cm -3. 8 N layer (n-type cladding layer G1) is 600 nm, non-doped Al 0.1 Ga 0.9 N layer (first guide layer H1) is 120 nm, and a quantum well structure (active layer I1) composed of GaN and AlGaN. grow up. Subsequently, the second guide layer J1 is grown to 120 nm, but an Al 0.1 Ga 0.9 N layer (lower layer J i1 ) is grown as non-doped up to 100 nm, and in the final 20 nm portion of the second guide layer J While doping Mg, it grows to 20 nm so as to become a p-type AlGaN layer (upper layer J p1 ) having an impurity concentration of about 5 × 10 19 cm −3 . Note that the thickness of the lower layer J i1 is preferably thicker than the thickness of the upper layer J p1 . Thus, in the process of light emission to propagate a second guide layer J in the active layer I, it is possible to suppress the adverse effect of light absorption by the impurity level of the upper layer J p.

Further, a p-type Al _0.5 Ga _0.5 N layer (p-type electron blocking layer K1) having an impurity concentration of about 5 × 10 ¹⁹ cm ⁻³ is formed to a thickness of 20 nm so as to form a heterointerface with the upper layer J _p1. The p-type Al _0.2 Ga _0.8 N layer (p-type cladding layer L1) having an impurity concentration of about 5 × 10 ¹⁹ cm ⁻³ is grown to 500 nm and the impurity concentration is about 1 × 10 ²⁰ cm ^−3. The p-type GaN layer (p-type contact layer M1) is grown in order of 25 nm.

Process (6) Device structure processing process (semiconductor mesa part formation)
Next, the substrate grown up to the p-type contact layer M1 is taken out of the MOCVD chamber, and subsequently, an SiO ₂ film having a thickness of about 300 nm is deposited over the entire surface of the p-type contact layer M1 by plasma CVD or the like. Thereafter, an etching mask 5 corresponding to the shape of the semiconductor mesa portion W is formed on the SiO ₂ film by a normal photolithography technique and etching technique. The etching mask 5 has a shape extending on the p-type contact layer M <b> 1 in the first region 10 along the Y-axis direction, which later becomes the optical waveguide direction, with a predetermined width.

Next, dry etching using chlorine (Cl ₂ ) gas or the like is performed using the etching mask 5 as a mask until the n-type contact layer F in the second region 20 is exposed. By this etching, the portions of the p-type contact layer M1 to the n-type cladding layer G1 that are not covered with the etching mask 5 are removed, so that the n-type cladding layer G to the p-type electron block layer K, p in the first region 10 are removed. A semiconductor mesa portion W1 composed of the mold cladding layer L2 and the p-type contact layer M2 is formed (see FIG. 3). Thereafter, the etching mask 5 is removed by etching.

Step (7) Device structure processing step (ridge structure formation)
Next, similarly, a SiO ₂ film having a thickness of about 300 nm is deposited again on the entire surface of the substrate by plasma CVD or the like. Thereafter, the etching mask 7 is formed on the central region of the p-type contact layer M2 by a normal photolithography technique and etching technique on the SiO ₂ film by the same procedure as that for forming the etching mask 5. The etching mask 7 has a shape covering the central portion of the p-type contact layer M2 with a predetermined width along the Y-axis direction. Next, using this etching mask 7 as a mask, dry etching is performed using chlorine (Cl ₂ ) gas or the like to the middle of the p-type cladding layer L2 as shown in FIG. A ridge structure R composed of the mold cladding layer L is formed. Thereafter, the etching mask 7 is removed by etching.

Step (8) Device structure processing step (electrode formation)
Subsequently, an SiO ₂ film having a thickness of about 300 nm is deposited on the entire surface of the substrate obtained after the step (7) by plasma CVD or the like again. A resist pattern having a predetermined shape is formed on the SiO ₂ film in the second region 20 by photolithography to cover the region excluding the formation region of the electrode layer Q. Thereafter, using this resist pattern as a mask, the SiO ₂ film is etched to form an opening in the formation region of the electrode layer Q. Next, a titanium (Ti) film and an aluminum (Al) film are sequentially formed on the entire upper surface of the base substrate 3 by, for example, vacuum deposition. Subsequently, the resist pattern is peeled and removed together with the Ti film and Al film formed thereon with an organic solvent or the like. As a result, an electrode layer Q in contact with the n-type contact layer F in the second region 20 is formed through the opening of the SiO ₂ film. Further, the SiO ₂ film at the top of the ridge structure R is removed by the same process to expose the p-type contact layer M, and then electrically connected to the p-type contact layer M in the same procedure as the electrode layer Q. In addition, an electrode layer P made of a laminate of nickel (Ni) and gold (Au) is formed.

Step (9) Device structure processing step (resonance surface formation)
Next, the resonator structure of the nitride semiconductor light emitting device 1 is formed by cleavage, dry etching using chlorine (Cl ₂ ) gas, or the like. Here, the resonator length is suitably 500 μm, for example. Thereafter, an end face coating may be applied to each end face of the resonator as necessary. At this time, for example, the front-side end surface reflectance is 20%, and the rear-side end surface reflectance is 98%, for example. Through the above steps, the nitride semiconductor light emitting device 1 of this embodiment made of a GaN-based semiconductor is formed.

Hereinafter, the effects of the nitride semiconductor light emitting device 1 according to the present embodiment will be described with reference to FIGS. 5 and 6A, 6B, 7A, and 7B and the conventional nitride semiconductor light emitting device 100. FIG. Comparison will be described. FIG. 5 is a cross-sectional view of a conventional nitride semiconductor light emitting device 100 to be compared. The nitride semiconductor light emitting device 100 does not have those second guide layer J is equivalent to the upper layer J _p of the nitride semiconductor light emitting device 1, the overall thickness of 120nm is undoped as the lower layer J _i It differs from the nitride semiconductor light emitting device 1 in a certain point. Other configurations are the same as those of the nitride semiconductor light emitting device 1 for easy comparison.

6 (a) and 6 (b) show the lower end of the conduction band in the second guide layer J, the p-type electron blocking layer K, and the p-type cladding layer L of the nitride semiconductor light emitting device 100 and the nitride semiconductor light emitting device 1, respectively. The energy level Ec is shown. As shown in FIG. 6 (a), in the case of a p-type electron blocking layer K side upper layer J _p nitride semiconductor light emitting device 100 having no the, p-type electron blocking layer with respect to the second guide layer J The barrier height Φs due to K is 160 meV.

On the other hand, as shown in FIG. 6 (b), in the case of a nitride semiconductor light emitting device 1 comprising a second guiding layer J having a top layer J _p to p-type electron blocking layer K side, the second guide layer J On the other hand, the barrier height Φs of the p-type electron block layer K is 230 meV, which is higher than that of the nitride semiconductor light emitting device 100. FIGS. 7A and 7B show the current density of electrons (solid line) when a bias voltage is applied so as to generate approximately the same level of light emission in the nitride semiconductor light emitting device 100 and the nitride semiconductor light emitting device 1, respectively. FIG. 6 is a diagram showing the distribution of current density (dotted line) of holes in each layer.

As shown in FIG. 7A, in the case of the nitride semiconductor light emitting device 100 having no upper layer J _p , electrons injected from the electrode layer Q are recombined with holes in the region of the active layer I. Is consumed for light emission. However, the second guide layer J, the p-type electron block layer K and the p-type cladding layer L after the active layer I also have a high electron current density. That is, it can be seen that some of the injected electrons pass through without contributing to light emission and are wasted. This is because, in the case of the nitride semiconductor light emitting device 100, the barrier height Φs of the p-type electron blocking layer is lowered, and the p-type electron blocking layer K cannot sufficiently function as a barrier layer, and therefore is active. It shows that the overflow phenomenon of electrons from the layer I to the p-type cladding layer L occurs remarkably.

On the other hand, as shown in FIG. 7 (b), in the case of a nitride semiconductor light emitting device 1 comprising a second guiding layer J having a top layer J _p, after reduction for light emission in the active layer I is The electron current density in the second guide layer J and the p-type electron block layer K is a small value. This is the case of the nitride semiconductor light emitting element 1, with the possible decrease in the height Φs barrier by p-type electron blocking layer piezoelectric polarization and spontaneous polarization is suppressed by the upper layer J _p is suppressed, p This shows that the type electron block layer K functions sufficiently as a barrier layer, and therefore, overflow of electrons from the active layer I to the p-type cladding layer L is sufficiently suppressed. As a result, the nitride semiconductor light emitting device 1 requires less injected current than the nitride semiconductor light emitting device 100 to generate the same amount of light emission.

In the nitride semiconductor light emitting device 1 according to the present embodiment, the second guide layer J has a top layer J _p where p-type impurity is added to the p-type electron blocking layer K side, the upper layer J _p and p-type electron The block layer K forms a heterojunction. Carriers generated by Mg doping of the upper layer J _p is piezoelectric polarization and the spontaneous polarization to relax the internal electric field, which is synthesized in the upper layer J _p and p-type electron blocking layer K. Therefore, not only the piezoelectric polarization occurring at the hetero-interface between the upper layer J _p and p-type electron blocking layer K, the barrier of the p-type electron blocking layer K due to the spontaneous polarization in the crystal of the upper layer layer J _p high It is possible to suppress a decrease in the thickness Φs. Therefore, the overflow of electrons from the active layer I to the p-type cladding layer L can be sufficiently suppressed. In addition, the oscillation threshold value of the nitride semiconductor light emitting device 1 can be improved with sufficient suppression of the overflow of electrons. The conventional nitride semiconductor light emitting device 100 and nitride semiconductor light emitting device 1 are not different in the block layer K, and the spontaneous polarization in the block layer K is the same in both cases.

In addition, no p-type impurity is intentionally added to the lower layer J _i on the p-type electron block layer K side. Thereby, absorption of light by the impurity level in the second guide layer J (specifically, the lower layer J _i ) can be avoided. Further, the diffusion of p-type impurities into the active layer I can be suppressed. Therefore, the generation of crystal defects in the active layer I due to the diffused p-type impurities in the active layer I is suppressed. As a result, a decrease in light emission characteristics is suppressed.

In the method for manufacturing the nitride semiconductor light emitting device 1 according to the present embodiment, in the guide layer forming step, crystal growth is performed without supplying p-type impurities in the initial stage to form the lower layer J _i, and p in the final stage. The upper layer _Jp is formed while supplying the type impurities. Further, the upper layer _Jp and the p-type electron block layer K form a heterojunction. Therefore, nitride semiconductor light emitting element 1 capable of sufficiently suppressing the overflow of electrons from active layer I to p-type cladding layer L can be easily manufactured.

FIG. 8 is a diagram for explaining the relationship between the doping concentration of the p-type impurity (Mg) in the lower layer J _i , the upper layer J _p and the p-type electron blocking layer K and the luminous efficiency indicating the ratio of the current consumed for light emission. It is a chart. When the lower layer J _i is not doped with a p-type impurity, light emission occurs when the Mg doping concentration of the upper layer J _p and the p-type electron blocking layer K is 5.9 × 10 ¹⁸ cm ^−3. The efficiency is 22%. When the Mg doping concentrations of the upper layer J _p and the p-type electron blocking layer K are both increased to 5.9 × 10 ¹⁹ cm ⁻³ and 5.9 × 10 ²⁰ cm ⁻³ , the luminous efficiency is 54% in each case. It can be seen that the emission efficiency tends to increase in proportion to the doping concentration.

However, even if the upper layer J _p is maintained at 5.9 × 10 ¹⁹ cm ⁻³ and only the concentration of the p-type electron blocking layer K is increased to 5.9 × 10 ²⁰ cm ⁻³ , the luminous efficiency is 55%. There is little change. Further, when the second guide layer J is the nitride semiconductor light emitting device 100 having no upper layer J _p , the luminous efficiency is 18% when the p-type electron block layer K is 5.9 × 10 ¹⁹ cm ^−3. You can see that it is only. Further, in the case of Mg in the lower layer _{J i} not upper layer _{J p} only is doped, the lower layer _{J i,} the upper layer _{J p} and p-type electron blocking layer K is 5.9 × ¹⁰ 19 ^{cm -3} The issue efficiency is very high at 54%. The value of the luminous efficiency is such that the lower layer J _i is not doped with p-type impurities, and the Mg doping concentrations of the upper layer J _p and the p-type electron blocking layer K are both 5.9 × 10 ¹⁹ cm ^{−. The} same as when ³ . However, in this case, since the second guide layer J is p-type, light absorption is increased in the second guide layer J, and the efficiency is effectively deteriorated. Thus, according to the nitride semiconductor light emitting device 1 according to this embodiment, the overflow of electrons can be sufficiently suppressed by adjusting the concentration of the p-type impurity of the upper layer J _p appropriately, the nitride semiconductor light emitting device The luminous efficiency of 1 is improved.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 9 is a sectional view showing a nitride semiconductor light emitting device 1A according to the second embodiment. In the nitride semiconductor light emitting device 1A, instead of the single-layer p-type electron block layer K, four p-type electron block layers K _{a having} different compositions and ¼ of the thickness of the p-type electron block layer K are used. It differs from the nitride semiconductor light emitting device 1 in that it has ~ _Kd . Other configurations are the same as those of the nitride semiconductor light emitting device 1. An example of the material of the p-type electron block layers K _{a to} K _d is as follows.
· P-type electron blocking layer _{K a:} Al _{0.5 Ga} 0.5 N
· P-type electron blocking layer _{K b:} Al _{0.425 Ga 0.575} N
· P-type electron blocking layer _{K c:} Al _{0.35 Ga 0.65} N
_-P- type electron block layer _Kd : _{Al0.275Ga0.725N}

  FIG. 10 is a view showing a modification of the nitride semiconductor light emitting device 1A according to the second embodiment. As shown in FIG. 9, the nitride semiconductor light emitting device 1B according to this variation includes a base substrate 3 including a substrate A, a buffer layer B, a base layer D1, a crystal growth limiting portion C, a concavo-convex layer D2, and a planarization layer E. Instead of the nitride semiconductor light emitting device 1B, the AlN substrate 3A is provided. Other configurations are the same as those of the nitride semiconductor light emitting device 1B.

11 (a) is a nitride semiconductor light emitting device 1A and the conduction band at the second guide layer J of nitride semiconductor light emitting device 1B of the modified example, p-type electron blocking layer K _a ~K _d and p-type clad layer L The energy level Ec at the lower end of is shown. FIG. 11B shows the current density of electrons in the vicinity of the second guide layer J, the p-type electron block layers K _{a to} K _d and the p-type cladding layer L of the nitride semiconductor light emitting device 1A and the nitride semiconductor light emitting device 1B. (Solid line) and hole current density (dotted line) are shown.

As shown in FIG. 11A, in the case of the nitride semiconductor light emitting devices 1A and 1B having the p-type electron block layers K _{a to} K _d , the p-type electron block with respect to the second guide layer J The barrier height Φs of the layers K _{a to} K _d is 330 meV, and it can be seen that the barrier height Φs is higher than that of the nitride semiconductor light emitting device 1. Further, as shown in FIG. 11B, with respect to the current density of holes, there is no significant difference between the nitride semiconductor light emitting devices 1A and 1B and the nitride semiconductor light emitting device 1. On the other hand, with respect to the electron current density, in the case of the nitride semiconductor light emitting device 1A and 1B comprises a p-type electron blocking layer K _a ~K _d is the active layer I, the second guide layer J and p-type electron blocking layer K In FIG. 4, a further decrease in the current density of electrons is observed. This is the case of the nitride semiconductor light emitting device 1A and 1B, the p-type electron blocking layer K _a ~K _d decrease in height Φs barrier due is further suppressed p-type electron blocking layer K _a ~K _d is It shows that the overflow of electrons from the active layer I to the p-type cladding layer L is more sufficiently suppressed because it functions more satisfactorily as a barrier layer.

  As mentioned above, although preferred embodiment of this invention was described, this embodiment can be variously changed in the range which does not deviate from the summary of this invention. Specifically, in this embodiment, the base layer D is made of GaN, and the layers E, F, G, H, I, J, K, L, and M are made of AlGaN, but may be made of AlGaInN. . When AlGaInN is used for any one of the layers, the In composition is generally limited to about 10%, and an In composition higher than that is possible.

The substrate A is a substrate made of sapphire, but may be an AlN substrate. In the embodiment described above, the buffer layer B is made of GaN, but may be made of AlN or the like as long as the same effect can be obtained. The etching masks 5 and 7 are made of SiO ₂ , but may be patterned with other materials. In addition, the stripe direction of the crystal growth limiting portion C is the GaN [1-100] direction, but may be along another crystal direction. In this embodiment, the crystal growth of the element structure is performed sequentially from the n side to the p side. However, the same structure may be formed upside down starting from the p side.

1 ... nitride semiconductor light emitting device, I ... active layer, L ... p-type cladding layer, K ... p-type electron blocking layer, J ... second guide layer, J i _... lower layer, J p _... upper layer.

Claims (4)

An active layer,
A p-type cladding layer provided on one side of the active layer;
A p-type electron blocking layer provided between the p-type cladding layer and the active layer;
A guide layer provided between the active layer and the p-type electron blocking layer,
The active layer, the p-type cladding layer, the p-type electron blocking layer, and the guide layer include a group III nitride semiconductor,
The nitride semiconductor light emitting device in which a portion of the guide layer located on the p-type electron block layer side includes a p-type impurity and forms a heterojunction with the p-type electron block layer.   2. The nitride semiconductor light emitting device according to claim 1, wherein a p-type impurity is not intentionally added to a portion of the guide layer located on the active layer side. A p-type contact layer provided on the p-type cladding layer;
An n-type contact layer provided on the other side of the active layer;
The nitride semiconductor light-emitting device according to claim 1, further comprising: Forming a guide layer on the substrate;
Forming a p-type electron blocking layer on the guide layer;
Forming a p-type cladding layer on the p-type electron blocking layer;
With
The guide layer, the p-type electron blocking layer, and the p-type cladding layer include a group III nitride semiconductor,
In the guide layer forming step, crystal growth is performed without supplying p-type impurities in the initial stage, and crystal growth is performed while supplying p-type impurities in the final stage.
A method for manufacturing a nitride semiconductor light emitting device, wherein the p-type electron blocking layer and a portion of the crystal grown while supplying the p-type impurity in the guide layer forming step form a heterojunction.

Images