JP2009205334A - Performance monitor circuit and performance monitor method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a performance monitor circuit capable of specifying a sampling interval by clock cycle and a method thereof. <P>SOLUTION: The performance monitor circuit and the performance monitor method are equipped with a buffer, stored a received packet in the transaction layer of a PCI Express in the buffer, and connected to the PCI express component transmitting the packet stored in the buffer. The performance monitor circuit includes: a first counter for measuring a data volume of the packet sent from the buffer; a second counter for measuring the number of clock cycles in which a packet exists in the buffer; a third counter for measuring the number of clock cycles in which a packet to be transmitted exists in the buffer, but it could not be transmitted; and a control circuit for performing control to repeat the measurement by first to third counters at a predetermined time interval. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a PCI Express component, and more particularly, to a circuit and a method for measuring and recording data transfer performance information of a PCI (Peripheral component interconnect) Express component.

Recently, PCI Express components such as a root complex, a switch, and an end point defined in Non-Patent Document 1 need to have a performance monitoring function. The reason is that PCI-SIG (PCI Special Interest Group), which is currently a PCI standardization organization, is developing a standard specification for virtualizing PCI Express devices under the name IOV (I / O Virtualization). This is because there is a possibility that an IOV-compatible PCI Express device will be realized in the near future. When a PCI Express device is virtualized, a computer system designer can connect one physical PCI Express device to multiple physical PCI Express devices on VMM (Virtual Machine Monitor) for the purpose of reducing costs by reducing the number of physical PCI Express devices. The virtual PCI Express device is divided and assigned to each OS operating on the VMM called a guest OS.

  Currently, the performance monitoring function provided in the components that make up the computer, such as the performance monitoring function provided by the Intel CPU (described in Non-Patent Document 2), is an event that occurs within the time set by the user. It only counts the number. Therefore, for example, when it is desired to analyze the number of events generated in 10 seconds at intervals of 1 second, it is necessary to instruct the performance monitor to measure the number of events for 1 second 10 times. In order to perform such an analysis, the Intel CPU as an example requires dedicated performance analysis software such as a Vtune analyzer sold by Intel. The user of the performance monitoring function designates a sampling period that is a time for measuring the number of events on the performance analysis software and a sampling interval that is an interval for measuring the number of events. Then, the performance analysis software gives instructions to the performance monitor according to the specifications, and automatically measures the number of events multiple times.

PCI Express Base Specification Revision 2.0, PCI-SIG, December 2006 Intel Itanium Architecture Software Developer's Manual Volume 2: System Architecture Revision 2.2, Intel, January 2006

As described above, if the computer system designer reduces the number of physical PCI Express devices, if the quality of service (QoS) performed by each guest OS is not guaranteed, the required performance as the computer system cannot be satisfied. So cost reduction doesn't make sense. Accordingly, the computer system designer needs to analyze the data transfer performance of the guest OS and assign one physical PCI Express device to a plurality of guest OSes so that QoS can be guaranteed. For this purpose, the PCI Express component existing on the data transfer path also needs to be equipped with a performance monitor function for analyzing the data transfer performance.

  In the performance analysis software, the shortest sampling interval is limited to milliseconds because of software execution time constraints. In recent years, CPUs have become increasingly multi-core and performance has been increasing. Accordingly, I / O needs to improve transfer performance, and in 2007, PCI Express components compatible with PCI Express Gen2 having a transfer performance of 5 Gbps per link have started to be shipped. This flow is expected to continue, and the amount of data processed by the PCI Express component per unit time will increase more and more. As a result, data transfer events such as packet collisions and congestion that had only been able to be analyzed sufficiently at the sampling interval in milliseconds until now will increase in the amount of data handled per unit time. It is conceivable that a large number of sampling intervals may occur so that sufficient analysis cannot be performed. Therefore, it is expected that a finer sampling interval will be required in the future. Currently, the PCI Express component runs in a few nanoseconds in one clock cycle, and when it becomes necessary to specify the sampling interval in microseconds, which is finer than a minimum of milliseconds, or in the same nanosecond unit as the operation clock cycle. Conceivable.

As described above, there are currently three problems in developing the PCI Express component.
(1) In an environment where a PCI Express device is virtualized and used, in order to guarantee the QoS of the guest OS, it is necessary to mount a performance monitor function that enables analysis of data transfer performance on the PCI Express component.
(2) When performing performance analysis of components constituting a computer by specifying a sampling period and a sampling interval, the conventional performance monitoring function requires dedicated performance analysis software. This means that the user of the performance monitoring function is charged with the purchase cost or development cost of the performance analysis software.
(3) In performance analysis using performance analysis software, the current sampling interval cannot be specified in units lower than milliseconds. Therefore, for example, performance analysis with a finer granularity of sampling intervals such as clock cycle units of PCI Express components cannot be performed.

  An object of the present invention is to provide a performance monitoring circuit and method for enabling analysis of data transfer performance of a PCI Express component, not requiring performance analysis software for performance analysis, and specifying a sampling interval in units of clock cycles. Is to provide.

The performance monitoring circuit and method of the present invention have the following configuration. A performance monitoring circuit comprising a buffer, storing a received PCI Express transaction layer packet in the buffer, and connecting to a PCI express component for transmitting the packet stored in the buffer, and a performance monitoring method using the performance monitoring circuit is there. A first counter that measures the amount of data of a packet transmitted from the buffer, a second counter that measures the number of clock cycles in which the packet exists in the buffer, and a clock in which a packet to be transmitted exists but could not be transmitted A third counter that measures the number of cycles and a control circuit that controls the measurement by the first to third counters to be repeated at predetermined time intervals.

  In another embodiment of the present invention, a memory circuit is provided, and the control circuit stores the measurement values obtained by the first to third counters in the memory circuit.

  According to still another aspect of the present invention, the first to third counters are initialized in response to the storage of the measurement values by the first to third counters in the storage circuit.

  According to still another aspect of the present invention, a measurement period by first to third counters repeated at a predetermined time and a predetermined time interval is set in the control register.

  According to still another aspect of the present invention, mask data for measuring the data amount of a desired packet is set in the mask register.

  According to still another aspect of the present invention, for each of the upstream buffer and the downstream buffer, the data amount of the packet transmitted from the buffer within a predetermined time, and the number of clock cycles in which the packet exists in the buffer And the number of clock cycles in which there is a packet to be transmitted in the buffer but could not be transmitted.

According to the performance monitoring circuit and method of the present invention, the sampling interval can be specified in units of clock cycles.

Hereinafter, the best mode for carrying out the present invention will be described in detail using examples.

FIG. 1 is an example of a computer system according to the first embodiment. The computer system includes a CPU 100, a memory 101, a root complex 110 and a switch 111, which are PCI Express components, and an end point 112 and an end point 113. The root complex 110 and the switch 111 are connected by a PCI Express link 140. The switch 111 is connected to the end point 112 and the end point 113 by PCI Express links 141 and 142, respectively.

  The functions of the service processor 120 are: power management (turn on / off) of each component of the computer system, management of component information, collection of transaction information and processing status history in the computer system at the time of failure, failure notification, Environmental (temperature / power) monitoring. In this embodiment, the management console 130 and the service processor 120 can communicate with each other via the interface 160. Communication between the service processor 120 and the management console 130 may be realized by a LAN interface or a serial interface, for example. A user of the computer system uses the management console 130 to manage / operate the computer system via the service processor 120.

  The service processor 120 includes interfaces 150, 151, 152, and 153 that can read and write setting values and read measurement results from the management console 180 to the performance monitor circuit in each PCI Express component. As an interface between each PCI Express component and the service processor 120, for example, an I2C interface which is a standard interface specification for hardware monitoring may be used.

  The performance monitor circuit of this embodiment is provided in the root complex 110, the switch 111, and the end point 112, which are PCI Express components. Normally, the PCI Express component (root complex, switch, end point, etc.) temporarily stores the TLP (Transaction Layer Packet) received by the PCI Express component, and configures the computer with the other PCI Express component after storing the packet. A buffer located in the transaction layer for transmission to other components (CPU, memory, etc.) is provided on the data transfer path. By providing the buffer with a performance monitor circuit, information necessary for analyzing the data transfer performance of the PCI Express component is obtained.

  Hereinafter, the function of the performance monitor circuit will be described using the performance monitor circuit included in the switch 111. The function of the performance monitor circuit does not differ depending on the type of PCI Express component.

  FIG. 2 shows the switch 111 in this embodiment. The switch 111 includes an upstream port 200, a downstream port 201, and a downstream port 202. The upstream port 200 has functions of a data link layer and a physical port layer of PCI Express, and receives a TLP (Transaction Layer Packet) from the root complex 110 via the PCI Express link 140, or to the root complex 110. Send TLP. Similarly, the downstream port 201 and the downstream port 202 have the functions of the PCI Express data link layer and physical port layer, respectively, and the TLP from the end point 112 and the end point 113 via the PCI Express links 141 and 142, respectively. Or the TLP is transmitted to the end point 112 and the end point 113.

  Each port constantly monitors the state of the buffer that receives the TLP at the root complex 110, end point 112, and end point 113 of the PCI Express component that is the destination of the TLP. If the destination PCI Express component has a free buffer and the port can send a TLP to the destination PCI Express component, the information is buffered (upstream buffer) 210 and buffer (downstream). Buffer) 211. The buffer 210 and the buffer 211 that have seen the information transmit the TLP addressed to the transmittable PCI Express component to the transmittable port (the buffer 211 is via the crossbar 220). The port that has received the TLP transmits the TLP to the destination PCI Express component. Also, each port monitors the state of the buffer 210 and the buffer 211, and sends information indicating that the switch 111 can receive the TLP to the PCI Express component that is also the transmission source of the TLP. The PCI Express component that is the TLP transmission source that has seen the information transmits the TLP to the switch 111, and each port transmits the TLP to the buffer 210 or the buffer 211 directly or via the crossbar switch 220.

  A buffer 210 and a buffer 211 are buffers located in the transaction layer of PCI Express, and store the TLP sent to the buffer once. Then, the destination is confirmed by looking at the TLP, and if the destination PCI Express component can be received, the TLP is sent to each port directly or via the crossbar switch 220. However, when the destination of the TLP transmitted by the buffer 211 is the performance monitor circuit 230, the TLP transmission operation is different. The TLP addressed to the performance monitor circuit 230 is issued by the CPU 100 when the user reads / writes the set value of the performance monitor circuit 230 or reads the measurement result via the OS operating on the CPU 100. When the TLP to be transmitted is addressed to the performance monitor circuit 230, the performance buffer 211 transmits the TLP to the performance monitor circuit 230 via the crossbar switch 220 and the path 252. In this embodiment, it is assumed that the performance monitor circuit 230 can process the TLP every clock cycle, and it is not checked whether the performance monitor circuit 230 can receive the TLP. If the performance monitor circuit is unable to receive TLP every cycle, the buffer 211 is the same as sending a TLP to the PCI Express component, so that the performance monitor circuit 230 can receive the TLP or before sending the TLP. It is necessary to confirm.

  The crossbar switch 220 sends the TLP sent from the downstream port 201 or the downstream port 202 or the performance monitor circuit 230 via the path 253 to the buffer 210. The TLP transmitted by the performance monitor circuit 230 is read data for setting values of the performance monitor circuit 230 and read data for recording measurement results. In addition, the crossbar switch 220 looks at the TLP destination sent from the buffer 211 and checks the TLP destination to the downstream port 201 or 202 connected to the destination PCI Express component or the performance monitor circuit 230. To send.

  The performance monitor circuit 230 is connected to the buffer 211 via the path 250. Through the path 250, the buffer 211 has information indicating that there is a TLP to be transmitted to the buffer 211 every clock cycle to the performance monitor circuit 230, and there is a TLP to be transmitted in the buffer 211, but transmission is not possible. Send information indicating. The information is realized by two level signals, for example, 1 ′ of one level signal indicates that a TLP to be transmitted exists in the buffer 211, and 1 ′ of another level signal exists in the buffer 211. Indicates that it cannot be sent. 0 'of both level signals indicates that neither state is present. Further, the performance monitor circuit 230 receives a copy of the TLP transmitted from the buffer 211 via the path 251. The performance monitor circuit 230 is directly connected to the interface 151 with the service processor 120.

  The internal configuration and processing contents of the performance monitor circuit of this embodiment will be described in detail with reference to FIG.

  Every clock cycle, the counter circuit 300 looks at information indicating that there is a TLP to be transmitted to the buffer 211 transmitted via the path 250, and if there is a TLP to be transmitted to the buffer 211, the counter circuit 300 Increase the value of the register 310 by 1. Similarly, every clock cycle, the counter circuit 300 sees information indicating that there is a TLP to be transmitted in the buffer 211 sent via the path 250 but cannot be transmitted, and transmits the TLP to the buffer 211. Is present but cannot be transmitted, the value of the counter register 311 is incremented by one. Also, every clock cycle, the counter circuit 300 receives a copy of the TLP transmitted by the buffer 211 via the path 251. When the counter circuit 300 receives the TLP, it first refers to the mask register 320.

  The mask register 320 is a register arbitrarily set by the user of the performance monitoring function of the switch 111 for performance analysis, and is used when the measurement of the number of TLPs transferred by the buffer 211 is limited to a predetermined TLP.

  An example of the mask register 320 is shown in FIG. The mask register 320 is composed of 272 bits. Each of the three fields 400 to 402 is composed of 1 bit. The fact that the field 400 is “enable” indicates that when the TLP header is received, the counter circuit 300 adds to the counter register 312 the packet size of the TLP header in units of DW (Double Word, 32 bits). Similarly, when the field 401 is “enable”, the counter circuit 300 adds to the counter register 312 the packet size of the TLP data in units of DW when the TLP data is received. “Enable” indicates that the counter circuit 300 adds the data size of the TLP digest to the counter register 312 in units of DW when receiving the TLP digest.

  The field 403 is composed of 13 bits, and is a field reserved for use when expanding the function of the control circuit in the future, and is not particularly used this time.

  The field 404 is composed of 128 bits which is the maximum size of the TLP header defined by the PCI Express specification, and the user of the performance monitor circuit sets the TLP header of the TLP whose data amount is to be measured in this field. The field 405 is composed of 128 bits having the same size as the field 404, and is used for designating validity / invalidity of each bit of the field 404. For example, when it is desired to mask the TLP with only a part of the bits of the TLP header set in the field 404, only the corresponding bit in the field 405 may be set to “1” to be “enable”. The counter circuit 300 looks at the fields 404 and 405, and when a TLP meeting the mask condition is transmitted from the buffer 211, the counter circuit 312 adds the TLP packet size in DW units to the counter register 312.

  It is effective to use the mask function of the mask register 320 described above in the following two cases.

  First, a TLP is composed of a TLP header, a TLP data, and a TLP digest, and the data transfer amount usually indicates only the amount of TLP data. The other two are data transfer overheads. When the data transfer amount is to be measured purely, the mask function of the mask register 320 is used.

  Second, since information indicating the issuer, issuer, transaction type, etc. is stored in the TLP header, data is classified into issuer units, issuer, transaction type by masking the TLP header. Transfer amount can be measured.

  Although the configuration of the mask register has been described above, only the minimum necessary mask function and configuration are described. The mask function and configuration are not particularly limited. For example, the mask function and configuration may be expanded according to the specifications of the PCI Express component on which the performance monitor circuit is mounted or the user's request for the performance monitor function.

  The control circuit 330 determines the number of TLPs transmitted by the buffer 211, the number of clock cycles in which there are TLPs to be transmitted to the buffer 211, and the number of clock cycles in which there are TLPs to be transmitted in the buffer 211 but cannot be transmitted. Measure according to the set value of 321.

  The measurement of the number of TLPs transmitted by the buffer 211 means measurement of the data transfer amount transmitted by the buffer. The TLP packet size transmitted by the buffer every clock cycle is added in units of DW (Double Word, 32 bits) which is the minimum packet size of the TLP. For example, when a 3DW TLP is transmitted in one clock cycle, +3 is added to the total TLP packet size measured so far. By this measurement, the data transfer amount of the data transfer path in which the buffer 211 exists within the sampling period can be known.

  The measurement of the number of clock cycles in which there is a TLP that can be transmitted to the buffer 211 indicates the usage rate of the data transfer path in which the buffer 211 exists during the sampling period.

  The measurement of the number of clock cycles in which a packet to be transmitted exists in the buffer 211 but could not be transmitted is a measurement of the time during which TLP transmission is delayed in the data transfer path ahead of the buffer 211, and the data transfer path is congested. Means measurement of degree. When the data transfer amount in the sampling period is lower than the expected value, the cause is (a) the TLP data amount issued by the TLP issuer is small, (b) the TLP transmission is delayed in the data transfer path ahead of the buffer. There are two possible cases. With this measurement, it is possible to measure the time during which TLP transmission is delayed in the data transfer path ahead of the buffer 211, and to know the degree of congestion of the data transfer path, so that the causes (a) and (b) can be distinguished.

  When the control circuit 330 receives the TLP addressed to the performance monitor circuit 230 via the path 252, the control circuit 330 looks at the TLP and reads / writes the mask register 320 and the control register 321, counter registers 310 to 312, The status register 322 and SRAM (storage circuit) 323 are read. After the read process, the control circuit 330 returns the read data to the CPU 100 via the path 253. When the user of the performance monitor function reads / writes the set value of the performance monitor circuit 230 or reads the measurement result via the management console 130, the mask register is read according to the request received from the interface 151. 320 reads / writes the control register 321 and reads the counter registers 310 to 312, the status register 322 and the SRAM 323. After the read process, the control circuit 330 returns the read data to the management console 130 via the interface 151.

  An example of the control register 321 is shown in FIG. The control register 330 has 112 bits and is divided into five fields 500 to 504. A field 500 is composed of 1 bit, and a value “1” indicates measurement start, and a value “0” indicates measurement stop. The user of the performance monitoring function can instruct the start and stop of measurement by operating the field 500. The control circuit 330 continues the measurement while the field 500 is set to “1”, and stops the measurement when the field 500 is set to “0”.

  The field 501 is composed of 1 bit and indicates initialization of the counter registers 310 to 312, the SRAM 323, and the status register 322 with a value of “1”, and does nothing with a value of “0”. When the initialization of the counter registers 310 to 312, the SRAM 323, and the status register 322 is instructed, the control circuit 330 clears the values stored in the counter registers 310 to 312 to “0”. Then, all values stored in all entries of the SRAM 323 are cleared to “0”, and all values stored in the status register 322 are also cleared to “0”. Until initialization is completed for each initialization target, the control circuit 330 does not start measurement even if “1” is set in the field 500. When the initialization process is completed, the field 501 returns to the value “0”. Normally, the user of the performance monitor function sets “1” in the field 501 before instructing the start of measurement, and sets the values stored in the counter registers 310 to 312, the SRAM 323, and the status register 322 to “0”. Clear to “”.

  The field 502 is composed of 14 bits, and is a field reserved for use when expanding the function of the control circuit in the future, and is not particularly used this time.

  A field 503 is composed of 48 bits, and is a field for setting a sampling interval in units of clock cycles. The user of the performance monitoring function sets a sampling interval for measurement in the field. The control circuit 330 stores the values of the counter registers 310 to 312 in the SRAM 323 after a clock cycle for the set sampling interval has elapsed. After initialization, the control circuit 330 starts storing the values of the counter registers 310 to 312 from entry 0 of the SRAM 323, and then stores the values of the counter registers 310 to 312 in the SRAM 323 while incrementing the entry number. repeat.

  A field 504 is composed of 48 bits and stores a sampling period (measurement period) in units of clock cycles. The user of the performance monitoring function sets a sampling period to be measured in the field. After the clock cycle for the set sampling period has elapsed, the control circuit 330 writes the value “1” in the flag field of the entry in which the value of the counter register 310 to 312 was last written in the SRAM 323.

  The status register 322 is a register that indicates the status of the performance monitor circuit of the switch 111. An example of the status register 322 is shown in FIG. The status register 322 includes 112 bits and is divided into seven fields 600 to 606.

  The field 600 is composed of 2 bits and indicates the status of the control circuit 330. “00” indicates that the control circuit 330 is not measuring, and “01” indicates that the control circuit 330 is measuring. “10” indicates that the field 500 of the control register 321 is set to “0” before the measurement is completed after the measurement is started, and “11” indicates that the measurement is stopped. When “1” is set in the field 500 and measurement is started, the control circuit 330 sets the field 600 to “01”. Next, when “0” is set in the field 500 after the start of measurement, the control circuit 330 sets “10” in the field 600. The control circuit 330 sets “11” when the value of the field 606 and the value of the field 504 of the control register 321 become the same.

  Each of the fields 601 to 603 is composed of 1 bit, and when an overflow occurs in the counter register, the control circuit 330 sets “1” and reports the overflow. The field 601 corresponds to the counter register 310, the field 602 corresponds to the counter register 311 and the field 603 corresponds to the counter register 312.

  A field 604 is composed of 11 bits, and is a field reserved for use when expanding the function of the control circuit in the future, and is not particularly used this time.

  The interval timer in the field 605 is composed of 48 bits and indicates the measurement time in units of clock cycles. If the measurement is being performed, the control circuit 330 increments the value of the interval timer by 1 every clock cycle. However, when the value of the sampling interval of the control register 321 and the value of the interval timer become equal, the control circuit 330 clears the interval timer to “0” and records the measurement time again if the measurement continues. .

  The event timer in field 606 is composed of 48 bits and indicates the measurement time in units of clock cycles. If the measurement is being performed, the control circuit 330 increments the value of the event timer by 1 every clock cycle. However, unlike the interval timer, the event timer is not cleared except for initialization. When the value of the sampling period of the control register 322 becomes equal to the value of the event timer, it indicates that the measurement of the performance monitor circuit 230 has ended.

  An example of the SRAM 323 is shown in FIG. In this embodiment, the number of SRAM entries is 1024. The SRAM 323 is composed of four fields 701 to 704. A field 700 indicates an entry number, but the actual SRAM does not have this field, and is a field that is provisionally defined for easy explanation. A field 701 is composed of 1 bit for each entry, and “1” indicates that the entry is the last value stored when measurement is completed. Fields 702 to 704 are fields for storing the value of each counter register, and each entry has the same number of bits as the counter register. The control circuit 330 stores the value of the counter register 310 in the field 702, the value of the counter register 311 in the field 703, and the value of the counter register 312 in the field 704.

  The configuration of the control register 321, the status register 322, and the SRAM 323 has been described above. However, the example used is the minimum necessary configuration, and the configuration and the number of bits of each field are not particularly specified. Depending on the specifications of the PCI Express component on which the performance monitor circuit is mounted, the necessary fields and the number of bits may be expanded.

  FIG. 8 shows a process flowchart executed by the control circuit 330 every clock cycle. In the flowchart shown in FIG. 8, the processing when the user of the performance monitoring function reads / writes the setting value of the performance monitoring circuit 230 or reads the measurement result via the CPU 100 or the management console 130. Not shown, but will be easily revisited. In parallel with the processing shown in FIG. 8, the control circuit 330 can execute processing accompanying the user's operation. Further, the processing when the user of the performance monitor function instructs initialization of the performance monitor circuit 230 by setting the field 501 of the control register 322 to “1” is not shown in FIG. It will be praised. The control circuit 330 that has received the initialization instruction from the performance monitor circuit 230 does not perform the process shown in FIG. 8 until the initialization process is completed.

  Hereinafter, each step of the processing flowchart shown in FIG. 8 will be described. In step 800, the control circuit 330 determines whether the start / stop of the field 500 of the control register 321 is set to “measurement start” of “1”. The control circuit 330 performs the process of step 801 when “measurement start” is set, and performs the process of step 802 when “0” is set to “measurement stop”. In step 801, the control circuit 330 sets the control circuit status in the field 600 of the status register 322 to “under measurement” of “01”.

  In step 802, the control circuit 330 determines whether the control circuit status in the status register 322 field 600 is “01” or “measuring”. If the setting is “measuring”, the control circuit 330 performs the process of step 803, and if the setting is any other setting, the process of the clock cycle ends. In step 803, the control circuit 330 sets the control circuit status in the field 600 of the status register 322 to “pause” of “10”, and ends the processing of the clock cycle.

  In step 804, the control circuit 330 determines whether the interval timer in the field 605 of the status register 322 is equal to the value of the sampling interval in the field 503 of the control register 321. The control circuit 330 performs the process of step 805 if they are equal, and performs the process of step 806 if they are not equal.

  In step 805, the control circuit 330 stores the values of the counter registers 310 to 312 in the SRAM 323. Further, the control circuit 330 reads the value from each counter / register in order to store the value in the SRAM 323, and simultaneously clears the value of each counter / register to “0”. Then, the control circuit 330 clears the value of the interval timer in the field 605 of the status register 322 to “0”. In step 806, the control circuit 330 increments the value of the interval timer in the field 605 of the status register 322 by +1.

  In step 807, the control circuit 330 determines whether the event timer in the field 606 of the status register 322 is equal to the value of the sampling period in the field 504 of the control register 321. The control circuit 330 performs the process of step 808 if they are equal, and performs the process of step 809 if they are not equal.

  In step 808, the control circuit 330 sets “1” to the flag of the field 701 of the entry stored last in the SRAM 323. Further, the control circuit status in the status register 322 field 600 is set to “11” “measurement end”, and the processing of the clock cycle is ended. In step 809, the control circuit 330 increments the event timer value in the status register 322 field 606 by one, and ends the processing of the clock cycle.

  According to the present embodiment, it is possible to realize a performance monitor circuit that can specify the sampling interval in units of clock cycles.

FIG. 9 shows the switch 111 of the second embodiment. The switch 111 of this embodiment is obtained by adding the performance monitoring function of the buffer 210 to the first embodiment. To measure the number of TLPs transmitted by the buffer 210, the number of clock cycles in which there is a TLP to be transmitted to the buffer 210, and the number of clock cycles in which there is a TLP to be transmitted in the buffer 210 but could not be transmitted, Similar to the buffer 211, a path 950 having the same function as the path 250 and a path 951 having the same function as the path 251 are provided. The performance monitor circuit 930 is an extension of the function of the performance monitor circuit 230 in order to perform the above three measurements of the buffer 210.

  FIG. 10 shows an example of the performance monitor circuit 930. Hereinafter, the performance monitor circuit 930 added to the performance monitor circuit 230 will be described. The configuration of the performance monitor circuit 930 other than the additional configuration is the same as the configuration of the performance monitor circuit 230.

  Every clock cycle, the counter circuit 1000 looks at the information indicating that there is a TLP to be transmitted to the buffer 210 transmitted via the path 950, and if there is a TLP to be transmitted to the buffer 210, the counter circuit 1000 Increase the value of the register 1010 by one. Similarly, every clock cycle, the counter circuit 1000 sees information indicating that there is a TLP to be sent in the buffer 210 sent through the path 950 but cannot send it, and sends it to the buffer 210. Is present but cannot be transmitted, the value of the counter register 1011 is incremented by one. Also, every clock cycle, counter circuit 1000 receives a copy of the TLP transmitted by buffer 210 via path 951. When the counter circuit 1000 receives the TLP, it first refers to the mask register 320, and if the TLP to be measured is indicated by the setting contents of the mask register 320, the packet size is stored in the counter register 1012 in DW units. Add to the value.

  The configuration of the control circuit 1030 is obtained by adding a configuration in which the same processing as the processing for the counter registers 310 to 312 is performed on the counter registers 1010 to 1012 to the configuration of the control circuit 330. The operation of the control circuit 1030 is also added to the SRAM 1023.

  An example of the SRAM 1023 is shown in FIG. The SRAM 1023 adds three fields 1102 to 1104 to the SRAM 323. Similarly to the fields 702 to 704, the fields 1102 to 1104 are configured with the same number of bits as the counter register in each entry. The control circuit 1030 stores the value of the counter register 1010 in the field 1102, the value of the counter register 1011 in the field 1103, and the value of the counter register 1012 in the field 1104.

  The control circuit 1030 adds the value of the counter registers 310 to 312 in addition to the value of the counter register in the clock cycle in which the value of the interval timer in the field 605 of the status register 322 is equal to the value of the sampling interval in the control register 321 field 503. The values 1010 to 1012 are stored in the SRAM 1021. Further, the control circuit 1030 reads the value from each counter / register in order to store the value in the SRAM 1023, and simultaneously clears the value of each counter / register to “0”.

  In addition, the status register 322 is also added with a field to be the status register 1022. FIG. 12 shows an example of the status register 1022. The added fields 1201 to 1203 are fields for the control circuit 1030 to set to “1” and report that an overflow has occurred when the counter registers 1010 to 1012 overflow.

  The switch 111 according to the second embodiment is an example in which the number of buffers for measuring the data transfer performance is 2, but even if the number of buffers for measuring the data transfer performance is further increased, the same expansion can be performed for each buffer. The performance monitor circuit can measure the data transfer performance of a plurality of buffers in the same way as when there is one buffer. Therefore, even when there are a plurality of buffers in the PCI Express component, the performance monitor circuit can perform measurement and record the measurement result at the same sampling interval and sampling period. Thereby, the temporal correlation of the measurement result of each buffer can be seen.

  According to the above embodiment, the performance monitor circuit can measure the data transfer amount, usage rate, and congestion level within the unit time of the data transfer path to be analyzed. Data transfer volume can be measured by dividing transaction types. Thereby, the computer system designer can obtain information necessary for analyzing the data transfer performance of the data transfer path.

  An example of how a computer system designer who divides one physical PCI Express device into a plurality of virtual PCI Express devices and allocates it to a plurality of guest OSs uses a performance monitor circuit will be described. First, the computer system designer measures the data transfer performance of each guest OS on the data transfer path connected to the PCI Express device. Thereafter, in order to guarantee the QoS of each guest OS, the computer system designer physically sets the guest OS so that the total data transfer performance of each guest OS does not exceed the maximum value of the data transfer performance of the data transfer path. Assign it to a device. In addition, after actually starting operation, the data transfer performance of each guest OS may not be as designed. Possible causes are that the guest OS behaves differently from the previous measurement, or that a circuit on the data transfer path is defective. In such a situation, the computer system designer looks at the usage rate of the data transfer path, the degree of congestion, and the like to find out the cause of the performance degradation. At that time, masking the TLP for measuring the data transfer amount contributes to improving the accuracy of analysis.

  As described above, the performance monitor circuit is implemented in the PCI Express component and operates in the same clock cycle as the PCI Express component in order to count the number of events that occur every clock cycle. Accordingly, the cycle interval and cycle period can be specified in units of clock cycles, and at least the register for storing the cycle interval and cycle period is sized to store the number of clock cycles that satisfy milliseconds. Similarly, the counter register used to count the number of events is at least large enough to count the number of events that occur in milliseconds. As described above, the sampling interval and sampling period in nanoseconds to milliseconds can be specified.

  However, the register that stores the cycle interval and cycle period and the counter register that is used to count the number of events are not particularly limited in size, so that the cycle interval and cycle period can be specified for 1 second, etc. You can expand or reduce as necessary.

  Next, the performance monitoring circuit can divide and execute the above three measurements and the recording of the measurement results within the sampling period according to the sampling interval specified by the user. For example, the sampling period is 10 seconds. When the sampling interval is also set to 10 seconds, recording is performed only once. When the sampling interval is set to 1 second, measurement for 1 second and recording of the measurement result are repeated 10 times.

  Furthermore, the performance monitor circuit can record the above three measurements and measurement results at the same sampling interval and sampling period when there are a plurality of buffers in the PCI Express component. Thereby, the temporal correlation of the measurement result of each buffer can be seen.

  As described above, according to the embodiment for carrying out the present invention, even when the performance analysis of the PCI Express component is performed by designating the sampling period and the sampling interval, the PCI Express is used without using the performance analysis software. Analysis of component data transfer performance is possible. Since the performance monitor circuit is mounted in the PCI Express component, it can operate in the same clock cycle as that of the PCI Express component, and the sampling interval can be specified in units of clock cycles smaller than milliseconds in performance analysis. As a result, it is possible to perform a performance analysis with a finer granularity than in the prior art.

1 is an example of a computer system according to a first embodiment. The switch in Example 1 is shown. 2 shows a configuration example of a performance monitor circuit according to the first embodiment. 2 shows an example of a mask register according to the first embodiment. 3 shows an example of a control register according to the first embodiment. 3 shows an example of a status register 322 according to the first embodiment. An example of the SRAM 323 according to the first embodiment is shown. An example of the process flowchart of the control circuit of Example 1 is shown. The switch in Example 2 is shown. 3 shows a configuration example of a performance monitor circuit according to a second embodiment. An example of SRAM of Example 2 is shown. An example of the status register of Example 2 is shown.

Explanation of symbols

100: CPU, 101: Memory, 110: Root Complex, 111: Switch, 112-113: End Point, 120: Service Processor, 130: Management Console, 140-142: PCI Express Link, 150-153: Interface between service processor and PCI Express component, 160: Interface between management console and service processor, 200: Upstream port, 201-202: Downstream port, 210-211: Buffer, 220: Crossbar Switch, 230, 930: Performance monitor circuit, 250, 950: Path for passing information for data transfer performance measurement to the performance monitor circuit, 251, 951: Copy of TLP transferred by buffer A path to be passed to the performance monitor circuit, 252 to 253: a path for reading the setting of the performance monitor circuit and a measurement result, 300: a counter circuit, 310-312, 1010 to 1012: a counter register, 320: a mask register, 321 Control register, 322, 1022: status register, 323, 1023: SRAM, 330, 1030: performance monitor circuit.

Claims (12)

A buffer, storing a received PCI Express transaction layer packet in the buffer, connecting to a PCI express component that transmits the packet stored in the buffer, and determining a data amount of the packet transmitted from the buffer A first counter for measuring, a second counter for measuring the number of clock cycles in which the packet is present in the buffer, and a second counter for measuring the number of clock cycles in which there is a packet to be transmitted but cannot be transmitted in the buffer. And a control circuit that controls to repeat the measurement by the first counter to the third counter at predetermined time intervals. 2. The performance monitor circuit according to claim 1, further comprising a storage circuit for storing measured values obtained by the first to third counters at the predetermined time interval. The control circuit initializes the first to third counters in response to storing the measured values by the first to third counters in the storage circuit at the predetermined time interval. The performance monitor circuit according to claim 2. 4. The performance monitor circuit according to claim 3, further comprising a control register that the control circuit refers to a measurement period by the first to third counters repeated at the predetermined time and the predetermined time interval. 5. The performance monitor circuit according to claim 4, further comprising a mask register referred to by the first counter for measuring a data amount of a desired packet in the packet. The buffers are an upstream buffer and a downstream buffer, and each of the upstream buffer and the downstream buffer includes the first to third counters. The performance monitor circuit according to claim 1. A buffer, storing a received PCI Express transaction layer packet in the buffer, connecting to a PCI express component that transmits the packet stored in the buffer, and determining a data amount of the packet transmitted from the buffer Measuring the number of clock cycles in which the packet is present in the buffer, measuring the number of clock cycles in which there is a packet to be transmitted but not being transmitted in the buffer, and the first to third counters The performance monitoring method characterized by repeating the measurement according to the above at predetermined time intervals. The data amount measured at the predetermined time interval, the number of clock cycles in which the packet exists in the buffer, and the number of clock cycles in which there is a packet to be transmitted in the buffer but cannot be transmitted are stored in a storage circuit. The performance monitoring method according to claim 7. In response to storage in the storage circuit, measurement of the amount of data, the number of clock cycles in which the packet is present in the buffer, and the number of clock cycles in which the packet to be transmitted exists in the buffer but could not be transmitted. 9. The performance monitoring method according to claim 8, wherein initialization is performed. 10. The performance monitoring method according to claim 9, wherein a measurement period repeated at the predetermined time and the predetermined time interval is set in a control register. 11. The performance monitoring method according to claim 10, wherein the first counter sets mask data for measuring a data amount of a desired packet among the packets in a mask register. The buffer is an upstream buffer and a downstream buffer, and for each of the upstream buffer and the downstream buffer, the amount of data and the clock cycle in which the packet is present in the buffer. 8. The performance monitoring method according to claim 7, wherein the number and the number of clock cycles in which a packet to be transmitted exists in the buffer but cannot be transmitted are measured.

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