JP2009031751A - Display device, its driving method, and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device and its driving method capable of taking in image data of a high frequency so as not to impair image quality, and to provide electronic equipment. <P>SOLUTION: A horizontal drive circuit 130A divides a plurality of signal lines into a plurality of groups, and provides a plurality of (four is taken as an example in the embodiment) signal drivers 131-134 for propagating the image data supplied to the signal line corresponding to each division group. Phases of horizontal start pulses HST1, HST2, HST3, HST4 and horizontal clock pulses HCK1, HCK2, HCK3, HCK4 being drive pulses for controlling to drive the plurality of the signal drivers 131-134 deviate with each of signal drivers 131-134. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a display device in which a thin film transistor as a switching element is formed on a transparent insulating substrate, a method for driving the display device, and an electronic device, and more particularly to improvement of a signal line driving technique.

  A display device, for example, a liquid crystal display device (liquid crystal display) using a liquid crystal cell as a pixel display element (electro-optical element) is an active matrix type in which pixels are arranged in a matrix and an output image is displayed via a liquid crystal display surface. Image display.

  Liquid crystal display devices are used in a wide range of electronic devices such as personal digital assistants (PDAs), mobile phones, digital cameras, video cameras, display devices for personal computers, etc., taking advantage of their low profile and low power consumption. Has been applied.

By the way, generally, the flickering of the screen called flicker is not recognized by human eyes if the frame frequency of the image is 60 Hz or higher.
However, this frequency is a frequency at which human motion blur is recognized not only in still image display but also in video display.
In order to improve this, as disclosed in Patent Document 1, for example, a frame frequency of 240 Hz, which is four times, is necessary to eliminate blurring of moving images.

  In the display method disclosed in Patent Document 1, with respect to a writing method using a thin film transistor (TFT), one frame image is written in 1/240 seconds by setting to sequentially display pixels from the left. Alternatively, writing is performed on the liquid crystal for 1/60 second by shifting the time, and frame rewriting is performed as if 1/240 second (FIG. 21 of Patent Document 1).

  Patent Document 2 discloses a technique that enables video data to be written at a data transfer rate of about 200 MHz.

In this liquid crystal display device, as shown in FIG. 1, data for one line is stored in the memory circuit 2 via the switch 1. In the liquid crystal display device, red (R), green (G), and blue (B) are switched by the switches 4-1 to 4-3 while storing data in the memory circuit 3 during the next one line period. Red (R) video data is selected from the video data.
Then, the R data is read from the memory circuit by one driver IC via the switch 5-1 (˜5-3) which is switched in conjunction with the switch 1, and this driver IC 6-1 (˜6-3) is read out. ) And simultaneously write to another driver IC. By writing in the same way for green (G) and blue (B), separate video data can be simultaneously written in each driver IC. Then, the liquid crystal display panel 7 displays an image based on the written video data of the driver IC.

JP 2006-78505 A JP 11-338438 A

  However, Patent Document 1 described above does not describe the input timing (input method) of image signal data to the data line driving circuit, and a specific writing system with an image frame frequency of 240 Hz is not constructed.

In the technique disclosed in Patent Document 2, as shown in FIG. 1, the image data is written in the driver ICs 6-1 to 6-3 in a synchronized manner and supplied to the three driver ICs. The data is also synchronized.
In this state, image data between adjacent ones, rising noise of the clock and falling noise at the falling edge are increased, and voltage fluctuations of the image data and the clock signal themselves are caused to be unstable.
For this reason, when the deformed image data is input, an error occurs in the image data of the driver IC, and the image quality is significantly impaired. The waveform after waveform shaping by the buffer circuit is a waveform that causes a data error.
In particular, in a state where the frequency exceeds 100 MHz, it is difficult to ignore the jumping noise in the adjacent wiring in the cable and the printed board.

Currently, VGA (800 pixels × 600 pixels) has a clock frequency of 27 MHz, and a quadruple high frame rate requires 108 MHz.
Further, in the case of UXGA (1600 pixels × 1400 pixels), the lowest frame frequency is 135 MHz, and its quadruple speed is 540 MHz, which is not a frequency that can be controlled by a normal print board.
Here, split driving is required, but it is limited to 4 to 5 splits due to the size of the panel system.
In this state, as described above, a jumping potential due to a high component due to the parasitic capacitance is generated in the adjacent wiring that supplies a signal to the driver IC. This appears as noise in the clock and image data, and as a result, the image quality of the panel is impaired as an error in the clock signal and image data.

  It is an object of the present invention to provide a display device, a driving method thereof, and an electronic device that can capture high-frequency image data without impairing image quality.

  The display device according to the first aspect of the present invention corresponds to a pixel portion in which pixel circuits for writing pixel data through switching elements are arranged to form a matrix of at least a plurality of columns, and a row arrangement of the pixel circuits. At least one scanning line for controlling the conduction of the switching element, a plurality of signal lines that are arranged to correspond to the column arrangement of the pixel circuit, and that propagate the pixel data; and the plurality of signal lines And a horizontal drive circuit including a plurality of signal drivers for propagating image data supplied to the signal line corresponding to each divided group, and each of the plurality of signal drivers is divided into a plurality of groups. In response to the individual drive pulses, the image data is propagated to the corresponding signal lines, and the drive pulses supplied to the respective signal drivers are positioned relative to each other. It is shifted.

  Preferably, data input to the signal driver is divided and input to adjacent drivers, and the image data is input to each signal driver at a timing synchronized with the drive pulse.

  Preferably, a drive pulse having a frequency higher than a normal frequency is divided, the drive pulses having phases shifted from each other are supplied to the signal drivers, and the image data is divided and input to the signal drivers. A multi-phase clock data generating circuit is arranged to be arranged in a data array and supplied to the horizontal drive circuit.

  Preferably, the multi-phase clock data generation circuit supplies driving pulses including independent clock pulses and start pulses that are out of phase to each signal driver.

  Preferably, the phase shift period Φ of the drive pulse satisfies the relationship of Φ ≦ (T / 2) / N, where N is the half period (T / 2) of the image clock and N is the number to be divided. Is set to

  Preferably, a selector switch for selecting and supplying image data in a time division manner is provided between each of the signal drivers and the corresponding signal line.

  The display device driving method according to the second aspect of the present invention corresponds to a pixel portion in which pixel circuits that write pixel data through switching elements form a matrix of at least a plurality of columns, and a row arrangement of the pixel circuits. At least one scanning line for controlling the conduction of the switching element, a plurality of signal lines that are arranged to correspond to the column arrangement of the pixel circuit, and that propagate the pixel data, and the plurality And a horizontal driving circuit including a plurality of signal drivers for propagating image data supplied to the signal lines corresponding to each divided group, and a method for driving a display device However, the drive signals received for each signal driver are supplied to the plurality of signal drivers by supplying individual drive pulses that are out of phase with each other. In response to the scan to propagate the image data to the corresponding signal line.

  According to a third aspect of the present invention, there is provided an electronic apparatus including a display device, wherein the display device includes a pixel unit in which pixel circuits for writing pixel data through a switching element form a matrix of at least a plurality of columns. And arranged corresponding to the row arrangement of the pixel circuits, arranged corresponding to the column arrangement of the pixel circuits, and at least one scanning line for controlling the conduction of the switching elements, A horizontal drive circuit including a plurality of signal lines to be propagated, and a plurality of signal drivers for dividing the plurality of signal lines into a plurality of groups and propagating image data supplied to the signal lines corresponding to each divided group; Each of the plurality of signal drivers receives an individual drive pulse and propagates image data to a corresponding signal line. Driving pulses to be supplied to the driver is out of phase with each other.

According to the present invention, individual drive pulses that are out of phase with each other are supplied to a plurality of signal drivers.
Then, in response to the drive pulse received for each signal driver, the image data is propagated to the corresponding signal line.

  According to the present invention, the control clock, the start pulse as the synchronization signal, and the frequency of the image data are multiplexed and multi-phased, so that high-frequency image data can be captured without impairing the image quality. It becomes possible.

  Before describing embodiments of the present invention, a general horizontal drive circuit will be described.

  FIG. 2 shows an example of a drive pulse supplied to a signal driver of a general horizontal drive circuit 130 as a comparative example of this embodiment. In this case, the signal driver is divided into four horizontal display areas and image data is input at a frequency four times as high.

In this example, as can be seen from FIG. 2, since the image signal data is captured by one control clock, the signal driver needs to process it as an input pulse at a data frequency synchronized with the moving image clock. .
In this state, when image data is input at a frequency four times for high frame rate (HIGH FRAME RATE) display, the followability of the signal driver IC and the impedance of the cable line that transmits the image data conform to the high frequency. Absent. For this reason, image data cannot be input to the liquid crystal display device.
Further, as shown in FIG. 3, not only the image data caused by the interference due to the jumping capacity between the signal lines at the high frequency but also the clock pulse itself is affected by the noise, and normal image display cannot be performed.
That is, as described above, the data supplied to each driver IC is also synchronized. In this state, the image data between adjacent wiring lines, the rising and falling noises NIS of the clock increase, and the image data and the clock signal itself fluctuate and become unstable. In the example shown in FIG. 2, the potentials of the jumping noise NIS of the horizontal clock pulses HCK1, HCK2, HCK3, and HCK4 due to the synchronization signal are increased with respect to each other as indicated by the symbol X in FIG. Note that the image data IMD shown in FIG. 3 has a normal waveform indicated by a broken line and an error portion indicated by a solid line.
As a solution to this, it is necessary to keep the frequency supplied to the signal driver lower and to shift the phase of the horizontal clock pulses HCK1, HCK2, HCK3, HCK4 so as not to increase the jumping noise. It is. By the way, in VGA, the clock frequency is usually 27 MHz at a frame frequency of 60 Hz, and the clock frequency is 108 MHz at a frame frequency of 240 Hz, which is four times the frame frequency.
In order to cope with the above-described problems, the present embodiment captures high-frequency image data as described above by multiplexing the control clock, the start pulse as a synchronization signal, and the frequency of the image data and multi-phase. A configuration that enables this is adopted.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 4 is a block diagram illustrating a configuration example of the liquid crystal display device according to the embodiment of the present invention.
As shown in FIG. 4, the liquid crystal display device 100 includes an effective pixel unit 110, a vertical drive circuit (VDRV) 120, a horizontal drive circuit (HDRV) 130A, and a multiphase clock data generation circuit 140.

In the effective pixel portion 110, a plurality of pixel circuits 111 are arranged in a matrix.
Each pixel circuit 111 includes a thin film transistor (TFT) 112, a liquid crystal cell 113, and a storage capacitor (storage capacitor) 114 as switching elements. The pixel electrode of the liquid crystal cell 113 is connected to the drain electrode (or source electrode) of the TFT 112. One electrode of the storage capacitor 114 is connected to the drain electrode of the TFT 112.
For each of these pixel circuits 111, gate (scanning) lines 115-1 to 115-m are wired along the pixel arrangement direction for each row, and signal lines 116-1 to 116-n are provided for each column. Wiring is performed along the pixel array direction.
The gate electrode of the TFT 112 of each pixel circuit 111 is connected to the same gate (scanning) line 115-1 to 115-m in each row unit. In addition, the source electrode (or drain electrode) of the TFT 112 of each pixel circuit 111 is connected to the same signal line 116-1 to 116-n for each column.
Further, in the liquid crystal cell 113, the pixel electrode is connected to the drain electrode of the TFT 112, and the counter electrode is connected to the common line 117. The storage capacitor 114 is connected between the drain electrode of the thin film transistor TFT and the common line 117.
A predetermined AC voltage is applied to the common line 117 as a common voltage Vcom by a VCOM circuit (not shown) formed integrally with a drive circuit on a glass substrate.
Each pixel circuit 111 writes pixel data to the storage capacitor 114 through the TFT 112 serving as a switching element. The liquid crystal cell 113 is modulated by a voltage based on pixel data written in the storage capacitor 114. The liquid crystal display device 100 displays an image by controlling the transmittance of light transmitted through a pair of polarizing plates (not shown) disposed before and after the liquid crystal cell 113.

  The gate lines 115-1 to 115-m are driven by the vertical drive circuit 120, and the signal lines 116-1 to 116-n are driven by the horizontal drive circuit 130A.

The vertical driving circuit 120 receives the vertical start signal VST, the vertical clock VCK, and the enable signal ENAB, scans in the vertical direction (row direction) every field period, and is connected to the scanning lines 115-1 to 115 -m. A process of sequentially selecting each pixel circuit 111 in units of rows is performed.
That is, when the gate pulse GP1 is applied to the gate line 115-1 from the vertical drive circuit 120, the pixel in each column of the first row is selected, and the scan pulse GP2 is applied to the gate line 115-2. In this case, the pixels in each column of the second row are selected. Similarly, gate pulses GP3,..., GPm are sequentially applied to the gate lines 115-3,.
The vertical start signal VST, the vertical clock VCK, and the enable signal ENAB are generated by another second timing controller (not shown) that is different from the timing controller of the multiphase data generation circuit 140.
The second timing controller is synchronized with the horizontal signals hst, hck1, hck2, hck3, hck4 and data d0 supplied to the multiphase data generation circuit 140.
The vertical driving circuit 120 is synchronized with the output enable signal OTEN that allows the data of the horizontal driving circuit 130A to be output to the signal lines 116-1 to 116-n.

  The horizontal drive circuit 130A divides the signal line into a plurality of groups (four groups are used in the present embodiment for simplification of description), and signal drivers 131 to 134 are provided corresponding to the respective divided groups.

  FIG. 6 shows an example of drive pulses supplied to the signal drivers 131 to 134 of the horizontal drive circuit 130A.

  In the present embodiment, the drive pulse is supplied individually to each of the signal drivers 131 to 134, and includes a horizontal start pulse HST that instructs the start of horizontal scanning and a horizontal clock pulse HCK that serves as a reference for horizontal scanning.

The horizontal start pulse HST2 supplied to the signal driver 132 is supplied with a phase shifted by (1/4) of the clock cycle from the horizontal start pulse HST1 supplied to the signal driver 131.
Similarly, the horizontal start pulse HST3 supplied to the signal driver 133 is supplied with the phase shifted by (1/4) of the clock cycle from the horizontal start pulse HST2 supplied to the signal driver 132.
The horizontal start pulse HST4 supplied to the signal driver 134 is supplied with a phase shifted (delayed) by ¼ of the clock period from the horizontal start pulse HST3 supplied to the signal driver 133.

The horizontal clock pulse HCK2 supplied to the signal driver 132 is supplied with a phase shifted (delayed) by ¼ of the clock period from the horizontal clock pulse HCK1 supplied to the signal driver 131.
Similarly, the horizontal clock pulse HCK3 supplied to the signal driver 133 is supplied with a phase shifted by (1/4) of the clock cycle from the horizontal clock pulse HCK2 supplied to the signal driver 132.
The horizontal clock pulse HCK4 supplied to the signal driver 134 is supplied with a phase shifted (delayed) by ¼ of the clock period from the horizontal clock pulse HCK3 supplied to the signal driver 133.

4 and 6, the signal driver 131 receives a horizontal start pulse HST1 for instructing start of horizontal scanning supplied from the multiphase clock data generation circuit 140, and a horizontal clock pulse HCK1 serving as a reference for horizontal scanning. To generate a sampling pulse.
Then, the signal driver 131 sequentially samples input image data R (red), G (green), and B (blue) in response to the generated sampling pulse, and serves as a data signal to be written to each pixel circuit 111. The signal lines 116-1 to 116-3 are supplied.

The signal driver 132 receives the horizontal start pulse HST2 for instructing the start of horizontal scanning supplied from the multiphase clock data generation circuit 140, and the horizontal clock pulse HCK2 that serves as a reference for horizontal scanning, and generates a sampling pulse.
Then, the signal driver 132 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulse, and serves as a data signal to be written to each pixel circuit 111. The signal lines 116-4 to 116-6 are supplied.

The signal driver 133 receives the horizontal start pulse HST3 for instructing the start of horizontal scanning supplied from the multiphase clock data generation circuit 140, and the horizontal clock pulse HCK3 that serves as a reference for horizontal scanning, and generates a sampling pulse.
Then, the signal driver 133 sequentially samples the input image data R (red), G (green), and B (blue) in response to the generated sampling pulse as a data signal to be written to each pixel circuit 111. The signal lines 116-7 to 116-9 are supplied.

The signal driver 134 receives the horizontal start pulse HST4 for instructing the start of horizontal scanning supplied from the multiphase clock data generation circuit 140 and the horizontal clock pulse HCK4 as a reference for horizontal scanning, and generates a sampling pulse.
Then, the signal driver 134 sequentially samples input image data R (red), G (green), and B (blue) in response to the generated sampling pulse, and serves as a data signal to be written to each pixel circuit 111. The signal lines 116-10 to 116-12 are supplied.

As described above, in the present embodiment, in the horizontal drive circuit 130A, a plurality of signal lines are divided into a plurality of groups, and a plurality of (this embodiment) that propagates image data supplied to the signal lines corresponding to each divided group. In the embodiment, signal drivers 131 to 134 of 4) are provided.
The phases of the horizontal start pulses HST1, HST2, HST3, HST4 and the horizontal clock pulses HCK1, HCK2, HCK3, HCK4, which are drive pulses for driving and controlling the plurality of signal drivers 131-134, are shifted by the signal drivers 131-134. ing.
More specifically, the data input to the signal drivers 131 to 134 is divided and input to adjacent signal drivers.
The signal drivers 131 to 134 are controlled by horizontal clock pulses HCK1 to HCK4 and horizontal start pulses HST1 to HST4 having independent phases, and image data is input at a timing synchronized with the independent clock pulses and start pulses.
That is, as shown in FIGS. 4 and 6, the four signal drivers 131 to 134 are operated independently of each other by shifting the phases of the horizontal start pulse HST and the horizontal clock pulse HCK (in this embodiment, the clocks 1/4 of the period). The final image signal is output in synchronization with the output enable signal OTEN.
As a result, the clock frequency, the start pulse frequency, and the image data frequency can be driven at a frequency lower than the initial frequency.

  The reason why the horizontal drive circuit 130A is driven in this manner in the present embodiment will be described below.

In general, human eyes cannot recognize flickering of a screen called flicker if the frame frequency of the image is 60 Hz or higher.
However, not only a still image display but also a moving image display, the blurring of a human moving image is recognized at this frequency. In order to improve this, a frame frequency of 240 Hz is necessary to eliminate blurring of the moving image.
Therefore, in the active matrix display device, when the moving image characteristic is a current problem, for example, in the liquid crystal display device, the number of frames to be displayed per second and the frame frequency are displayed four times higher than usual to improve the moving image characteristic. . Since it is normally operated at 60 Hz, it is 240 Hz.
Normally, in UXGA (1600 × RGB × 1200), the clock is 135 MHz, and it can operate with a normal silicon IC.
However, if the frequency is higher than this and the frame frequency is quadrupled, the frequency becomes 540 MHz, and it is difficult for the silicon IC to operate at this high frequency.
Further, it is difficult to transmit a mounting cable for connecting the image signal generation to the liquid crystal display device at this frequency due to signal interference between the signal lines. In order to overcome this, it is necessary to lower the frequency.
In the present embodiment, it is possible to cope with this frequency reduction while maintaining the clock of the image data.

  Next, the multiphase clock data generation circuit 140 of this embodiment will be described.

The multiphase clock data generation circuit 140 receives a horizontal start pulse hst and horizontal clock pulses hck1 to hck4 supplied from a graphics IC (not shown), for example, and divides the frequency into 1/4.
The multi-phase clock data generation circuit 140 generates a divided horizontal start pulse HST1 and a horizontal clock pulse HCK1 whose phase is shifted by 1/4 of the clock cycle from the horizontal start pulse HST1 (a signal driver of the horizontal drive circuit 130A). 131.
In addition, the multiphase clock data generation circuit 140 generates a horizontal start pulse HST2 whose phase is shifted by 1/4 of the clock cycle from the horizontal start pulse HST1. The multiphase clock data generation circuit 140 uses the horizontal drive circuit 130A to convert the horizontal start pulse HST2 and the divided horizontal clock pulse HCK2 whose phase is shifted (delayed) by 1/4 of the clock period from the horizontal start pulse HST2. The signal driver 132 is supplied.
Further, the multiphase clock data generation circuit 140 generates a horizontal start pulse HST3 whose phase is shifted (delayed) by ¼ of the clock period from the horizontal start pulse HST2. The multi-phase clock data generation circuit 140 uses the horizontal drive circuit 130A to convert the horizontal start pulse HST3 and the horizontal clock pulse HCK3 after the frequency division from the horizontal start pulse HST3 with a phase shifted by 1/4 of the clock cycle (delayed). To the signal driver 133.
In addition, the multiphase clock data generation circuit 140 generates a horizontal start pulse HST4 whose phase is shifted (delayed) by ¼ of the clock cycle from the horizontal start pulse HST3. The multi-phase clock data generation circuit 140 uses the horizontal drive circuit 130A to output the horizontal clock pulse HCK4 obtained by dividing the horizontal start pulse HST4 and the horizontal clock pulse HCK4 after the phase is shifted (delayed) by 1/4 of the clock cycle from the horizontal start pulse HST4 To the signal driver 134.

  The phase shift period Φ of the clock is set so as to satisfy the condition of Φ ≦ (T / 2) / N, where N is the half period (T / 2) of the image clock and the number of frequency division is N. Is done.

  The multiphase clock data generation circuit 140 arranges the supplied image data d0 in a line buffer. Then, the multiphase clock data generation circuit 140 rearranges the image data into a plurality of (four in the present embodiment) independent line memory buffers from the state where the image data is arranged in the frequency dividing process and the line memory buffer, and each line memory An independent output is supplied from the buffer circuit to the signal driver side.

FIG. 7 is a diagram illustrating a specific configuration example of the multiphase clock data generation circuit 140 according to the present embodiment.
FIG. 8 is a diagram for explaining an example of timing control and data writing after frequency division in the multiphase clock data generation circuit according to the present embodiment.

  The multiphase clock data generation circuit 140 includes a timing controller (TC) 141, a data memory buffer and counter 142, a first counter and flip-flop (CT / FF) 143, a second CNT / FF 144, a third CNT / FF 145, and a fourth CNT / It has FF146.

The timing controller 141 receives, for example, a horizontal start pulse hst1 and a horizontal clock pulse hck1 to hck4 having a regular quadruple frequency, and sends trigger point signals a1 to a4 whose phases are shifted by Φ to the first to fourth CNT / FFs 143 to 146. Supply.
Specifically, the timing controller 141 supplies the trigger point signal a1 to the first CNT / FF, and supplies the trigger point signal a2 that is Φ out of phase with the trigger point signal a1 to the second CNT / FF 144.
Furthermore, the timing controller 141 supplies the trigger point signal a3 whose phase is shifted by Φ to the trigger point signal a2 to the third CNT / FF 145, and the trigger point signal a4 whose phase is shifted by Φ to the fourth CNT / FF 145. Supply.

In addition, the timing controller 141 receives, for example, a horizontal start pulse hst1 and a horizontal clock pulse hck1 to hck4 having a regular quadruple frequency, and supplies trigger point signals b1 to b4 whose phases are shifted by Φ to the data memory buffer and the counter 142. To do.
Specifically, the timing controller 141 supplies the trigger point signal b1 and the trigger point signal b2 whose phase is shifted by Φ from the trigger point signal b1 to the data memory buffer and the counter 142.
Further, the timing controller 141 supplies the trigger point signal b3 whose phase is shifted by Φ from the trigger point signal b2 and the trigger point signal a4 whose phase is shifted by Φ from the trigger point signal a3 to the data memory buffer and the counter 142.

  The timing controller 141 generates the trigger point signals a1 to a4 and b1 to b4 so that synchronization is maintained.

  The timing controller 141 generates an output enable signal OTEN, which is a control signal for the horizontal period, and outputs it to the horizontal drive circuit 130A and the vertical drive circuit.

The data memory buffer and counter 142 receives the input data d0, and synchronizes with the trigger point signals b1 to b4 by the timing controller 141 to extend the cycle by four times and shift the data D1, D2, D3, D4 by Φ. , ... are sorted and output.
The rearranged data D1, D2, D3, D4,... Are formed from R (red), G (green), and B (blue) data.

The first CNT / FF 143 receives the trigger point signal a1 from the timing controller 141 and divides the horizontal start pulse hst and the horizontal clock pulse hck1.
Then, the first CNT / FF 143 uses the divided horizontal start pulse HST1 and the horizontal clock pulse HCK1 whose phase is shifted (delayed) by ¼ of the clock period from the horizontal start pulse HST1 to the signal driver 131 of the horizontal drive circuit 130A. To supply.

The second CNT / FF 144 divides the horizontal start pulse hst and the horizontal clock pulse hck2 in response to the trigger point signal a2, and the phase is shifted from the horizontal start pulse HST1 by 1/4 of the clock cycle (delayed). A pulse HST2 is generated.
The second CNT / FF 144 uses the horizontal start pulse HST2 and the horizontal clock pulse HCK2 obtained by dividing the phase shifted from the horizontal start pulse HST2 by a quarter of the clock period (delayed) by the signal driver of the horizontal drive circuit 130A. 132.

The third CNT / FF 145 receives the trigger point signal a3, divides the horizontal start pulse hst and the horizontal clock pulse hck3, and the horizontal start is shifted (delayed) by ¼ of the clock period from the horizontal start pulse HST2. A pulse HST3 is generated.
The third CNT / FF 145 is a signal driver for the horizontal drive circuit 130A that converts the horizontal start pulse HST3 and the divided horizontal clock pulse HCK3 whose phase is ¼ shifted (delayed) from the horizontal start pulse HST3 to the clock cycle. 133.

The fourth CNT / FF 146 receives the trigger point signal a4, divides the horizontal start pulse hst and the horizontal clock pulse hck4, and the horizontal start pulse whose phase is shifted by 1/4 of the clock cycle (delayed) from the horizontal start pulse HST3. A pulse HST4 is generated.
The fourth CNT / FF 146 uses this horizontal start pulse HST4 and the horizontal clock pulse HCK4 whose frequency is shifted (delayed) by 1/4 of the clock cycle from the horizontal start pulse HST4 as a signal driver for the horizontal drive circuit 130A. 134.

In this way, as shown in FIG. 8, the multi-phase clock data generation circuit 140 displays the horizontal clock pulses hck1 to hk4 having a regular quadruple frequency and the horizontal drive synchronized with the horizontal frame pulse for displaying the quadruple high frame rate. The horizontal start pulse hst is input.
The timing controller 141 generates trigger point signals b1 to b4. The data memory buffer and counter 142 receives the trigger point signals b1 to b4, accumulates horizontal image data within one horizontal period, and rearranges image data suitable for each independent signal driver 131 to 134 in an array. I do.

Here, an output data period and an input data period of one horizontal period are shown. As a result, the data can be processed.
here,
T is “the period of the horizontal clock pulse HCK which is the control clock of the signal driver (IC)”,
T1 is “a data period of one horizontal period after four divisions”,
T2 is “a data period of one horizontal period”,
T3 is “one horizontal period”
Respectively.

  In the above period, the following relationship holds.

[Equation 1]
T3 ≧ T1 ≧ T2

That is, for example, the data period T1 of one horizontal period after four divisions is larger than the data period T2 of one horizontal period of high frequency before the original division and shorter than one horizontal period T3.
Satisfying this relationship is a condition that satisfies the timing chart for realizing the characteristic function of the present embodiment.

Further, as shown in FIGS. 7 and 8, the horizontal clock pulses HCK1 to HCK4 and the horizontal start pulses HST1 to HST4, which are supplied to the signal drivers 131 to 134 of the present embodiment and are out of phase, are converted into independent CNTs. / FF143-146.
To this circuit, an image clock pulse hck supplied from an original video source and a start pulse hst for a synchronization signal are input.
This is frequency-divided by the control of the timing controller 141, and the image data d0 input at the same time is also reproduced as four independent data D1 to D4 from the state where the image data d0 is arranged in the frequency-division processing and the data memory buffer and counter 142. Arranged.
In each of the first to fourth CNT / FFs 143 to 146, the line memory buffers 143, 144, 145, and 146 can supply independent outputs to each signal driver side.
In addition, in this state, the phase can be shifted in a form corresponding to the frequency division using the frequency-divided clock.

As described above and indicated by the symbol Y in FIG. 9, the horizontal clock pulse HCK1 is out of phase with the horizontal clock pulse HCK2, and therefore, only the jumping noise NIS of the horizontal clock pulse HCK2 is affected.
Similarly, the horizontal clock pulse HCK2 is affected only by the jumping noise NIS only in the horizontal clock pulse HCK3.
That is, noise resulting from redundant jumping potentials of the horizontal clock pulses HCK1, HCK2, HCK3, and HCK4 due to the synchronization signal is reduced.
Therefore, the waveform of the image data IMD after waveform shaping by a buffer circuit (not shown) of each signal driver 131 to 134 has no error portion as shown in FIG. A regular rectangular waveform is obtained.

As described above, the phase shift period Φ is equal to the half cycle (T / 2) of the input image clock or equal to or less than the divided integer value N.
This relationship is represented by Φ ≦ (T / 2) / N.

  Next, the operation according to the above configuration will be described with reference to FIGS.

  As shown in FIG. 4, the vertical drive circuit 120 receives the vertical start signal VST, the vertical clock VCK, and the enable signal ENAB, and sequentially selects each pixel circuit 111 in units of rows. The vertical drive circuit 120 receives each signal, scans in the vertical direction (row direction) for each field period, and sequentially selects each pixel circuit 111 connected to the scan lines 115-1 to 115 -m in units of rows. Processing is performed.

Then, the multiphase clock data generation circuit 140 receives a horizontal start pulse hst and a horizontal clock pulse hck1 to hck4 of, for example, a regular quadruple frequency supplied from a graphics IC (not shown) and divides the frequency into 1/4. Is done.
In the multi-phase clock data generation circuit 140, the divided horizontal start pulse HST1 and the horizontal clock pulse HCK1 whose phase is shifted from the horizontal start pulse HST1 by 1/4 of the clock cycle (delayed) are the signal drivers of the horizontal drive circuit 130A. 131.
Similarly, in the multiphase clock data generation circuit 140, a horizontal start pulse HST2 whose phase is shifted (delayed) by 1/4 of the clock cycle from the horizontal start pulse HST1 is generated.
In the multi-phase clock data generation circuit 140, the horizontal drive pulse 130A is obtained by dividing the horizontal start pulse HST2 and the horizontal clock pulse HCK2 whose frequency is shifted (delayed) by 1/4 of the clock period from the horizontal start pulse HST2. Is supplied to the signal driver 132.
In addition, the multiphase clock data generation circuit 140 generates a horizontal start pulse HST3 whose phase is shifted (delayed) by ¼ of the clock cycle from the horizontal start pulse HST2.
In the multi-phase clock data generating circuit 140, the horizontal start pulse HST3 and the horizontal clock pulse HCK3 after frequency division are shifted from the horizontal start pulse HST3 by a quarter of the clock cycle (delayed). Is supplied to the signal driver 133.
Further, the multi-phase clock data generation circuit 140 generates a horizontal start pulse HST4 whose phase is shifted (delayed) by ¼ of the clock cycle from the horizontal start pulse HST3.
In the multi-phase clock data generation circuit 140, the horizontal drive pulse 130A is obtained by dividing the horizontal start pulse HST4 and the horizontal clock pulse HCK4 after phase division by 1/4 of the clock cycle (delayed) from the horizontal start pulse HST4. To the signal driver 134.

  In the multiphase clock data generation circuit 140, the supplied image data D0 is arranged in a line buffer. In the multiphase clock data generation circuit 140, the image data is rearranged into a plurality of (four in the present embodiment) independent line memory buffers from the state of the frequency division processing and the line memory buffer, and each line An independent data output from the memory buffer is supplied to the signal driver side (FIG. 8).

Then, the signal driver 131 receives the horizontal start pulse HST1 for instructing the start of horizontal scanning supplied from the multiphase clock data generation circuit 140 and the horizontal clock pulse HCK1 as a reference for horizontal scanning to generate a sampling pulse. .
Further, in the signal driver 131, input image data R (red), G (green), and B (blue) are sequentially sampled in response to the generated sampling pulse.
In the signal driver 131, in synchronization with the output enable signal OTEN, a data signal to be written to each pixel circuit 111 is supplied to each signal line 116-1 to 116-3.

Similarly, the signal driver 132 receives a horizontal start pulse HST2 for instructing the start of horizontal scanning that is out of phase with the horizontal start pulse HST1 and the horizontal clock pulse HCK1, and a horizontal clock pulse HCK2 serving as a reference for horizontal scanning. A sampling pulse is generated.
Further, in the signal driver 132, input image data R (red), G (green), and B (blue) are sequentially sampled in response to the generated sampling pulse.
In the signal driver 132, the data signal to be written to each pixel circuit 111 is supplied to each signal line 116-4 to 116-6 in synchronization with the output enable signal OTEN.

The signal driver 133 receives the horizontal start pulse HST3 for instructing the start of horizontal scanning, which is out of phase with the horizontal start pulse HST2 and the horizontal clock pulse HCK2, and the horizontal clock pulse HCK3 which is a reference for horizontal scanning, and receives a sampling pulse. Generated.
Further, in the signal driver 133, input image data R (red), G (green), and B (blue) are sequentially sampled in response to the generated sampling pulse.
In the signal driver 133, in synchronization with the output enable signal OTEN, a data signal to be written to each pixel circuit 111 is supplied to each signal line 116-7 to 116-9.

The signal driver 134 receives the horizontal start pulse HST4 for instructing the start of horizontal scanning, which is out of phase with the horizontal start pulse HST3 and the horizontal clock pulse HCK3, and the horizontal clock pulse HCK4 which serves as a reference for horizontal scanning. Generated.
Further, in the signal driver 134, input image data R (red), G (green), and B (blue) are sequentially sampled in response to the generated sampling pulse.
In the signal driver 133, in synchronization with the output enable signal OTEN, a data signal to be written to each pixel circuit 111 is supplied to each signal line 116-10 to 116-12.

  The vertical drive circuit 120 receives the output enable signal OTEN that allows the output of the data of the horizontal drive circuit 130A to the signal lines 116-1 to 116-n, and the output enable signal OTEN changes from the active high level to the non-active level. The gate pulse can be output at the timing of falling to the active low level.

As described above, according to the present embodiment, in the horizontal drive circuit 130A, a plurality of signal lines are divided into a plurality of groups, and image data supplied to the signal lines is propagated corresponding to each divided group. A plurality of signal drivers 131 to 134 are provided.
The phases of the horizontal start pulses HST1, HST2, HST3, HST4 and the horizontal clock pulses HCK1, HCK2, HCK3, HCK4, which are drive pulses for driving and controlling the plurality of signal drivers 131-134, are shifted by the signal drivers 131-134. ing.
The signal drivers 131 to 134 are controlled by horizontal clock pulses HCK1 to HCK4 and horizontal start pulses HST1 to HST4 having independent phases, and image data is input at a timing synchronized with the independent clock pulse and start pulse.
In this embodiment, the signal drivers 131 to 134 are operated independently of the horizontal start pulse HST and the horizontal clock pulse HCK, and the final image signal is synchronized with the output enable signal OTEN. It is configured to output.
Therefore, according to the present embodiment, the clock frequency, the start pulse frequency, and the image data frequency can be driven at a frequency lower than the initial frequency.

As a result, high-speed image transfer at high pixels is possible without impairing image quality.
In addition, the display at a high frame rate significantly improves the moving image characteristics of the display device compared to those at the existing frame frequency, eliminating the flow of images.
In addition, since an image signal driver operable at a normal clock frequency can be used, a display device can be produced with an inexpensive IC. There is no need to use a special high-speed image signal driver.

The present invention is also effective for a method of writing image data in a panel in a time division manner. In particular, in order to reduce the frame of the panel, as shown in FIG. 10, even when a time division switch is used, if the number of time divisions does not sufficiently satisfy the electrical characteristics and image characteristics in the horizontal selection period, Application of the invention is required.
In this case, the signal driver connected to the time division switch receives the clock pulse (control clock), the start pulse, and the image data out of phase and divides the frequency as described above.

In FIG. 10, the signal SV by the signal drivers 131 to 134 is transferred to the signal lines 116 (-1 to -12) via the selector SEL having a plurality of transfer gates TMG.
Each transfer gate (analog switch) TGM is turned on by a selection signal S1 having an external complementary level and its inverted signal XS1, a selection signal S2 and its inverted signal XS2, a selection signal S3 and its inverted signal XS3,. Be controlled.

  As described above, in the active matrix display device of high definition (UXGA) and high-speed frame rate method, it is possible to adopt the selector time division driving method that reduces the number of connection terminals and improves the mechanical reliability of connection.

  Note that CMOS signaling, LVDS (Low Voltage Differential Signaling), and TMDS (Transition Minimized Differential Signaling) can be applied to transfer the digital data used in this embodiment. These transfer methods are used on the input side and output side of the multiphase clock data generation circuit 140 in the present embodiment.

  An active matrix display device typified by the active matrix liquid crystal display device according to the above embodiment is used as a display for OA equipment such as a personal computer and a word processor, and a television receiver. In addition, the present display device is particularly suitable for use as a display unit of an electronic device such as a mobile phone or a PDA in which the device main body is being reduced in size and size.

That is, the display device 100 according to the present embodiment can be applied to various electronic devices illustrated in FIGS.
For example, display devices for electronic devices in various fields, such as digital cameras, notebook personal computers, mobile phones, video cameras, etc., that display video signals input to electronic devices or generated in electronic devices as images or videos. It is possible to apply to.
Hereinafter, examples of electronic devices to which such a display device is applied will be described.

  FIG. 11A illustrates an example of a television 300 to which the present invention is applied. The television 300 includes a video display screen 303 including a front panel 301, a filter glass 302, and the like. Then, the display device according to the embodiment of the present invention is manufactured by using the video display screen 303.

  10B and 10C show an example of a digital camera 310 to which the present invention is applied. The digital camera 310 includes an imaging lens 311, a flash light emitting unit 312, a display unit 313, a control switch 314, and the like. And it is produced by using the display apparatus which concerns on embodiment of this invention for the display part 313. FIG.

  FIG. 11D shows a video camera 320 to which the present invention is applied. The video camera 320 includes a main body 321, a subject shooting lens 322 on the side facing forward, a start / stop switch 323 at the time of shooting, a display unit 324, and the like. Then, the display device according to the embodiment of the present invention is manufactured by using the display unit 224 for the display device.

  11E and 11F show a mobile terminal device 330 to which the present invention is applied. The mobile terminal device 330 includes an upper housing 331, a lower housing 332, a connecting portion (here, a hinge portion) 333, a display 334, a sub display 335, a picture light 336, a camera 337, and the like. And it is produced by using the display apparatus which concerns on embodiment of this invention for the display 334 or the sub display 335. FIG.

  FIG. 11G shows a laptop personal computer 340 to which the present invention is applied. The laptop personal computer 340 includes a main body 341 including a keyboard 342 operated when inputting characters and the like, a display unit 343 for displaying images, and the like. Then, the display device according to the embodiment of the present invention is manufactured by using the display unit 343.

  In the above embodiment, the case where the present invention is applied to an active matrix liquid crystal display device has been described as an example. However, the present invention is not limited to this, and can be similarly applied to other active matrix display devices such as an EL display device using an electroluminescence (EL) element as an electro-optical element of each pixel. is there.

FIG. 1 is a diagram for explaining an existing technology that enables video data to be written at a data transfer rate of about 200 MHz. FIG. 2 is a diagram illustrating an example of a driving pulse supplied to a signal driver of a general horizontal driving circuit as a comparative example of the present embodiment. FIG. 3 is a diagram for explaining the problem of FIG. FIG. 4 is a block diagram illustrating a configuration example of the liquid crystal display device according to the embodiment of the present invention. FIG. 5 is a waveform diagram showing the relationship between the output enable signal and the gate pulse. FIG. 6 is a diagram illustrating an example of drive pulses supplied to each signal driver of the horizontal drive circuit. FIG. 7 is a diagram showing a specific configuration example of the multiphase clock data generation circuit according to the present embodiment. FIG. 8 is a diagram for explaining an example of writing data after timing control and frequency division in the multiphase clock data generation circuit according to the present embodiment. FIG. 9 is a diagram for explaining the effect of the present embodiment. FIG. 10 is a block diagram showing a configuration example of a liquid crystal display device according to an embodiment of the present invention using a time division switch. FIG. 11 is a diagram illustrating an example of an electronic apparatus to which the display device according to this embodiment is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Liquid crystal display device, 110 ... Effective pixel part, 120 ... Vertical drive circuit (VDRV), 130A ... Horizontal drive circuit (HDRV), 131-134 ... Signal driver, 140 ...・ Multi-phase clock data generator.

Claims (11)

A pixel portion in which pixel circuits for writing pixel data through the switching elements are arranged to form a matrix of at least a plurality of columns;
At least one scan line arranged to correspond to the row arrangement of the pixel circuit, and for controlling conduction of the switching element;
A plurality of signal lines arranged to correspond to the column arrangement of the pixel circuits and propagating the pixel data;
A horizontal driving circuit including a plurality of signal drivers that divide the plurality of signal lines into a plurality of groups and that propagate the image data supplied to the signal lines corresponding to each divided group;
Each of the plurality of signal drivers is
Receive individual drive pulses to propagate the image data to the corresponding signal line,
The drive pulses supplied to each signal driver are out of phase with each other. Data input to the signal driver is divided and input to adjacent drivers,
Each signal driver above
The display device according to claim 1, wherein the image data is input at a timing synchronized with the drive pulse. A drive pulse having a frequency higher than the normal frequency is divided, the drive pulses having phases shifted from each other are supplied to the signal drivers, and the image data is divided and arranged in a data array input to the signal drivers. The display device according to claim 1, further comprising a multiphase clock data generation circuit that supplies the horizontal drive circuit. A drive pulse having a frequency higher than the normal frequency is divided, the drive pulses having phases shifted from each other are supplied to the signal drivers, and the image data is divided and arranged in a data array input to the signal drivers. The display device according to claim 2, further comprising a multiphase clock data generation circuit that supplies the horizontal drive circuit. The multi-phase clock data generation circuit
The display device according to claim 3, wherein drive pulses including independent clock pulses and start pulses that are out of phase are supplied to each signal driver. The multi-phase clock data generation circuit
The display device according to claim 4, wherein drive pulses including independent clock pulses and start pulses that are out of phase are supplied to each signal driver. The phase deviation period Φ of the drive pulse is set so as to satisfy the relationship of Φ ≦ (T / 2) / N, where N is the half period (T / 2) of the image clock and the number of frequency divisions is N. The display device according to claim 4. The phase shift period Φ of the drive pulse is set so as to satisfy the relationship of Φ ≦ (T / 2) / N, where N is the half period (T / 2) of the image clock and the number to be divided is N. The display device according to claim 6. The display device according to claim 1, further comprising a selector switch for selecting and supplying image data in a time-sharing manner between each of the signal drivers and the corresponding signal line. A pixel portion in which pixel circuits for writing pixel data through the switching elements are arranged to form a matrix of at least a plurality of columns;
At least one scan line arranged to correspond to the row arrangement of the pixel circuit, and for controlling conduction of the switching element;
A plurality of signal lines arranged to correspond to the column arrangement of the pixel circuits and propagating the pixel data;
A plurality of signal lines are divided into a plurality of groups, and a horizontal driving circuit including a plurality of signal drivers for propagating image data supplied to the signal lines is arranged for each divided group,
Supplying individual drive pulses that are out of phase with each other to the plurality of signal drivers,
A method for driving a display device, wherein image data is propagated to a corresponding signal line in response to a driving pulse received for each signal driver. Having a display device;
The display device
A pixel portion in which pixel circuits for writing pixel data through the switching elements are arranged to form a matrix of at least a plurality of columns;
At least one scan line arranged to correspond to the row arrangement of the pixel circuit, and for controlling conduction of the switching element;
A plurality of signal lines arranged to correspond to the column arrangement of the pixel circuits and propagating the pixel data;
A horizontal driving circuit including a plurality of signal drivers that divide the plurality of signal lines into a plurality of groups and that propagate the image data supplied to the signal lines corresponding to each divided group;
Each of the plurality of signal drivers is
Receive individual drive pulses to propagate the image data to the corresponding signal line,
The drive pulses supplied to each signal driver are electronic devices that are out of phase with each other.

Images