JP2008529283A - Composition and method for making interconnect elements having metal traces embedded in the surface of a dielectric - Google Patents

Abstract

  An interconnect element (201) is provided that includes a dielectric element (210) having a major surface. The metal interconnect patterns (208 and 208 ′) are embedded in recesses that extend inwardly from the major surface, and the outer surface of the interconnect pattern is substantially coplanar with the major surface and one of the major surfaces. Extends in more than one direction. The protruding conductive film (220) is conductive on the outer surface of at least one pattern of the metal interconnect pattern (208 ′) such that it contacts the dielectric element (210) along at least a portion of the major surface. Extending on the major surface in at least one direction parallel to a plane defined by the major surface so as to be in contact with each other.

Description

[Cross-reference of related applications]
This application claims the benefit of this priority based on the priority from Japanese Patent Application No. 2005-15970 filed on January 24, 2005, the disclosure of which is incorporated herein by reference.

[Field of the Invention]
The present invention particularly relates to interconnect structures and other interconnect structures for microelectronics, such as printed wiring boards or others, for example in the packaging of microelectronic units such as integrated circuits (“ICs” or “chips”). The present invention relates to a circuit panel including a type of wiring board.

  There is a current need to provide interconnect elements having either a single layer or multiple layers of metal interconnect patterns that allow selective interconnection to external circuit elements.

  According to one aspect of the invention, the interconnect element includes a dielectric element having a major surface. A metal interconnect pattern extending in one or more directions of the major surface is embedded in a recess extending inwardly from the major surface. The outer surface of the interconnect pattern is substantially coplanar with the major surface. The protruding conductive film extends on the major surface in at least one direction parallel to a plane defined by the major surface. The protruding conductive film contacts the dielectric element along at least a portion of the major surface and conductively contacts the outer surface of at least one pattern of the metal interconnect pattern.

  According to one or more preferred embodiments of the present invention, the interconnect element covers only a portion of the major surface and at least one of the metal interconnect patterns such that the protruding conductive film is exposed by the insulating cover film. An insulating cover film may further be included.

  According to one or more preferred embodiments of the present invention, at least a portion of the protruding conductive film conductively interconnects each pattern of the metal interconnect pattern.

  According to a preferred embodiment of the present invention, the primary surface is a first primary surface, the dielectric element includes a second primary surface spaced from the first primary surface, and a plurality of second surfaces. The recess extends inwardly from the second major surface. In such an embodiment, the metal interconnect pattern is a first metal interconnect pattern embedded in the first recess, and the interconnect element comprises a plurality of directions extending in one or more directions of the second major surface. It further includes a second metal interconnect pattern. These second metal interconnect patterns are embedded in the second recesses and have an outer surface that is substantially coplanar with the second major surface. Further, at least some of the first metal interconnect patterns are conductively connected to at least some of the second metal interconnect patterns.

  According to one or more preferred embodiments of the present invention, at least some of the first metal interconnect patterns are conductively connected to at least some of the second metal interconnect patterns. The connection is provided by one or more conductors extending through the dielectric element in a direction perpendicular to the plane defined by the first major surface of the dielectric element.

  Preferably, the one or more conductors extending through the dielectric element include a conductor covering the inside of a through hole extending through the dielectric element.

  In certain aspects of the invention, the assembly includes interconnect elements as specified herein, and further includes external circuit elements. The exposed leads of such circuit elements are inserted into through holes that are in conductive contact with the conductors to provide a conductive interconnection to the interconnect elements.

  According to another preferred embodiment of the present invention, the solid conductive post extends through a dielectric element that contacts the inner surface of at least some of the first and second metal interconnect patterns; These inner surfaces are recessed inwardly from the first and second major surfaces of the dielectric element.

  In accordance with another preferred embodiment of the present invention, the first insulating cover film includes a first major surface first portion and a first metal such that the protruding conductive film is exposed by the insulating cover film. Above at least one of the interconnect patterns.

  An assembly according to certain aspects of the invention includes interconnect elements and external circuit elements as specified herein. The exposed contact of the external circuit element is conductively connected to the protruding conductive film of the interconnect element.

  Preferably, the protruding conductive film is conductively connected to the contact through an anisotropic conductive film.

  In accordance with another aspect of the present invention, a method for manufacturing an interconnect element is provided. In this way, the method provides a structure including a first metal layer overlying a second metal layer. A plurality of metal interconnect patterns are patterned from the first metal layer of the structure, followed by formation of a dielectric element that covers the metal interconnect pattern of the structure. Then, the second metal layer is such that a plurality of metal interconnect patterns are embedded in the dielectric element and that these patterns have an outer surface that is coplanar with the first major surface of the dielectric element. Selectively removed with respect to the plurality of metal interconnect patterns. In a plane defined by the major surface so as to contact the dielectric element along at least a portion of the first major surface and conductively contact the outer surface of at least one pattern of the metal interconnect pattern. A protruding conductive film is formed that extends over the first major surface in at least one parallel direction.

  Preferably, forming the dielectric element includes pressing a layer comprising an uncured resin over the plurality of metal interconnect patterns.

  In accordance with certain aspects of the present invention, the metal interconnect pattern is a first metal interconnect pattern embedded in a first recess extending inwardly from the first major surface. Preferably, the method includes providing a second structure including a third metal layer overlying the fourth metal layer, and patterning a plurality of second metal interconnect patterns from the third metal layer. Further comprising the steps of: Forming the dielectric element further includes pressing the second structure against the second major surface of the dielectric element away from the first major surface. The fourth metal layer is then selectively removed with respect to the plurality of second metal interconnect patterns. In this manner, the second metal interconnect pattern is embedded in the second major surface of the dielectric element, and the second metal interconnect pattern has an outer surface that is coplanar with the second major surface. Have. Further in accordance with this aspect of the invention, a through hole extending through the dielectric element is formed between the first metal interconnect pattern and the second metal interconnect pattern, and the projecting conductive film. At the same time, a conductor covering the inside of the through hole is formed, and such conductor connects the first metal interconnect pattern to the second metal interconnect pattern.

  According to one embodiment of the present invention, a multilayer interconnect element or multilayer wiring board is provided in which metal traces of the interconnect layer are embedded in recesses in the surface of the dielectric element. In addition, these metal traces are in such a way that even when the number of interconnecting elements connected to each other is large, the metal traces are much less prone to twisting, shorting with adjacent interconnects, or breaking. It is formed. In such an embodiment, the surface of each interconnect element presents a substantially planar major surface with conductive contacts on the surface for interconnection with other microelectronic elements. In this way, the metal traces do not protrude in a way that interferes with the mounting of the electronic component. Also, improved reliability of electrical connections is achieved between several interconnect elements comprising a multilayer interconnect element or multilayer wiring board having three or more layers provided with such embedded metal traces. Can be done. It may also be possible to achieve a reduction in the manufacturing process required to produce such interconnect elements.

  In the interconnect element 22 according to one embodiment of the invention shown in FIG. 2 (M), the dielectric element 20 preferably comprises one or more thermoplastics, or essentially consists of eg PEEK (polyetheretherketone). Resins, PES resins, PPS (polyphenylene sulfide) resins, PEN (polyethylene naphthalate) resins, PEEK-PES resin polymer mixtures, and liquid crystal polymers comprise one or more thermoplastic resins which are specific examples of preferred resins. The thickness of the dielectric element is preferably several tens of microns to several hundreds of microns.

  Embedded in dielectric element 20 are first interconnect patterns 12 and 12a provided as the first metal wiring layer and second interconnect patterns 13 and 13a provided by the second metal wiring layer. It is. Each of the first interconnect pattern and the second interconnect pattern includes a plurality of metal traces and contacts or other metal interconnect features. The thickness of each metal wiring layer is preferably about 10 to several tens of microns. These contacts and metal traces function to provide a conductive interconnect between the interconnect element 22 and other microelectronic elements outside it and / or between different external microelectronic elements. Such microelectronic elements are, for example, microelectronic substrates, circuit panels, integrated circuits (“ICs” or “chips”), packaged chips, ie such chips are simply active circuit elements or “on-chip integrated passive elements”. Whether it contains passive circuit elements, commonly known as (IPOC), or, among other things, a chip having a combination of active and passive types of circuit elements, with package elements coupled to these elements It can be any of the chips.

  A plurality of solid metal columns 18 extend through the dielectric element 20 between the first interconnect pattern 12 and the second interconnect pattern 13. These struts most preferably comprise copper or consist essentially of copper. Preferably, the post includes high purity copper. The length or “height” of each strut in the dielectric element 20 is preferably, for example, a few tens of microns to about 150 microns. However, this height can be somewhat higher or lower than the stated preferred range.

  In certain embodiments, the chip, circuit panel or packaged chip is directly or indirectly conductive to interconnect patterns 12 and 12a that include traces and contacts exposed on first major surface 24 of interconnect element 22. Interconnected or coupled together. On the second major surface 26 of the interconnect element 22 remote from the first major surface 24, the interconnect element contacts 13 and 13a are connected to the circuit panel, another chip or another packaged chip. It can be further coupled directly or indirectly to the package element. In another embodiment, metal traces on one or both major surfaces 24 and 26 of the interconnect element 22 can be contacted by the packaged chip and the pressure between the interconnect element and the packaged chip. As a result, conductive communication with the packaged chip can be maintained under moderate pressure that may cause some deflection of the dielectric element 20.

In one embodiment of manufacturing a multilayer interconnect element or wiring board, heating to a temperature of, for example, 150 ° C. to 350 ° C. is appropriate, and a pressure between 20 kg / cm ² and 100 kg / cm ² is preferred. In addition, one or both of the first and second major surfaces 24 and 26 are to be mounted, particularly when an electronic component such as an integrated circuit (IC or chip) having a large number of terminals of fine pitch is to be mounted. It is preferred that the metal traces exposed to be coated with a binding metal. Gold is well suited for use as the bonding metal layer 10.

  The details of the present invention will be described based on the embodiments shown in the figures. 1A to 1K and FIGS. 2L to 2M are cross-sectional views showing a series of processes (A) to (M) in the first embodiment according to the present invention.

  First, a patternable conductive structure 2 made from a three metal layer structure is prepared as shown in FIG. This patternable conductive structure 2 comprises an etching barrier layer (intermediate layer) 6 comprising a metal such as nickel or consisting essentially of a metal such as nickel on the surface of a carrier layer 4 made of copper, for example. And a metal layer 8 for producing an interconnection layer made, for example, of copper, has a three-layer structure formed on the surface of this etching barrier layer 6.

  Subsequently, as shown in FIG. 1B, a protective layer 10 made of, for example, a photoresist is provided on the surface of the carrier layer 4 described above. Layer 10 protects carrier layer 4 when metal layer 8 is patterned, for example, by photolithography and selective etching, to form interconnect pattern 12. Note that 12a shows an interconnect pattern that is neither a conductive metal post nor any other conductive pillar extending therefrom.

  Subsequently, as shown in FIG. 1C, a photoresist layer 14 is formed on the surface on which the aforementioned interconnect patterns 12 and 12a are formed.

  Subsequently, as shown in FIG. 1D, an exposure process is performed on the photoresist layer 14 described above. Following exposure, 14a is an exposed portion and 14b is an unexposed portion.

  This is followed by a development process as shown in FIG. Reference numeral 16 denotes holes generated by the development process.

  Following this, as shown in FIG. 1 (F), a post-exposure process is preferably performed. Preferably, the exposure in this process is greater than the previous exposure with respect to FIG. The exposed photoresist is then removed by a soft etching process, followed by preferably ultrasonic cleaning.

  Subsequent to this, as shown in FIG. 1G, the patterned resist layer 14a is a metal column 18 or the like as a vertically rising feature extending upward from the interconnect pattern 12 in the hole 16 described above. It is used as a mask for making a conductive pillar. Preferably these struts comprise or consist essentially of one or more metals, preferably copper, formed by plating. This process is such that the conductive column 18 preferably has a length or height that extends beyond the major surface 23 of the resist layer 14a described above, with the end 18 or top 19 of the column 18 on the resist layer 14a. Implemented to protrude.

  Subsequently, referring to FIG. 1 (H), the grinding or polishing process until the end or uppermost portion 19a of the conductive column 18 is coplanar with the surface of the resist layer 14a (that is, located on the same plane). Is executed. After processing in this way, the top 19a presents a flat surface.

  Subsequently, as shown in FIG. 1I, the aforementioned photoresist layer 14a is removed by peeling or the like, and at the same time, the aforementioned protective layer 10 is also removed from the surface of the carrier layer 4.

  Subsequently, as shown in FIG. 1 (J), an interlayer insulating layer made of a dielectric element, preferably a resin, is formed on the surface on which the conductive column 18 is formed through a method such as pressure bonding. 20 is formed. In one embodiment, the interlayer insulation layer comprises an uncured resin, and such a layer is provided, for example, in the form of an epoxy prepreg. Thereafter, the interlayer insulating layer 20 is polished or ground until the end face of the conductive column 18 is exposed. FIG. 1J shows the planarized state of the interlayer insulating layer 20 and the pillars 18 in the partially formed first interconnect structure 2 ′ after the grinding process.

  Following this, a first such interconnect structure 2 'having an insulating layer 20 is formed in the state shown in FIG. In addition, a patternable conductive structure 2 having an exposed interconnect pattern 12 as shown in FIG. 1B is provided. The two structures 2 and 2 ′ are then aligned with each other such that the end face 19 a of the metal post or conductive pillar 18 contacts the interconnect pattern 12 of the structure 2. Then pressure and heat are applied to join and bond the metal struts 18 to the interconnect pattern of the conductive structure 2 facing each other. FIG. 1K shows the state after this integration.

  This bonding process connects the metal struts 18 to the interconnect pattern, which is done via metal-to-metal bonding to the interconnect patterns 13 and 13 of the struts 18, particularly via copper-to-copper contact. This process integrates the two structures 2 and 2 'into a single unit.

  Subsequently, as shown in FIG. 2 (L), the respective carrier layers 4 and 4 (FIG. 1 (A)) are removed by, for example, etching.

  Subsequently, as shown in FIG. 2 (M), the aforementioned etching barrier layers 6 and 6 made of nickel are removed by etching, for example.

  Given this type of manufacturing method, the interconnect layer and the insulating layer are coplanar as shown in FIG. 2M, and the outer surface 21 of the interconnect patterns 12 and 12a is the first major surface. An interconnect element or wiring board is manufactured that is coplanar with 24 and is manufactured such that the outer surface 21a of the interconnect patterns 13 and 13a is coplanar with the second major surface 26.

  3A to 3H and FIGS. 4I to 4M are cross-sectional views showing a series of processes (A) to (M) in the second embodiment according to the present invention.

  As shown in FIG. 3A, two patternable conductive structures 32 and 32 and a core 30 made of, for example, a resin are prepared. An adhesive sheet 34 made of, for example, a prepreg or the like is formed on part of both sides of the core 30. The prepreg is made of, for example, an epoxy resin. Since the core 30 is an unnecessary area, it is removed later.

  Each of the aforementioned patternable conductive structures 32 is attacked by a corrosive solution in which the metal layer 40 for producing an interconnect layer comprising, for example, copper or consisting essentially of copper attacks the first metal. Note that it has a three-layer structure overlying an etching barrier layer (intermediate layer) 34 that includes, or consists essentially of, such metals. For example, when the first metal comprises copper or consists essentially of copper, the etch barrier layer can comprise nickel or consist essentially of nickel. Copper can be etched by a corrosion solution that does not attack nickel substantially. Similarly, the first metal 40 and the etching barrier layer 34 are provided on or covering the surface of the carrier layer 36 made of, for example, copper. The patternable conductive structure is preferably manufactured by rolling, although other methods can be used.

  Subsequently, as shown in FIG. 3 (B), the patternable conductive structures 32 and 32 have the adhesive sheet described above so that the metal layer 36 as a carrier faces the surface of the core material 30. It is bonded to both surfaces of the core material 30 via 34. The adhesive sheet 34 is disposed at one or more locations in the patternable conductive structure away from the location (active area) where the interconnect pattern is to be formed. In this way, the adhesive sheet 34 is preferably arranged only in unnecessary areas.

  Following this, as shown in FIG. 3C, the interconnect layer 42 is formed by selectively etching the metal layer 40 of each of the patternable conductive structures 32 and 32 described above. Is done.

  Following this, as shown in FIG. 3D, a photoresist layer 44 is deposited on both surfaces 43 of the interconnect layer 42. These resist layers 44 have a thickness that is essentially the same as the end face of the conductive column 48 (FIG. 1 (F)) to be formed, or have a slightly lower surface. The

  Subsequently, as shown in FIG. 3E, each of the aforementioned resist layers 44 is patterned by photolithography or the like to form the holes 46.

  Subsequently, as shown in FIG. 3 (F), a metal column 48 or other conductive column 48 is formed inside the hole of the resist layer 44. Preferably, these pillars are manufactured by plating with a metal such as copper, for example, using the resist layer 44 as a mask. The manufacture of these conductive pillars 48 is achieved by the interlayer insulation layer 44 as in the previous embodiment where the metal pillars 48 are shown in FIGS. 1 (A) -1 (K) and 2 (L) -2 (M). This can be done by suitably overplating to the extent that it extends beyond the major surface 45. Thereafter, grinding or polishing is performed to make the outer surface of the conductive column 48 coplanar with the major surface 45 of the interlayer insulating layer 44.

  Subsequently, as shown in FIG. 3G, each of the resist layers 44 is removed.

  Subsequently, as shown in FIG. 3H, an interlayer insulating layer 50 is formed on each of the surfaces on which the interconnect layer 42 and the conductive pillars 48 are formed. These insulating layers are formed by, for example, a pressure bonding method, and then the end surfaces of the conductive columns 48 are exposed by grinding the interlayer insulating layer 50 described above.

  Subsequently, as shown in FIG. 4 (I), interconnect structures 52 and 52 are aligned and mounted on each of the aforementioned interlayer insulating layers 50 and 50, respectively.

  Each of the aforementioned interconnect structures 52 and 52 includes an interconnect layer that includes an interconnect pattern 60. This interconnect layer may comprise, for example, copper or consist essentially of copper. Similarly, the interconnect layer covers an etching barrier layer (intermediate layer 56) made of, for example, nickel. Similarly, the etching barrier layer covers a carrier layer 54 made of, for example, copper. In addition, each of these interconnect structures 52 and 52 is oriented such that the side on which interconnect pattern 60 is formed faces each of interlayer insulating layers 50 and 50, and various conductive columns 48 correspond. Provided in alignment with the interconnect layer 60.

  Subsequent to this, as shown in FIG. 4J, the interconnect structures 52 and 52 are aligned with the interlayer insulating layers 50 and 50 described above and bonded by application of heat and pressure. As a result, the various conductive columns 48 are integrated with the corresponding interconnect layer 60 by metal-to-metal bonds, such as copper-to-copper bonds. Further, the interlayer insulating layer 50 is bonded to the structure 52.

  Subsequent to this, as shown in FIG. 4 (K), the one integrated in FIG. 4 (J) has each interconnect element from the first interconnect layer 42 and the first interconnect layer 42. In order to separate the unwanted core 30 from the active area, which is the two interconnect elements 55 with the second interconnect layer 60 on one side of the remote interconnect element 55, the aforementioned adhesive 34 is adhered. It is cut at the part.

  Following this, the aforementioned carrier layers 54 (FIGS. 4 (I) and 36 (FIG. 4 (I)) are removed from the interconnect element 55. FIG. 4 (L) shows that these carrier layers 54 and 36 are removed. The state after being done.

  Following this, each of the previously described etch barrier layers 58 and 38 of FIG. 4 (L) is removed as shown in FIG. 4 (M).

  This type of manufacturing method allows the interconnect patterns 60, 42 to be on each of the first and second major surfaces of the interlayer insulation layer such that the outer surface of the interconnect pattern and these major surfaces are coplanar. An interconnection element 55 or a wiring board as shown in FIG. 4 (M) provided as a metal pattern embedded in the recess is manufactured.

  Further, since the manufacturing process for the two interconnect elements or wiring boards proceeds simultaneously on both sides until the interconnect elements are separated from the core material 30, this can improve manufacturing efficiency and increase productivity. it can.

  FIGS. 5 (H)-(K) simultaneously produce two interconnect elements in a variation of the embodiment shown in FIGS. 3 (A) -3 (H) and FIGS. 4 (I) -4 (M). It is sectional drawing which shows a series of processes for.

  In the present embodiment, the same structure as that shown in FIG. 3H is prepared according to the processing described previously with reference to FIGS. After this, these processes differ from the embodiment described previously with respect to FIGS. 4 (I) -4 (M). FIG. 5H shows the same structure as that shown in FIG.

  Following this, as shown in FIG. 5 (I), metal layers 59 and 59 are provided on opposite sides of the core material 30. For example, these metal layers comprising or consisting essentially of copper are bonded, bonded or adhered to the interlayer dielectric layers 50 and 50 by the application of heat and pressure. In doing so, a conductive connection is made by a metal-to-metal contact, for example, a copper-copper bond, so that a portion of the metal layers 59 and 59 has excellent conductivity to the metal posts or conductive posts 48 and 48. Have a secure connection with. Furthermore, other portions of the metal layers 59 and 59 adhere well to the outer surfaces of the interlayer insulating layers 50 and 50.

  Subsequently, as shown in FIG. 5 (J), the mask layer covering the top is patterned, for example, by photolithography patterning, and the above-described metal layers 59 and 59 are selectively selected from within the openings of the mask layer. The interconnect patterns 61 and 61 are manufactured by etching.

  This is followed by cutting on the unwanted areas bonded by the adhesive sheet 34 in the same manner as previously illustrated and described with respect to FIG. 4 (K), after which the previous carrier layers 36 and 36 are cut. (FIG. 4I) is removed. In such a process, the etching barrier layer 38 (FIG. 4I) in which the interconnect layers 61 and 61 are formed is used as a mask. Finally, the etch barrier layer 38 may be removed to provide a pair of interconnect elements 65 that are joined together via the adhesive layer 36 and the core 30. These interconnect elements 65 are then provided with a core as previously described with respect to FIG. 4 (M) to provide a pair of interconnect elements 65 joined together via the adhesive layer 36 and the core 30. Can be separated from These interconnect elements 65 can then be separated from the core as previously described with respect to FIG. 4 (K).

  When this is done, the first interconnect pattern 61 on one major surface 63 of the interlayer dielectric layer (dielectric element) is the major surface of the interlayer dielectric layer 50 as shown in FIG. Protrudes above 63. On the other hand, there are cuts and protrusions on one major surface 63 of the interlayer insulating layer 50, but the metal interconnect pattern 42 has the outer surface 69 of these interconnect patterns 42 coplanar with the major surface 67. Thus, it is buried in the other main surface of the interlayer insulating layer 50. Thus, a double-sided interconnection type interconnection element or wiring board is provided.

  Subsequent to this stage of manufacturing, as shown in FIG. 5 (K), the interconnect elements 65 can be joined together in a multi-layer interconnect element having different arrangements, for example via a central connect element other than the core 30 described above. In one example, the interconnection elements 65 are joined together by heat and pressure on opposite sides of the dielectric connection element 75 or “core connector”. Such a core connector 75 may or may not have a conductive pattern on metal posts or conductive posts, vias, or metal connectors extending vertically therethrough. In a particular example, the protruding interconnect pattern 61 faces inward, i.e. towards the dielectric connecting element, and the interconnect pattern 42 faces outward. In this way, the interconnect pattern 42 that is coplanar with the exposed major surface of the dielectric element 50 faces outward. In such a case, the aforementioned interconnect element or wiring board is well suited for the manufacture of a multilayer interconnect element 65 or wiring board having an embedded interconnect pattern 42 such that it is flat at its outermost surface 69. Is suitable.

  6A to 6D are sectional views showing a series of processes in the third embodiment according to the present invention.

  As shown in FIG. 6A, a core substrate 70 and two outer interconnection elements 72 and 72 facing the opposing surfaces (front surface and rear surface) of the core substrate 70 are prepared. The core substrate 70 in this example has four interconnect layers, where 74 is an interlayer insulation layer, 76 is an inner interconnect pattern, 78 is an outer interconnect pattern, and 80 is an interlayer connection. The outer interconnect pattern 78 protrudes over the outer major surface 79. Thus, the outer (main) surface 79 has protrusions and notches.

  Each of the aforementioned outer interconnect elements 72 and 72 includes an interconnect pattern 86 comprising a metal, such as copper, overlying an etch barrier layer 84 or consisting essentially of a metal, such as copper. The etch barrier comprises or consists essentially of a material such as nickel that is not attacked by a corrosive solution that attacks the metal from which the interconnect pattern 86 is made. Similarly, the etch barrier layer 84 is on a carrier layer 82 that preferably comprises or consists essentially of copper. Extending from the interconnect pattern 86 are a plurality of metal posts or conductive posts 88 that preferably comprise a metal such as copper or consist essentially of a metal such as copper. The interlayer insulating layer 90 covers the inner surface of the interconnect pattern 86 and fills the space between the conductive columns 88. The end face 89 of the conductive column 88 is exposed at the outer surface 91 of the interlayer insulating layer 90.

  In addition, the interconnect elements 72 and 72 are oriented on both surfaces of the core substrate 70 such that the end surfaces 89 of the conductive columns 88 and 88 and the outer surface 91 of the interlayer insulating layer 90 face the core substrate 70. Placed. The interconnect elements and the core substrate are aligned such that each of the conductive posts 88 and 88 is aligned with the position of each of the outer interconnect patterns 78 and 78 of the core substrate 70.

  Following this, heat and pressure are used to bond, eg, bond, bond or fuse, the aforementioned interconnect elements 72 and 72 to the exposed surface of the aforementioned dielectric layer and interconnect pattern 78 of the aforementioned core substrate 70. Is applied. FIG. 6B shows the state after this bonding process.

  This bonding process not only strongly connects the end faces of the conductive columns 88 and 88 to the outer interconnect pattern 78 of the core substrate 70 by copper-copper bonding, but also integrates the interlayer insulating layers 74 and 90 with each other. Adhere, bond or preferably fuse.

  Subsequently, as shown in FIG. 6C, the material of the carrier layer without attacking the material of the etching barrier layer 84, preferably nickel, is used, for example, through etching using a corrosive that etches copper. The carrier layers 82 and 82 (FIG. 6B) are removed.

  Subsequently, as shown in FIG. 6D, the aforementioned etching barrier layer 84 is removed by etching, for example. When this is done, this can provide a multilayer interconnect element or wiring board having six interconnect layers in which the interconnect pattern of each interconnect layer is coplanar with the outer surface of each insulating layer.

  This type of manufacturing method provides a multilayer interconnection element or wiring board in which the outermost surface is flat and the interconnection pattern is embedded in these outermost surfaces and is coplanar with these surfaces. Can do. Such a method utilizes the core substrate 70 as a base having cuts and protrusions on its surface by the interconnect layer 78. Thereafter, the interconnect elements 72 and 72 described above are such that the conductive pillars 88 and the exposed surface 91 of the interlayer insulating layer 90 face inward toward the core substrate 70, and the interconnect patterns 86 and 86 face outward. It is aligned and joined to face.

  In the above embodiment, the number of layers for the core substrate 70 is four, and the number of layers in the multilayer interconnection element or wiring board manufactured therefrom is six, but this is merely an example. Please note that. The number of layers in the core substrate 70 is not limited to four. Rather, the number of layers can be different, and it is possible to provide a multilayer wiring board having two layers more than the number of layers in the core substrate 70. .

  FIGS. 7A to 7H and FIGS. 8A to 8H are sectional views showing a fourth embodiment according to the present invention. FIGS. 7A-H illustrate a series of processes for a method of manufacturing an interconnect element 111 (FIG. 7H) used in the outermost layer of a multilayer interconnect element or wiring board. . 8 (A)-(H) are for processing a core interconnect element or wiring board to integrate the aforementioned interconnect element 111 with a core wiring board, and by further processing the interconnect element 111. FIG. A series of processes for finishing a multilayer wiring board is shown.

  First, a method of manufacturing the interconnection element 111 will be described with reference to FIGS.

  As shown in FIG. 7 (A), a three-layer metal structure 100 is provided in a manner as previously described with respect to the structure 2 shown in FIG. 1 (A). The three layer metal structure includes a metal layer 106 made in an interconnect pattern made, for example, from copper. Such a layer 106 is on an etching barrier layer 104 made of nickel, for example, on one surface of a carrier layer 102 made of copper, for example. The structure 100 can be manufactured by rolling, for example.

  Subsequently, as shown in FIG. 7B, the above-described metal layer 106 (FIG. 7A) is selectively etched to produce an interconnect pattern 108 including, for example, traces, contacts, and the like. .

  Subsequently, as shown in FIG. 7C, a resist layer 110 is deposited on the exposed surface of the interconnect pattern 108 and patterned by photolithography or the like. Reference numeral 112 denotes a hole formed in the resist layer 110, and a metal column or conductive column 114 (FIG. 7D) described below is formed in the hole 112.

  Subsequently, as shown in FIG. 7D, preferably, the conductive pillar 114 is manufactured by plating a metal such as copper using the resist layer 110 described above as a mask. In this case, the conductive pillar 114 is formed so as to slightly protrude from the surface of the resist layer 110. This is to enable the next grinding process to align the top of the conductive column 114 at a specified height despite the variability in the plating process.

  Subsequently, as shown in FIG. 7E, the protruding portion of the conductive column 114 is such that the end surface thereof is coplanar with the outer (main) surface 105 of the resist layer 110 (that is, the same plane). To be ground).

  Subsequently, as shown in FIG. 7F, the aforementioned resist layer is removed.

  Subsequently, as shown in FIG. 7G, an interlayer insulating layer 116 is provided on the interconnect pattern 108 to insulate each of the conductive pillars 114 described above. After this stage of processing, the top or end 115 of the conductive column 114 is exposed.

  Following this, as shown in FIG. 7 (H), the ends of the conductive pillars 114 described above are adjusted to be level with the surface of the interlayer insulating layer 116 to complete the interconnect element 118. It is polished or ground to become.

  Note that two of these interconnect elements 118 are prepared and provided according to the process shown in FIGS. 8 (A) -8 (H).

  Next, with reference to FIGS. 8A to 8H, a method for manufacturing to provide a multilayer interconnection element or wiring board according to the present embodiment will be described.

  First, as shown in FIG. 8A, a core interconnection element or core wiring board 120 is prepared.

  The core interconnect element 120 is provided with four interconnect layers 122 therein, each of which is separated from each other and insulated by an interlayer insulating layer 124. Metal layers 126 and 126 are provided on the outermost surface.

  Following this, as shown in FIG. 8B, a through hole 128 is formed that extends from the outermost surface through the core interconnect element 120 described above.

  Subsequently, as shown in FIG. 8C, the through-hole interconnect layer 130 is manufactured by plating a metal such as copper using electroless plating or electroplating. The interconnect layer 130 is formed on the surface of the core interconnect element 120 including the surface of the through hole 128 described above.

  Following this, as shown in FIG. 8 (D), the holes inside the through-hole interconnect layer 130 are filled with a conductive paste or insulating paste 132 and then protruded from the top or bottom. The portion of the conductive paste or insulating paste 132 is polished or ground to remove protrusions and cuts.

  Subsequently, as shown in FIG. 8E, a metal layer 134 containing a metal such as copper or consisting essentially of a metal such as copper is produced on the surface by electroless plating and / or electroplating. The

  Subsequently, as shown in FIG. 8 (F), the metal layer 134 (FIG. 8 (E)), the through-hole interconnect layer 130, and the metal layer 126 are selectively etched to interconnect layer 136. Is made.

  Subsequent to this, as shown in FIG. 8G, the aforementioned interconnect elements 118 and 118 manufactured using the method shown in FIGS. Aligned and bonded to 120 exposed surfaces.

  Interconnect elements 118 and 118 are positioned such that the ends of conductive pillars 114 and interlayer insulating layer 116 face the exposed surface of interconnect layer 136 of core interconnect element 120. The interconnect elements are aligned such that each of the conductive pillars 114 is aligned with the corresponding interconnect layer 136. Thereafter, pressure and heat are applied to bond, bond or fuse the interconnect element 118 to the core interconnect element 120.

  This is followed by removal of the carrier layers 102, 102 (FIG. 7A) of the previously described interconnect elements 118 and 118, followed by removal of the etch barrier layers 104, 104 (FIG. 7A). . FIG. 8H shows a state after these etching barrier layers are removed.

  This manufacturing method produces a multilayer interconnection element or wiring board having through holes for electrical connection between layers and having a flat outer surface.

  9A to 9I are cross-sectional views showing a series of processes in the fifth embodiment of the present invention.

  First, referring to FIGS. 9 (A) to 9 (B), two interconnection elements used for the outermost layer of the wiring board are prepared. With reference to FIGS. 9C-9D, one or more interconnect elements are provided for use in the intermediate layer.

  First, an interconnection element 182 (FIG. 9B) for the outermost layer is provided. Only one interconnect element 182 is shown for ease of reference.

  The interconnect element 182 includes a metal layer 188 comprising a metal, such as copper, or consisting essentially of a metal, such as copper, including a metal that is not attacked by a first metal, for example, a corrosive that attacks copper. Or a three-layer metal structure 180 (FIG. 9A) provided with a metal layer 188 overlying an etch barrier layer 186 consisting essentially of this metal. The metal on which the etching barrier layer is formed can be, for example, nickel. Such a layer 186 covers one surface of the carrier layer 184 comprising a metal such as copper or consisting essentially of a metal such as copper. The metal layer 188 is patterned, for example, by a photolithography process to produce an interconnect layer 190 that includes interconnect patterns such as traces, contacts, and the like.

  Referring to FIGS. 9C-D, an interconnect element 194 for the intermediate layer is provided. Although only one intermediate layer interconnect element 194 is shown in FIG. 9D, a plurality of interconnect elements 194 may be provided. In the present embodiment, three are prepared by way of example. Each interconnect element 194 for the intermediate layer has a metal layer 198 formed on both sides of the interlayer insulating layer 196 (FIG. 9C), and then these metal layers 198 on both sides are patterned by a photolithography process or the like. It can be manufactured by preparing a three-layer structure 192.

  Subsequent to this, a plurality of interconnect elements 194 in this example, particularly as shown, are stacked with an interlayer dielectric layer 202 therebetween, and then the aforementioned interconnects for the outermost layer 182. The connecting elements are stacked at specified locations on both outer surfaces of this stack. After this, heat and pressure are applied to join interconnect element 182 as the outermost layer with interconnect element 194 disposed therebetween, so as to join components 202, 194, 194, 194 and 202. Is applied. FIG. 9E shows a state after these components are joined.

  This is followed by removal of the carrier layer 184 (FIG. 9A) from the outermost surface of the integrated layered unit as described above, followed by removal of the etch barrier layer 186, followed by the designation. A through hole 204 is provided at the position. FIG. 9F shows a state after the through hole 204 is formed.

  Subsequently, the surface of the layered unit including the inner peripheral surface of the through-hole 204 described above is plated with a lower layer containing a metal such as copper or consisting essentially of a metal such as copper by electroless plating. 206 is fabricated, followed by deposition of a resist layer 208 that serves as a mask layer for through-hole fabrication and is patterned, for example, by photolithography. FIG. 9G shows a state after the resist layer 208 is manufactured.

  Subsequently, as shown in FIG. 9 (H), the resist layer 208 includes a metal such as copper at the uppermost portion of the plated lower layer 206, or consists essentially of a metal such as copper. Used as a mask to produce the through-hole interconnect layer 210. Note that the fact that the inner peripheral surface of the aforementioned through-hole interconnect layer 210 can be filled with conductive paste or insulating paste 132 is the same as in the embodiment shown in FIG.

  Following this, the aforementioned resist layer 208 (FIG. 9G) is removed, and the aforementioned plated underlayer 206 is also removed to expose the interconnect layer 190. This increases the level of integration by allowing multiple intermediate interconnect elements 195, each having an interconnect layer, to be joined together and electrically connected in a single multilayer interconnect element. Therefore, it is possible to provide a multilayer wiring board that uses the through-hole interconnection layer 210 as an interlayer connection means.

  10A to 10H are cross-sectional views of a series of processes according to the sixth embodiment of the present invention.

  As shown in FIG. 10A, a three-layer metal structure 140 is prepared. The three-layer metal structure 140 includes, for example, a metal such as nickel, or includes a metal such as copper that is layered on top of an etching barrier layer 144 that is essentially made of a metal such as nickel, or It has a metal underlayer 146 consisting essentially of a metal such as copper. Similarly, the etching barrier layer covers the surface of the carrier layer 142 including, or consisting essentially of, a metal such as copper. The metal structure 140 can be manufactured by rolling, for example.

  Subsequently, as shown in FIG. 10B, a first photoresist layer 148 is deposited and patterned on the metal structure 140 described above. Following this, as shown in FIG. 10C, a metal interconnect pattern, such as an interconnect layer 150 including traces and / or contacts, is used to form a metal such as copper using the resist layer 148 as a mask. A surface roughening process is performed to roughen the surface of this interconnect layer 150 after it is manufactured by plating.

  Following this, as shown in FIG. 10D, a second resist layer 152 is deposited and patterned to cover the first photoresist layer 148. Reference numeral 154 denotes a hole formed in the resist layer 152, in which a conductive column 156 (FIG. 10E) described below is formed.

  Subsequently, as shown in FIG. 10E, a metal column or other conductive column 156 is manufactured by plating a metal, for example, copper using the second resist layer 152 as a mask. The These conductive columns 156 are manufactured on the roughened surface of the interconnect layer 150 to enable excellent adhesion between the interconnect layer 150 and the conductive columns 156, and to achieve excellent contact characteristics. To do.

  Subsequently, as shown in FIG. 10F, the second resist layer 152 described above is removed. 158 is the resulting interconnect element after such layer 152 is removed.

  This is followed by a second interconnect element 158a constructed from the aforementioned interconnect element 158 with the conductive pillar 156 removed from the interconnect element 158 (more precisely, the conductive pillar 156 was not made). Structure) is prepared.

  Given this, the surface 155 of the interconnect element 158 from which the conductive pillars 156 and the interconnect layer 150 extend and the surface 155 from which the interconnect layer 150 of the interconnect element 158a extend are arranged to face each other and the interconnect element Each of the 158 conductive posts 156 is aligned to contact the corresponding interconnect layer 150 of the interconnect element 158a. An interlayer insulating layer 160 is interposed between the interconnection element 158a and the interconnection element 158. In this state, heat and pressure are applied to bond, eg, bond, bond or fuse the interconnect elements 158a and 158 together. FIG. 10G shows the state after this joining process.

  Following this, the carrier layers 142 and 142 of the interconnect elements 158 and 158a are removed, followed by the removal of the etch barrier layers 144 and 144. Thereafter, the aforementioned metal underlayers 146 and 146 are also removed.

  This provides a multilayer interconnection element or wiring board in which the interconnect layer 150 is made coplanar with both surfaces of the interlayer dielectric layer 160. FIG. 10H shows a wiring board manufactured by removing the metal lower layers 146 and 146.

  The multilayer interconnect element or wiring board shown and described in this embodiment has a structure in which the outermost surfaces of the dielectric elements are flat and the interconnect pattern exposed on these surfaces is coplanar with them. Similar to the previous ones (multilayer interconnect elements or wiring boards).

  On the other hand, referring to FIGS. 10 (A) to 10 (H), the interconnect elements are aligned with each other with the surface of the end of the conductive column 156 in contact with the corresponding interconnect layer 150. Bonded and integrated. The aforementioned carrier layers 142 and 142, the aforementioned etching barrier layers 144 and 144, and the aforementioned metal underlayers 146 and 146 of each of the aforementioned interconnection elements 158 and 158a are sequentially removed.

  Referring to FIG. 10H, the interconnection element 158 formed with the conductive pillars 156 and the interconnection element 158a formed without these conductive pillars are layered together with the interlayer insulating layer 160 interposed therebetween. I am doing. In a variation of such an embodiment, interconnect elements 158 and 158 having conductive pillars 156 extending from the interconnect elements are formed in an interlayer dielectric layer 160 with conductive pillars 156 interposed between the two interconnect elements 158. They can be joined together and in contact with each other.

  11 (A) to 11 (F) and FIGS. 12 (G) to 12 (I) are cross-sectional views illustrating a method of manufacturing a multilayer circuit board according to another embodiment of the present invention.

  A three-layer metal plate 200 is prepared at the preliminary stage of manufacture shown in FIG. The three-layer metal plate 200 includes a support plate 202, preferably consisting essentially of a first metal such as copper. An etch stop layer 204 is disposed over the surface of the support plate, and is composed of an etch distinguishable material such as nickel that is not attacked by a particular etchant that attacks copper. Preferably, the etch stop layer has a thickness that is at least somewhat less than the thickness of the support plate. A third metal layer 206, preferably consisting essentially of copper, is arranged to cover the rear surface of the etch stop layer opposite the support plate. The third metal layer 206 functions as a layer on which the circuit wiring pattern is patterned.

  Next, as shown in FIG. 11B, conductive wiring patterns 208 and 208 'are formed by selectively etching the metal layer 206 described above. The patterned wiring films 208 and 208 'can have different functions and different widths 209 and can be oriented in substantially different directions. Next, as shown in FIG. 11C, the pair of patterned three-layer metal plates 200 having the exposed wiring patterns 208 and 208 ′ are arranged so that the wiring patterns 208 and 208 ′ are at the center of the insulating layer 210. Laminate with the intermediate insulating layer 210 to form a unit facing inward and embedded in the outer surface 211 of the insulating layer. This laminating can be performed, for example, by applying heat and pressure.

  Subsequently, as shown in FIG. 11D, the support plate is removed from the intermediate etching stop layer 204. Then, a through hole 212 (FIG. 11E) is formed to extend through the insulating layer 210, the etching stopper layer 204, and the wiring film 208 on the exposed surface of the insulating layer.

  Next, as shown in FIG. 11F, a conductive film 214 made essentially of copper, for example, is formed so as to cover the etching stop layer 204 and the insulating layer 210 and in the inner surface of the through hole 212. The conductive film is preferably formed by subjecting a metal such as copper to a treatment such as electroless plating and / or electroplating.

  Subsequently, as shown in FIG. 12G, a resist film is formed on the surface of the conductive film 214 and processed by photolithography so as to form a resist pattern 216. Referring to FIG. 12H, the conductive film 214 on both sides of the insulating layer is then etched with the underlying etch stop layer using the resist pattern 216 as a mask. As a result of this etching, two conductive film patterns are produced. The through-hole conductive film 218 covers the inner surface of the through-hole 212 and electrically connects a part of the external wiring pattern 208 embedded in each surface of the insulating layer 210. A second conductive film 220 is simultaneously formed by this etching process, and this conductive film is called a protruding conductive film 220. This protruding cover film 220 is subsequently used to interconnect the wiring substrate to an external component, for example to an integrated microelectronic device or microelectromechanical device or ("chip") or to the substrate of a packaged chip. Can be done.

  Next, as shown in FIG. 12I, an insulating cover film 222 is provided at a position covering the exposed wiring pattern 208 with the protruding conductive film 220 exposed on the surface of the wiring substrate 201. In one embodiment, the cover film is provided by applying a preformed film having adhesive properties from a roll. In another embodiment, the cover film is provided by deposition and subsequent patterning, for example by photolithography.

  Preferably, the underside of the cover film 222, i.e. the surface 225 of the film facing the insulating layer 210, is substantially smooth rather than rough. This facilitates sticking and positioning of the cover film with respect to the insulating layer 210. In this manner, the cover film can be attached so that the position of the cover film does not cause misalignment with respect to the protruding conductive film 220 or the clearance hole 224 that is opened therefor.

  Further, since the inner surface 225 of the cover film is not rough, it is easier to apply to the insulating layer, and the risk that the cover film touches the corners of the wiring film 208 and is damaged in the process to reduce its protective effect is reduced. It is.

  The wiring board 201 according to FIG. 12 (I) provides benefits in allowing external interconnection between the wiring film 208 ′ and external circuit elements via the protruding conductive film 220. At the same time, other wiring patterns 208 of the substrate are protected against short circuits, bridges, or other undesirable electrical interactions with external circuit elements by an insulating cover film 222 provided thereon. Furthermore, the conductive film 218 provided in the through hole provides interconnection between the wiring patterns 208 on each of the upper surface and the lower surface of the insulating layer.

  FIG. 13 is a cross-sectional view showing a wiring board 203 according to a modified version of the embodiment shown in FIG. In this embodiment, different sets of embedded wiring patterns 208a, 208b on the same surface of the insulating layer 210 are conductively interconnected by a crossover conductive film 226 that is patterned to cover the surface of the insulating layer 210. . Preferably, the crossover conductive film and the through-hole conductive film 218 and projecting conductive material in a manner similar to that previously described with reference to FIGS. 12 (F), 12 (G) and 12 (H). Formed simultaneously with the conductive film 220.

  As further shown in FIG. 13, the lead wire 228 of the electronic component, for example, the lead wire of the packaged chip can be inserted into the through hole of the substrate in contact with the through hole conductive film 218, for example, This through-hole conductive film can be soldered or otherwise bonded to provide an interconnection between the substrate 203 and such a packaged chip.

  FIGS. 14A and 14B further illustrate surface mount interconnections between the packaged chip 240 and the wiring substrate 205 according to one embodiment of the present invention. In this case, the wiring board 205 may be the same as or similar to one of the aforementioned boards, for example, the wiring board 201 (FIG. 12I) or the wiring board 203 (FIG. 13). Alternatively, a simpler form of wiring board is available that includes a conductive wiring pattern 208 ′ embedded in at least a recess 232 in the outer surface 234 of the insulating layer 230. A protruding conductive film 220 or metal interconnect post or pad protrudes over the exposed surface of the wiring pattern 208 ′, and this exposed surface is defined by the outer surface 234 of the insulating layer 230. Preferably the conductive film is formed by deposition of a metal layer, preferably containing copper, and masked etching, or by electroless plating and / or electroplating.

  The packaged chip is mounted on the package substrate 242 illustrated here in an exemplary manner as a dielectric element 248 having a conductive wiring pattern 244 on one side on which the chip 246 is mounted. A chip 246 is included.

  In particular, as shown in FIG. 14 (A), the packaged chip 240 has an anisotropic conductive film (in order to conductively interconnect the two components forming the assembly as shown in FIG. 14 (B). “ACF”) 246 is pressed against and held by the wiring board 205. Conductive interconnects are established only where the ACF 246 is compressed to a significant degree, such as between the protruding conductive film 220 and the opposite mounting surface 244 of the packaged chip.

  Other embedded wiring patterns of the substrate 230 that are in contact with the ACF 246 but not the protruding conductive film 220 are not at risk of creating undesirable conductive interconnections, such as short circuit. This is because the ACF 246 is compressed only where the ACF 246 covers features such as the protruding conductive film 220 that extends above the surface 234 of the surface. In addition, by properly controlling the width 236 of the protruding conductive film 220, the force applied to compress the ACF 246 against the wiring 244 can be reduced via a current holding interface between the two components to reduce resistance. It can be spread over the selected surface area to ensure both the validity of the contact pressure and the validity of the surface area.

  Since these and other variations and combinations of the foregoing features are available, the foregoing description of the preferred embodiment should be taken as illustrative rather than limiting of the present invention.

  Among other things, the present invention provides an interconnect element, such as a wiring, in which a plurality of metal traces of the interconnect layer are exposed on one surface of a dielectric element, eg, an interlayer insulating layer made of a resin such as a thermoplastic resin. It can be used for plates and the like. Posts or interlayer contact posts made of a metal such as copper extend through such dielectric elements. Such posts or pillars can provide interlayer connections corresponding to at least a portion of the interconnect layers of the respective layers of the multilayer wiring board. Furthermore, the present invention finds application in methods of making interconnect elements and methods of manufacturing multilayer wiring boards.

It is sectional drawing of a series of processes (A)-(K) by the 1st Embodiment of this invention. It is sectional drawing of a series of processes (L)-(M) by the 1st Embodiment of this invention. It is sectional drawing which shows the process by the 2nd Embodiment of this invention. FIG. 6 is a cross-sectional view further illustrating a process according to the second embodiment of the present invention. It is sectional drawing which shows the process by the modified version of the 2nd Embodiment of this invention. It is sectional drawing which shows a series of processes in 3rd Embodiment by this invention. FIG. 6 is a cross-sectional view illustrating a series of processes in a method for manufacturing an interconnect element for an outermost layer according to a fourth embodiment of the present invention. According to such a fourth embodiment, the core wiring board is processed, the interconnection elements for the outermost layer are integrated with the core wiring board, and the interconnection for the outermost layer. It is sectional drawing which shows a series of processes for finishing a wiring board by processing an element. It is sectional drawing which shows a series of processes in 5th Embodiment by this invention. It is sectional drawing which shows a series of processes in 6th Embodiment by this invention. It is sectional drawing which shows a series of processes by the 7th Embodiment of this invention. It is sectional drawing which shows a series of processes by the 7th Embodiment of this invention. It is sectional drawing which shows the interconnection element by the modified version of 7th Embodiment shown by FIG. 12 (I), and its interconnection with an external circuit element. FIG. 13 is a cross-sectional view showing an interconnection element according to a further modified version of the seventh embodiment shown in FIG. 12 (I) and its interconnection with external circuit elements.

Claims (14)

A dielectric element having a major surface and a plurality of recesses extending inwardly from the major surface;
A plurality of metal interconnect patterns embedded in the plurality of recesses, the plurality of metal interconnect patterns having an outer surface that is substantially coplanar with the major surface and extending in one or more directions of the major surface A metal interconnect pattern;
A plane defined by the major surface so as to contact the dielectric element along at least a portion of the major surface and conductively contact the outer surface of at least one pattern of the metal interconnect pattern. And a projecting conductive film extending on the major surface in at least one direction parallel to the interconnecting element.   The mutual cover of claim 1, further comprising an insulating cover film covering only a portion of the major surface and at least one of the metal interconnect patterns such that the protruding conductive film is exposed by the insulating cover film. Connection element.   The interconnect element of claim 1, wherein at least a portion of the protruding conductive film electrically interconnects each of the metal interconnect patterns.   The primary surface is a first primary surface, and the dielectric element includes a second primary surface spaced from the first primary surface and a plurality of inwardly extending from the second primary surface. A second recess, wherein the metal interconnect pattern is a first metal interconnect pattern embedded in the first recess, the interconnect element further comprising one of the second major surfaces A plurality of second metal interconnect patterns embedded in the second recess extending in the above direction, the second metal interconnect pattern having an outer surface that is substantially coplanar with the second major surface. The interconnect of claim 1, comprising a metal interconnect pattern, wherein at least some of the first metal interconnect pattern are conductively connected to at least some of the second metal interconnect pattern. element.   The at least some of the first metal interconnect patterns are one or more extending through the dielectric element in a direction perpendicular to the plane defined by the first major surface of the dielectric element. The interconnect element of claim 4, wherein the interconnect element is conductively connected to the at least some second metal interconnect pattern by a conductor.   The interconnect element of claim 5, wherein the one or more conductors extending through the dielectric element include a conductor covering an interior of a through hole extending through the dielectric element.   The external circuit element of claim 6, further comprising an external circuit element having an exposed lead inserted in the through hole in conductive contact with the conductor to provide a conductive interconnect to the interconnect element. An assembly that contains a number of interconnecting elements.   The one or more conductors extending through the dielectric element are at least some of the first and second metal interconnect patterns recessed inwardly from the first and second major surfaces. The interconnect element of claim 5, comprising solid conductive posts in contact with the inner surface of the substrate.   A first insulating cover film covering a first portion of the first major surface and at least one of the first metal interconnect patterns such that the protruding conductive film is exposed by the insulating cover film; The interconnect element according to claim 4, further comprising:   The assembly including an interconnect element according to claim 1, further comprising an external circuit element including an exposed contact that is conductively connected to the protruding conductive film.   The assembly of claim 10, wherein the protruding conductive film is conductively connected to the contacts via an anisotropic conductive film. Providing a structure including a first metal layer overlying a second metal layer;
Patterning a plurality of metal interconnect patterns from the first metal layer;
Forming a dielectric element overlying the structure;
Selective to the plurality of metal interconnect patterns such that the plurality of metal interconnect patterns having an outer surface that is coplanar with the first major surface of the dielectric element is embedded in the dielectric element; Removing the second metal layer;
Defined by the major surface so as to contact the dielectric element along at least a portion of the first major surface and conductively contact an outer surface of at least one pattern of the metal interconnect pattern. Forming a projecting conductive film extending on the first major surface in at least one direction parallel to the formed plane.   The method of claim 12, wherein the step of forming the dielectric element comprises pressing a layer comprising an uncured resin over the plurality of metal interconnect patterns. The metal interconnect pattern is a first metal interconnect pattern embedded in a first recess extending inwardly from the first major surface, and the method is further overlying a fourth metal layer. Providing a second structure including three metal layers; and patterning a plurality of second metal interconnect patterns from the third metal layer to form the dielectric element Pressing the second structure against a second major surface of the dielectric element remote from the first major surface; and wherein the second metal interconnect pattern is formed on the dielectric element. The plurality of second metal interconnects are embedded in the second major surface and the second metal interconnect pattern has an outer surface that is coplanar with the second major surface. For connection pattern It includes a step of removing said fourth metal layer 択的, wherein the method comprises
Forming a through hole extending through the dielectric element between the first metal interconnect pattern and the second metal interconnect pattern;
Forming a conductor covering the inside of the through-hole to simultaneously connect the first metal interconnect pattern to the second metal interconnect pattern when forming the protruding conductive film; and The method of claim 12.

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