JP2008218759A - Electrode structure for semiconductor chip, semiconductor device to which semiconductor chip is flip-chip bonded, and manufacturing method therefor - Google Patents

Electrode structure for semiconductor chip, semiconductor device to which semiconductor chip is flip-chip bonded, and manufacturing method therefor Download PDF

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JP2008218759A
JP2008218759A JP2007054958A JP2007054958A JP2008218759A JP 2008218759 A JP2008218759 A JP 2008218759A JP 2007054958 A JP2007054958 A JP 2007054958A JP 2007054958 A JP2007054958 A JP 2007054958A JP 2008218759 A JP2008218759 A JP 2008218759A
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insulating film
semiconductor chip
metal layer
electrode pad
semiconductor
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Keiji Miki
啓司 三木
Takatoshi Osumi
貴寿 大隅
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13005—Structure
    • H01L2224/13006—Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electrode structure for a semiconductor chip that will enable air bubbles produced in underfill resin to be controlled when flip-chip bonding a semiconductor chip onto a wiring substrate, the semiconductor chip having a metal bump made of solder, and filling up a gap between the semiconductor chip and the wiring substrate with the underfill resin. <P>SOLUTION: An angle θ made by the neighborhood part of an electrode pad 13 on a semiconductor chip 11's surface and a metal bump 17's base part is made to be an obtuse angle. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、配線基板にフリップチップ実装される半導体チップの電極構造、並びにその半導体チップがフリップチップ実装された半導体装置及びその製造方法に関する。   The present invention relates to an electrode structure of a semiconductor chip flip-chip mounted on a wiring board, a semiconductor device in which the semiconductor chip is flip-chip mounted, and a method for manufacturing the same.

近年、情報通信機器や事務用電子機器の小型化および高機能化が進むのに伴って、これらの電子機器に搭載される半導体集積回路装置等の半導体装置に対して小型化と共に、入出力のための外部端子の数を増加することが要求されている。しかし、半導体チップの周辺部に電極パッドを形成してワイヤボンディング方式で外部回路と接続する方式では外部端子数の増加と小型化の両立が困難になってきている。   In recent years, as information communication devices and office electronic devices have become smaller and more sophisticated, semiconductor devices such as semiconductor integrated circuit devices mounted on these electronic devices have been reduced in size and input / output. Therefore, it is required to increase the number of external terminals. However, in the method in which electrode pads are formed in the peripheral portion of the semiconductor chip and connected to an external circuit by a wire bonding method, it is difficult to achieve both an increase in the number of external terminals and a reduction in size.

これらの要求を実現させる技術として、電極パッドを能動領域上に形成して、ワイヤボンディングやインナーリードボンディングを行うパッドオンエレメントと呼ばれる技術や、能動領域上に形成された電極パッド上にバンプと呼ばれる外部接続端子を形成して、バンプを介して外部回路と接続するフリップチップ技術が採用されるようになってきた。   As a technique for realizing these requirements, a technique called a pad-on element in which an electrode pad is formed on an active region and wire bonding or inner lead bonding is performed, or a bump is called on an electrode pad formed on the active area. Flip chip technology has been adopted in which external connection terminals are formed and connected to external circuits via bumps.

図１１は、フリップチップ実装方法により形成されたＢＧＡ（Ｂａｌｌ Ｇｒｉｄ Ａｒｒａｙ）型の従来の半導体装置の構造を示す概略断面図であり、半導体チップを配線基板にフリップチップ実装し、半導体チップと配線基板との間隙を充填するアンダーフィル樹脂を注入した状態を示す。   FIG. 11 is a schematic cross-sectional view showing the structure of a conventional semiconductor device of BGA (Ball Grid Array) type formed by a flip chip mounting method. The semiconductor chip is flip-chip mounted on a wiring board, and the semiconductor chip and the wiring board are shown. The state which injected the underfill resin which fills the gap | interval with is shown.

図１１に示すように、この従来の半導体装置は、主面上に複数の電極パッド１０３が形成され、その電極パッド１０３の上方に金属バンプ１０６が形成されている半導体チップ１０１が、金属バンプ１０６に対応する位置に金属電極１１３が形成されている配線基板１１１上にフェイスダウンで搭載されている。また、配線基板１１１の半導体チップ搭載面とは反対側の面には、半田ボール１１４が形成されている。   As shown in FIG. 11, the conventional semiconductor device includes a semiconductor chip 101 in which a plurality of electrode pads 103 are formed on a main surface and metal bumps 106 are formed above the electrode pads 103. Are mounted face-down on a wiring board 111 on which a metal electrode 113 is formed at a position corresponding to. Solder balls 114 are formed on the surface of the wiring substrate 111 opposite to the semiconductor chip mounting surface.

また、半導体チップ１０１と配線基板１１１とは熱膨張係数に差があるため、熱履歴等を受けた場合には接合部とりわけ半田からなる金属バンプ１０６のチップ側根元部分に応力がかかる。そこで、この応力集中を緩和するため、半導体チップ１０１と配線基板１１１との間の金属バンプ１０６以外の部分に、アンダーフィル樹脂１１２を注入・硬化して、補強する構造をとるのが一般的である。   In addition, since there is a difference in thermal expansion coefficient between the semiconductor chip 101 and the wiring substrate 111, stress is applied to the chip-side root portion of the metal bump 106 made of solder when receiving a thermal history or the like. Therefore, in order to alleviate this stress concentration, it is common to adopt a structure in which an underfill resin 112 is injected and cured in a portion other than the metal bump 106 between the semiconductor chip 101 and the wiring substrate 111 to be reinforced. is there.

アンダーフィル樹脂１１２には、図１１に示すように、エポキシ系樹脂などのベースとなる樹脂１１２ａの他に、半導体チップ１０１の熱膨張係数と似た熱膨張係数にするために、適当な大きさのフィラー成分１１２ｂが添加される。また、アンダーフィル樹脂１１２は、外部からの水分の浸入を抑制し、耐湿性を高める役割も果たしている。   As shown in FIG. 11, the underfill resin 112 has an appropriate size in order to have a thermal expansion coefficient similar to that of the semiconductor chip 101 in addition to the resin 112 a serving as a base such as an epoxy resin. The filler component 112b is added. The underfill resin 112 also plays a role of suppressing moisture ingress from the outside and improving moisture resistance.

続いて、この従来の半導体装置の製造方法について、図面を用いて説明する。図１２（ａ）〜（ｄ）は、従来の半導体装置の製造方法を工程順に示す断面図である。まず、図１２（ａ）に示すように、金属バンプ１０６に対応する位置に金属電極１１３が形成されている配線基板１１１上に半導体チップ１０１をフェイスダウンで搭載する（フリップチップ実装）。   Next, a method for manufacturing this conventional semiconductor device will be described with reference to the drawings. 12A to 12D are cross-sectional views showing a conventional method for manufacturing a semiconductor device in the order of steps. First, as shown in FIG. 12A, the semiconductor chip 101 is mounted face down on the wiring substrate 111 on which the metal electrode 113 is formed at a position corresponding to the metal bump 106 (flip chip mounting).

次に、図１２（ｂ）に示すように、半導体チップ１０１が搭載された配線基板１１１をリフロー（熱処理）することにより金属バンプ１０６を溶融させ、半導体チップ１０１と配線基板１１１とを接合することで、半導体チップ１０１と配線基板１１１とを金属バンプ１０６を介して電気的に接続する。   Next, as shown in FIG. 12B, the metal bumps 106 are melted by reflowing (heat treating) the wiring substrate 111 on which the semiconductor chip 101 is mounted, and the semiconductor chip 101 and the wiring substrate 111 are joined. Thus, the semiconductor chip 101 and the wiring substrate 111 are electrically connected via the metal bumps 106.

次に、図１２（ｃ）に示すように、半導体チップ１０１と配線基板１１１との隙間を清浄化し、ディスペンサ装置３２を用いて、その間隙にアンダーフィル樹脂１１２を注入する。このとき、アンダーフィル樹脂１１２の注入はチップの周辺部から行うが、毛細管現象によりアンダーフィル樹脂１１２がチップ全面に浸入して、半導体チップ１０１と配線基板１１１との間隙に充填される。その後、熱処理することによりアンダーフィル樹脂１１２を硬化して封止する。   Next, as shown in FIG. 12C, the gap between the semiconductor chip 101 and the wiring substrate 111 is cleaned, and the underfill resin 112 is injected into the gap using the dispenser device 32. At this time, the underfill resin 112 is injected from the peripheral portion of the chip. However, the underfill resin 112 penetrates the entire surface of the chip due to a capillary phenomenon and fills the gap between the semiconductor chip 101 and the wiring substrate 111. Thereafter, the underfill resin 112 is cured and sealed by heat treatment.

次に、図１２（ｄ）に示すように、配線基板１１１の半導体チップ搭載面とは反対側の面に、半田ボール１１４を載置し、リフローすることにより外部機器との接続に使用する端子を形成して、ＢＧＡ型の半導体装置を実現していた。   Next, as shown in FIG. 12D, a solder ball 114 is placed on the surface opposite to the semiconductor chip mounting surface of the wiring substrate 111, and the terminals used for connection to an external device by reflowing. Forming a BGA type semiconductor device.

ところが、近年、半導体装置の小型化、高機能化の進展に伴って、金属バンプのピッチが小さくなったり、半導体チップと配線基板との間隙が狭くなったりすることが多くなってきた。また、金属バンプの配置が、チップ周辺部のみの配置（ペリフェラル配置）からチップ全面への配置（エリア配置）へと変化してきており、チップ周辺部に複数列の金属バンプを配置し、且つチップ中央部に数個の金属バンプを配置した半導体装置が登場してきている。この場合、金属バンプの配置に粗密が生じることになる。   However, in recent years, with the progress of miniaturization and higher functionality of semiconductor devices, the pitch of metal bumps has become smaller and the gap between a semiconductor chip and a wiring board has become increasingly smaller. In addition, the arrangement of metal bumps has changed from the arrangement of only the periphery of the chip (peripheral arrangement) to the arrangement of the entire surface of the chip (area arrangement), and a plurality of rows of metal bumps are arranged on the chip periphery. Semiconductor devices with several metal bumps arranged at the center have appeared. In this case, the arrangement of the metal bumps becomes rough.

このように、金属バンプのピッチが小さくなったり、半導体チップと配線基板との間隙が小さくなったり、金属バンプの配置に粗密が生じたりすると、前述したようなチップ周辺部からのアンダーフィル樹脂の注入が困難になる。すなわち、半導体チップと配線基板との間隙に浸入したアンダーフィル樹脂内に気泡が発生しやすくなる。このように気泡が発生する原因は必ずしも明確ではないが、半導体チップと配線基板との間隙（ギャップ）が小さくなるために、アンダーフィル樹脂の浸入が困難になることや、半導体チップ表面、金属バンプ表面、あるいは配線基板の表面とアンダーフィル樹脂との濡れ性に違いがあること、金属バンプの配置に粗密が生じることによりアンダーフィル樹脂の浸入速度に差が生じ、気泡を巻き込んでしまう場合があることなどが原因として考えられる。   As described above, when the pitch of the metal bumps is reduced, the gap between the semiconductor chip and the wiring board is reduced, or the arrangement of the metal bumps is rough, the underfill resin from the periphery of the chip as described above can be obtained. Injection becomes difficult. That is, bubbles are likely to be generated in the underfill resin that has entered the gap between the semiconductor chip and the wiring board. The reason why bubbles are generated in this way is not always clear, but since the gap between the semiconductor chip and the wiring board is small, it is difficult to penetrate the underfill resin, and the surface of the semiconductor chip, metal bumps There may be a difference in the wettability between the surface or the surface of the wiring board and the underfill resin, and the density of the metal bumps may cause a difference in the penetration rate of the underfill resin, which may entrap bubbles. This may be the cause.

アンダーフィル樹脂内に気泡が発生してしまうと、半導体チップと配線基板との接合強度が低下するばかりでなく、隣接する２つの金属バンプ間に亘って気泡が形成されると、その後の熱履歴によって半田からなる金属バンプが溶融し、気泡を伝って隣接端子がショートしてしまう場合がある。   If bubbles are generated in the underfill resin, not only the bonding strength between the semiconductor chip and the wiring board is lowered, but also when the bubbles are formed between two adjacent metal bumps, the subsequent heat history As a result, the metal bump made of solder melts, and the adjacent terminals may be short-circuited through the bubbles.

このようにアンダーフィル樹脂内に発生する気泡を抑制する方法として、アンダーフィル樹脂そのものの物性を調整したり、フィラー成分の粒径を小さくしたりすることによって狭いギャップであっても浸入を容易にする方法（例えば、特許文献１参照）や、半導体チップが実装された配線基板を酸素プラズマなどの活性物質の雰囲気にさらすことによって、アンダーフィル樹脂との濡れ性を改善して注入性を向上させ気泡の発生を抑制する方法（例えば、特許文献２）、また、アンダーフィル樹脂浸入の際にガイドとして作用する突起パターンを基板側に形成し、浸入速度差を少なくすることによって気泡の発生を抑制する方法（例えば、特許文献３）などがある。   As a method for suppressing bubbles generated in the underfill resin in this way, it is easy to enter even in a narrow gap by adjusting the physical properties of the underfill resin itself or by reducing the particle size of the filler component. By improving the wettability with the underfill resin by exposing the wiring substrate on which the semiconductor chip is mounted to an atmosphere of an active material such as oxygen plasma (see, for example, Patent Document 1). A method for suppressing the generation of bubbles (for example, Patent Document 2), and a protrusion pattern that acts as a guide at the time of infiltration of the underfill resin is formed on the substrate side, thereby suppressing the generation of bubbles by reducing the difference in the intrusion speed. There is a method (for example, Patent Document 3).

これらの方法によって、比較的大きなボイドは抑制することができるが、金属バンプとして、バンプ形成の際に熱処理を行って球形状にする半田バンプを使用する場合には、別の問題が起こる。以下、この問題について図１３を用いて説明する。   Although these methods can suppress relatively large voids, another problem arises when using solder bumps that are heat treated during bump formation to form spherical shapes as metal bumps. Hereinafter, this problem will be described with reference to FIG.

図１３（ａ）は、従来の半導体チップにおける金属バンプの根元部分の拡大断面図である。従来の半導体チップの電極構造は、図１３（ａ）に示すように、半導体チップ１０１の主面１０２上に電極パッド１０３と、電極パッド１０３の上方に開口部を有する絶縁膜１０４とが形成され、その電極パッド１０３の上方に下地金属層１０５が形成され、その下地金属層１０５上に半田からなる金属バンプ１０６が形成された構成となっているため、半導体チップ表面と金属バンプの根元部分とのなす角度θが鋭角になっている。そのため、図１３（ｂ）に示すように、アンダーフィル樹脂１１２を注入した際に、金属バンプ１０６の根元部分にまで樹脂１１２ａが入らず、気泡となったり、図１３（ｃ）に示すように、樹脂１１２ａは浸入できても、フィラー成分１１２ｂが浸入できなかったりして、結果的に金属バンプの根元部分の強度補強が充分でなくなってしまう場合があった。   FIG. 13A is an enlarged cross-sectional view of a base portion of a metal bump in a conventional semiconductor chip. In the conventional semiconductor chip electrode structure, as shown in FIG. 13A, an electrode pad 103 is formed on a main surface 102 of a semiconductor chip 101, and an insulating film 104 having an opening is formed above the electrode pad 103. Since the base metal layer 105 is formed above the electrode pad 103 and the metal bump 106 made of solder is formed on the base metal layer 105, the surface of the semiconductor chip and the base portion of the metal bump are formed. Is an acute angle. Therefore, as shown in FIG. 13 (b), when the underfill resin 112 is injected, the resin 112a does not enter the base portion of the metal bump 106, resulting in bubbles or as shown in FIG. 13 (c). Even if the resin 112a can permeate, the filler component 112b cannot permeate, resulting in insufficient strength reinforcement at the base of the metal bump.

また、半導体製造プロセスの著しい進化に伴って、半導体チップの構造も微細化、高集積化が進み、配線材料として比較的抵抗の小さい銅配線が用いられたり、層間絶縁膜として比誘電率の低い、いわゆるＬｏｗ−ｋ材料が用いられたりするケースが多くなってきている。しかし、ｌｏｗ−ｋ材料は機械的強度が弱いため、実装後にｌｏｗ−ｋ膜にクラックや剥離が生じてしまうことが多くなってきた。
特開２００４−３０７６５０号公報 特許第３４７３４３３号公報 特開２００４−２２１３２０号公報 In addition, along with the remarkable evolution of the semiconductor manufacturing process, the structure of the semiconductor chip has been miniaturized and highly integrated, copper wiring having a relatively low resistance is used as a wiring material, and the relative dielectric constant is low as an interlayer insulating film. In many cases, so-called Low-k materials are used. However, since the low-k material has a low mechanical strength, cracks and peeling often occur in the low-k film after mounting.
JP 2004-307650 A Japanese Patent No. 3473433 JP 2004-221320 A

本発明は、上記問題に鑑み、半導体チップと配線基板とを半田からなる金属バンプを介して電気的に接続し、前記半導体チップと前記配線基板との間隙にアンダーフィル樹脂を充填してなる半導体装置において、アンダーフィル樹脂の注入に際して気泡の発生を抑制できるとともに、アンダーフィル樹脂の樹脂やフィラー成分の充填性を向上できる半導体チップの電極構造、並びにその半導体チップがフリップチップ実装された半導体装置及びその製造方法を提供することを目的とする。   In view of the above problems, the present invention provides a semiconductor in which a semiconductor chip and a wiring board are electrically connected via metal bumps made of solder, and a gap between the semiconductor chip and the wiring board is filled with an underfill resin. In the apparatus, the generation of bubbles during the injection of the underfill resin can be suppressed, and the filling structure of the resin and filler component of the underfill resin can be improved, and the semiconductor device in which the semiconductor chip is flip-chip mounted and It aims at providing the manufacturing method.

本発明の請求項１記載の半導体チップの電極構造は、主面上に形成された電極パッドと、前記電極パッドの上面の一部から前記主面にかけて形成された第１絶縁膜と、前記電極パッドの上方に形成され、前記電極パッドと電気的に接続する半田からなる金属バンプと、を備えた半導体チップの電極構造であって、該半導体チップ表面の前記電極パッドの近傍部分と前記金属バンプの根元部分とがなす角度は、鈍角であることを特徴とする。   The electrode structure of a semiconductor chip according to claim 1 of the present invention includes an electrode pad formed on a main surface, a first insulating film formed from a part of an upper surface of the electrode pad to the main surface, and the electrode An electrode structure of a semiconductor chip comprising a metal bump made of solder that is formed above the pad and electrically connected to the electrode pad, wherein the vicinity of the electrode pad on the surface of the semiconductor chip and the metal bump The angle formed by the root portion of is an obtuse angle.

この構成により、半導体チップを配線基板にフリップチップ実装し、アンダーフィル樹脂を注入する際に、半田からなる金属バンプの根元部分に狭い領域がなくなるため、樹脂やフィラー成分が浸入しやすくなり、アンダーフィル樹脂内の気泡の発生が抑制される。   With this configuration, when a semiconductor chip is flip-chip mounted on a wiring board and an underfill resin is injected, there is no narrow area at the base of the metal bumps made of solder, so that the resin and filler components can easily enter and Generation of bubbles in the fill resin is suppressed.

また、本発明の請求項２記載の半導体チップの電極構造は、請求項１記載の半導体チップの電極構造であって、前記第１絶縁膜から露出する前記電極パッドの上面の一部から前記第１絶縁膜の表面の一部にかけて形成された第２絶縁膜と、前記第２絶縁膜から露出する前記電極パッドの上面から前記第２絶縁膜の表面の一部にかけて形成された下地金属層と、を備え、前記金属バンプは、前記下地金属層の表面に形成されており、前記第２絶縁膜の表面と前記金属バンプの根元部分とがなす角度が鈍角であることを特徴とする。   The electrode structure of a semiconductor chip according to claim 2 of the present invention is the electrode structure of the semiconductor chip according to claim 1, wherein a part of the upper surface of the electrode pad exposed from the first insulating film is the first electrode structure. A second insulating film formed over a portion of the surface of the first insulating film; and a base metal layer formed over the surface of the second insulating film from the upper surface of the electrode pad exposed from the second insulating film; The metal bumps are formed on the surface of the base metal layer, and an angle formed between the surface of the second insulating film and a base portion of the metal bumps is an obtuse angle.

この構成により、一般的なウェハープロセスにおける設備及び材料を利用して第１絶縁膜および第２絶縁膜を形成することができるため、製造コストを増加することなく本発明の電極構造を実現できる。   With this configuration, since the first insulating film and the second insulating film can be formed using equipment and materials in a general wafer process, the electrode structure of the present invention can be realized without increasing the manufacturing cost.

また、本発明の請求項３記載の半導体チップの電極構造は、請求項１記載の半導体チップの電極構造であって、前記第１絶縁膜から露出する前記電極パッドの上面の一部から前記第１絶縁膜の表面の一部にかけて形成された第２絶縁膜と、前記第２絶縁膜から露出する前記電極パッドの上面の一部から、前記第２絶縁膜の表面および前記第１絶縁膜の上面にかけて形成された第３絶縁膜と、前記第３絶縁膜から露出する前記電極パッドの上面から前記第３絶縁膜の表面の一部にかけて形成された下地金属層と、を備え、前記金属バンプは、前記下地金属層の表面に形成されており、前記第３絶縁膜の表面と前記金属バンプの根元部分とがなす角度が鈍角であることを特徴とする。   According to a third aspect of the present invention, there is provided an electrode structure of a semiconductor chip according to the first aspect, wherein the first structure is formed from a part of the upper surface of the electrode pad exposed from the first insulating film. A second insulating film formed over a part of the surface of the first insulating film, and a part of the upper surface of the electrode pad exposed from the second insulating film, the surface of the second insulating film and the first insulating film; A third insulating film formed over the upper surface; and a base metal layer formed from the upper surface of the electrode pad exposed from the third insulating film to a part of the surface of the third insulating film; Is formed on the surface of the base metal layer, and the angle formed by the surface of the third insulating film and the base portion of the metal bump is an obtuse angle.

この構成により、第３絶縁膜から露出する電極パッドの上面を除く半導体チップの主面の上方が第３絶縁膜により覆われるので、半導体チップの主面上に形成されている電極パッドや内部配線、第１絶縁膜、第２絶縁膜による凹凸が緩和され、更にアンダーフィル樹脂の充填性が良好となる。   With this configuration, the upper part of the main surface of the semiconductor chip excluding the upper surface of the electrode pad exposed from the third insulating film is covered with the third insulating film, so that the electrode pads and internal wirings formed on the main surface of the semiconductor chip are covered. The unevenness due to the first insulating film and the second insulating film is alleviated, and the filling property of the underfill resin is improved.

また、本発明の請求項４記載の半導体チップの電極構造は、請求項１記載の半導体チップの電極構造であって、前記第１絶縁膜から露出する前記電極パッドの上面から前記第１絶縁膜の表面の一部にかけて形成された第１金属層と、前記第１金属層の上面の一部から前記第１絶縁膜の上面にかけて形成された第４絶縁膜と、前記第４絶縁膜から露出する前記第１金属層の上面から前記第４絶縁膜の表面の一部にかけて形成された第２金属層と、を備え、前記金属バンプは、前記第２金属層の表面に形成されており、前記第４絶縁膜の表面と前記金属バンプの根元部分とがなす角度が鈍角であることを特徴とする。   The electrode structure of a semiconductor chip according to claim 4 of the present invention is the electrode structure of the semiconductor chip according to claim 1, wherein the first insulating film extends from the upper surface of the electrode pad exposed from the first insulating film. A first metal layer formed over a portion of the surface of the first metal layer, a fourth insulating film formed over a portion of the upper surface of the first metal layer and an upper surface of the first insulating film, and exposed from the fourth insulating film. A second metal layer formed from the upper surface of the first metal layer to a part of the surface of the fourth insulating film, and the metal bumps are formed on the surface of the second metal layer, The angle formed by the surface of the fourth insulating film and the base portion of the metal bump is an obtuse angle.

この構成により、ｌｏｗ−ｋ材料などの脆弱膜を用いる場合においても第１金属層および第４絶縁膜によってｌｏｗ−ｋ材料のクラックや剥離現象を抑制することができる。   With this configuration, even when a fragile film such as a low-k material is used, cracks and peeling phenomenon of the low-k material can be suppressed by the first metal layer and the fourth insulating film.

また、本発明の請求項５記載の半導体チップの電極構造は、請求項１ないし３のいずれかに記載の半導体チップの電極構造であって、前記下地金属層は、その上面の投影面積が前記電極パッドの上面の投影面積よりも小さいことを特徴とする。   The electrode structure of the semiconductor chip according to claim 5 of the present invention is the electrode structure of the semiconductor chip according to any one of claims 1 to 3, wherein the projected area of the upper surface of the base metal layer is the above-described surface area. It is smaller than the projected area of the upper surface of the electrode pad.

この構成により、半田からなる金属バンプの下地となる金属層の上面の投影面積が、その直下の金属層の上面の投影面積よりも小さいため、金属バンプにかかる応力に対する耐力が強くなり、信頼性の高い半導体装置を実現できる。   With this configuration, the projected area of the upper surface of the metal layer, which is the base of the metal bump made of solder, is smaller than the projected area of the upper surface of the metal layer immediately below it. A high semiconductor device can be realized.

また、本発明の請求項６記載の半導体チップの電極構造は、請求項４記載の半導体チップの電極構造であって、前記第１金属層は、その上面の投影面積が前記電極パッドの上面の投影面積よりも大きいことを特徴とする。   The electrode structure of the semiconductor chip according to claim 6 of the present invention is the electrode structure of the semiconductor chip according to claim 4, wherein the projected area of the upper surface of the first metal layer is the upper surface of the electrode pad. It is characterized by being larger than the projected area.

この構成により、接合部とりわけ電極パッド部分にかかる応力が第１金属層によって緩和されるため、電極パッドの面積を小さくすることが可能となる。したがって、半導体チップの内部配線の引き回しが容易になるため、設計自由度が高くなる。   With this configuration, since the stress applied to the joint portion, particularly the electrode pad portion, is alleviated by the first metal layer, the area of the electrode pad can be reduced. Therefore, the internal wiring of the semiconductor chip can be easily routed, and the degree of design freedom is increased.

また、本発明の請求項７記載の半導体チップの電極構造は、請求項４もしくは６のいずれかに記載の半導体チップの電極構造であって、前記第２金属層は、その上面の投影面積が前記第１金属層の上面の投影面積よりも小さいことを特徴とする。   The electrode structure of the semiconductor chip according to claim 7 of the present invention is the electrode structure of the semiconductor chip according to claim 4 or 6, wherein the projected area of the upper surface of the second metal layer is It is smaller than the projected area of the upper surface of the first metal layer.

この構成により、半田からなる金属バンプの下地となる金属層の上面の投影面積が、その直下の金属層の上面の投影面積よりも小さいため、金属バンプにかかる応力に対する耐力が強くなり、信頼性の高い半導体装置を実現できる。   With this configuration, the projected area of the upper surface of the metal layer, which is the base of the metal bump made of solder, is smaller than the projected area of the upper surface of the metal layer immediately below it. A high semiconductor device can be realized.

また、本発明の請求項８記載の半導体装置は、請求項１ないし７のいずれかに記載の電極構造を有する半導体チップと、前記半導体チップがフリップチップ実装される配線基板と、前記半導体チップと前記配線基板との間隙を充填するアンダーフィル樹脂と、を備えることを特徴とする。   A semiconductor device according to an eighth aspect of the present invention is a semiconductor chip having the electrode structure according to any one of the first to seventh aspects, a wiring board on which the semiconductor chip is flip-chip mounted, and the semiconductor chip. And an underfill resin that fills a gap with the wiring board.

この構成により、アンダーフィル樹脂内の気泡の発生が抑制されるので、高信頼性の半導体装置を得ることができる。   With this configuration, generation of bubbles in the underfill resin is suppressed, so that a highly reliable semiconductor device can be obtained.

また、本発明の請求項９記載の半導体装置の製造方法は、半導体ウェハの主面上に、半導体素子と電極パッドを有する半導体チップを複数個形成する工程と、前記半導体チップが形成された前記半導体ウェハの主面上に、前記電極パッドの上面の一部が露出するように第１絶縁膜を形成する工程と、前記第１絶縁膜から露出する前記電極パッドの上面の一部から前記第１絶縁膜の表面の一部にかけて第２絶縁膜を形成する工程と、前記第２絶縁膜から露出する前記電極パッドの上面から前記第２絶縁膜の表面の一部にかけて下地金属層を形成する工程と、前記下地金属層上に半田からなる金属バンプを形成する工程と、前記半導体ウェハを個々の前記半導体チップに分割する工程と、を含むことを特徴とする。   According to a ninth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: forming a plurality of semiconductor chips having semiconductor elements and electrode pads on a main surface of a semiconductor wafer; and forming the semiconductor chip. Forming a first insulating film on the main surface of the semiconductor wafer such that a part of the upper surface of the electrode pad is exposed; and a part of the upper surface of the electrode pad exposed from the first insulating film. Forming a second insulating film over a part of the surface of the first insulating film; and forming a base metal layer from the upper surface of the electrode pad exposed from the second insulating film to a part of the surface of the second insulating film. The method includes a step, a step of forming metal bumps made of solder on the base metal layer, and a step of dividing the semiconductor wafer into the individual semiconductor chips.

また、本発明の請求項１０記載の半導体装置の製造方法は、半導体ウェハの主面上に、半導体素子と電極パッドを有する半導体チップを複数個形成する工程と、前記半導体チップが形成された前記半導体ウェハの主面上に、前記電極パッドの上面の一部が露出するように第１絶縁膜を形成する工程と、前記第１絶縁膜から露出する前記電極パッドの上面の一部から前記第１絶縁膜の表面の一部にかけて第２絶縁膜を形成する工程と、前記第２絶縁膜から露出する前記電極パッドの上面の一部から、前記第２絶縁膜の表面および前記第１絶縁膜の上面にかけて第３絶縁膜を形成する工程と、前記第３絶縁膜から露出する前記電極パッドの上面から前記第３絶縁膜の表面の一部にかけて下地金属層を形成する工程と、前記下地金属層上に半田からなる金属バンプを形成する工程と、前記半導体ウェハを個々の前記半導体チップに分割する工程と、を含むことを特徴とする。   According to a tenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: forming a plurality of semiconductor chips having semiconductor elements and electrode pads on a main surface of a semiconductor wafer; and forming the semiconductor chip. Forming a first insulating film on the main surface of the semiconductor wafer such that a part of the upper surface of the electrode pad is exposed; and a part of the upper surface of the electrode pad exposed from the first insulating film. A step of forming a second insulating film over a portion of the surface of the first insulating film; and a portion of the upper surface of the electrode pad exposed from the second insulating film, and the surface of the second insulating film and the first insulating film Forming a third insulating film over the upper surface of the substrate, forming a base metal layer from the upper surface of the electrode pad exposed from the third insulating film to a part of the surface of the third insulating film, and the base metal From solder on layer Forming a metal bump that is characterized by and a step of dividing the semiconductor wafer into individual semiconductor chip.

また、本発明の請求項１１記載の半導体装置の製造方法は、半導体ウェハの主面上に、半導体素子と電極パッドを有する半導体チップを複数個形成する工程と、前記半導体チップが形成された前記半導体ウェハの主面上に、前記電極パッドの上面の一部が露出するように第１絶縁膜を形成する工程と、前記第１絶縁膜から露出する前記電極パッドの上面から前記第１絶縁膜の表面の一部にかけて第１金属層を形成する工程と、前記第１金属層の上面の一部から前記第１絶縁膜の上面にかけて第４絶縁膜を形成する工程と、前記第４絶縁膜から露出する前記第１金属層の上面から前記第４絶縁膜の表面の一部にかけて第２金属層を形成する工程と、前記第２金属層上に半田からなる金属バンプを形成する工程と、前記半導体ウェハを個々の前記半導体チップに分割する工程と、を含むことを特徴とする。   According to another aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: forming a plurality of semiconductor chips having semiconductor elements and electrode pads on a main surface of a semiconductor wafer; and forming the semiconductor chip. Forming a first insulating film on the main surface of the semiconductor wafer so that a part of the upper surface of the electrode pad is exposed; and the first insulating film from the upper surface of the electrode pad exposed from the first insulating film. Forming a first metal layer over a portion of the surface of the first metal layer; forming a fourth insulating film over a portion of the top surface of the first metal layer from the top surface of the first insulating film; and the fourth insulating film. Forming a second metal layer from an upper surface of the first metal layer exposed from a part of the surface of the fourth insulating film; forming a metal bump made of solder on the second metal layer; The semiconductor wafer is individually Characterized in that it comprises a step of dividing the conductor chip, the.

また、本発明の請求項１２記載の半導体装置の製造方法は、請求項９ないし１１のいずれかに記載の製造方法によって製造した半導体チップを、配線基板上にフェイスダウンで搭載する工程と、前記半導体チップが搭載された前記配線基板を熱処理して前記半導体チップと前記配線基板とを前記金属バンプを介して電気的に接続する工程と、前記半導体チップが電気的に接続された前記配線基板と前記半導体チップとの間隙に封止用のアンダーフィル樹脂を注入する工程と、前記アンダーフィル樹脂を熱処理により硬化して封止する工程と、を含むことを特徴とする。   According to a twelfth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising a step of mounting a semiconductor chip manufactured by the manufacturing method according to any one of the ninth to eleventh aspects face down on a wiring board, Heat treating the wiring board on which the semiconductor chip is mounted to electrically connect the semiconductor chip and the wiring board via the metal bumps; and the wiring board to which the semiconductor chip is electrically connected; The method includes a step of injecting a sealing underfill resin into a gap between the semiconductor chip and a step of curing and sealing the underfill resin by heat treatment.

これらの方法によれば、従来の半導体チップの製造方法および半導体装置の製造方法に大きな変更を加えることなく、半田からなる金属バンプの根元部分と半導体チップ表面とがなす角度を鈍角にすることができ、アンダーフィル樹脂の気泡を抑制して、信頼性の高い半導体チップならびに半導体装置を製造することができる。   According to these methods, the angle formed between the base portion of the metal bump made of solder and the surface of the semiconductor chip can be made obtuse without greatly changing the conventional semiconductor chip manufacturing method and semiconductor device manufacturing method. In addition, it is possible to manufacture highly reliable semiconductor chips and semiconductor devices by suppressing bubbles in the underfill resin.

本発明によれば、半導体素子が形成された半導体チップ上に電極パッドを形成し、前記電極パッドの上方に半田からなる金属バンプを形成した半導体チップの電極構造において、半導体チップ表面の電極パッド近傍部分と金属バンプの根元部分とがなす角度を鈍角にすることができ、この電極構造を有する半導体チップを配線基板上に搭載し、半導体チップと配線基板との間隙にアンダーフィル樹脂を充填する際に気泡の発生を抑制したり、フィラー成分の充填性を高めたりすることができるので、信頼性の高い半導体装置を製造することができる。   According to the present invention, in an electrode structure of a semiconductor chip in which an electrode pad is formed on a semiconductor chip on which a semiconductor element is formed and a metal bump made of solder is formed above the electrode pad, in the vicinity of the electrode pad on the surface of the semiconductor chip When the semiconductor chip having this electrode structure is mounted on the wiring board and the gap between the semiconductor chip and the wiring board is filled with the underfill resin, the angle formed by the portion and the base part of the metal bump can be made obtuse. In addition, since the generation of bubbles can be suppressed and the filling property of the filler component can be improved, a highly reliable semiconductor device can be manufactured.

以下、本発明の各実施の形態に係る半導体チップの電極構造、並びにその半導体チップを実装した半導体装置について図面を参照しながら説明する。図１〜３は本発明の第１〜３の実施の形態に係る半導体チップにおける金属バンプの根元部分の拡大断面図であり、金属バンプの中心を通る断面を示している。また、図４は本発明の各実施の形態に係る半導体装置の概略断面図であり、本発明の各実施の形態に係る半導体チップを配線基板にフリップチップ実装し、半導体チップと配線基板との間隙を充填するアンダーフィル樹脂を注入した状態を示す。なお、同一の部材には同じ符号を付して、適宜、説明を省略する。   Hereinafter, an electrode structure of a semiconductor chip and a semiconductor device mounting the semiconductor chip according to each embodiment of the present invention will be described with reference to the drawings. 1 to 3 are enlarged cross-sectional views of the base portion of the metal bump in the semiconductor chip according to the first to third embodiments of the present invention, showing a cross section passing through the center of the metal bump. FIG. 4 is a schematic cross-sectional view of the semiconductor device according to each embodiment of the present invention. The semiconductor chip according to each embodiment of the present invention is flip-chip mounted on a wiring board, and the semiconductor chip and the wiring board are separated. The state which injected the underfill resin which fills a gap | interval is shown. In addition, the same code | symbol is attached | subjected to the same member and description is abbreviate | omitted suitably.

本発明の各実施の形態に係る半導体チップの主面上には、図示しないが、少なくとも１個の半導体素子と、その半導体素子に電気的に接続する少なくとも１個の電極パッドが形成されている。図１〜３には、任意の電極パッドと、その電極パッドに電気的に接続する金属バンプを拡大して示している。   Although not shown, at least one semiconductor element and at least one electrode pad electrically connected to the semiconductor element are formed on the main surface of the semiconductor chip according to each embodiment of the present invention. . 1-3, an arbitrary electrode pad and a metal bump electrically connected to the electrode pad are shown in an enlarged manner.

まず、本発明の第１の実施の形態に係る半導体チップの電極構造、並びにその半導体チップを実装した半導体装置について、図１および図４を用いて説明する。図１に示すように、Ａｌからなる電極パッド１３が形成された半導体チップ１１の主面１２上には、電極パッド１３の上面の一部から主面１２にかけて、チッ化シリコンからなる第１絶縁膜１４が形成されており、第１絶縁膜１４の開口部から電極パッド１３の上面の一部が露出する。   First, an electrode structure of a semiconductor chip and a semiconductor device mounted with the semiconductor chip according to the first embodiment of the present invention will be described with reference to FIGS. As shown in FIG. 1, the first insulation made of silicon nitride is formed on the main surface 12 of the semiconductor chip 11 on which the electrode pad 13 made of Al is formed, from a part of the upper surface of the electrode pad 13 to the main surface 12. A film 14 is formed, and a part of the upper surface of the electrode pad 13 is exposed from the opening of the first insulating film 14.

また、電極パッド１３の周縁部の上方には、第１絶縁膜１４から露出する電極パッド１３の上面の一部から、電極パッド１３の周縁部上方の第１絶縁膜１４の上面の少なくとも一部にかけて、ポリイミドからなる第２絶縁膜１５が形成されており、第２絶縁膜１５の開口部から電極パッド１３の上面の一部が露出する。   Further, above the peripheral portion of the electrode pad 13, at least part of the upper surface of the first insulating film 14 above the peripheral portion of the electrode pad 13 from a part of the upper surface of the electrode pad 13 exposed from the first insulating film 14. Then, a second insulating film 15 made of polyimide is formed, and a part of the upper surface of the electrode pad 13 is exposed from the opening of the second insulating film 15.

また、電極パッド１３の上方には、第２絶縁膜１５の上面の少なくとも一部と、第２絶縁膜１５の開口部の内周面と、第２絶縁膜１５から露出する電極パッド１３の上面とを覆うように、第２絶縁膜１５から露出する電極パッド１３の上面から第２絶縁膜１５の上面の少なくとも一部にかけて下地金属層１６が形成されている。ここでは、下地金属層１６は、その上面の投影面積が電極パッド１３の上面の投影面積よりも小さくなるように形成する。   Further, above the electrode pad 13, at least a part of the upper surface of the second insulating film 15, the inner peripheral surface of the opening of the second insulating film 15, and the upper surface of the electrode pad 13 exposed from the second insulating film 15. A base metal layer 16 is formed from the upper surface of the electrode pad 13 exposed from the second insulating film 15 to at least a part of the upper surface of the second insulating film 15. Here, the base metal layer 16 is formed so that the projected area of the upper surface thereof is smaller than the projected area of the upper surface of the electrode pad 13.

下地金属層１６は、下部金属層と上部金属膜によって構成される。下部金属層は、例えばスパッタリング法によって形成されたＴｉからなるバリアメタルおよびＣｕからなる下部金属膜によって構成される。上部金属膜は、下部金属層の上方に電解めっき法によって形成されたＮｉからなる。   The base metal layer 16 includes a lower metal layer and an upper metal film. The lower metal layer is composed of, for example, a barrier metal made of Ti and a lower metal film made of Cu formed by sputtering. The upper metal film is made of Ni formed by electrolytic plating above the lower metal layer.

また、下地金属層１６の表面には、半田からなる金属バンプ１７が形成されている。この電極パッド１３の上方に形成された金属バンプ１７は、下地金属層１６を介して電極パッド１３と電気的に接続する。   Further, metal bumps 17 made of solder are formed on the surface of the base metal layer 16. The metal bumps 17 formed above the electrode pads 13 are electrically connected to the electrode pads 13 through the base metal layer 16.

この第１の実施の形態に係る半導体チップの電極構造によれば、金属バンプ１７の根元部分が第２絶縁膜１５の上方に形成されるので、金属バンプの根元部分と半導体チップ表面の電極パッドの近傍部分（ここでは第２絶縁膜１５の側面となる）とのなす角度θは鈍角になっている。このため、図４に示すように、半導体チップ１１を配線基板２１にフリップチップ実装し、アンダーフィル樹脂２２を注入する際に、金属バンプ１７の根元部分に狭い領域がなくなるため、樹脂やフィラー成分が浸入しやすくなり、アンダーフィル樹脂２２内の気泡の発生が抑制される。また、半田からなる金属バンプ１７の下地となる金属層（下地金属層１６）の上面の投影面積を、その直下の金属層である電極パッド１３の上面の投影面積よりも小さくすることで、金属バンプ１７にかかる応力に対する耐力が強くなり、信頼性の高い半導体装置を実現できる。   According to the electrode structure of the semiconductor chip according to the first embodiment, since the base portion of the metal bump 17 is formed above the second insulating film 15, the base portion of the metal bump and the electrode pad on the surface of the semiconductor chip are formed. Is an obtuse angle with an adjacent portion (here, the side surface of the second insulating film 15). Therefore, as shown in FIG. 4, when the semiconductor chip 11 is flip-chip mounted on the wiring substrate 21 and the underfill resin 22 is injected, there is no narrow area at the base portion of the metal bump 17, so that the resin and filler components Can easily enter, and the generation of bubbles in the underfill resin 22 is suppressed. Further, the projected area of the upper surface of the metal layer (underlying metal layer 16) which is the base of the metal bump 17 made of solder is made smaller than the projected area of the upper surface of the electrode pad 13 which is the metal layer immediately below the metal layer. The proof stress against the stress applied to the bump 17 is increased, and a highly reliable semiconductor device can be realized.

なお、第１絶縁膜１４を構成する材料は、チッ化シリコンに限られず、酸化シリコンやポリイミドなどでもよい。また、第２絶縁膜１５を構成する材料についても、ポリイミドに限られず、ＢＣＢ膜などでもよい。また、下地金属層１６の下部金属層のバリアメタルを構成する材料は、Ｔｉに限られず、第２絶縁膜１５との強い密着性を有する材料であればよく、例えばＴｉＷやＣｒ等を用いてもよい。また、下部金属層の下部金属膜を構成する材料は、Ｃｕに限られず、導電性を有する材料であればよい。また、ここではスパッタリング法および電解めっき法によって下地金属層１６を形成したが、これに限られず、例えば無電解めっき法によって、Ａｌからなる電極パッド１３上に直接Ｎｉを形成してもよい。   The material constituting the first insulating film 14 is not limited to silicon nitride, and may be silicon oxide, polyimide, or the like. Further, the material forming the second insulating film 15 is not limited to polyimide, but may be a BCB film or the like. The material constituting the barrier metal of the lower metal layer of the base metal layer 16 is not limited to Ti, and may be any material that has strong adhesion to the second insulating film 15. For example, TiW or Cr is used. Also good. Moreover, the material which comprises the lower metal film of a lower metal layer is not restricted to Cu, What is necessary is just a material which has electroconductivity. In addition, here, the base metal layer 16 is formed by the sputtering method and the electrolytic plating method. However, the present invention is not limited to this. For example, Ni may be directly formed on the electrode pad 13 made of Al by an electroless plating method.

続いて、本発明の第２の実施の形態に係る半導体チップの電極構造、並びにその半導体チップを実装した半導体装置について、図２および図４を用いて説明する。この第２の実施の形態は、第１絶縁膜１４および第２絶縁膜１５上に、さらに第３絶縁膜１８が形成されている点が、前述した第１の実施の形態と異なる。   Subsequently, an electrode structure of a semiconductor chip according to a second embodiment of the present invention and a semiconductor device mounted with the semiconductor chip will be described with reference to FIGS. The second embodiment is different from the first embodiment described above in that a third insulating film 18 is further formed on the first insulating film 14 and the second insulating film 15.

すなわち、図２に示すように、半導体チップ１１の主面１２の上方に、ポリイミドからなる第３絶縁膜１８が、第２絶縁膜１５から露出する電極パッド１３の上面の一部から、第２絶縁膜１５の表面および第１絶縁膜１４の上面にかけて形成されており、第３絶縁膜１８の開口部から電極パッド１３の上面の一部が露出する。なお、第３絶縁膜１８を構成する材料はポリイミドに限られず、ＢＣＢ膜などでもよい。   That is, as shown in FIG. 2, the third insulating film 18 made of polyimide is formed above the main surface 12 of the semiconductor chip 11 from the part of the upper surface of the electrode pad 13 exposed from the second insulating film 15. It is formed over the surface of the insulating film 15 and the upper surface of the first insulating film 14, and a part of the upper surface of the electrode pad 13 is exposed from the opening of the third insulating film 18. In addition, the material which comprises the 3rd insulating film 18 is not restricted to a polyimide, A BCB film | membrane etc. may be sufficient.

また、電極パッド１３の上方には、下地金属層１６が、電極パッド１３の周縁部上方の第３絶縁膜１８の上面の少なくとも一部と、第３絶縁膜１８の開口部の内周面と、第３絶縁膜１８から露出する電極パッド１３の上面とを覆うように、第３絶縁膜１８から露出する電極パッド１３の上面から、電極パッド１３の周縁部上方の第３絶縁膜１８の上面の少なくとも一部にかけて形成されている。   In addition, above the electrode pad 13, the base metal layer 16 includes at least part of the upper surface of the third insulating film 18 above the peripheral edge of the electrode pad 13 and the inner peripheral surface of the opening of the third insulating film 18. The upper surface of the third insulating film 18 above the periphery of the electrode pad 13 from the upper surface of the electrode pad 13 exposed from the third insulating film 18 so as to cover the upper surface of the electrode pad 13 exposed from the third insulating film 18. It is formed over at least a part of.

この第２の実施の形態に係る半導体チップの電極構造によれば、金属バンプ１７の根元部分が、電極パッド１３の周縁部上方の第３絶縁膜１８の上方に形成されるので、前述した第１の実施の形態と同様に、金属バンプの根元部分と半導体チップ表面の電極パッドの近傍部分（ここでは第２絶縁膜１５の膜厚によって形成された第３絶縁膜１８の段部の外側面となる）とのなす角度θは鈍角になっている。このため、図４に示すように、半導体チップ１１を配線基板２１にフリップチップ実装し、アンダーフィル樹脂２２を注入する際に、金属バンプ１７の根元部分に狭い領域がなくなるため、樹脂やフィラー成分が浸入しやすくなり、アンダーフィル樹脂２２内の気泡の発生が抑制される。   According to the electrode structure of the semiconductor chip according to the second embodiment, the base portion of the metal bump 17 is formed above the third insulating film 18 above the peripheral edge portion of the electrode pad 13, so As in the first embodiment, the base portion of the metal bump and the vicinity of the electrode pad on the surface of the semiconductor chip (here, the outer surface of the step portion of the third insulating film 18 formed by the thickness of the second insulating film 15) Is an obtuse angle. Therefore, as shown in FIG. 4, when the semiconductor chip 11 is flip-chip mounted on the wiring substrate 21 and the underfill resin 22 is injected, there is no narrow area at the base portion of the metal bump 17, so that the resin and filler components Can easily enter, and the generation of bubbles in the underfill resin 22 is suppressed.

また、第３絶縁膜１８から露出する電極パッド１３の上面を除く半導体チップ１１の主面の上方が第３絶縁膜１８により覆われているため、半導体チップ１１の主面上に形成されている電極パッド１３や内部配線（図示せず）、第１絶縁膜１４、第２絶縁膜１５による凹凸が緩和され、更にアンダーフィル樹脂２２の充填性が良好となる。   Further, since the upper surface of the main surface of the semiconductor chip 11 excluding the upper surface of the electrode pad 13 exposed from the third insulating film 18 is covered with the third insulating film 18, it is formed on the main surface of the semiconductor chip 11. Unevenness due to the electrode pad 13, internal wiring (not shown), the first insulating film 14 and the second insulating film 15 is alleviated, and the filling property of the underfill resin 22 is improved.

また、半田からなる金属バンプ１７の下地となる金属層（下地金属層１６）の上面の投影面積を、その直下の金属層である電極パッド１３の上面の投影面積よりも小さくすることで、金属バンプ１７にかかる応力に対する耐力が強くなり、信頼性の高い半導体装置を実現できる。   Further, the projected area of the upper surface of the metal layer (underlying metal layer 16) which is the base of the metal bump 17 made of solder is made smaller than the projected area of the upper surface of the electrode pad 13 which is the metal layer immediately below the metal layer. The proof stress against the stress applied to the bump 17 is increased, and a highly reliable semiconductor device can be realized.

なお、下地金属層１６の下部金属層のバリアメタルを構成する材料は、Ｔｉに限られず、第３絶縁膜１８との強い密着性を有する材料であればよく、例えばＴｉＷやＣｒ等を用いてもよい。   The material constituting the barrier metal of the lower metal layer of the base metal layer 16 is not limited to Ti, and any material having strong adhesion to the third insulating film 18 may be used. For example, TiW or Cr is used. Also good.

続いて、本発明の第３の実施の形態に係る半導体チップの電極構造、並びにその半導体チップを実装した半導体装置について、図３および図４を用いて説明する。この第３の実施の形態に係る半導体チップは、図３に示すように、電極パッド１３の上方に、第１絶縁膜１４から露出する電極パッド１３の上面と、第１絶縁膜１４の開口部の内周面と、電極パッド１３の露出面の周囲の第１絶縁膜１４の上面とを覆うように、第１絶縁膜１４から露出する電極パッド１３の上面から第１絶縁膜１４の上面の一部にかけて第１金属層１９が形成されている。ここでは、第１金属層１９は、その上面の投影面積が電極パッド１３の上面の投影面積よりも大きくなるように形成する。   Subsequently, an electrode structure of a semiconductor chip according to a third embodiment of the present invention and a semiconductor device on which the semiconductor chip is mounted will be described with reference to FIGS. As shown in FIG. 3, the semiconductor chip according to the third embodiment has an upper surface of the electrode pad 13 exposed from the first insulating film 14 and an opening of the first insulating film 14 above the electrode pad 13. The upper surface of the first insulating film 14 is exposed from the upper surface of the electrode pad 13 exposed from the first insulating film 14 so as to cover the inner peripheral surface of the first insulating film 14 and the upper surface of the first insulating film 14 around the exposed surface of the electrode pad 13. A first metal layer 19 is formed over a portion. Here, the first metal layer 19 is formed so that the projected area of the upper surface thereof is larger than the projected area of the upper surface of the electrode pad 13.

第１金属層１９は、下部金属層と上部金属膜によって構成される。下部金属層は、例えばスパッタリング法によって形成されたＴｉからなるバリアメタルおよびＣｕからなる下部金属膜によって構成される。上部金属膜は、下部金属層の上方に電解めっき法によって形成されたＣｕからなる。   The first metal layer 19 includes a lower metal layer and an upper metal film. The lower metal layer is composed of, for example, a barrier metal made of Ti and a lower metal film made of Cu formed by sputtering. The upper metal film is made of Cu formed by electrolytic plating above the lower metal layer.

また、半導体チップ１１の主面１２の上方に、第１金属層１９の上面の一部から第１絶縁膜１４の上面にかけて、ポリイミドからなる第４絶縁膜２０が形成されており、第４絶縁膜２０の開口部から第１金属層１９の上面の一部が露出する。なお、第４絶縁膜２０を構成する材料はポリイミドに限られず、ＢＣＢ膜などでもよい。   Further, a fourth insulating film 20 made of polyimide is formed above the main surface 12 of the semiconductor chip 11 from a part of the upper surface of the first metal layer 19 to the upper surface of the first insulating film 14, and the fourth insulating film is formed. A part of the upper surface of the first metal layer 19 is exposed from the opening of the film 20. In addition, the material which comprises the 4th insulating film 20 is not restricted to a polyimide, A BCB film | membrane etc. may be sufficient.

また、第１金属層１９の上方には、下地金属層（第２金属層）１６が、第１金属層１９の周縁部上方の第４絶縁膜２０の上面の少なくとも一部と、第４絶縁膜２０の開口部の内周面と、第４絶縁膜２０から露出する第１金属層１９の上面とを覆うように、第４絶縁膜２０から露出する第１金属層１９の上面から、第１金属層１９の周縁部上方の第４絶縁膜２０の上面の少なくとも一部にかけて形成されている。ここでは、下地金属層（第２金属層）１６は、その上面の投影面積が第１金属層１９の上面の投影面積よりも小さくなるように形成する。   In addition, above the first metal layer 19, a base metal layer (second metal layer) 16 is provided with at least a part of the upper surface of the fourth insulating film 20 above the peripheral edge of the first metal layer 19 and the fourth insulation. From the upper surface of the first metal layer 19 exposed from the fourth insulating film 20 so as to cover the inner peripheral surface of the opening of the film 20 and the upper surface of the first metal layer 19 exposed from the fourth insulating film 20, The first metal layer 19 is formed over at least part of the upper surface of the fourth insulating film 20 above the peripheral edge. Here, the base metal layer (second metal layer) 16 is formed so that the projected area of the upper surface thereof is smaller than the projected area of the upper surface of the first metal layer 19.

この第３の実施の形態に係る半導体チップの電極構造によれば、金属バンプ１７の根元部分が、第１金属層１９の周縁部上方の第４絶縁膜２０の上方に形成されるので、前述した第１、２の実施の形態と同様に、金属バンプの根元部分と半導体チップ表面の電極パッド近傍部分（ここでは第１金属層１９の膜厚によって形成された第４絶縁膜２０の段部の外側面となる）とのなす角度θは鈍角となっている。このため、図４に示すように、半導体チップ１１を配線基板２１にフリップチップ実装し、アンダーフィル樹脂２２を注入する際に、金属バンプ１７の根元部分に狭い領域がなくなるため、樹脂やフィラー成分が浸入しやすくなり、アンダーフィル樹脂２２内の気泡の発生が抑制される。   According to the electrode structure of the semiconductor chip according to the third embodiment, the base portion of the metal bump 17 is formed above the fourth insulating film 20 above the peripheral edge of the first metal layer 19. As in the first and second embodiments, the base portion of the metal bump and the portion near the electrode pad on the surface of the semiconductor chip (here, the step portion of the fourth insulating film 20 formed by the thickness of the first metal layer 19) Is an obtuse angle. Therefore, as shown in FIG. 4, when the semiconductor chip 11 is flip-chip mounted on the wiring substrate 21 and the underfill resin 22 is injected, there is no narrow area at the base portion of the metal bump 17, so that the resin and filler components Can easily enter, and the generation of bubbles in the underfill resin 22 is suppressed.

また、ｌｏｗ−ｋ材料などの脆弱膜を用いる場合においても、第１金属層１９および第４絶縁膜２０によってｌｏｗ−ｋ材料のクラックや剥離現象を抑制することができる。また、第１金属層１９の上面の投影面積を電極パッド１３の投影面積よりも大きくすることで、接合部とりわけ電極パッド部分にかかる応力が第１金属層１９によって緩和されるので、電極パッド１３の面積を小さくすることが可能となり、半導体チップ１１の内部配線（図示せず）の引き回しが容易となり、設計自由度が高くなる。また、半田からなる金属バンプ１７の下地となる金属層（下地金属層１６）の上面の投影面積を、その直下の金属層である第１金属層１９の上面の投影面積よりも小さくすることで、金属バンプ１７にかかる応力に対する耐力が強くなり、信頼性の高い半導体装置を実現できる。また、第４絶縁膜２０から露出する第１金属層１９の上面を除く半導体チップ１１の主面の上方が第４絶縁膜２０で覆われているため、半導体チップ１１の主面上に形成されている電極パッド１３や内部配線（図示せず）、第１絶縁膜１４、第１金属層１９による凹凸が緩和され、更にアンダーフィル樹脂２２の充填性が良好となる。   Further, even when a fragile film such as a low-k material is used, the first metal layer 19 and the fourth insulating film 20 can suppress cracks and peeling phenomenon of the low-k material. In addition, by making the projected area of the upper surface of the first metal layer 19 larger than the projected area of the electrode pad 13, stress applied to the joint portion, particularly the electrode pad portion, is relieved by the first metal layer 19. The area of the semiconductor chip 11 can be reduced, the internal wiring (not shown) of the semiconductor chip 11 can be easily routed, and the degree of design freedom is increased. Further, the projected area of the upper surface of the metal layer (underlying metal layer 16) that is the base of the metal bump 17 made of solder is made smaller than the projected area of the upper surface of the first metal layer 19 that is the metal layer immediately below it. The proof stress against the stress applied to the metal bumps 17 is increased, and a highly reliable semiconductor device can be realized. In addition, since the upper surface of the semiconductor chip 11 excluding the upper surface of the first metal layer 19 exposed from the fourth insulating film 20 is covered with the fourth insulating film 20, it is formed on the main surface of the semiconductor chip 11. The unevenness due to the electrode pads 13 and the internal wiring (not shown), the first insulating film 14 and the first metal layer 19 is alleviated, and the filling property of the underfill resin 22 is further improved.

なお、第１金属層１９の下部金属層のバリアメタルを構成する材料は、Ｔｉに限られず、第１絶縁膜１４との強い密着性を有する材料であればよく、例えばＴｉＷやＣｒ等を用いてもよい。また、下部金属層の下部金属膜を構成する材料は、Ｃｕに限られず、導電性を有する材料であればよい。また、ここではスパッタリング法および電解めっき法によって第１金属層１９を形成したが、これに限られず、例えば無電解めっき法によって、Ａｌからなる電極パッド１３上に直接Ｎｉを形成してもよい。   The material constituting the barrier metal of the lower metal layer of the first metal layer 19 is not limited to Ti, and any material having strong adhesion to the first insulating film 14 may be used. For example, TiW or Cr is used. May be. Moreover, the material which comprises the lower metal film of a lower metal layer is not restricted to Cu, What is necessary is just a material which has electroconductivity. Here, the first metal layer 19 is formed by the sputtering method and the electrolytic plating method. However, the present invention is not limited to this. For example, Ni may be directly formed on the electrode pad 13 made of Al by an electroless plating method.

続いて、上記のように構成された各半導体装置の製造方法について図面を参照しながら説明する。但し、前述の図１〜４に基づいて説明した部材と同一の部材には同一符号を付して、説明を省略する。   Next, a method for manufacturing each semiconductor device configured as described above will be described with reference to the drawings. However, the same members as those described with reference to FIGS. 1 to 4 described above are denoted by the same reference numerals, and description thereof is omitted.

図５（ａ）〜（ｄ）、図６（ａ）〜（ｄ）、および図７（ａ）〜（ｄ）は、上記した本発明の第１の実施の形態に係る半導体装置の製造方法を示す工程断面図であり、半田からなる金属バンプの中心を通る断面構成を工程順に示している。   FIGS. 5A to 5D, FIGS. 6A to 6D, and FIGS. 7A to 7D illustrate the method of manufacturing the semiconductor device according to the first embodiment of the present invention described above. FIG. 2 is a process cross-sectional view showing a cross-sectional configuration passing through the center of a metal bump made of solder in order of processes.

まず、図５（ａ）に示すように、半導体ウェハ１０の主面１２上に、少なくとも１つの半導体素子（図示せず）と、その半導体素子に電気的に接続する電極パッド１３とを有する半導体チップを複数個形成した後、半導体チップが形成された半導体ウェハ１０の主面１２上に、電極パッド１３の上方に開口部を有する第１絶縁膜１４を形成する。   First, as shown in FIG. 5A, a semiconductor having at least one semiconductor element (not shown) and an electrode pad 13 electrically connected to the semiconductor element on the main surface 12 of the semiconductor wafer 10. After forming a plurality of chips, a first insulating film 14 having an opening above the electrode pad 13 is formed on the main surface 12 of the semiconductor wafer 10 on which the semiconductor chips are formed.

次に、図５（ｂ）に示すように、電極パッド１３の周縁部の上方に、電極パッド１３の上面の一部が露出するように、第１絶縁膜１４から露出する電極パッド１３の上面の一部から、電極パッド１３の周縁部上方の第１絶縁膜１４の上面の少なくとも一部にかけて第２絶縁膜１５を形成する。   Next, as shown in FIG. 5B, the upper surface of the electrode pad 13 exposed from the first insulating film 14 so that a part of the upper surface of the electrode pad 13 is exposed above the peripheral portion of the electrode pad 13. The second insulating film 15 is formed from a part of the first insulating film 14 to at least a part of the upper surface of the first insulating film 14 above the peripheral edge of the electrode pad 13.

次に、図５（ｃ）に示すように、電極パッド１３の露出面、第２絶縁膜１５の表面、および第１絶縁膜１４の上面に、スパッタリング法により、ＴｉからなるバリアメタルおよびＣｕからなる下部金属膜から構成される下部金属層１６ａを形成する。なお、下部金属層１６ａの形成は、スパッタリング法に限らず、真空蒸着法、ＣＶＤ法、または無電解めっき法等を用いてもよい。   Next, as shown in FIG. 5C, a barrier metal made of Ti and Cu are formed on the exposed surface of the electrode pad 13, the surface of the second insulating film 15, and the upper surface of the first insulating film 14 by sputtering. A lower metal layer 16a composed of the lower metal film is formed. The formation of the lower metal layer 16a is not limited to the sputtering method, and a vacuum deposition method, a CVD method, an electroless plating method, or the like may be used.

次に、図５（ｄ）に示すように、めっきレジスト膜３１をマスクとして用いた電解めっき法により、電極パッド１３の上方に、下部金属層１６ａをシードとしてＮｉからなる上部金属膜１６ｂを形成する。   Next, as shown in FIG. 5D, an upper metal film 16b made of Ni is formed above the electrode pad 13 by electrolytic plating using the plating resist film 31 as a mask, using the lower metal layer 16a as a seed. To do.

次に、図６（ａ）に示すように、上部金属膜１６ｂ上に電解めっき法により半田めっきを行う。次に、図６（ｂ）に示すように、まず、めっきレジスト膜３１を除去した後、ウェットエッチングにより余分な下部金属層１６ａを除去する。その結果、電極パッド１３の上方に、第２絶縁膜１５の上面の少なくとも一部と、第２絶縁膜１５の開口部の内周面と、第２絶縁膜１５から露出する電極パッド１３の上面とを覆う下地金属層１６が形成される。   Next, as shown in FIG. 6A, solder plating is performed on the upper metal film 16b by electrolytic plating. Next, as shown in FIG. 6B, first, after removing the plating resist film 31, the excess lower metal layer 16a is removed by wet etching. As a result, above the electrode pad 13, at least a part of the upper surface of the second insulating film 15, the inner peripheral surface of the opening of the second insulating film 15, and the upper surface of the electrode pad 13 exposed from the second insulating film 15. Is formed.

次に、図６（ｃ）に示すように、リフロー（熱処理）することにより、半田からなる金属バンプ１７を略球形状にする。その結果、下地金属層１６上に半田からなる金属バンプ１７が形成される。   Next, as shown in FIG. 6C, reflow (heat treatment) is performed to make the metal bumps 17 made of solder into a substantially spherical shape. As a result, metal bumps 17 made of solder are formed on the base metal layer 16.

次に、図６（ｄ）に示すように、裏面研磨およびダイシングを行い、半導体ウェハを個々の半導体チップ１１に分割して、複数個の半導体チップ１１を得る。次に、図７（ａ）に示すように、金属バンプ１７に対応する位置に金属電極２３が形成されている配線基板２１上に半導体チップ１１をフェイスダウンで搭載する（フリップチップ実装）。   Next, as shown in FIG. 6D, backside polishing and dicing are performed to divide the semiconductor wafer into individual semiconductor chips 11 to obtain a plurality of semiconductor chips 11. Next, as shown in FIG. 7A, the semiconductor chip 11 is mounted face down on the wiring substrate 21 on which the metal electrode 23 is formed at a position corresponding to the metal bump 17 (flip chip mounting).

次に、図７（ｂ）に示すように、半導体チップ１１が搭載された配線基板２１をリフロー（熱処理）することにより金属バンプ１７を溶融させ、半導体チップ１１と配線基板２１とを接合することで、半導体チップ１１と配線基板２１とを金属バンプ１７を介して電気的に接続する。   Next, as shown in FIG. 7B, the metal bumps 17 are melted by reflowing (heat treating) the wiring board 21 on which the semiconductor chip 11 is mounted, and the semiconductor chip 11 and the wiring board 21 are joined. Thus, the semiconductor chip 11 and the wiring substrate 21 are electrically connected via the metal bumps 17.

次に、図７（ｃ）に示すように、半導体チップ１１と配線基板２１との隙間を清浄化し、ディスペンサ装置３２を用いて封止用のアンダーフィル樹脂２２をチップ周辺部から注入し、半導体チップ１１と配線基板２１との隙間をアンダーフィル樹脂２２で充填した後、熱処理することによりアンダーフィル樹脂２２を硬化して封止する。   Next, as shown in FIG. 7C, the gap between the semiconductor chip 11 and the wiring substrate 21 is cleaned, and a sealing underfill resin 22 is injected from the periphery of the chip using the dispenser device 32. After the gap between the chip 11 and the wiring substrate 21 is filled with the underfill resin 22, the underfill resin 22 is cured and sealed by heat treatment.

次に、図７（ｄ）に示すように、配線基板２１の半導体チップ搭載面とは反対側の面に、半田ボール２４を載置し、リフローすることにより外部機器との接続に使用する端子を形成する。   Next, as shown in FIG. 7 (d), a solder ball 24 is placed on the surface opposite to the semiconductor chip mounting surface of the wiring substrate 21, and the terminals used for connection to an external device are reflowed. Form.

以上の工程により、上記した第１の実施の形態に係る半導体装置を得ることができる。   Through the above steps, the semiconductor device according to the first embodiment described above can be obtained.

続いて、上記した本発明の第２の実施の形態に係る半導体装置の製造方法について説明する。第２の実施の形態に係る半導体装置の製造方法は、図５から図７に示す工程において、図５に示す工程を図８に示す工程に置き換えればよい。図８（ａ）〜（ｅ）は、上記した本発明の第２の実施の形態に係る半導体装置の製造方法のうち、前述した本発明の第１の実施の形態に係る半導体装置の製造方法と異なる部分について示す工程断面図であり、半田からなる金属バンプの中心を通る断面構成を工程順に示している。   Then, the manufacturing method of the semiconductor device which concerns on the above-mentioned 2nd Embodiment of this invention is demonstrated. In the method of manufacturing a semiconductor device according to the second embodiment, the process shown in FIG. 5 may be replaced with the process shown in FIG. 8A to 8E show the semiconductor device manufacturing method according to the first embodiment of the present invention described above, among the semiconductor device manufacturing methods according to the second embodiment of the present invention described above. FIG. 6 is a process cross-sectional view showing a different part from FIG. 1 and shows a cross-sectional configuration passing through the center of a metal bump made of solder in the order of processes.

まず、図８（ａ）、（ｂ）に示すように、図５（ａ）、（ｂ）に示す工程と同様に、半導体ウェハ１０の主面１２上に半導体チップを複数個形成した後、第１絶縁膜１４と第２絶縁膜１５を形成する。   First, as shown in FIGS. 8A and 8B, after forming a plurality of semiconductor chips on the main surface 12 of the semiconductor wafer 10, similarly to the steps shown in FIGS. 5A and 5B, A first insulating film 14 and a second insulating film 15 are formed.

次に、図８（ｃ）に示すように、半導体ウェハ１０の主面１２の上方に、電極パッド１３の上面の一部が露出するように、第２絶縁膜１５から露出する電極パッド１３の上面の一部から、第２絶縁膜１５の表面および第１絶縁膜１４の上面にかけて第３絶縁膜１８を形成する。   Next, as shown in FIG. 8C, the electrode pad 13 exposed from the second insulating film 15 is exposed above the main surface 12 of the semiconductor wafer 10 so that a part of the upper surface of the electrode pad 13 is exposed. A third insulating film 18 is formed from a part of the upper surface to the surface of the second insulating film 15 and the upper surface of the first insulating film 14.

次に、図８（ｄ）に示すように、電極パッド１３の露出面、第３絶縁膜１８の開口部の内周面、および第３絶縁膜１８の上面に、スパッタリング法により下部金属層１６ａを形成する。なお、上述したように、下部金属層１６ａの形成は、スパッタリング法に限らず、真空蒸着法、ＣＶＤ法、または無電解めっき法等を用いてもよい。   Next, as shown in FIG. 8D, the lower metal layer 16a is formed on the exposed surface of the electrode pad 13, the inner peripheral surface of the opening of the third insulating film 18, and the upper surface of the third insulating film 18 by sputtering. Form. As described above, the formation of the lower metal layer 16a is not limited to the sputtering method, and a vacuum deposition method, a CVD method, an electroless plating method, or the like may be used.

次に、図８（ｅ）に示すように、図５（ｄ）に示す工程と同様に、めっきレジスト膜３１をマスクとして用いた電解めっき法により、電極パッド１３の上方に、下部金属層１６ａをシードとしてＮｉからなる上部金属膜１６ｂを形成する。   Next, as shown in FIG. 8E, similarly to the step shown in FIG. 5D, the lower metal layer 16a is formed above the electrode pad 13 by electrolytic plating using the plating resist film 31 as a mask. Is used as a seed to form an upper metal film 16b made of Ni.

この後、図６（ａ）〜（ｄ）、図７（ａ）〜（ｄ）に示す工程と同様の工程を行うことによって、上記した第２の実施の形態に係る半導体装置を得ることができる。すなわち、まず、図６（ａ）に示す工程と同様に、上部金属膜１６ｂ上に電解めっき法により半田めっきを行う。次に、図６（ｂ）に示す工程と同様に、めっきレジスト膜３１を除去した後、ウェットエッチングにより余分な下部金属層１６ａを除去する。次に、図６（ｃ）に示す工程と同様に、リフロー（熱処理）することにより、半田からなる金属バンプ１７を略球形状にする。次に、図６（ｄ）に示す工程と同様に、半導体ウェハを個々の半導体チップ１１に分割する。   Thereafter, by performing the same steps as those shown in FIGS. 6A to 6D and FIGS. 7A to 7D, the semiconductor device according to the second embodiment described above can be obtained. it can. That is, first, similarly to the process shown in FIG. 6A, solder plating is performed on the upper metal film 16b by electrolytic plating. Next, similarly to the step shown in FIG. 6B, after removing the plating resist film 31, the excess lower metal layer 16a is removed by wet etching. Next, similarly to the step shown in FIG. 6C, the metal bumps 17 made of solder are formed into a substantially spherical shape by reflowing (heat treatment). Next, the semiconductor wafer is divided into individual semiconductor chips 11 as in the step shown in FIG.

次に、図７（ａ）に示す工程と同様に、配線基板２１上に半導体チップ１１をフェイスダウンで搭載する。次に、図７（ｂ）に示す工程と同様に、配線基板２１をリフロー（熱処理）することにより金属バンプ１７を溶融させ、半導体チップ１１と配線基板２１とを接合する。次に、図７（ｃ）に示す工程と同様に、半導体チップ１１と配線基板２１との隙間をアンダーフィル樹脂２２で充填した後、熱処理することによりアンダーフィル樹脂２２を硬化して封止する。次に、図７（ｄ）に示すように、配線基板２１の半導体チップ搭載面とは反対側の面に、半田ボール２４を載置し、リフローすることにより外部機器との接続に使用する端子を形成する。   Next, as in the process shown in FIG. 7A, the semiconductor chip 11 is mounted face-down on the wiring board 21. Next, similarly to the step shown in FIG. 7B, the metal substrate 17 is melted by reflowing (heat treating) the wiring substrate 21, and the semiconductor chip 11 and the wiring substrate 21 are bonded. Next, similarly to the process shown in FIG. 7C, after filling the gap between the semiconductor chip 11 and the wiring substrate 21 with the underfill resin 22, the underfill resin 22 is cured and sealed by heat treatment. . Next, as shown in FIG. 7 (d), a solder ball 24 is placed on the surface opposite to the semiconductor chip mounting surface of the wiring substrate 21, and the terminals used for connection to an external device are reflowed. Form.

続いて、上記した本発明の第３の実施の形態に係る半導体装置の製造方法について説明する。第３の実施の形態に係る半導体装置の製造方法は、図５から図７に示す工程において、図５に示す工程を図９、１０に示す工程に置き換えればよい。図９（ａ）〜（ｄ）、および図１０（ａ）〜（ｃ）は、上記した本発明の第３の実施の形態に係る半導体装置の製造方法のうち、前述した本発明の第１の実施の形態に係る半導体装置の製造方法と異なる部分について示した工程断面図であり、半田からなる金属バンプの中心を通る断面構成を工程順に示している。   Then, the manufacturing method of the semiconductor device which concerns on the above-mentioned 3rd Embodiment of this invention is demonstrated. In the method of manufacturing the semiconductor device according to the third embodiment, in the steps shown in FIGS. 5 to 7, the steps shown in FIG. 5 may be replaced with the steps shown in FIGS. 9 (a) to 9 (d) and FIGS. 10 (a) to 10 (c) show the above-described first method of the present invention in the semiconductor device manufacturing method according to the third embodiment of the present invention. It is process sectional drawing shown about the part different from the manufacturing method of the semiconductor device which concerns on this embodiment, and has shown the cross-sectional structure which passes along the center of the metal bump consisting of solder in order of a process.

まず、図９（ａ）に示すように、図５（ａ）に示す工程と同様に、半導体ウェハ１０の主面１２上に半導体チップ１１を複数個形成した後、第１絶縁膜１４を形成する。次に、図９（ｂ）に示すように、電極パッド１３の露出面、第１絶縁膜１４の開口部の内周面、および第１絶縁膜１４の上面に、スパッタリング法により、ＴｉからなるバリアメタルおよびＣｕからなる下部金属膜から構成される下部金属層１９ａを形成する。なお、下部金属層１９ａの形成は、スパッタリング法に限らず、真空蒸着法、ＣＶＤ法、または無電解めっき法等を用いてもよい。   First, as shown in FIG. 9A, as in the step shown in FIG. 5A, after a plurality of semiconductor chips 11 are formed on the main surface 12 of the semiconductor wafer 10, a first insulating film 14 is formed. To do. Next, as shown in FIG. 9B, the exposed surface of the electrode pad 13, the inner peripheral surface of the opening of the first insulating film 14, and the upper surface of the first insulating film 14 are made of Ti by sputtering. A lower metal layer 19a composed of a lower metal film made of a barrier metal and Cu is formed. The formation of the lower metal layer 19a is not limited to the sputtering method, and a vacuum deposition method, a CVD method, an electroless plating method, or the like may be used.

次に、図９（ｃ）に示すように、めっきレジスト膜３３を用いた電解めっき法により、電極パッド１２の上方に、Ｃｕからなる上部金属膜１９ｂを形成する。ここでは、上部金属膜１９ｂの上面の投影面積が、電極パッド１３の上面の投影面積よりも大きくなるように形成する。また、上部金属膜１９ｂの厚みは５μｍとした。   Next, as shown in FIG. 9C, an upper metal film 19b made of Cu is formed above the electrode pad 12 by electrolytic plating using the plating resist film 33. Next, as shown in FIG. Here, the upper metal film 19b is formed such that the projected area of the upper surface is larger than the projected area of the upper surface of the electrode pad 13. The thickness of the upper metal film 19b was 5 μm.

次に、図９（ｄ）に示すように、まず、めっきレジスト膜３３を除去した後、次にウェットエッチングにより余分な下部金属層１９ａを除去する。このとき、下部金属層１９ａよりも上部金属膜１９ｂが充分に厚いので、エッチングによって上部金属膜１９ｂが消失することなく、第１金属層１９が形成される。その結果、電極パッド１３の上方に、第１絶縁膜１４から露出する電極パッド１３の上面と、第１絶縁膜１４の開口部の内周面と、電極パッド１３の露出面の周囲の第１絶縁膜１４の上面とを覆う第１金属層１９が形成される。   Next, as shown in FIG. 9D, first, the plating resist film 33 is removed, and then the excess lower metal layer 19a is removed by wet etching. At this time, since the upper metal film 19b is sufficiently thicker than the lower metal layer 19a, the first metal layer 19 is formed without the upper metal film 19b disappearing by etching. As a result, above the electrode pad 13, the upper surface of the electrode pad 13 exposed from the first insulating film 14, the inner peripheral surface of the opening of the first insulating film 14, and the first around the exposed surface of the electrode pad 13. A first metal layer 19 covering the upper surface of the insulating film 14 is formed.

次に、図１０（ａ）に示すように、半導体ウェハ１０の主面１２の上方に、第１金属層１９の上面の一部が露出するように、第１金属層１９の上面の一部から第１絶縁膜１４の上面にかけて第４絶縁膜２０を形成する。   Next, as shown in FIG. 10A, a part of the upper surface of the first metal layer 19 is exposed so that a part of the upper surface of the first metal layer 19 is exposed above the main surface 12 of the semiconductor wafer 10. A fourth insulating film 20 is formed over the upper surface of the first insulating film 14.

次に、図１０（ｂ）に示すように、第１金属層１９の露出面、第４絶縁膜２０の開口部内周面、および第４絶縁膜２０の上面に、スパッタリング法により下部金属層１６ａを形成する。なお、下部金属層１６ａの形成は、スパッタリング法に限らず、真空蒸着法、ＣＶＤ法、または無電解めっき法等を用いてもよい。   Next, as shown in FIG. 10B, the lower metal layer 16a is formed on the exposed surface of the first metal layer 19, the inner peripheral surface of the opening of the fourth insulating film 20, and the upper surface of the fourth insulating film 20 by sputtering. Form. The formation of the lower metal layer 16a is not limited to the sputtering method, and a vacuum deposition method, a CVD method, an electroless plating method, or the like may be used.

次に、図１０（ｃ）に示すように、図５（ｄ）に示す工程と同様に、めっきレジスト膜３１をマスクとして用いた電解めっき法により、第１金属層１９の上方に、下部金属層１６ａをシードとしてＮｉからなる上部金属膜１６ｂを形成する。   Next, as shown in FIG. 10C, as in the step shown in FIG. 5D, the lower metal is formed above the first metal layer 19 by electrolytic plating using the plating resist film 31 as a mask. An upper metal film 16b made of Ni is formed using the layer 16a as a seed.

この後、図６（ａ）〜（ｄ）、図７（ａ）〜（ｄ）に示す工程と同様の工程を行うことによって、上記した第３の実施の形態に係る半導体装置を得ることができる。すなわち、まず、図６（ａ）に示す工程と同様に、上部金属膜１６ｂ上に電解めっき法により半田めっきを行う。次に、図６（ｂ）に示す工程と同様に、めっきレジスト膜３１を除去した後、ウェットエッチングにより余分な下部金属層１６ａを除去する。次に、図６（ｃ）に示す工程と同様に、リフロー（熱処理）することにより、半田からなる金属バンプ１７を略球形状にする。次に、図６（ｄ）に示す工程と同様に、半導体ウェハを個々の半導体チップ１１に分割する。   Thereafter, by performing the same steps as those shown in FIGS. 6A to 6D and FIGS. 7A to 7D, the semiconductor device according to the third embodiment described above can be obtained. it can. That is, first, similarly to the process shown in FIG. 6A, solder plating is performed on the upper metal film 16b by electrolytic plating. Next, similarly to the step shown in FIG. 6B, after removing the plating resist film 31, the excess lower metal layer 16a is removed by wet etching. Next, similarly to the step shown in FIG. 6C, the metal bumps 17 made of solder are formed into a substantially spherical shape by reflowing (heat treatment). Next, the semiconductor wafer is divided into individual semiconductor chips 11 as in the step shown in FIG.

次に、図７（ａ）に示す工程と同様に、配線基板２１上に半導体チップ１１をフェイスダウンで搭載する。次に、図７（ｂ）に示す工程と同様に、配線基板２１をリフロー（熱処理）することにより金属バンプ１７を溶融させ、半導体チップ１１と配線基板２１とを接合する。次に、図７（ｃ）に示す工程と同様に、半導体チップ１１と配線基板２１との隙間をアンダーフィル樹脂２２で充填した後、熱処理することによりアンダーフィル樹脂２２を硬化して封止する。次に、図７（ｄ）に示すように、配線基板２１の半導体チップ搭載面とは反対側の面に、半田ボール２４を載置し、リフローすることにより外部機器との接続に使用する端子を形成する。   Next, as in the process shown in FIG. 7A, the semiconductor chip 11 is mounted face-down on the wiring board 21. Next, similarly to the step shown in FIG. 7B, the metal substrate 17 is melted by reflowing (heat treating) the wiring substrate 21, and the semiconductor chip 11 and the wiring substrate 21 are bonded. Next, similarly to the process shown in FIG. 7C, after filling the gap between the semiconductor chip 11 and the wiring substrate 21 with the underfill resin 22, the underfill resin 22 is cured and sealed by heat treatment. . Next, as shown in FIG. 7 (d), a solder ball 24 is placed on the surface opposite to the semiconductor chip mounting surface of the wiring substrate 21, and the terminals used for connection to an external device are reflowed. Form.

本発明に係る半導体チップの電極構造、並びにその半導体チップがフリップチップ実装された半導体装置及びその製造方法は、半田からなる金属バンプを有する半導体チップを配線基板にフリップチップ実装し、前記半導体チップと前記配線基板との間隙にアンダーフィル樹脂を充填する際に、アンダーフィル樹脂内に発生する気泡を抑制することができ、信頼性の高い半導体装置を歩留まりよく製造するための手法として有用である。   An electrode structure of a semiconductor chip according to the present invention, a semiconductor device in which the semiconductor chip is flip-chip mounted, and a manufacturing method thereof include flip-chip mounting a semiconductor chip having metal bumps made of solder on a wiring board, and the semiconductor chip When the underfill resin is filled in the gap with the wiring board, bubbles generated in the underfill resin can be suppressed, which is useful as a technique for manufacturing a highly reliable semiconductor device with a high yield.

本発明の第１の実施の形態に係る半導体チップの電極構造を示す拡大断面図The expanded sectional view which shows the electrode structure of the semiconductor chip which concerns on the 1st Embodiment of this invention 本発明の第２の実施の形態に係る半導体チップの電極構造を示す拡大断面図The expanded sectional view which shows the electrode structure of the semiconductor chip which concerns on the 2nd Embodiment of this invention 本発明の第３の実施の形態に係る半導体チップの電極構造を示す拡大断面図The expanded sectional view which shows the electrode structure of the semiconductor chip which concerns on the 3rd Embodiment of this invention 本発明の各実施の形態に係る半導体装置の構成を示す概略断面図Schematic sectional view showing a configuration of a semiconductor device according to each embodiment of the present invention 本発明の第１の実施の形態に係る半導体装置の製造方法を示す工程断面図Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 1st Embodiment of this invention 本発明の各実施の形態に係る半導体装置の製造方法を示す工程断面図Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on each embodiment of this invention 本発明の各実施の形態に係る半導体装置の製造方法を示す工程断面図Process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on each embodiment of this invention 本発明の第２の実施の形態に係る半導体装置の製造方法を示す工程断面図Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 2nd Embodiment of this invention 本発明の第３の実施の形態に係る半導体装置の製造方法を示す工程断面図Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention 本発明の第３の実施の形態に係る半導体装置の製造方法を示す工程断面図Sectional drawing which shows the manufacturing method of the semiconductor device which concerns on the 3rd Embodiment of this invention 従来の半導体装置の構成を示す概略断面図Schematic sectional view showing the structure of a conventional semiconductor device 従来の半導体装置の製造方法を示す工程断面図Process sectional view showing a conventional method of manufacturing a semiconductor device （ａ）は従来の半導体チップの電極構造を示す拡大断面図、（ｂ）および（ｃ）は従来の半導体装置の問題点を説明するための概略断面図(A) is an enlarged sectional view showing an electrode structure of a conventional semiconductor chip, and (b) and (c) are schematic sectional views for explaining problems of the conventional semiconductor device.

符号の説明Explanation of symbols

１０ 半導体ウェハ
１１ 半導体チップ
１２ 主面
１３ 電極パッド
１４ 第１絶縁膜
１５ 第２絶縁膜
１６ 下地金属層
１６ａ 下部金属層
１６ｂ 上部金属膜
１７ 金属バンプ
１８ 第３絶縁膜
１９ 第１金属層
１９ａ 下部金属層
１９ｂ 上部金属膜
２０ 第４絶縁膜
２１ 配線基板
２２ アンダーフィル樹脂
２３ 金属電極
２４ 半田ボール（ＢＧＡボール）
３１、３３ めっきレジスト膜
３２ ディスペンサ装置
１０１ 半導体チップ
１０２ 主面
１０３ 電極パッド
１０４ 絶縁膜
１０５ 下地金属層
１０６ 金属バンプ
１１１ 配線基板
１１２ アンダーフィル樹脂
１１２ａ アンダーフィル樹脂の樹脂成分
１１２ｂ アンダーフィル樹脂のフィラー成分
１１３ 金属電極
１１４ 半田ボール（ＢＧＡボール） DESCRIPTION OF SYMBOLS 10 Semiconductor wafer 11 Semiconductor chip 12 Main surface 13 Electrode pad 14 1st insulating film 15 2nd insulating film 16 Base metal layer 16a Lower metal layer 16b Upper metal film 17 Metal bump 18 3rd insulating film 19 1st metal layer 19a Lower metal Layer 19b Upper metal film 20 Fourth insulating film 21 Wiring board 22 Underfill resin 23 Metal electrode 24 Solder ball (BGA ball)
31, 33 Plating resist film 32 Dispenser device 101 Semiconductor chip 102 Main surface 103 Electrode pad 104 Insulating film 105 Underlying metal layer 106 Metal bump 111 Wiring substrate 112 Underfill resin 112a Resin component of underfill resin 112b Filler component of underfill resin 113 Metal electrode 114 Solder ball (BGA ball)

Claims (12)

主面上に形成された電極パッドと、前記電極パッドの上面の一部から前記主面にかけて形成された第１絶縁膜と、前記電極パッドの上方に形成され、前記電極パッドと電気的に接続する半田からなる金属バンプと、を備えた半導体チップの電極構造であって、
該半導体チップ表面の前記電極パッドの近傍部分と前記金属バンプの根元部分とがなす角度は、鈍角である
ことを特徴とする半導体チップの電極構造。 An electrode pad formed on the main surface, a first insulating film formed from a part of the upper surface of the electrode pad to the main surface, and formed above the electrode pad and electrically connected to the electrode pad A semiconductor bump electrode structure comprising metal bumps made of solder,
An electrode structure of a semiconductor chip, wherein an angle formed between a portion near the electrode pad on the surface of the semiconductor chip and a base portion of the metal bump is an obtuse angle. 請求項１記載の半導体チップの電極構造であって、
前記第１絶縁膜から露出する前記電極パッドの上面の一部から前記第１絶縁膜の表面の一部にかけて形成された第２絶縁膜と、
前記第２絶縁膜から露出する前記電極パッドの上面から前記第２絶縁膜の表面の一部にかけて形成された下地金属層と、
を備え、
前記金属バンプは、前記下地金属層の表面に形成されており、
前記第２絶縁膜の表面と前記金属バンプの根元部分とがなす角度が鈍角である
ことを特徴とする半導体チップの電極構造。 The electrode structure of the semiconductor chip according to claim 1,
A second insulating film formed from a part of the upper surface of the electrode pad exposed from the first insulating film to a part of the surface of the first insulating film;
A base metal layer formed from the upper surface of the electrode pad exposed from the second insulating film to a part of the surface of the second insulating film;
With
The metal bump is formed on the surface of the base metal layer,
An electrode structure of a semiconductor chip, wherein an angle formed between a surface of the second insulating film and a base portion of the metal bump is an obtuse angle. 請求項１記載の半導体チップの電極構造であって、
前記第１絶縁膜から露出する前記電極パッドの上面の一部から前記第１絶縁膜の表面の一部にかけて形成された第２絶縁膜と、
前記第２絶縁膜から露出する前記電極パッドの上面の一部から、前記第２絶縁膜の表面および前記第１絶縁膜の上面にかけて形成された第３絶縁膜と、
前記第３絶縁膜から露出する前記電極パッドの上面から前記第３絶縁膜の表面の一部にかけて形成された下地金属層と、
を備え、
前記金属バンプは、前記下地金属層の表面に形成されており、
前記第３絶縁膜の表面と前記金属バンプの根元部分とがなす角度が鈍角である
ことを特徴とする半導体チップの電極構造。 The electrode structure of the semiconductor chip according to claim 1,
A second insulating film formed from a part of the upper surface of the electrode pad exposed from the first insulating film to a part of the surface of the first insulating film;
A third insulating film formed from a part of the upper surface of the electrode pad exposed from the second insulating film to the surface of the second insulating film and the upper surface of the first insulating film;
A base metal layer formed from the upper surface of the electrode pad exposed from the third insulating film to a part of the surface of the third insulating film;
With
The metal bump is formed on the surface of the base metal layer,
An electrode structure of a semiconductor chip, wherein an angle formed between a surface of the third insulating film and a base portion of the metal bump is an obtuse angle. 請求項１記載の半導体チップの電極構造であって、
前記第１絶縁膜から露出する前記電極パッドの上面から前記第１絶縁膜の表面の一部にかけて形成された第１金属層と、
前記第１金属層の上面の一部から前記第１絶縁膜の上面にかけて形成された第４絶縁膜と、
前記第４絶縁膜から露出する前記第１金属層の上面から前記第４絶縁膜の表面の一部にかけて形成された第２金属層と、
を備え、
前記金属バンプは、前記第２金属層の表面に形成されており、
前記第４絶縁膜の表面と前記金属バンプの根元部分とがなす角度が鈍角である
ことを特徴とする半導体チップの電極構造。 The electrode structure of the semiconductor chip according to claim 1,
A first metal layer formed from the upper surface of the electrode pad exposed from the first insulating film to a part of the surface of the first insulating film;
A fourth insulating film formed from a part of the upper surface of the first metal layer to the upper surface of the first insulating film;
A second metal layer formed from an upper surface of the first metal layer exposed from the fourth insulating film to a part of a surface of the fourth insulating film;
With
The metal bump is formed on the surface of the second metal layer,
An electrode structure of a semiconductor chip, wherein an angle formed between a surface of the fourth insulating film and a base portion of the metal bump is an obtuse angle. 前記下地金属層は、その上面の投影面積が前記電極パッドの上面の投影面積よりも小さいことを特徴とする請求項１ないし３のいずれかに記載の半導体チップの電極構造。   4. The electrode structure of a semiconductor chip according to claim 1, wherein a projected area of the upper surface of the base metal layer is smaller than a projected area of the upper surface of the electrode pad. 前記第１金属層は、その上面の投影面積が前記電極パッドの上面の投影面積よりも大きいことを特徴とする請求項４記載の半導体チップの電極構造。   5. The electrode structure of a semiconductor chip according to claim 4, wherein the projected area of the upper surface of the first metal layer is larger than the projected area of the upper surface of the electrode pad. 前記第２金属層は、その上面の投影面積が前記第１金属層の上面の投影面積よりも小さいことを特徴とする請求項４もしくは６のいずれかに記載の半導体チップの電極構造。   7. The electrode structure of a semiconductor chip according to claim 4, wherein the projected area of the upper surface of the second metal layer is smaller than the projected area of the upper surface of the first metal layer. 8. 請求項１ないし７のいずれかに記載の電極構造を有する半導体チップと、前記半導体チップがフリップチップ実装される配線基板と、前記半導体チップと前記配線基板との間隙を充填するアンダーフィル樹脂と、を備えることを特徴とする半導体装置。   A semiconductor chip having the electrode structure according to any one of claims 1 to 7, a wiring board on which the semiconductor chip is flip-chip mounted, an underfill resin that fills a gap between the semiconductor chip and the wiring board, A semiconductor device comprising: 半導体ウェハの主面上に、半導体素子と電極パッドを有する半導体チップを複数個形成する工程と、
前記半導体チップが形成された前記半導体ウェハの主面上に、前記電極パッドの上面の一部が露出するように第１絶縁膜を形成する工程と、
前記第１絶縁膜から露出する前記電極パッドの上面の一部から前記第１絶縁膜の表面の一部にかけて第２絶縁膜を形成する工程と、
前記第２絶縁膜から露出する前記電極パッドの上面から前記第２絶縁膜の表面の一部にかけて下地金属層を形成する工程と、
前記下地金属層上に半田からなる金属バンプを形成する工程と、
前記半導体ウェハを個々の前記半導体チップに分割する工程と、
を含むことを特徴とする半導体装置の製造方法。 Forming a plurality of semiconductor chips having semiconductor elements and electrode pads on the main surface of the semiconductor wafer;
Forming a first insulating film on a main surface of the semiconductor wafer on which the semiconductor chip is formed so that a part of the upper surface of the electrode pad is exposed;
Forming a second insulating film from a part of the upper surface of the electrode pad exposed from the first insulating film to a part of the surface of the first insulating film;
Forming a base metal layer from the upper surface of the electrode pad exposed from the second insulating film to a part of the surface of the second insulating film;
Forming a metal bump made of solder on the base metal layer;
Dividing the semiconductor wafer into individual semiconductor chips;
A method for manufacturing a semiconductor device, comprising: 半導体ウェハの主面上に、半導体素子と電極パッドを有する半導体チップを複数個形成する工程と、
前記半導体チップが形成された前記半導体ウェハの主面上に、前記電極パッドの上面の一部が露出するように第１絶縁膜を形成する工程と、
前記第１絶縁膜から露出する前記電極パッドの上面の一部から前記第１絶縁膜の表面の一部にかけて第２絶縁膜を形成する工程と、
前記第２絶縁膜から露出する前記電極パッドの上面の一部から、前記第２絶縁膜の表面および前記第１絶縁膜の上面にかけて第３絶縁膜を形成する工程と、
前記第３絶縁膜から露出する前記電極パッドの上面から前記第３絶縁膜の表面の一部にかけて下地金属層を形成する工程と、
前記下地金属層上に半田からなる金属バンプを形成する工程と、
前記半導体ウェハを個々の前記半導体チップに分割する工程と、
を含むことを特徴とする半導体装置の製造方法。 Forming a plurality of semiconductor chips having semiconductor elements and electrode pads on the main surface of the semiconductor wafer;
Forming a first insulating film on a main surface of the semiconductor wafer on which the semiconductor chip is formed so that a part of the upper surface of the electrode pad is exposed;
Forming a second insulating film from a part of the upper surface of the electrode pad exposed from the first insulating film to a part of the surface of the first insulating film;
Forming a third insulating film from a part of the upper surface of the electrode pad exposed from the second insulating film to the surface of the second insulating film and the upper surface of the first insulating film;
Forming a base metal layer from the upper surface of the electrode pad exposed from the third insulating film to a part of the surface of the third insulating film;
Forming a metal bump made of solder on the base metal layer;
Dividing the semiconductor wafer into individual semiconductor chips;
A method for manufacturing a semiconductor device, comprising: 半導体ウェハの主面上に、半導体素子と電極パッドを有する半導体チップを複数個形成する工程と、
前記半導体チップが形成された前記半導体ウェハの主面上に、前記電極パッドの上面の一部が露出するように第１絶縁膜を形成する工程と、
前記第１絶縁膜から露出する前記電極パッドの上面から前記第１絶縁膜の表面の一部にかけて第１金属層を形成する工程と、
前記第１金属層の上面の一部から前記第１絶縁膜の上面にかけて第４絶縁膜を形成する工程と、
前記第４絶縁膜から露出する前記第１金属層の上面から前記第４絶縁膜の表面の一部にかけて第２金属層を形成する工程と、
前記第２金属層上に半田からなる金属バンプを形成する工程と、
前記半導体ウェハを個々の前記半導体チップに分割する工程と、
を含むことを特徴とする半導体装置の製造方法。 Forming a plurality of semiconductor chips having semiconductor elements and electrode pads on the main surface of the semiconductor wafer;
Forming a first insulating film on a main surface of the semiconductor wafer on which the semiconductor chip is formed so that a part of the upper surface of the electrode pad is exposed;
Forming a first metal layer from the upper surface of the electrode pad exposed from the first insulating film to a part of the surface of the first insulating film;
Forming a fourth insulating film from a part of the upper surface of the first metal layer to the upper surface of the first insulating film;
Forming a second metal layer from an upper surface of the first metal layer exposed from the fourth insulating film to a part of a surface of the fourth insulating film;
Forming a metal bump made of solder on the second metal layer;
Dividing the semiconductor wafer into individual semiconductor chips;
A method for manufacturing a semiconductor device, comprising: 請求項９ないし１１のいずれかに記載の製造方法によって製造した半導体チップを、配線基板上にフェイスダウンで搭載する工程と、
前記半導体チップが搭載された前記配線基板を熱処理して前記半導体チップと前記配線基板とを前記金属バンプを介して電気的に接続する工程と、
前記半導体チップが電気的に接続された前記配線基板と前記半導体チップとの間隙に封止用のアンダーフィル樹脂を注入する工程と、
前記アンダーフィル樹脂を熱処理により硬化して封止する工程と、
を含むことを特徴とする半導体装置の製造方法。 Mounting the semiconductor chip manufactured by the manufacturing method according to claim 9 on a wiring board face down;
Heat treating the wiring board on which the semiconductor chip is mounted to electrically connect the semiconductor chip and the wiring board via the metal bumps;
Injecting a sealing underfill resin into a gap between the wiring substrate to which the semiconductor chip is electrically connected and the semiconductor chip;
Curing and sealing the underfill resin by heat treatment;
A method for manufacturing a semiconductor device, comprising:
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Publication number Priority date Publication date Assignee Title
WO2011083524A1 (en) * 2010-01-05 2011-07-14 パナソニック株式会社 Semiconductor device, and method for producing same
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011083524A1 (en) * 2010-01-05 2011-07-14 パナソニック株式会社 Semiconductor device, and method for producing same
JP2011142119A (en) * 2010-01-05 2011-07-21 Panasonic Corp Semiconductor device and method of manufacturing the same
CN102656677A (en) * 2010-01-05 2012-09-05 松下电器产业株式会社 Semiconductor device, and method for producing same
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JP2016051741A (en) * 2014-08-28 2016-04-11 ルネサスエレクトロニクス株式会社 Semiconductor device manufacturing method
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