JP2008205454A - Selective epitaxy process control - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for selectively and epitaxially growing a substance containing silicon on the surface of a substrate contained in a process chamber. <P>SOLUTION: In one or more embodiments, pressure in the process chamber is decreased when the substance is deposited on the substrate and the pressure is increased when the substance is etched off from the substrate. In the embodiments, process gas flows into the process chamber through a first zone and a second zone so that a desired ratio of a gas flow rate through the first zone to a gas flow rate through the second zone is achieved. In one or more embodiments, the first zone denotes a radially inner zone and the second zone denotes a radially outer zone wherein a ratio of inner zone gas flow rate to an outer zone gas flow rate during the deposition is smaller than that during the etching. In one or more embodiments, the selective epitaxy process includes a step of repeating, until an epitaxial layer grows to a desired thickness, a cycle composed of: the deposition, an etching process after the deposition, and a desired purge cycle. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

Related applications

  [0001] This application claims the benefit of US Patent Application No. 11 / 669,550, filed January 31, 2007, the disclosure of which is incorporated herein in its entirety.

  [0002] Embodiments of the present invention generally relate to the field of electronic manufacturing processes and devices, and more particularly to methods of depositing silicon-containing films while forming electronic devices.

background

  [0003] As smaller transistors are manufactured, ultra-shallow source / drain junctions become a manufacturing challenge. In general, CMOS (complementary metal oxide semiconductor) devices less than 100 nm require junction depths less than 30 nm. Selective epitaxial deposition is often used to form an epilayer of a silicon-containing material (eg, Si, SiGe, SiC) at the junction. In general, selective epitaxial deposition allows the growth of an epitaxial layer ("epi layer") with a silicon moat that does not grow in the dielectric region. Selective epitaxy can be used to fabricate features in semiconductor devices such as high source / drain, source / drain extensions, contact plugs or base layer deposition of bipolar devices.

  [0004] In general, selective epitaxy processes require a deposition reaction and an etching reaction. The deposition reaction and the etching reaction are performed simultaneously at relatively different reaction rates with respect to the epitaxial layer and the polycrystalline layer. During the deposition process, an epitaxial layer is formed on the single crystal surface, and the polycrystalline layer is deposited on at least a second layer, such as an existing polycrystalline layer and / or an amorphous layer. However, the deposited polycrystalline layer is generally etched at a faster rate than the epitaxial layer. Therefore, by changing the concentration of the etching gas, the net selection process deposits epitaxial material and limits or does not deposit polycrystalline material. For example, an epitaxial layer of silicon-containing material can be formed on a single crystal silicon surface by a selective epitaxial process and is not deposited on a spacer.

  [0005] Selective epitaxial deposition of silicon-containing materials is between the formation of high source / drain features and source / drain extension features, for example, during the formation of silicon-containing MOSFET (metal oxide semiconductor field effect transistor) devices. It has become a useful technology. The source / drain extension feature etches the silicon surface to create a recessed source / drain feature, and then fills the etched surface with a selectively grown epi layer, such as silicon germanium (SiGe) material. Manufactured by. Selective epitaxy allows near complete dopant activation with in situ doping, thus eliminating the post-anneal process. Therefore, the junction depth can be accurately defined by silicon etching and selective epitaxy. On the other hand, an ultra-shallow source / drain junction necessarily results in an increase in series resistance. Also, junction consumption during silicide formation further increases the series resistance. In order to compensate for junction consumption, the high source / drain grows epitaxially and selectively on the junction. Typically, the high source / drain layer is undoped silicon.

  [0006] However, current selective epitaxy processes have several drawbacks. In order to maintain selectivity during current epitaxial processes, not only the chemical concentration of the precursors but also the reaction temperature must be adjusted and adjusted throughout the deposition process. If not enough silicon precursor is added, the etch reaction becomes dominant and the overall process is slowed down. Also, harmful over-etching of the substrate features occurs. If not enough etch precursor is added, the deposition reaction predominates to reduce the selectivity to form single and polycrystalline materials across the substrate surface. Also, current selective epitaxy processes usually require high reaction temperatures, such as above 800 ° C. and above 1000 ° C. Such high temperatures are undesirable during the manufacturing process due to thermal issues and possible uncontrolled nitridation reactions to the substrate surface. Further, the process in the conventional method of simultaneously depositing and etching at temperatures below about 800 ° C. results in unacceptable low growth rates.

[0007] Therefore, there is a need for a method of selectively and epitaxially depositing silicon compounds or silicon-containing compounds. It would be desirable to provide a method for depositing such compounds with the desired dopant. Furthermore, methods for forming silicon-containing compounds having various element concentrations while having a high deposition rate and maintaining a process temperature of about 800 ° C. or less must be versatile.
Overview
[0008] According to one embodiment, a method for selectively and epitaxially forming a silicon-containing material on a substrate surface comprises:
a) placing a substrate comprising a single crystal surface and at least a dielectric surface into a process chamber, said process chamber comprising a first zone and a second zone;
b) exposing the substrate to a silicon-containing deposition gas and maintaining the process chamber pressure below about 50 Torr to form an epitaxial layer on the single crystal surface and a second material on the dielectric surface;
c) subsequently stopping the flow of the deposition gas to the process chamber, increasing the pressure of the process chamber, exposing the substrate to the etching gas, maintaining a relatively high etching gas partial pressure and etching the second material. When;
d) subsequently stopping the flow of etching gas to the process chamber and flowing the purge gas flow to the process chamber;
e) repeating steps b), c) and d) at least once in sequence;
including.

  [0009] In one embodiment, the method further includes a step of controlling the gas flow to the first zone and the second zone to obtain a ratio of the first zone gas flow to the second zone gas flow; ) And step c), changing the ratio of the first zone gas flow and the second zone gas flow so that the ratio is different. In certain embodiments, the first zone includes an inner radial zone, the second zone includes an outer radial zone, and the gas is a ratio of an inner zone gas flow to an outer zone gas flow (I / O) to the process chamber. ) And is flowed in a manner that maintains the I / O below about 1 while exposing the substrate to the deposition gas and maintaining the I / O above about 1 while exposing the substrate to the etching gas. According to certain embodiments, little etching gas flows into the process chamber and deposition gas flows into the process chamber. In one or more embodiments, the I / O during exposure of the substrate to the deposition gas is about 0.2 to 1.0, and the I / O during exposure of the substrate to the etching gas is greater than about 1.0, Less than about 6.0.

  [0010] According to certain embodiments, the pressure in the chamber during exposure to the etching gas is at least about twice the chamber pressure during exposure of the substrate to the deposition gas. In one or more embodiments, the pressure in the chamber during exposure to the etching gas is about 2 to about 10 times the pressure in the process chamber during exposure of the substrate to the deposition gas. According to one or more embodiments, the temperature during the process is maintained below about 800 ° C., for example, below about 750 ° C. throughout the process.

  [0011] In another embodiment, a method for selectively and epitaxially forming a silicon-containing material on a substrate surface comprises placing a substrate comprising a single crystal surface and at least a dielectric surface in a process chamber. The step wherein the process chamber includes a first gas flow zone and a second gas flow zone; and a silicon-containing deposition gas is flowed into the first pressure chamber and the second zone into the first pressure process chamber and less than one Obtaining a deposition gas flow ratio of the first zone to the second zone; and subsequently stopping the deposition gas flow to the process chamber, increasing the pressure of the process chamber to the second pressure, Flowing an inner radial zone and an outer radial zone of the process chamber at an etching gas flow ratio of the one zone gas flow to the second zone gas flow; Stopping the etching gas to the process chamber and flowing a purge gas to the process chamber; and flowing a deposition gas, flowing an etching gas, and flowing a purge gas until a silicon-containing material is formed to a desired thickness. Repeating at least once. In one or more embodiments, an increase in pressure during etching increases the substrate temperature and decreases the pressure during purging, resulting in a decrease in substrate temperature.

  [0012] In one embodiment, the second pressure is at least twice the first pressure. In certain embodiments, the second pressure is about 5 to 10 times the first pressure. According to an embodiment, the gas flow ratio between the first zone and the second zone during the flow of the deposition gas is about 0.2 to 1.0. In one or more embodiments, the gas flow ratio between the first zone and the second zone during the etching gas flow is greater than about 1.0 and less than about 6.0.

  [0013] In another embodiment, a method for selectively and epitaxially forming a silicon-containing material on a substrate surface comprises placing a substrate comprising a single crystal surface and at least one dielectric surface in a process chamber. Performing the deposition step including flowing a silicon-containing gas into the process chamber where the process chamber includes a first gas flow zone and a second gas flow zone; and an etching gas is not flowed into the process chamber; Performing an etching step that includes flowing an etching gas to a process chamber in which the contained gas is not flowed into the process chamber; performing a purging step in which a purge gas is flowed, wherein the single process cycle includes a deposition step; Etching step and purging step Thus, the process cycle is repeated at least once, and gas is flowed into the first zone and the second zone, and the process chamber pressure, the first zone and the first zone between the deposition step, the etching step, and the purge step, respectively The gas flow ratio between the two zones is obtained, and at least one of the process chamber pressures or the gas flow ratio is different in the deposition step and the etching step. In one embodiment, the process pressure is lower during deposition than during etching. In certain embodiments, lower pressure in the process chamber will result in lower substrate temperature.

  [0014] In one embodiment, the gas flow ratio between the first zone and the second zone is smaller during the deposition step than during the etching step. In one embodiment, the first zone includes an internal radial zone of the process chamber and the second zone includes an external radial zone of the chamber. In certain embodiments, the pressure during etching is at least twice the pressure during deposition. In one or more embodiments, the process is performed at a temperature less than about 800 ° C.

  [0015] In order that the above features of the present invention may be understood in detail, a more specific description of the invention briefly summarized above may be referred to by the embodiments, some of which are illustrated in the accompanying drawings. It is shown. It should be noted, however, that the accompanying drawings show only typical embodiments of the invention and are therefore not considered to limit the scope of the invention, and that the invention may allow other equally effective embodiments. Should.

[0019] Before describing some exemplary embodiments of the present invention, it is to be understood that the present invention is not limited to the details of construction or process steps set forth in the following description. The invention is capable of other embodiments and can be practiced in various ways.
Detailed description
[0020] Embodiments of the present invention generally provide a process for selectively and epitaxially depositing a silicon-containing material on a single crystal surface of a substrate in the manufacture of electronic devices. Exposing a patterned substrate containing a single crystal surface (eg, silicon or silicon germanium) and at least a second surface, an amorphous surface and / or a polycrystalline surface (eg, oxide or nitride) to an epitaxial process, An epitaxial layer is formed on the single crystal surface with or without forming a limited polycrystalline layer on the two surfaces. According to one or more embodiments, the epitaxial process is also referred to as an alternating gas supply (AGS) process, where the epitaxial process repeats a cycle of deposition and etching processes until it grows to the desired thickness of the epitaxial layer. including. The AGS process is described in co-assigned co-assigned US patent application Ser. No. 11 / 001,774, published as US Patent Application Publication No. 2006/0115934, referred to as Selective Epitaxy Process With Alternate Gas Supply. According to one or more embodiments, the alternating gas supply process may include repeating a cycle of a deposition process, an etching process, and a purge process until the epitaxial layer is grown to a desired thickness.

  [0021] In one or more embodiments, the deposition process includes exposing the substrate surface to a deposition gas containing at least a silicon source. Typically, the deposition gas also contains a carrier gas. In one or more embodiments, the deposition gas may include a dopant source as well as a germanium source or a carbon source. During the deposition process, an epitaxial layer is formed on the single crystal surface of the substrate and a polycrystalline layer is formed on a second surface, such as an amorphous and / or polycrystalline surface. Subsequently, the substrate is exposed to an etching gas. The etching gas includes a carrier gas and an etching agent, such as chlorine gas or hydrogen chloride. The etching gas removes silicon-containing material deposited during the deposition process. According to certain embodiments, the polycrystalline layer is removed at a faster rate than the epitaxial layer during the etching process. Therefore, the net result of the deposition and etching process is to form a silicon-containing material grown epitaxially on the single crystal surface while minimizing the growth of the polycrystalline silicon-containing material on the second surface, if any. To do. In one or more embodiments, the pressure in the processing chamber is adjusted between the deposition and etching steps such that the pressure is higher during etching than during deposition. According to one or more embodiments, an increase in pressure results in an increase in substrate temperature. In other embodiments, the gas distribution to a zone of the processing chamber may be coordinated and different between the deposition of the etching step and the deposition step. The cycle of the deposition process and the etching process can be repeated as required to obtain the desired thickness of the silicon-containing material. Silicon-containing materials that can be deposited according to embodiments of the present invention include silicon, silicon germanium, silicon carbon, silicon germanium carbon, and dopant variants thereof.

  [0022] In one embodiment of the process, the use of chlorine gas as an etchant reduces the overall process temperature to less than about 800 ° C. In general, the deposition process may be performed at a lower temperature than the etching reaction because it often requires high temperatures for the etchant to be activated. For example, silane is pyrolyzed to deposit silicon at about 500 ° C. or lower, and hydrogen chloride requires an activation temperature of about 700 ° C. or higher for hydrogen chloride to act as an effective etchant. Therefore, if hydrogen chloride is used in the process, the overall process temperature is determined by the higher temperature required to activate the etchant. Chlorine contributes to the overall process by lowering the overall process temperature required. Chlorine can be activated at temperatures as low as about 500 ° C. Therefore, by incorporating chlorine into the process as an etchant, the overall process temperature can be significantly reduced over processes using hydrogen chloride as an etchant, for example, 200 ° C. to 300 ° C. Chlorine also etches silicon-containing materials faster than hydrogen chloride. Therefore, the chlorine etchant increases the overall speed of the process.

  [0023] The carrier gas can be any suitable inert gas or hydrogen. Although noble gases such as argon or helium can be used as the inert carrier gas, according to certain embodiments, nitrogen is an economically suitable inert carrier gas. Nitrogen is usually less expensive than hydrogen, argon or helium. One drawback arising from using nitrogen as the carrier gas is the nitridation of materials on the substrate during the deposition process. However, high temperatures exceeding 800 ° C. are required to activate nitrogen in such a manner. Thus, in one or more embodiments, nitrogen can be used as an inert carrier gas in processes performed at temperatures below the nitrogen activation threshold. The combined effect of using chlorine as the etchant and nitrogen as the carrier gas significantly increases the overall process speed.

  [0024] Throughout this application, the term "silicon-containing" material, compound, film or layer should be construed to include a composition containing at least silicon, germanium, carbon, boron, arsenic, phosphorus, gallium And / or aluminum. Other elements such as metals, halogens or hydrogen may also be incorporated into silicon-containing materials, compounds, films or layers, usually in parts per million (ppm). The compound or alloy of a silicon-containing material may be represented by abbreviations such as Si for silicon, silicon germanium for SiGe, silicon carbon for SiC, and silicon germanium carbon for SiGeC. The abbreviations do not represent chemical formulas according to stoichiometry, nor do they represent certain oxidation / reduction states of silicon-containing materials.

  [0025] According to one or more embodiments, the AGS process is modified to alter different nucleation rates and mechanisms between the silicon crystal substrate and the dielectric film. According to embodiments of the present invention, independent optimization of the film growth reaction between the deposition reaction and the film etching reaction and a series of alternating deposition and etching cycles to obtain a high selective growth rate without losing selectivity. Used for. Although the present invention should not be limited by any particular theory, in certain embodiments, silicon nucleation on a dielectric surface may be performed during deposition and etching of a cycle with deposition gas, etching gas, gas flow distribution, substrate temperature, and By changing one or more of the reactor pressures, a selective process with a high deposition rate can be obtained that is suppressed below the critical size. In individual embodiments, during the film deposition step, the reactor pressure is relatively low, for example, maintained by fully opening the pressure control valve, and the silicon-containing source does not introduce any etching gas into the process chamber. Is introduced into the reactor. It is understood that the pressure can be reduced in the chamber by other means. According to one or more embodiments, the low pressure deposition cycle maintains a low deposition partial pressure and reduces the temperature of the wafer by thermal conduction, thus suppressing excessive film nucleation on the dielectric film. .

  [0026] In one or more embodiments, the reactor pressure during the film etching process is increased, for example, by fully closing the pressure control valve, and an etching gas, eg, HCl, is introduced into the reactor, but is being etched. The deposition gas is not flowed. According to embodiments of the present invention, this high pressure etch cycle provides a high etchant partial pressure and raises the temperature of the wafer by heat conduction, thus increasing film etch efficiency. By optimizing the cycle time of the deposition and etching steps, it is possible to maintain a balance between epitaxial growth on the silicon substrate and the absence of nucleation on the dielectric film without loss of selectivity. High selective growth rate can be obtained.

  [0027] An exemplary embodiment of an epitaxial process for depositing a silicon-containing layer typically includes loading a patterned substrate into a process chamber and adjusting the conditions in the process chamber to a desired temperature. including. According to one or more embodiments, the process chamber pressure is kept relatively low, for example, less than about 50 Torr. In individual embodiments, the pressure drops to about 20 Torr or less. While the pressure is kept relatively low, the deposition process is initiated by flowing a deposition gas, such as a silicon source gas, while forming a polycrystalline layer on the amorphous and / or polycrystalline surface of the substrate. An epitaxial layer is formed on the single crystal surface.

  [0028] According to one or more embodiments, during deposition, the flow distribution within the process chamber is shifted from a second zone of the process chamber, eg, an outer radial zone, to a first zone, eg, an inner radial zone. A larger amount of deposition gas is maintained to flow. The inner and outer radial zones of the process chamber are selected to match the diameter of the processed substrate. However, it is understood that the flow distribution of gas into the process chamber can be varied in other ways. In an exemplary embodiment, the internal radial zone may be a coaxial central zone of the substrate having a diameter about half that of the substrate being processed. The outer radial zone then comprises a region surrounding the inner radial zone. As an example, in a process chamber for processing a circular substrate having a diameter of 300 mm, the internal zone may be a 75 mm central region of the substrate.

[0029] Referring to FIG. 1, a schematic plan view of a process chamber 100 containing a substrate 110 is shown. The process chamber includes a first or inner radial zone 112 and a second or outer radial zone 114 containing a substrate 110. The gas source 120 is in fluid communication with the inner zone gas conduit 122 and the outer zone gas conduits 124, 126. The gas conduits 122, 124, 126 may be connected to a distribution port 130 that is in fluid communication with the chamber. The distribution port 130 may be in communication with one or more internal zone ports 132 and two or more external zone ports 134, 136. Inner zone metering valve 142 and outer zone metering valve 144 control the amount of process gas flowing to inner radial zone 112 and outer radial zone 114, respectively. Metering valves 142 and 144 may be adjusted to reduce the diameter of inner zone gas conduit 122 and outer zone gas conduit 124. By reducing the diameter of the gas conduit, the amount of gas flowing into the zone can be reduced, and by increasing the diameter of the gas conduit, the amount of gas flowing into the zone can be increased. Such gas distribution devices are available from EpiCentura®, which includes an Accusett ^™ metering valve available from Applied Materials, Santa Clara, California. It will be appreciated that other methods of reducing the flow to each zone can be used. For example, instead of a metering valve, the gas flow may be controlled by a mass flow controller or other suitable flow controller that regulates the amount of gas flowing into the conduit. Furthermore, the flow distribution within the chamber can be varied in ways other than providing flow in the inner and outer radial zones.

  [0030] The ratio of the amount of gas flowing in the inner radial zone 112 to the amount of gas flowing in the outer radial zone 114 can be expressed as I / O, where I is the amount of gas flowing in the inner radial zone 112. Where O is the amount of gas flowing into the outer radial zone 114. In one or more embodiments, the I / O ratio is less than about 1 during deposition. According to certain embodiments, the I / O ratio is from about 0.2 to 1.0, and in individual embodiments from about 0.4 to 0.8.

  [0031] The deposition process is then terminated and, according to one or more embodiments, the pressure in the process chamber is ramped or increased to a higher pressure, for example, greater than about 50 Torr. According to one or more embodiments, the pressure can be ramped to, for example, about 100 Torr or more, about 300 Torr. According to certain embodiments, increasing the pressure in the process chamber results in an increase in substrate temperature without changing the temperature set point of the substrate processing apparatus. In other words, the temperature of the substrate can be changed without changing the power supplied to the substrate heating element, which is typically a heating lamp. Etching gas is then flowed into the process chamber to the inner radial zone and the outer radial zone. According to one or more embodiments, the deposition gas is not flowed and the etching gas is flowed to the process chamber. In one embodiment of the present invention, the flow distribution of the inner radial zone and the outer radial zone is adjusted so that the inner radial zone is larger than the flow to the outer radial zone. According to one or more embodiments, the I / O ratio during etching is greater than about 1, for example, about 1.0 to 6.0, and more specifically about 1.0 to 3.0. Preferably, the polycrystalline layer is etched at a faster rate than the epitaxial layer. The etching step minimizes or completely removes the polycrystalline layer while removing only the epitaxial layer boundaries. The etching process is then terminated. The thickness of the epitaxial layer and the polycrystalline layer is then determined by measuring the thickness. If the predetermined thickness of the epitaxial layer or polycrystalline layer is achieved, the epitaxial process is terminated. However, if the predetermined thickness is not achieved, the deposition and etching steps are repeated as a cycle until the predetermined thickness is achieved.

  [0032] The sequence of deposition and etching steps may further include purging the process chamber. After purging, the thickness of the epitaxial layer can be determined, and if necessary, the sequence of deposition, etching, and optionally purging steps may be repeated. During the purge step, the pressure in the process chamber drops below the pressure maintained in the chamber during etching, and according to some embodiments, the pressure may be reduced to the same pressure as during deposition. . According to one or more embodiments, a decrease in pressure within the process chamber causes a rapid decrease in substrate temperature. Thus, the substrate temperature can be controlled by changing the temperature in the process chamber without supplying additional power to the process chamber heating lamp. Further, during purging, the I / O ratio can be adjusted so that the amount of purge gas increases from the inner radial zone to the outer radial zone.

  [0033] Exemplary details of the process sequence are further described herein. The substrate loaded into the process chamber is typically a patterned substrate. A patterned substrate is a substrate that includes electronic features formed in or on the substrate surface. The patterned substrate typically contains a single crystal surface and at least one second surface that is non-single crystal, such as a polycrystalline or amorphous surface. A single crystal surface typically includes a bare crystal substrate or a deposited single crystal layer made of a material such as silicon, silicon germanium or silicon carbon. Polycrystalline or amorphous surfaces may include dielectric materials such as oxide, nitride, specifically silicon oxide or silicon nitride, as well as amorphous silicon surfaces.

[0034] The epitaxial process begins by adjusting the process chamber containing the patterned substrate to a predetermined temperature and pressure during the deposition steps described above. The temperature is adjusted to the specific process being performed. In previous processes, the process chamber is maintained at a pressure, temperature and flow distribution that is consistent throughout the epitaxial process. However, according to embodiments of the present invention, the temperature may vary between the deposition step, the etching step, and the purge step. In one embodiment, the temperature increases during the etching step. During deposition, the process chamber is maintained at a temperature in the range of about 250 ° C to about 1000 ° C, specifically 500 ° C to about 800 ° C, more specifically about 550 ° C to about 750 ° C. The appropriate temperature for performing the epitaxial process may depend on the specific precursor used to deposit and / or etch the silicon-containing material. In one example, chlorine (Cl ₂ ) gas works exceptionally well as an etchant for silicon-containing materials at lower temperatures than processes using more common etchants. Thus, in one embodiment, a suitable temperature for preheating the process chamber is about 750 ° C. or less, specifically about 650 ° C. or less, more specifically about 550 ° C. or less. During deposition, the process chamber is typically maintained at a pressure of about 1 Torr to about 50 Torr.

  [0035] During the deposition process, the patterned substrate is exposed to a deposition gas to form an epitaxial layer on the single crystal surface while forming a polycrystalline layer on the second surface. The substrate is exposed to the deposition gas for about 0.5 seconds to about 30 seconds, such as from about 1 second to about 20 seconds, and more particularly from about 5 seconds to about 10 seconds. The individual exposure time of the deposition process is determined in relation to the specific precursor used in the process and the temperature, as well as the time of exposure during the etching process. In general, the substrate is exposed to the deposition gas long enough to form the maximum thickness of the epitaxial layer while forming the minimum thickness of the polycrystalline layer that can be easily etched.

  [0036] The deposition gas contains at least a silicon source and a carrier gas, and may contain at least one second element source such as a germanium source and / or a carbon source. Also, the deposition gas can further include a dopant compound to provide a source of dopant, such as boron, arsenic, phosphorus, gallium and / or aluminum.

[0037] The silicon source is typically supplied to the process chamber at a flow rate in the range of about 5 seem to about 500 seem, for example, about 10 seem to about 300 seem, more specifically about 50 seem to about 200 seem, for example 50 seem. Silicon sources useful for deposition gases for depositing silicon-containing compounds include silanes, halogenated silanes, and organosilanes. Silicon sources useful for deposition gases for depositing silicon-containing compounds include silanes, halogenated silanes, and organosilanes. Examples of silane include higher silanes having silane (SiH ₄ ) and empirical formula Si _x H _{(2x + 2)} , such as disilane (Si ₂ H ₆ ), trisilane (Si ₃ H ₈ ), tetrasilane (Si ₄ H ₁₀ ), and the like. Can be mentioned. Halogenated silanes include compounds having the empirical formula X ′ _y Si _x H _{(2x + 2-y)} , where X ′ = F, Cl, Br or I, such as hexachlorodisilane (Si ₂ Cl ₆ ), tetrachlorosilane ( SiCl ₄ ), dichlorosilane (Cl ₂ SiH ₂ ) and trichlorosilane (Cl ₃ SiH). Organosilanes include compounds having the empirical formula R _y Si _x H _{(2x + 2-y)} , where R = methyl, ethyl, propyl, butyl, for example, methylsilane ((CH ₃ ) SiH ₃ ), dimethylsilane (( CH _{3) 2} SiH _2), ethylsilane _{((CH 3 CH 2) SiH} 3), disilane _{((CH 3) Si 2 H} 5), dimethyl disilane _{((CH 3) 2 Si 2} H 4) and hexamethyldisilane ((CH ₃ ) ₆ Si ₂ ). Organosilane compounds have been found to be advantageous not only in silicon sources, but also in embodiments in which carbon is incorporated into the deposited silicon-containing compound.

[0038] A silicon source is typically supplied to the process chamber along with a carrier gas. The carrier gas has a flow rate of about 1 slm (standard liters per minute) to about 100 slm, such as about 5 slm to about 75 slm, more specifically about 10 slm to about 50 slm, such as about 25 slm. Carrier gases may include nitrogen (N ₂ ), hydrogen (H ₂ ), argon, helium and combinations thereof. The inert carrier gas can be selected based on the precursor or precursors used and / or the process temperature during the epitaxial process. The carrier gas may be the same for each of the deposition and etching steps. However, some embodiments may use different carrier gases in specific steps. For example, nitrogen can be used as a carrier gas for the silicon source during deposition and the etchant during etching.

  [0039] Nitrogen can be used as a carrier gas in embodiments featuring low temperature (eg, <800 ° C.) processes. Low temperature processes are easier to use in part by the use of chlorine gas in the etching process. Nitrogen remains inert during the low temperature deposition process. Therefore, nitrogen is not incorporated into the deposited silicon-containing material during the low temperature process. Finally, because nitrogen is much cheaper than hydrogen, argon or helium, low temperature processes can economically utilize nitrogen as a carrier gas. Although nitrogen has several advantages, the present invention does not limit the use of nitrogen as a carrier gas, and other suitable carrier gases such as halogens and noble gases can be used.

[0040] The deposition gas may also contain at least one second element source, such as a germanium source and / or a carbon source. A germanium source can be added to the process chamber along with a silicon source and a carrier gas to form a silicon-containing compound such as a silicon germanium material. The germanium source is typically supplied to the process chamber at a flow rate in the range of about 0.1 sccm to about 20 sccm, such as about 0.5 sccm to about 10 sccm, more specifically about 1 ccm to about 5 sccm, such as about 5 sccm. Germanium sources useful for depositing silicon-containing compounds include germane (GeH ₄ ), higher germane and organogermane. Examples of the higher germane include compounds having an empirical formula Ge _x H _{(2x + 2)} , such as digermane (Ge ₂ H ₆ ), trigermane (Ge ₃ H ₈ ), and tetragermane (Ge ₄ H ₁₀ ). Examples of the organogermane include methyl germane ((CH ₃ ) GeH ₃ ), dimethyl germane ((CH ₃ ) ₂ GeH ₂ ), ethyl germane ((CH ₃ CH ₂ ) GeH ₃ ), methyl digermane ((CH ₃ ) Ge ₂ H ₅ ), dimethyl digermane ((CH ₃ ) ₂ Ge ₂ H ₄ ) and hexamethyl digermane ((CH ₃ ) ₆ Ge ₂ ). It has been found that germane and organic germane compounds are advantageous germanium and carbon sources in embodiments while incorporating germanium and carbon into deposited silicon-containing compounds, ie, SiGe and SiGeC compounds. The germanium concentration in the epitaxial layer ranges from about 1 atomic% to about 30 atomic%, for example, about 20%. The germanium concentration may be stepped within the epitaxial layer, preferably stepwise with a germanium concentration higher in the lower portion of the epitaxial layer than in the upper portion of the epitaxial layer.

[0041] Alternatively, a carbon source can be added to the process chamber along with a silicon source and a carrier gas to form a silicon-containing compound, such as a silicon carbon material. The carbon source is typically supplied to the process chamber at a flow rate in the range of about 0.1 sccm to about 20 sccm, such as about 0.5 sccm to about 10 sccm, more specifically 1 sccm to about 5 sccm, such as about 2 sccm. Carbon sources useful for depositing silicon-containing compounds include organosilanes, ethyl, propyl and butyl alkyls, alkenes and alkynes. Examples of such a carbon source include methylsilane (CH ₃ SiH ₃ ), dimethylsilane ((CH ₃ ) ₂ SiH ₂ ), ethylsilane (CH ₃ CH ₂ SiH ₃ ), methane (CH ₄ ), and ethylene (C ₂ H _4). ), Ethyne (C ₂ H ₂ ), propane (C ₃ H ₈ ), propene (C ₃ H ₆ ), butyne (C ₄ H ₆ ) and the like. The carbon concentration of the epitaxial layer ranges from about 200 ppm to about 5 atomic percent, such as from about 1 atomic percent to about 3 atomic percent, such as 1.5 atomic percent. In one embodiment, the carbon concentration may be stepped within the epitaxial layer, and preferably may be stepped at a lower carbon concentration at the beginning of the epitaxial layer than the final portion of the epitaxial layer. Alternatively, both a germanium source and a carbon source can be added to the process chamber during deposition with a silicon source and a carrier gas to form a silicon-containing compound, such as silicon carbon or silicon germanium carbon material.

[0042] The deposition gas used may further include at least one dopant compound to provide an elemental dopant source such as boron, arsenic, phosphorus, gallium or aluminum. The dopant provides a deposited silicon-containing compound with various conductive properties such as directional electron flow in the controlled and desired path required by the electronic device. Silicon-containing compound films are doped with specific dopants to achieve the desired conductive properties. In one example, the silicon-containing compound is doped p-type using, for example, diborane to add boron at a concentration in the range of about 10 ¹⁵ atoms / cm ³ to about 10 ²¹ atoms / cm ³ . In one example, the p-type dopant has a concentration of at least 5 × 10 ¹⁹ atoms / cm ³ . In other examples, the p-type dopant ranges from about 1 × 10 ²⁰ atoms / cm ³ to about 2.5 × 10 ²¹ atoms / cm ³ . In other examples, the silicon-containing compound is doped n-type using, for example, phosphorus and / or arsenic at a concentration of about 10 ¹⁵ atoms / cm ³ to about 10 ²¹ atoms / cm ³ .

[0043] The dopant source is typically deposited during deposition at a flow rate in the range of about 0.1 sccm to about 20 sccm, such as about 0.5 sccm to about 10 sccm, more particularly about 1 sccm to about 5 sccm, such as about 2 sccm. Supplied to the process chamber. Boron-containing dopants useful as a dopant source include borane and organoborane. Examples of borane include borane, diborane (B ₂ H ₆ ), triborane, tetraborane, and pentaborane. Examples of alkylborane include empirical formula R _x BH _(3-x) , where R = methyl, ethyl, propyl Or compounds having butyl, x = 1, 2 or 3. Examples of the alkyl borane include trimethyl borane ((CH ₃ ) ₃ B), dimethyl borane ((CH ₃ ) ₂ BH), triethyl borane ((CH ₃ CH ₂ ) ₃ B) and diethyl borane ((CH ₃ CH ₂ ) _2. BH). Dopants also include arsine (AsH ₃ ), phosphine (PH ₃ ), and alkyl phosphines, such as the empirical formula R _x PH _(3-x) , where R = methyl, ethyl, propyl or butyl, x = 1, 2, or 3. Examples of the alkylphosphine include trimethylphosphine ((CH ₃ ) ₃ P), dimethylphosphine ((CH ₃ ) ₂ PH), triethylphosphine ((CH ₃ CH ₂ ) ₃ P), and diethylphosphine ((CH ₃ CH ₂ ) _2. PH). Aluminum and gallium dopant sources include empirical formulas R _x MX _(3-x) where M = Al or Ga, R = methyl, ethyl, propyl, butyl, X = Cl or F, x = 0, 1, Examples include alkylated and / or halogenated derivatives as described in 2 or 3. Examples of aluminum and gallium dopant sources include trimethylaluminum (Me ₃ Al), triethylaluminum (Et ₃ Al), dimethylaluminum chloride (Me ₂ AlCl), aluminum chloride (AlCl ₃ ), trimethylgallium (Me ₃ Ga), Examples include trimethyl gallium (Et ₃ Ga), dimethyl gallium chloride (Me ₂ GaCl), and gallium chloride (GaCl ₃ ).

  [0044] After the deposition process is complete, in one example, the process chamber may be flushed with a purge or carrier gas and / or the process chamber may be evacuated by a vacuum pump. The purge process and / or the exhaust process removes excess deposition gas, reaction byproducts and other contaminants. In another example, once the deposition process is complete, the etching process is started immediately without purging or evacuating the process chamber.

  [0045] The etching process removes silicon-containing material from the deposited substrate surface during deposition. The etching process removes both epitaxial or single crystalline material and amorphous or polycrystalline material. If there is a polycrystalline layer deposited on the substrate surface, it is removed at a faster rate than the epitaxial layer. The duration of the etching process is balanced with the duration of the deposition process, resulting in a net deposition of the epitaxial layer selectively formed on the desired area of the substrate. Therefore, the net result of the deposition and etching process is to form a selectively and epitaxially grown silicon-containing material while minimizing any growth of the polycrystalline silicon-containing material.

[0046] During etching, the substrate is exposed to the etching gas for a time ranging from about 10 seconds to about 90 seconds, such as from about 20 seconds to about 60 seconds, more particularly from 30 seconds to about 45 seconds. The etching gas includes at least one etchant and a carrier gas. The etchant is typically supplied to the process chamber at a rate in the range of about 10 sccm to about 700 sccm, such as about 50 sccm to about 500 sccm, and more particularly about 100 sccm to 400 sccm, such as about 200 sccm. Etching agents used for the etching gas include chlorine (Cl ₂ ), hydrogen chloride (HCl), boron trichloride (BCl ₃ ), carbon tetrachloride (CCl ₄ ), chlorine trifluoride (ClF ₃ ), and combinations thereof. It is good to mention a combination.

[0047] The etchant is typically supplied to the process chamber along with a carrier gas. The carrier gas has a flow rate ranging from about 1 slm to about 100 slm, such as from about 5 slm to about 75 slm, more particularly from 10 slm to about 50 slm, such as 25 slm. Carrier gases may include nitrogen (N ₂ ), hydrogen (H ₂ ), argon, helium and combinations thereof. In some embodiments, an inert carrier gas is used, including nitrogen, argon, helium, and combinations thereof. The carrier gas may be selected based on one or more individual precursors and / or temperatures used during the epitaxial process.

  [0048] After completion of the etching process, in one embodiment, the process chamber may be flushed with a purge or carrier gas and / or the process chamber may be evacuated with a vacuum pump. The purge process and / or the exhaust process removes excess deposition gas, reaction byproducts and other contaminants. In another example, once the etching process is complete, the purge process is not used. The pressure in the process chamber may be lowered to less than about 50 Torr, for example, to about 10 Torr between barges, and the gas flow distribution may be adjusted.

  [0049] The thickness of the epitaxial layer or polycrystalline layer can be determined after one or more deposition, etching, and optionally purging cycles. If the predetermined thickness is achieved, the epitaxial process can be terminated. However, if the predetermined thickness is not achieved, the deposition and etching is repeated as a cycle until the desired thickness is achieved. The epitaxial layer is typically grown to have a thickness in the range of about 10 angstroms to about 2000 angstroms, specifically about 100 angstroms to about 1500 angstroms, more specifically 400 angstroms to about 1200 angstroms, for example, about 800 angstroms. . Polycrystalline layers are typically deposited with a thickness in the range of about 500 Angstroms, if any. The desired or predetermined thickness of the epitaxial silicon-containing layer or the polycrystalline silicon-containing layer is specific to the specific manufacturing process. In one example, the epitaxial layer can reach a predetermined thickness, but the polycrystalline layer becomes too thick. The excess polycrystalline layer can be further etched.

  [0050] In one example, source / drain extensions are formed in a MOSFET device, as shown in FIGS. 2A-2E, where a silicon-containing layer is epitaxially and selectively deposited on the surface of the substrate. The FIG. 2A is a diagram showing source / drain regions 232 formed by implanting ions into the surface of the substrate 230. The segments of the source / drain region 232 are bridged by the gate oxide layer 235 and the gate 236 formed on the spacer 234. In order to form the source / drain extension, a portion of the source / drain region 232 is etched and wet cleaned to obtain a recess 238 as shown in FIG. 2B. Etching the gate 236 can be avoided by depositing a hard mask before etching the source / drain 232 portion.

  [0051] FIG. 2C is a diagram illustrating one embodiment of an epitaxial process described herein in which a silicon-containing epitaxial layer 240 and an optional polycrystalline layer 242 are not deposited on a spacer 234 at the same time and Selectively deposited. Polycrystalline layer 242 is formed on gate 236 by adjusting the deposition and etching processes as desired. Alternatively, the polycrystalline layer 242 is continuously etched from the gate 236 as the epitaxial layer 240 is deposited over the source / drain regions 232.

  [0052] As another example, silicon-containing epitaxial layer 240 and polycrystalline layer 242 are SiGe-containing layers having a germanium concentration in the range of about 1 atomic percent to about 50 atomic percent, for example, about 24 atomic percent or less. Multiple layers of SiGe containing layers containing various amounts of silicon and germanium may be stacked to form a silicon containing epitaxial layer 240 with graded elemental concentrations. For example, the first SiGe layer may be deposited at a germanium concentration in the range of about 15 atomic percent to about 25 atomic percent, and the second SiGe layer is deposited at a germanium concentration in the range of about 25 atomic percent to about 35 atomic percent. It is good to be done.

  [0053] In other examples, the silicon-containing epitaxial layer 240 and the polycrystalline layer 242 range from about 200 ppm to about 5 atomic percent, specifically about 3 atomic percent or less, more specifically about 1 atomic percent to about 2 atomic percent. For example, a SiC-containing layer having a carbon concentration of about 1.5 atomic percent. In other embodiments, the silicon-containing epitaxial layer 240 and the polycrystalline silicon layer 242 have a germanium concentration in the range of about 1 atomic percent to about 50 atomic percent, specifically about 24 atomic percent or less, and about 200 ppm to about 5 atomic percent, Specifically, it is a SiGeC-containing layer having a carbon concentration of about 3 atomic% or less, more specifically about 1 atomic% to about 2 atomic%, for example, about 1.5 atomic%.

[0054] Multilayers containing Si, SiGe, SiC, or SiGeC can be deposited in various orders to form graded elemental concentrations within the silicon-containing epitaxial layer 240. The silicon-containing layer is generally about 1 × 10 ¹⁹ atoms / cm ³ to about 2.5 × 10 ²¹ atoms / cm ³ , more specifically about 5 × 10 ¹⁹ atoms / cm ³ to about 2 × 10 ²⁰ atoms / cm. Doped with a dopant (eg, boron, arsenic, phosphorus, gallium or aluminum) having a concentration in the cm ³ range. The dopant added to the individual layers of silicon-containing material forms a graded dopant. For example, the silicon-containing epitaxial layer 240 includes a first SiGe-containing layer having a dopant concentration (eg, boron) in the range of about 5 × 10 ¹⁹ atoms / cm ^{3 to} about 1 × 10 ²⁰ atoms / cm ³ and about 1 × 10 ^20. Formed by deposition of a second SiGe-containing layer having a dopant concentration (eg, boron) in the range of atoms / cm ³ to about 2 × 10 ²⁰ atoms / cm ³ .

  [0055] The carbon incorporated in the SiC-containing layer and the SiGeC-containing layer is generally located at an interstitial site in the crystal lattice immediately after deposition of the silicon-containing layer. The interstitial carbon content is about 10 atomic percent or less, such as about 5 atomic percent or less, more specifically about 1 atomic percent to about 3 atomic percent, such as about 2 atomic percent. The silicon-containing epitaxial layer 240 can be annealed to incorporate at least some interstitial carbon if not all of the substitution sites in the crystal lattice. The annealing process can include spike annealing, laser annealing or thermal annealing such as rapid thermal process (RTP) in a gas atmosphere such as oxygen, nitrogen, hydrogen, argon, helium or combinations thereof. The annealing process can be performed immediately after the silicon-containing layer is deposited or immediately after various other process steps that the substrate can withstand.

[0056] During the next step, FIG. 2D shows a spacer 244, typically a nitride spacer (eg, Si ₃ N ₄ ) deposited on the spacer 234. Spacers 244 are typically deposited in different chambers by CVD or ALD techniques. Therefore, the substrate is removed from the process chamber used to deposit the silicon-containing epitaxial layer 240. During transfer between the two chambers, the substrate is exposed to ambient conditions, such as temperature, pressure, or an atmosphere containing water and oxygen. When depositing spacers 244 or other semiconductor processes (eg, annealing, deposition or implantation), the substrate is exposed to ambient conditions a second time before depositing higher layer 248. In one embodiment, the native oxide is free or minimal (e.g., from an epitaxial layer containing a minimum germanium concentration, rather than from an epitaxial layer formed at a germanium concentration greater than about 5 atomic%). , Less than about 5 atomic percent) of an epitaxial layer (not shown) is deposited on top of the epitaxial layer 240 prior to exposing the substrate to ambient temperature.

  [0057] FIG. 2E illustrates another example in which a higher layer 248 composed of a silicon-containing material is selectively and epitaxially deposited on an epitaxial layer 240 (eg, SiGe doped). It is. During the deposition process, the polycrystalline layer 242 is further grown, deposited or etched on the gate 236.

  [0058] In one embodiment, the higher layer 248 epitaxially deposits silicon that contains little or no germanium or carbon. However, in alternative embodiments, the higher layer still contains germanium and / or carbon. For example, the higher layer 248 may have about 5 atomic percent or less germanium. In other examples, the higher layer 248 may have about 2 atomic percent or less of carbon. The higher layer 248 may be doped with a dopant such as boron, arsenic, phosphorus, aluminum or gallium.

  [0059] Silicon-containing compounds are used in bipolar device manufacturing (eg, base, emitter connection), BiCMOS device manufacturing (eg, base, emitter connection) and CMOS device manufacturing (eg, channel, source / drain, source / drain extension, high Source / drain, substrate, strained silicon, silicon on insulator and contact plug) are used within the scope of process embodiments for depositing silicon-containing layers. Other embodiments of the process teach the growth of silicon-containing layers that can be used for gate, base connection, collector connection, emitter connection, high source / drain and other uses.

  [0060] The process is extremely useful for depositing selective epitaxial silicon-containing layers in the MOSFETs and bipolar transistors shown in FIGS. 3A-3C. FIGS. 3A-3B are epitaxially grown on MOSFET devices. It is a figure which shows the silicon-containing compound which was made. A silicon-containing compound is deposited on the source / drain features of the device. The silicon-containing compound adheres and grows from the underlying layer's crystal lattice and maintains this configuration as the silicon-containing compound is grown to the desired thickness. FIG. 3A illustrates a silicon-containing compound deposited as a recessed source / drain layer, and FIG. 3B illustrates a silicon-containing compound deposited as a recessed source / drain layer and a higher source / drain layer. .

[0061] The source / drain region 312 is formed by ion implantation. In general, substrate 310 is doped n-type and source / drain region 312 is doped p-type. The silicon-containing epitaxial layer 313 is selectively grown directly above the source / drain regions 312 and / or the substrate 310. A silicon-containing epitaxial layer 314 is selectively grown on the silicon-containing layer 313 in accordance with aspects herein. The gate oxide layer 318 bridges the segment's silicon-containing layer 313. In general, the gate oxide layer 318 is composed of silicon dioxide, silicon oxynitride, or hafnium oxide. The spacer 316 partially surrounds the gate oxide layer 318, which is typically an insulating material such as a nitride / oxide stack (eg, Si ₃ N ₄ / SiO ₂ / Si ₃ N ₄ ). The gate layer 322 (eg, polycrystalline silicon) may have a protective layer 319 such as silicon dioxide along vertical sides as in FIG. 3A. Alternatively, the gate layer 322 may have a spacer 316 and an offset layer 320 (eg, Si ₃ N ₄ ) disposed on both sides.

[0062] In another example, FIG. 3C shows a silicon-containing epitaxial layer 334 deposited as the base layer of a bipolar transistor. The silicon-containing epitaxial layer 334 is selectively grown in various embodiments of the present invention. A silicon-containing epitaxial layer 334 is deposited on the n-type collector layer 332 previously deposited on the substrate 330. The transistor further includes an insulating layer 333 (eg, SiO ₂ or Si ₃ N ₄ ), a contact layer 336 (eg, heavily doped polycrystalline Si), an offset layer 338 (Si ₃ N ₄ ), a first 2 insulating layers 340 (SiO ₂ or Si ₃ N ₄ ).

  [0063] Embodiments of the invention teach processes for depositing silicon-containing compounds on various substrates. Substrates for which embodiments of the present invention are useful include crystalline silicon (eg, Si <100> and Si <111>), silicon oxide, silicon germanium, doped or undoped wafers and patterned substrates. Also, but not limited to, semiconductor wafers such as unpatterned wafers. The substrate has various shapes (for example, circular, square, rectangular) and sizes (for example, OD 200 mm, OD 300 mm OD).

  [0064] In one embodiment, the silicon-containing compound deposited by the processes described herein comprises a germanium concentration in the range of about 0 atomic% to about 95 atomic%. In other embodiments, the germanium concentration ranges from about 1 atomic percent to about 30 atomic percent, preferably from about 15 atomic percent to about 30 atomic percent, for example, about 20 atomic percent. The silicon-containing compound also includes a carbon concentration in the range of about 0 atomic percent to about 5 atomic percent. In other embodiments, the carbon concentration is in the range of about 200 ppm to about 3 atomic percent, preferably about 1.5 atomic percent.

[0065] Germanium and / or carbon silicon-containing compound films are manufactured by the various processes of the present invention and may have consistent, scattered or graded elemental concentrations. Graded silicon germanium films are disclosed in U.S. Patent Application No. 10 / 014,466, published as Applied Materials, Inc., U.S. Patent No. 6,770,134 and U.S. Patent Publication No. 200201774827. Which is incorporated herein in its entirety to describe a method of depositing a graded silicon-containing compound film. In one example, a silicon source (eg, SiH ₄ ) and a germanium source (eg, GeH ₄ ) are used to selectively and epitaxially deposit a silicon germanium-containing film. In this example, the ratio of silicon source to germanium source can be varied to provide control of elemental concentrations such as silicon and germanium while growing graded films. In other examples, a silicon source and a carbon source (eg, CH ₃ SiH ₃ ) are used to selectively and epitaxially deposit a silicon carbon-containing film. The ratio of silicon source to carbon source can be varied to control the element concentration while growing a uniform or graded film. In another example, a silicon source, a germanium source, and a carbon source are used to selectively and epitaxially deposit a silicon germanium carbon-containing film. The ratio of silicon source, germanium source and carbon source can be varied independently to control the element concentration while growing a uniform or graded film.

  [0066] MOSFET devices formed by the processes described herein can contain PMOS or NMOS elements. A PMOS element having a p-type channel has holes that participate in channel conduction, and an NMOS element having an n-type channel has electrons that participate in channel conduction. Thus, for example, a silicon-containing material such as SiGe can be deposited in the recessed region to form a PMOS element. In other examples, a silicon-containing film, such as SiC, can be deposited in the recessed area to form an NMOS element. SiGe materials are used in PMOS applications for several reasons. SiGe materials may incorporate more boron than silicon alone, thereby lowering the junction resistance. Further, the SiGe / silicide layer interface on the substrate surface has a lower Schottky barrier than the Si / silicide interface.

  [0067] Furthermore, SiGe epitaxially grown on the top surface of silicon has compressive stress in the film because the lattice constant of SiGe is larger than that of silicon. The compressive stress is shifted laterally to form compressive strain in the PMOS channel and increase hole mobility. For NMOS applications, since the lattice constant of SiC is smaller than silicon, SiC can be used in the recessed region to create tensile stress in the channel. Tensile stress is transferred to the channel, increasing electron mobility. Thus, in one embodiment, the first silicon-containing layer is formed with a first lattice strain value and the second silicon-containing layer is formed with a second lattice strain value. For example, a SiC layer having a thickness of about 50 angstroms to about 200 angstroms is deposited on the substrate surface, and a SiGe layer having a thickness of about 150 angstroms to about 1000 angstroms is successively deposited on the SiC layer. The SiC layer can be grown epitaxially and has less strain than SiGe epitaxially grown on the SiC layer.

  [0068] In the embodiments described herein, the silicon-containing compound film is selectively and epitaxially deposited by a chemical vapor deposition (CVD) process. Chemical vapor deposition processes include atomic layer deposition (ALD) processes and / or atomic layer epitaxy (ALE) processes. Chemical vapor deposition includes plasma assisted CVD (PA-CVD), atomic layer CVD (ALCVD), organometallic or metal organic CVD (OMCVD or MOCVD), laser assisted CVD (LA-CVD), ultraviolet light CVD (UV- This includes the use of many techniques such as CVD), hot wire CVD (HWCVD), reduced pressure CVD (RP-CVD), ultra high vacuum CVD (UHV-CVD) and the like. In one embodiment, the preferred process is to use thermal CVD to epitaxially grow or deposit silicon-containing compounds, but silicon-containing compounds include silicon, SiGe, SiC, SiGeC, and their doped Variations and combinations thereof may be mentioned.

  [0069] The process of the present invention can be performed in equipment known in the ALE, CVD and ALD arts. The apparatus may contain multiple gas lines to maintain the deposition gas and etch gas separated prior to entering the process chamber. Thereafter, the gas contacts the heated substrate on which the silicon-containing compound film is grown. Hardware that can be used to deposit a silicon-containing film includes the EpiCentura.RTM. System and the Poly Gen® system available from Applied Materials, Inc., located in Santa Clara, California. The ALD apparatus was published as U.S. Patent Publication No. 20030079686, filed Dec. 21, 2001, assigned to Applied Materials, and U.S. Patent Application No. 10 / 032,284, entitled "GasDelivery Apparatus and Methods for ALD". And is hereby incorporated by reference in its entirety to describe the apparatus.

  [0070] The present invention is more fully described by the following examples, without limiting the invention in any way.

Example 1
[0071] Selective epitaxy of silicon and SiGe into two types of patterned substrates: a substrate with a recessed structure and a substrate without a recessed structure. Each type of substrate was inserted into an EPICentura RP processing chamber with Accusett ^™ metering valve. The SiGe layer was selectively deposited for use as a “marker layer” for subsequent selective silicon deposition using a conventional coflow process. The process conditions for silicon deposition were as follows: the deposition pressure was 10 torr, silane was flowed at 50 sccm, dichlorosilane was flowed at 15 sccm, and hydrogen carrier gas was flowed at 5 SLM. The I / O ratio defined above was set to 100/250 using a metering valve. Deposition was performed at 750 ° C. for 5 seconds. An etching step was performed. The process chamber pressure was raised to about 100 Torr, HCl etchant was flowed at 650 sccm with 5 SLM hydrogen carrier gas, and the gas was flowed at 760 ° C. for 6.5 seconds with an I / O ratio of 250/100. The process chamber was then purged by reducing the pressure to 10 Torr at 750 ° C. for 10 seconds and flowing hydrogen purge gas at an I / O ratio of 100/250. This sequence of deposition, etching and purging was repeated 17 times.

  [0072] Selective silicon films were successfully grown on a portion of a substrate with low density pattern of recesses at a rate of 74 angstroms / minute with a smooth shape and no facets. Using the same process, a growth rate of 91 angstroms per minute was obtained in a region of the substrate having a high density pattern of recesses. These growth rates and film properties are comparable to results obtained at a temperature of 800 ° C. using conventional methods of flowing an etching gas and a deposition gas simultaneously. By controlling the process parameters, a high growth rate was obtained at a lower process pressure.

Example 2
[0073] The process conditions of Example 1 were repeated on a substrate with a high density of recesses. During deposition, the process chamber pressure was maintained at 5 Torr and during etching the pressure was increased to 70 Torr. During the purge, the pressure was reduced to 5 Torr. The growth rate obtained in this example exceeded 100 angstroms per minute, but examination of the film using a microscope showed a small facet profile.

Example 3
[0074] The process conditions of Example 2 were repeated with a substrate having no concave pattern structure, but in this example, nitrogen was used as the carrier gas and the temperature was lowered to 700 ° C. The resulting growth rate is 35 angstroms / minute, approximately twice the growth rate observed using conventional methods of simultaneously flowing an etch gas and a deposition gas into the process chamber, about 12-15 angstroms / minute.

  [0075] Reference throughout this specification to "one embodiment," "one embodiment," "one or more embodiments," or "embodiments" is specifically described in connection with the embodiments. Meaning any feature, structure, material, or characteristic is included in at least one embodiment of the invention. Thus, appearances of the phrases “in one or more embodiments,” “in an embodiment,” “in an embodiment,” or “in an embodiment” in various places throughout this specification are Does not necessarily imply the same embodiment. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. The order of description of the above methods should not be considered limiting, and the methods can be used with operations described or omitted or added from the order.

  [0076] While the invention herein has been described by specific embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the method and apparatus of the present invention without departing from the spirit and scope of the invention. Thus, it is intended that the present invention include modifications and variations that are within the scope of the appended claims and their equivalents.

FIG. 1 is a schematic plan view of a processing chamber and gas distribution system according to the present invention. FIG. 2A is a schematic diagram showing a manufacturing technique of a source / drain extension device in a MOSFET. FIG. 2B is a schematic diagram showing a technique for manufacturing a source / drain extension device in a MOSFET. FIG. 2C is a schematic diagram showing a manufacturing technique of the source / drain extension device in the MOSFET. FIG. 2D is a schematic diagram showing a technique for manufacturing a source / drain extension device in a MOSFET. FIG. 2E is a schematic diagram showing a manufacturing technique of a source / drain extension device in a MOSFET. FIG. 3A illustrates several devices having silicon-containing layers selectively and epitaxially deposited by applying the embodiments described herein. FIG. 3B illustrates several devices having silicon-containing layers selectively and epitaxially deposited by applying the embodiments described herein. FIG. 3C shows several devices having silicon-containing layers selectively and epitaxially deposited by applying the embodiments described herein.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Process chamber, 110 ... Substrate, 112 ... Inner radial zone, 114 ... Outer radial zone, 120 ... Gas source, 122 ... Inner zone gas conduit, 124, 126 ... Outer zone gas conduit, 130 ... Distribution port, 132 ... inner zone port, 134, 136 ... outer zone port, 142 ... inner zone metering valve, 144 ... outer zone metering valve, 230 ... substrate, 232 ... source / drain region, 234 ... spacer, 235 ... gate oxide layer, 236 ... Gate, 238 ... Recess, 240 ... Epitaxial layer, 242 ... Polycrystalline layer, 244 ... Spacer, 248 ... Higher layer, 310 ... Substrate, 312 ... Source / drain region, 313 ... Epitaxial layer, 314 ... Epitaxial layer, 316 ... Spacers, 318 ... Gate oxide layers 320 ... offset layer, 322 ... gate layer, 330 ... substrate, 333 ... insulating layer, 334 ... epitaxial layer, 336 ... contact layer, 338 ... offset layer, 340 ... second insulation layer.

Claims (20)

A method of selectively and epitaxially forming a silicon-containing material on a substrate surface,
a) placing a substrate comprising a single crystal surface and at least a dielectric surface into a process chamber, said process chamber comprising a first zone and a second zone;
b) exposing the substrate to a silicon-containing deposition gas and maintaining the process chamber pressure below about 50 Torr to form an epitaxial layer on the single crystal surface and a second material on the dielectric surface A step to do;
c) Subsequently, the flow of the deposition gas to the process chamber is stopped, the pressure of the process chamber is increased, the substrate is exposed to an etching gas, and a relatively high etching gas partial pressure is maintained and the second material is removed. Etching step;
d) subsequently stopping the flow of etching gas to the process chamber and flowing purge gas to the process chamber;
e) repeating steps b), c) and d) at least once in sequence;
Including said method.   Controlling the gas flow to the first zone and the second zone to obtain a ratio of the first zone gas flow to the second zone gas flow, so that the ratio is different between step b) and step c) The method of claim 1, further comprising changing the ratio of the first zone gas flow to the second zone gas flow.   The first zone includes an internal radial zone, the second zone includes an external radial zone, and the gas obtains a ratio (I / O) of the internal zone gas flow to the external zone gas flow to the process chamber. 3. The method of claim 2 wherein the I / O is maintained at less than about 1 while the substrate is exposed to the deposition gas and maintained at an I / O of greater than about 1 while the substrate is exposed to the etching gas. The method described in 1.   4. The method of claim 3, wherein little etching gas is flowed into the process chamber and the deposition gas flows into the process chamber.   The I / O during exposure of the substrate to the deposition gas is about 0.2-1.0, and the I / O during exposure of the substrate to the etching gas is greater than about 1.0, about 6 4. The method of claim 3, wherein the method is less than 0.0.   The method of claim 1, wherein increasing the process chamber pressure increases the substrate temperature during exposure to the etching gas, and decreases the chamber pressure during exposure to the purge gas, thereby decreasing the substrate temperature. .   The method of claim 6, wherein the pressure of the process chamber during exposure to the etching gas is about 2 to about 10 times the pressure of the process chamber during exposure of the substrate to the deposition gas.   The method of claim 6, wherein the temperature of the process is maintained below about 800 ° C. during the entire process.   The method of claim 7, wherein the temperature of the process is maintained below about 750 ° C. during the entire process. A method of selectively and epitaxially forming a silicon-containing material on a substrate surface,
Placing a substrate comprising a single crystal surface and at least a dielectric surface into a process chamber, said process chamber comprising a first gas flow zone and a second gas flow zone;
Flowing a silicon-containing deposition gas into the process chamber at a first pressure and into the first zone and the second zone, wherein the deposition gas flow ratio between the first zone and the second zone is less than 1; And said step;
Subsequently, the deposition gas flow to the process chamber is stopped, the pressure of the process chamber is increased to a second pressure, and an etching gas is passed to the inner radial zone and the outer radial zone of the process chamber beyond the first. Flowing at an etching gas flow ratio between the zone gas flow and the second zone gas flow;
Subsequently, stopping the flow of etching gas to the process chamber and flowing the purge gas flow to the process chamber;
Repeating the continuous steps of flowing the deposition gas, the etching gas, and the purge gas at least once until a silicon-containing material having a desired thickness is formed;
Including said method.   The method of claim 10, wherein increasing the process chamber pressure increases the substrate temperature during exposure to the etching gas and decreases the chamber pressure during exposure to the purge gas, thereby decreasing the substrate temperature.   The method of claim 11, wherein the second pressure is about 2-10 times the first pressure.   13. The method of claim 12, wherein a gas flow ratio between the first zone and the second zone is about 0.2 to 1.0 while flowing the deposition gas.   13. The method of claim 12, wherein a gas flow ratio between the first zone and the second zone is greater than about 1.0 and less than about 6.0 while flowing the etching gas. A method of selectively and epitaxially forming a silicon-containing material on a substrate surface,
Placing a substrate comprising a single crystal surface and at least a dielectric surface into a process chamber, said process chamber comprising a first gas flow zone and a second gas flow zone;
Performing a deposition step comprising flowing a silicon-containing gas into the process chamber where no etching gas is flowed into the process chamber;
Performing an etching step comprising flowing an etching gas into the process chamber where no silicon-containing gas is flowed into the process chamber;
Performing a purge step in which a purge gas is flowed, wherein a single process cycle includes a deposition step, an etching step, and a purge step, the process cycle being repeated at least once to pass gas to the first zone and the second zone Flow to obtain a gas flow ratio of the process chamber pressure and the first zone to the second zone during each of the deposition step, the etch step, and the purge step, and at least one of the process chamber pressure and the gas Said step wherein the flow ratio is different between said deposition step and said etching step;
Including said method.   16. The method of claim 15, wherein the pressure in the process chamber is lower during the deposition than during etching, resulting in a lower substrate temperature during deposition than during etching.   The method of claim 16, wherein the gas flow ratio between the first zone and the second zone is smaller during the deposition step than during the etching step.   The method of claim 17, wherein the first zone comprises an inner radial zone of the process chamber and the second zone comprises an outer radial zone of the chamber.   The method of claim 17, wherein the pressure during etching is at least twice the pressure during deposition.   The method of claim 19, wherein the process is performed at a temperature of less than about 800 ° C.

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