JP2007142291A - Semiconductor structure and its growing method - Google Patents

Semiconductor structure and its growing method Download PDF

Info

Publication number
JP2007142291A
JP2007142291A JP2005336419A JP2005336419A JP2007142291A JP 2007142291 A JP2007142291 A JP 2007142291A JP 2005336419 A JP2005336419 A JP 2005336419A JP 2005336419 A JP2005336419 A JP 2005336419A JP 2007142291 A JP2007142291 A JP 2007142291A
Authority
JP
Japan
Prior art keywords
layer
substrate
thickness
sige
composition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005336419A
Other languages
Japanese (ja)
Inventor
Junko Nakatsuru
順子 中津留
Daiki Date
大樹 伊達
Manabu Ikemoto
学 池本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Anelva Corp
Original Assignee
Canon Anelva Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Anelva Corp filed Critical Canon Anelva Corp
Priority to JP2005336419A priority Critical patent/JP2007142291A/en
Publication of JP2007142291A publication Critical patent/JP2007142291A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Recrystallisation Techniques (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor structure which has a high-quality Ge epitaxial layer using a thin buffer layer, and to provide its growing method. <P>SOLUTION: The semiconductor structure has an Si substrate, an SiGe layer of a thickness equal to or smaller than the critical thickness which is formed on it and contains a Ge composition ≥20% and ≤80%, and a Ge epitaxial layer which is formed on the SiGe layer. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、シリコン(Si)基板のような単結晶基板上にゲルマニウム(Ge)のような格子不整合となる結晶層をエピタキシャル成長した構造およびその成長方法に関し、特に、高品質のエピタキシャル結晶層を成長するために結晶層成長の前に基板上に形成するバッファ層の構造およびその成長方法に関する。   The present invention relates to a structure in which a crystal layer having lattice mismatch such as germanium (Ge) is epitaxially grown on a single crystal substrate such as a silicon (Si) substrate, and a growth method thereof. The present invention relates to a structure of a buffer layer formed on a substrate before crystal layer growth for growth and a growth method thereof.

Si基板上にGeエピタキシャル層を成長する技術は、Si基板上にGe光検出器や高電子移動度のデバイス等を形成するために不可欠の技術である。しかし、SiとGeとでは4.2%の格子不整合があるため、Si基板上に直接成長したGeエピタキシャル層には多数の貫通転位が生じるとともに表面粗さも大きいものとなり、上記のデバイスに適用するための品質としては不十分なものであった。   The technique of growing a Ge epitaxial layer on a Si substrate is an indispensable technique for forming a Ge photodetector, a high electron mobility device, or the like on the Si substrate. However, since there is a 4.2% lattice mismatch between Si and Ge, the Ge epitaxial layer grown directly on the Si substrate has a large number of threading dislocations and a large surface roughness. The quality for doing so was insufficient.

このため、貫通転位密度(TDD)が低く且つ平坦な表面を有するGe層を成長するための様々な方法が提案されてきている。 これらの提案では、Siに近い組成からGeに近い組成にいたる傾斜組成をもち且つ内部の歪が十分に緩和された厚いバッファ層をGe層の成長前にSi基板上に成長させる方法が用いられている。また、この厚いバッファ層に化学機械研磨(CMP)を組み合わせた方法も提案されている。   For this reason, various methods for growing a Ge layer having a low threading dislocation density (TDD) and a flat surface have been proposed. In these proposals, a method is used in which a thick buffer layer having a graded composition from a composition close to Si to a composition close to Ge and having sufficiently relaxed internal strain is grown on the Si substrate before the growth of the Ge layer. ing. A method in which this thick buffer layer is combined with chemical mechanical polishing (CMP) has also been proposed.

特許文献1には、Si基板上にGe層を成長するためのバッファ層として、まず厚さ方向に1μmあたり10%Geの率でGe組成を変化させた傾斜組成SiGe層を0%Geから50%Geとなるまで成長し、さらに均一キャップ層を成長した後CMPによって平坦化し、その後さらに同一のGe組成変化率で50%Geから75%Geとなるまで傾斜組成SiGe層を成長し、さらに温度を下げて同一のGe組成変化率で75%Geから92%Geとなるまで傾斜組成SiGe層を成長する技術が開示されている。この方法ではバッファ層を形成するための総成長膜厚は10μm以上におよび、さらに途中でCMP工程を用いる必要がある。   In Patent Document 1, as a buffer layer for growing a Ge layer on a Si substrate, a gradient composition SiGe layer in which the Ge composition is changed at a rate of 10% Ge per μm in the thickness direction is first changed from 0% Ge to 50%. Then, a uniform cap layer is grown and then flattened by CMP. Thereafter, a gradient composition SiGe layer is grown from 50% Ge to 75% Ge at the same Ge composition change rate, and the temperature is further increased. Is a technique for growing a graded composition SiGe layer from 75% Ge to 92% Ge at the same Ge composition change rate. In this method, the total growth film thickness for forming the buffer layer is 10 μm or more, and it is necessary to use a CMP process in the middle.

特許文献2には、Si基板上にZnSe層を成長させる際のバッファ層として、Si基板側から、Ge組成0.9%のSiGeエピタキシャル層を膜厚0.5〜0.8μm、膜厚0.5〜0.8μmのGe組成0.95%のSiGeエピタキシャル層を膜厚0.5〜0.8μm、数μmのGeエピタキシャル層をこの順に成長させた積層構造を用いることが開示されている。さらに、各層を成長するごとに650℃〜800℃のアニール処理を行っている。この方法でも、2層のSiGeエピタキシャル層の成長膜厚は1μm〜1.6μmにおよぶ。   In Patent Document 2, as a buffer layer for growing a ZnSe layer on a Si substrate, a SiGe epitaxial layer having a Ge composition of 0.9% is formed with a film thickness of 0.5 to 0.8 μm and a film thickness of 0 from the Si substrate side. It is disclosed to use a laminated structure in which a SiGe epitaxial layer having a Ge composition of 0.95% with a thickness of 0.5 to 0.8 μm and a Ge epitaxial layer with a thickness of 0.5 to 0.8 μm and several μm are grown in this order. . Furthermore, an annealing process at 650 ° C. to 800 ° C. is performed every time each layer is grown. Even in this method, the growth thickness of the two SiGe epitaxial layers ranges from 1 μm to 1.6 μm.

特許文献1および特許文献2による方法では、μmオーダーの厚いバッファ層を成長するためには長い成長時間が必要であり、生産性を低下させてしまうという問題点があった。さらに、CMP工程などを採用すると、その工程のための設備が必要となり、さらにその工程のための処理時間が必要となるため生産性を低下させるという問題点があった。さらに、このような方法を採用しても、平均表面粗さ(RMS)は数nmまでしか低減されていないという問題もあった。
特許第3535527号公報 特開2005−303246号公報
The methods according to Patent Document 1 and Patent Document 2 have a problem that a long growth time is required to grow a thick buffer layer on the order of μm, and productivity is lowered. Furthermore, when a CMP process or the like is employed, equipment for the process is required, and further, a processing time for the process is required, leading to a problem that productivity is lowered. Furthermore, even if such a method is adopted, there is a problem that the average surface roughness (RMS) is reduced only to several nm.
Japanese Patent No. 3535527 JP 2005-303246 A

本発明の課題は、シリコン(Si)基板のような単結晶基板上にゲルマニウム(Ge)のような格子不整合となる結晶層を高品質に成長する方法において、新たなバッファ層の膜構成および成長方法を提案し、きわめて薄いバッファ層を採用して成長時間を短縮すると共に、貫通転位密度の低減と表面の平坦性を達成しようとするものである。   An object of the present invention is to provide a new buffer layer film structure and a method for growing a crystal layer having lattice mismatch such as germanium (Ge) with high quality on a single crystal substrate such as a silicon (Si) substrate. A growth method is proposed, and an extremely thin buffer layer is employed to shorten the growth time and to achieve a reduction in threading dislocation density and surface flatness.

本発明の目的は、上記の課題に鑑み、薄いバッファ層を採用した高品質のGeエピタキシャル層を有する半導体構造およびその成長方法を提供することにある。 In view of the above problems, an object of the present invention is to provide a semiconductor structure having a high-quality Ge epitaxial layer employing a thin buffer layer and a growth method thereof.

本発明に係る半導体構造およびその成長方法は、上記の目的を達成するため、次のように構成される。   The semiconductor structure and the growth method thereof according to the present invention are configured as follows in order to achieve the above object.

本発明の半導体構造(請求項1に対応)は、Si基板と、その上に形成された臨界膜厚以下の厚さのGe組成が20%以上80%以下のSiGe層と、前記SiGe層上に形成されたGeエピタキシャル層とを有することを特徴として構成される。   The semiconductor structure of the present invention (corresponding to claim 1) includes a Si substrate, a SiGe layer having a Ge composition of 20% or more and 80% or less formed on the Si substrate, and a SiGe layer on the SiGe layer. And a Ge epitaxial layer formed thereon.

また、本発明の半導体構造(請求項2に対応)は、上記の構成において、前記SiGe層の厚さが5nm以上20nm以下の範囲にあることを特徴として構成される。 A semiconductor structure according to the present invention (corresponding to claim 2) is characterized in that, in the above-described configuration, the thickness of the SiGe layer is in the range of 5 nm to 20 nm.

本発明の半導体構造(請求項3に対応)は、Si基板と、その上に形成されたGe組成が20%以上50%以下のSiGe層と、前記SiGe層上に形成されたGeエピタキシャル層とを有し、前記SiGe層の厚さが5nm以上50nm以下の範囲にあることを特徴とする。   The semiconductor structure of the present invention (corresponding to claim 3) includes a Si substrate, a SiGe layer having a Ge composition of 20% or more and 50% or less formed thereon, and a Ge epitaxial layer formed on the SiGe layer. And the thickness of the SiGe layer is in the range of 5 nm to 50 nm.

本発明の成長方法(請求項4に対応)は、Si基板上にGe層を成長する方法であって、前記Si基板上に臨界膜厚以下の厚さにGe組成が20%以上80%以下のSiGe層をエピタキシャル成長する工程と、前記SiGe層上にGe層を形成する工程とを有することを特徴として構成される。
本発明の成長方法(請求項5に対応)は、Si基板上にGe層を成長する方法であって、 前記Si基板上に臨界膜厚以下の厚さにGe組成が20%以上80%以下のSiGe層をエピタキシャル成長する工程と、前記SiGe層上にGe層を形成する工程とを有し、前記SiGe層の厚さが5nm以上20nm以下の範囲にあることを特徴として構成される。
本発明の成長方法(請求項6に対応)は、Si基板上にGe層を成長する方法であって、 前記Si基板上にGe組成が20%以上50%以下のSiGe層をエピタキシャル成長する工程と、 前記SiGe層上にGe層を形成する工程とを有し、前記SiGe層の厚さが5nm以上50nm以下の範囲にあることを特徴とする。
The growth method of the present invention (corresponding to claim 4) is a method of growing a Ge layer on a Si substrate, wherein the Ge composition has a thickness of not more than a critical film thickness on the Si substrate, and the Ge composition is not less than 20% and not more than 80%. A step of epitaxially growing the SiGe layer, and a step of forming a Ge layer on the SiGe layer.
A growth method according to the present invention (corresponding to claim 5) is a method of growing a Ge layer on a Si substrate, wherein the Ge composition has a thickness of not more than a critical film thickness on the Si substrate, and the Ge composition is not less than 20% and not more than 80%. A step of epitaxially growing the SiGe layer and a step of forming a Ge layer on the SiGe layer, wherein the thickness of the SiGe layer is in the range of 5 nm to 20 nm.
The growth method of the present invention (corresponding to claim 6) is a method of growing a Ge layer on a Si substrate, wherein a SiGe layer having a Ge composition of 20% to 50% is epitaxially grown on the Si substrate; Forming a Ge layer on the SiGe layer, wherein the thickness of the SiGe layer is in the range of 5 nm to 50 nm.

本発明によれば次の効果を奏する。本発明によれば、きわめて薄いバッファ層を用いて成長時間を短縮できると共に、表面が平坦で貫通転位が伸びないエピタキシャル層が得られる。   The present invention has the following effects. According to the present invention, an extremely thin buffer layer can be used to shorten the growth time, and an epitaxial layer having a flat surface and no threading dislocations can be obtained.

以下に、本発明の好適な実施形態(実施例)を添付図面に基づいて説明する。   DESCRIPTION OF EMBODIMENTS Preferred embodiments (examples) of the present invention will be described below with reference to the accompanying drawings.

図1は、本発明の一実施例としてSi基板上にGe層をSiGeバッファ層を介してエピタキシャル成長したときの半導体構造の基本的な膜構造を示すものであり、図1において、1はSi基板、2はSiGeバッファ層、3はGeシード層、4はGe層である。   FIG. 1 shows a basic film structure of a semiconductor structure when a Ge layer is epitaxially grown on a Si substrate through a SiGe buffer layer as one embodiment of the present invention. In FIG. 2 is a SiGe buffer layer, 3 is a Ge seed layer, and 4 is a Ge layer.

図1を用いて本発明の第1の実施例の半導体構造の膜構成を説明する。図1において、1はSi(100)基板、2はGe組成が50%で膜厚方向に均一な組成のSiGeバッファ層であり、膜厚は13nmである。3はGeシード層で膜厚30nm、4はGe層で膜厚は1μmである。   The film structure of the semiconductor structure according to the first embodiment of the present invention will be described with reference to FIG. In FIG. 1, 1 is a Si (100) substrate, 2 is a SiGe buffer layer having a Ge composition of 50% and a uniform composition in the film thickness direction, and the film thickness is 13 nm. 3 is a Ge seed layer with a film thickness of 30 nm, and 4 is a Ge layer with a film thickness of 1 μm.

続いて、本発明の第2の実施例として、第1の実施例の半導体構造の成長方法を説明する。
まず、Si(100)基板1はDHF処理により清浄化し、エピタキシャル成長前に真空中で750℃で熱処理を行った。Ge組成50%のSiGeバッファ層2は13nmの厚さに、基板温度は450℃で成長した。Ge層の成長は2段階の成長プロセスを用いた。第1段階でGeシード層を基板温度350℃で30nmの厚さに成長し、続いて第2段階でGe層を基板温度550℃で1μmの厚さに成長した。
Subsequently, as a second embodiment of the present invention, a semiconductor structure growth method of the first embodiment will be described.
First, the Si (100) substrate 1 was cleaned by DHF treatment and heat-treated at 750 ° C. in vacuum before epitaxial growth. The SiGe buffer layer 2 having a Ge composition of 50% was grown to a thickness of 13 nm and a substrate temperature of 450 ° C. The Ge layer was grown using a two-stage growth process. In the first stage, the Ge seed layer was grown to a thickness of 30 nm at a substrate temperature of 350 ° C., and then in the second stage, the Ge layer was grown to a thickness of 1 μm at a substrate temperature of 550 ° C.

第1の比較例として、図1の膜構成で、Ge組成50%のSiGeバッファ層2を膜厚2nmとし、他は第1の実施例と同一の試料を作製した。作製条件もSiGeバッファ層2の膜厚が2nmであることを除いて実施例2の条件と同一とした。 As a first comparative example, the same sample as that of the first example except that the SiGe buffer layer 2 having a Ge composition of 50% and a film thickness of 2 nm was formed in the film configuration of FIG. The production conditions were also the same as those in Example 2 except that the thickness of the SiGe buffer layer 2 was 2 nm.

第2の比較例として、図1の膜構成で、SiGeバッファ層2に替えて膜厚10nmのSiバッファ層を用い、他は第1の実施例と同一の試料を作製した。作製条件は、Siバッファ層の成長温度が成長520℃である点およびGeシード層3の成長温度が370℃であることを除いて第2の実施例と同一とした。   As a second comparative example, the same sample as that of the first embodiment except that a 10 nm-thickness Si buffer layer was used in place of the SiGe buffer layer 2 in the film configuration of FIG. The production conditions were the same as in the second example except that the growth temperature of the Si buffer layer was 520 ° C. and the growth temperature of the Ge seed layer 3 was 370 ° C.

第1および第2の実施例によれば、Ge組成50%のSiGeバッファ層2は島状に凝集することなく全膜厚に亘って層状に成長された。さらに、膜厚13nmのGe組成50%のSiGeバッファ層は、Si基板上にエピタキシャル成長したときの臨界膜厚以下の範囲にあり、ひずみの緩和による貫通転位を生じることなく成長された。したがって、島状凝集の影響によるバッファ層表面の凹凸も、貫通転位の影響によるクロスハッチ構造による凹凸もみられず、成長後のバッファ層2表面の平坦性はきわめて良好であった。なお、ここで臨界膜厚とはSiGeバッファ層の表面に貫通転位が現れない最大の厚さを意味する。 According to the first and second examples, the SiGe buffer layer 2 having a Ge composition of 50% was grown in layers over the entire film thickness without agglomerating into islands. Further, the SiGe buffer layer having a thickness of 13 nm and having a Ge composition of 50% is in a range equal to or less than the critical thickness when epitaxially grown on the Si substrate, and was grown without causing threading dislocations due to strain relaxation. Therefore, the unevenness on the surface of the buffer layer due to the influence of island-like agglomeration and the unevenness due to the cross-hatch structure due to the influence of threading dislocation were not observed, and the flatness of the surface of the buffer layer 2 after growth was very good. Here, the critical film thickness means the maximum thickness at which threading dislocations do not appear on the surface of the SiGe buffer layer.

また第1および第2の実施例によれば、Geシード層3もバッファ層2の上に平坦に成長され、成長直後のGeシード層3の平均表面粗さ(RMS)は1.32nm、さらにGeエピタキシャル層の成長温度である550℃まで昇温した後のGeシード層3の平均表面粗さ(RMS)は0.13nmと平坦度がさらに良好になっていることが認められた。図2AにSiバッファ層を用いた第2の比較例で形成したGeシード層表面の走査電子顕微鏡(SEM)写真を、図2Cに第2の実施例で形成したGeシード層表面の走査電子顕微鏡(SEM)写真を示す。第2の比較例ではRMSは60nmオーダーのピットが見られ、RMSも2.14nmと粗いのに対して、第2の実施例ではピットは見られず、RMSも1.32nmと平坦である。この結果、第1および第2の実施例のGeシード層3上に形成したGeエピタキシャル層4の表面も極めて平坦なものが得られた。 Further, according to the first and second embodiments, the Ge seed layer 3 is also grown flat on the buffer layer 2, and the average surface roughness (RMS) of the Ge seed layer 3 immediately after the growth is 1.32 nm. It was recognized that the average surface roughness (RMS) of the Ge seed layer 3 after raising the temperature to 550 ° C., which is the growth temperature of the Ge epitaxial layer, was 0.13 nm, and the flatness was further improved. FIG. 2A shows a scanning electron microscope (SEM) photograph of the surface of the Ge seed layer formed in the second comparative example using the Si buffer layer, and FIG. 2C shows a scanning electron microscope of the surface of the Ge seed layer formed in the second embodiment. (SEM) A photograph is shown. In the second comparative example, RMS has pits on the order of 60 nm and the RMS is as coarse as 2.14 nm, whereas in the second example, no pit is seen and the RMS is flat at 1.32 nm. As a result, the surface of the Ge epitaxial layer 4 formed on the Ge seed layer 3 of the first and second examples was also extremely flat.

図3A,3Bは第2の比較例の方法で成長した試料の断面TEM写真、図4A,4Bは第2の実施例の方法で成長した試料の断面TEM写真、図5A,5Bは第1の比較例の方法で成長した試料の断面TEM写真である。このように、第1の比較例第2の比較例ともにGeエピタキシャル層内に貫通転位が伸びているが、第2の実施例で成長した方法では転位はバッファ層内に閉じ込められており、Geエピタキシャル層内には貫通転位は伸びていない。   3A and 3B are cross-sectional TEM photographs of the sample grown by the method of the second comparative example, FIGS. 4A and 4B are cross-sectional TEM photographs of the sample grown by the method of the second embodiment, and FIGS. 5A and 5B are the first It is a cross-sectional TEM photograph of the sample grown by the method of the comparative example. Thus, in both the first comparative example and the second comparative example, threading dislocations extend in the Ge epitaxial layer, but in the method grown in the second embodiment, the dislocations are confined in the buffer layer, No threading dislocations extend in the epitaxial layer.

以上述べたように、第1および第2の発明によれば、13nmと薄いバッファ層を用いることで成長時間が短縮されるとともに、高品質のGeエピタキシャル層が得られるという顕著な効果を奏する。   As described above, according to the first and second inventions, the use of a buffer layer as thin as 13 nm shortens the growth time and provides a remarkable effect that a high-quality Ge epitaxial layer can be obtained.

図1を用いて本発明の第3の実施例の半導体構造の膜構成を説明する。図1において、1はSi(100)基板、2はGe組成が膜厚方向に25%で均一なSiGeバッファ層であり、膜厚は20nmである。3はGeシード層で膜厚30nm、4はGe層で膜厚は1μmである。 The film structure of the semiconductor structure of the third embodiment of the present invention will be described with reference to FIG. In FIG. 1, 1 is a Si (100) substrate, 2 is a uniform SiGe buffer layer with a Ge composition of 25% in the film thickness direction, and the film thickness is 20 nm. 3 is a Ge seed layer with a film thickness of 30 nm, and 4 is a Ge layer with a film thickness of 1 μm.

続いて、本発明の第4の実施例として、第3の実施例の半導体構造の成長方法を説明する。
まず、Si(100)基板1はDHF処理により清浄化し、エピタキシャル成長前に真空中で750℃で熱処理を行った。Ge組成25%のSiGeバッファ層2は20nmの厚さに、基板温度は520℃で成長した。Ge層の成長は2段階の成長プロセスを用いた。第1段階でGeシード層を基板温度350℃で30nmの厚さに成長し、続いて第2段階でGe層を基板温度550℃で1μmの厚さに成長した。
Subsequently, as a fourth embodiment of the present invention, a semiconductor structure growth method of the third embodiment will be described.
First, the Si (100) substrate 1 was cleaned by DHF treatment and heat-treated at 750 ° C. in vacuum before epitaxial growth. The SiGe buffer layer 2 having a Ge composition of 25% was grown to a thickness of 20 nm and a substrate temperature of 520 ° C. The Ge layer was grown using a two-stage growth process. In the first stage, the Ge seed layer was grown to a thickness of 30 nm at a substrate temperature of 350 ° C., and then in the second stage, the Ge layer was grown to a thickness of 1 μm at a substrate temperature of 550 ° C.

第3および第4の実施例によれば、Ge組成25%のSiGeバッファ層2は島状に凝集することなく全膜厚に亘って層状に成長された。さらに、膜厚20nmのGe組成25%のSiGeバッファ層は、Si基板上にエピタキシャル成長したときの臨界膜厚以下の範囲にあり、ひずみの緩和による貫通転位を生じることなく成長された。したがって、成長後のバッファ層2表面の平坦性はきわめて良好であった。 According to the third and fourth examples, the SiGe buffer layer 2 having a Ge composition of 25% was grown in layers over the entire film thickness without agglomerating into islands. Furthermore, the SiGe buffer layer having a Ge composition of 25% with a film thickness of 20 nm is in the range below the critical film thickness when epitaxially grown on the Si substrate, and was grown without causing threading dislocations due to strain relaxation. Therefore, the flatness of the surface of the buffer layer 2 after the growth was very good.

また第3および第4の実施例によれば、Geシード層3もバッファ層2の上に平坦に成長され、成長直後のGeシード層3の平均表面粗さ(RMS)は1.52nm、さらにGeエピタキシャル層の成長温度である550℃まで昇温した後のGeシード層3の平均表面粗さ(RMS)は0.15nmと平坦度がさらに良好になっていることが認められた。図2Bに第2の実施例で形成したGeシード層表面の走査電子顕微鏡(SEM)写真を示す。第2の実施例と同様に、本実施例ではピットは見られず、RMSも1.52nmと平坦である。この結果、第3および第4の実施例のGeシード層3上に形成したGeエピタキシャル層4の表面も極めて平坦なものが得られた。また、本実施例でもGeエピタキシャル層への貫通転位の伸びは見られなかった。   Further, according to the third and fourth embodiments, the Ge seed layer 3 is also grown flat on the buffer layer 2, and the average surface roughness (RMS) of the Ge seed layer 3 immediately after the growth is 1.52 nm. It was confirmed that the average surface roughness (RMS) of the Ge seed layer 3 after raising the temperature to 550 ° C., which is the growth temperature of the Ge epitaxial layer, was 0.15 nm and the flatness was further improved. FIG. 2B shows a scanning electron microscope (SEM) photograph of the surface of the Ge seed layer formed in the second example. Similar to the second embodiment, no pits are seen in this embodiment, and the RMS is flat at 1.52 nm. As a result, the surface of the Ge epitaxial layer 4 formed on the Ge seed layer 3 of the third and fourth examples was also extremely flat. Also in this example, no elongation of threading dislocations into the Ge epitaxial layer was observed.

以上述べたように、第3および第4の発明によれば、20nmと薄いバッファ層を用いることで成長時間が短縮されるとともに、高品質のGeエピタキシャル層が得られるという顕著な効果を奏する。 As described above, according to the third and fourth inventions, by using a buffer layer as thin as 20 nm, the growth time is shortened, and a remarkable effect is obtained in that a high-quality Ge epitaxial layer is obtained.

以上の実施例での説明で理解できるように、本発明は、バッファ層膜厚を臨界膜厚以下にすることで貫通転位の影響によるクロスハッチ構造を生じさせず、また、バッファ層のGe組成を80%以下にすることで島状の成長が生じることを抑制するもので、この方法によってGeシード層を成長するバッファ層表面を平坦に維持するものである。Ge組成が80%を超えると島状の成長が生じる可能性がきわめて高くなることが確認されている。また、Ge組成を20%未満にすると、バッファ層上に成長するGeシード層の成長核の密度が低下し表面粗さが増大してしまう。なお、SiGeバッファ層の臨界膜厚はGe組成が80%の場合でも20nmより大きく、膜厚を20nm以下としておけばGe組成が20〜80%の範囲でバッファ層に貫通転位は生じない。また、SiGeバッファ層の臨界膜厚はGe組成が50%の場合でも50nmより大きく、膜厚を50nm以下としておけばGe組成が20〜50%の範囲でバッファ層に貫通転位は生じない。 As can be understood from the description in the above embodiments, the present invention does not cause a cross-hatch structure due to the influence of threading dislocations by setting the buffer layer thickness to a critical thickness or less, and the Ge composition of the buffer layer. By controlling the thickness of the Si seed layer to 80% or less, island-shaped growth is suppressed, and the surface of the buffer layer on which the Ge seed layer is grown is maintained flat by this method. It has been confirmed that if the Ge composition exceeds 80%, the possibility of island-like growth is extremely high. On the other hand, when the Ge composition is less than 20%, the density of the growth nuclei of the Ge seed layer grown on the buffer layer is lowered and the surface roughness is increased. The critical film thickness of the SiGe buffer layer is larger than 20 nm even when the Ge composition is 80%. If the film thickness is 20 nm or less, threading dislocations do not occur in the buffer layer within the range of Ge composition of 20 to 80%. The critical film thickness of the SiGe buffer layer is greater than 50 nm even when the Ge composition is 50%. If the film thickness is 50 nm or less, threading dislocations do not occur in the buffer layer within the range of the Ge composition of 20 to 50%.

さらに、Geシード層およびGeエピタキシャル層を成長したときに、第1から第4の実施例では転位はバッファ層内に閉じ込められるが、第1の比較例の結果から見られるように、バッファ層厚が2nmと特に薄い場合には転位がGe層内に伸びてしまう。発明者の検討によればバッファ層厚は5nm以上必要であった。 Further, when the Ge seed layer and the Ge epitaxial layer are grown, in the first to fourth examples, dislocations are confined in the buffer layer, but as can be seen from the results of the first comparative example, the buffer layer thickness When the thickness is as thin as 2 nm, dislocations extend into the Ge layer. According to the inventors' investigation, the buffer layer thickness is required to be 5 nm or more.

なお、本発明の第1から第4の実施例では、半導体基板としてSi(100)基板を、エピタキシャル層としてGe層を、バッファ層としてSiGe層を用いたがこれらに限定されるものではない。   In the first to fourth embodiments of the present invention, the Si (100) substrate is used as the semiconductor substrate, the Ge layer is used as the epitaxial layer, and the SiGe layer is used as the buffer layer. However, the present invention is not limited to these.

本発明は、シリコン(Si)基板のような単結晶基板上にゲルマニウム(Ge)のような格子不整合となる結晶層を高品質に成長すると共に成長時間の短縮に用いられる。   INDUSTRIAL APPLICABILITY The present invention is used for growing a crystal layer having lattice mismatch such as germanium (Ge) with high quality on a single crystal substrate such as a silicon (Si) substrate and shortening the growth time.

本発明の第1実施例に係る半導体構造の膜構成を示す図である縦断面図である。It is a longitudinal cross-sectional view which is a figure which shows the film | membrane structure of the semiconductor structure based on 1st Example of this invention. 本発明の第1実施例および比較例に係るGeシード層の表面状態を示す図である。It is a figure which shows the surface state of Ge seed layer which concerns on 1st Example of this invention, and a comparative example. 本発明の第1実施例および比較例に係るGeシード層の表面状態を示す図である。It is a figure which shows the surface state of Ge seed layer which concerns on 1st Example of this invention, and a comparative example. 本発明の第1実施例および比較例に係るGeシード層の表面状態を示す図である。It is a figure which shows the surface state of Ge seed layer which concerns on 1st Example of this invention, and a comparative example. 本発明の第2の比較例に係る半導体構造を示す断面TEM写真である。It is a cross-sectional TEM photograph which shows the semiconductor structure which concerns on the 2nd comparative example of this invention. 本発明の第2の比較例に係る半導体構造を示す断面TEM写真である。It is a cross-sectional TEM photograph which shows the semiconductor structure which concerns on the 2nd comparative example of this invention. 本発明の第2の実施例に係る半導体構造を示す断面TEM写真である。It is a cross-sectional TEM photograph which shows the semiconductor structure based on the 2nd Example of this invention. 本発明の第2の実施例に係る半導体構造を示す断面TEM写真である。It is a cross-sectional TEM photograph which shows the semiconductor structure based on the 2nd Example of this invention. 本発明の第2の実施例に係る半導体構造を示す断面TEM写真である。It is a cross-sectional TEM photograph which shows the semiconductor structure based on the 2nd Example of this invention. 本発明の第2の実施例に係る半導体構造を示す断面TEM写真である。It is a cross-sectional TEM photograph which shows the semiconductor structure based on the 2nd Example of this invention.

符号の説明Explanation of symbols

1 Si基板
2 SiGeバッファ層
3 Geシード層
4 Geエピタキシャル層

1 Si substrate 2 SiGe buffer layer 3 Ge seed layer 4 Ge epitaxial layer

Claims (6)

Si基板と、その上に形成された臨界膜厚以下の厚さのGe組成が20%以上80%以下のSiGe層と、前記SiGe層上に形成されたGeエピタキシャル層とを有することを特徴とする半導体構造。   A Si substrate, a SiGe layer having a Ge composition with a thickness less than or equal to a critical film thickness formed on the Si substrate and having a Ge composition of 20% or more and 80% or less, and a Ge epitaxial layer formed on the SiGe layer, Semiconductor structure. 前記SiGe層の厚さが5nm以上20nm以下の範囲にあることを特徴とする請求項1に記載の半導体構造。   2. The semiconductor structure according to claim 1, wherein the thickness of the SiGe layer is in the range of 5 nm to 20 nm. Si基板と、その上に形成されたGe組成が20%以上50%以下のSiGe層と、前記SiGe層上に形成されたGeエピタキシャル層とを有し、前記SiGe層の厚さが5nm以上50nm以下の範囲にあることを特徴とする半導体構造。   It has a Si substrate, a SiGe layer having a Ge composition of 20% or more and 50% or less formed thereon, and a Ge epitaxial layer formed on the SiGe layer, and the thickness of the SiGe layer is 5 nm or more and 50 nm. A semiconductor structure characterized by being in the following range. Si基板上にGe層を成長する方法であって、前記Si基板上に臨界膜厚以下の厚さにGe組成が20%以上80%以下のSiGe層をエピタキシャル成長する工程と、前記SiGe層上にGe層を形成する工程とを有することを特徴とする成長方法。   A method of growing a Ge layer on a Si substrate, the step of epitaxially growing a SiGe layer having a Ge composition of 20% or more and 80% or less on the Si substrate to a thickness of a critical film thickness or less, and on the SiGe layer And a step of forming a Ge layer. 前記SiGe層の厚さが5nm以上20nm以下の範囲にあることを特徴とする請求項4に記載の成長方法。   The growth method according to claim 4, wherein the thickness of the SiGe layer is in the range of 5 nm to 20 nm. Si基板上にGe層を成長する方法であって、 前記Si基板上にGe組成が20%以上50%以下のSiGe層をエピタキシャル成長する工程と、 前記SiGe層上にGe層を形成する工程とを有し、前記SiGe層の厚さが5nm以上50nm以下の範囲にあることを特徴とする成長方法。
A method of growing a Ge layer on a Si substrate, comprising: epitaxially growing a SiGe layer having a Ge composition of 20% to 50% on the Si substrate; and forming a Ge layer on the SiGe layer. And a thickness of the SiGe layer is in the range of 5 nm to 50 nm.
JP2005336419A 2005-11-21 2005-11-21 Semiconductor structure and its growing method Pending JP2007142291A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005336419A JP2007142291A (en) 2005-11-21 2005-11-21 Semiconductor structure and its growing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005336419A JP2007142291A (en) 2005-11-21 2005-11-21 Semiconductor structure and its growing method

Publications (1)

Publication Number Publication Date
JP2007142291A true JP2007142291A (en) 2007-06-07

Family

ID=38204770

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005336419A Pending JP2007142291A (en) 2005-11-21 2005-11-21 Semiconductor structure and its growing method

Country Status (1)

Country Link
JP (1) JP2007142291A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009027163A (en) * 2007-07-11 2009-02-05 Commiss Energ Atom Method for manufacturing semiconductor-on-insulator (soi) substrate for microelectronics and optoelectronics
WO2009075321A1 (en) * 2007-12-13 2009-06-18 Shin-Etsu Chemical Co., Ltd. MULTILAYER SUBSTRATE INCLUDING GaN LAYER, METHOD FOR MANUFACTURING THE MULTILAYER SUBSTRATE INCLUDING GAN LAYER, AND DEVICE
JP2010226082A (en) * 2008-10-02 2010-10-07 Sumitomo Chemical Co Ltd Semiconductor substrate, electronic device, and method of manufacturing the semiconductor substrate
JP2015088756A (en) * 2013-10-31 2015-05-07 三星電子株式会社Samsung Electronics Co.,Ltd. Substrate structure, cmos device including the same, and method of manufacturing the same
JP2015162571A (en) * 2014-02-27 2015-09-07 富士通株式会社 Ge-BASED SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF THE SAME AND OPTICAL INTERCONNECT SYSTEM
US9536950B2 (en) 2014-04-25 2017-01-03 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
KR20190093498A (en) * 2018-02-01 2019-08-09 에이에스엠 아이피 홀딩 비.브이. A method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982638A (en) * 1995-09-14 1997-03-28 Toshiba Corp Semiconductor substrate
JP2002359367A (en) * 2001-05-31 2002-12-13 Sharp Corp Semiconductor substrate, its manufacturing method and semiconductor device
JP3535527B2 (en) * 1997-06-24 2004-06-07 マサチューセッツ インスティテュート オブ テクノロジー Controlling threading dislocations in germanium-on-silicon using graded GeSi layer and planarization
JP2005303246A (en) * 2004-04-14 2005-10-27 Witty Mate Corp METHOD OF GROWING HIGH QUALITY ZnSe EPITAXIAL LAYER ONTO NEW Si SUBSTRATE

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0982638A (en) * 1995-09-14 1997-03-28 Toshiba Corp Semiconductor substrate
JP3535527B2 (en) * 1997-06-24 2004-06-07 マサチューセッツ インスティテュート オブ テクノロジー Controlling threading dislocations in germanium-on-silicon using graded GeSi layer and planarization
JP2002359367A (en) * 2001-05-31 2002-12-13 Sharp Corp Semiconductor substrate, its manufacturing method and semiconductor device
JP2005303246A (en) * 2004-04-14 2005-10-27 Witty Mate Corp METHOD OF GROWING HIGH QUALITY ZnSe EPITAXIAL LAYER ONTO NEW Si SUBSTRATE

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009027163A (en) * 2007-07-11 2009-02-05 Commiss Energ Atom Method for manufacturing semiconductor-on-insulator (soi) substrate for microelectronics and optoelectronics
WO2009075321A1 (en) * 2007-12-13 2009-06-18 Shin-Etsu Chemical Co., Ltd. MULTILAYER SUBSTRATE INCLUDING GaN LAYER, METHOD FOR MANUFACTURING THE MULTILAYER SUBSTRATE INCLUDING GAN LAYER, AND DEVICE
JP2010226082A (en) * 2008-10-02 2010-10-07 Sumitomo Chemical Co Ltd Semiconductor substrate, electronic device, and method of manufacturing the semiconductor substrate
JP2015088756A (en) * 2013-10-31 2015-05-07 三星電子株式会社Samsung Electronics Co.,Ltd. Substrate structure, cmos device including the same, and method of manufacturing the same
JP2015162571A (en) * 2014-02-27 2015-09-07 富士通株式会社 Ge-BASED SEMICONDUCTOR DEVICE, MANUFACTURING METHOD OF THE SAME AND OPTICAL INTERCONNECT SYSTEM
US9536950B2 (en) 2014-04-25 2017-01-03 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
US9825034B2 (en) 2014-04-25 2017-11-21 Samsung Electronics Co., Ltd. Semiconductor device and method of fabricating the same
KR20190093498A (en) * 2018-02-01 2019-08-09 에이에스엠 아이피 홀딩 비.브이. A method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures
KR102689598B1 (en) * 2018-02-01 2024-07-29 에이에스엠 아이피 홀딩 비.브이. A method for depositing a semiconductor structure on a surface of a substrate and related semiconductor structures

Similar Documents

Publication Publication Date Title
EP2133908A1 (en) Method for manufacturing deformation silicon substrate
JP4842094B2 (en) Epitaxial silicon carbide single crystal substrate manufacturing method
JP4826475B2 (en) Manufacturing method of semiconductor wafer
JP2007142291A (en) Semiconductor structure and its growing method
US20130334536A1 (en) SINGLE-CRYSTAL REO BUFFER ON AMORPHOUS SiOx
CN113658848A (en) Method for manufacturing semiconductor substrate, method for manufacturing SOI wafer, and SOI wafer
KR100738766B1 (en) Method for producing semiconductor substrate and method for fabricating field effect transistor
TWI260698B (en) Method for producing semiconductor substrate and method for fabricating field effect transistor, and semiconductor substrate and field effect transistor
JP4449357B2 (en) Method for manufacturing epitaxial wafer for field effect transistor
KR101358541B1 (en) Ⅲ-nitride semiconductor growth substrate, ⅲ-nitride semiconductor epitaxial substrate, ⅲ-nitride semiconductor element, ⅲ-nitride semiconductor freestanding substrate, and method for fabricating these
JP5338559B2 (en) Manufacturing method of silicon epitaxial wafer
JP6796407B2 (en) Manufacturing method of SiC epitaxial wafer
JP2007180285A (en) Process for producing sgoi substrate
JP2005244187A (en) Strained silicon wafer and manufacturing method thereof
JP2006040972A (en) Silicon epitaxial wafer and its manufacturing method
JP2017071525A (en) Method of manufacturing semiconductor laminate
JP2009302140A (en) Silicon epitaxial wafer, and manufacturing method therefor
JP2004349522A (en) Manufacturing method of semiconductor substrate
JP2007036134A (en) Semiconductor wafer and method for manufacturing semiconductor device
JP4557505B2 (en) Manufacturing method of semiconductor substrate
JPS58138034A (en) Manufacture of semiconductor device
JP2006324466A (en) Manufacturing method of semiconductor wafer
TWI221311B (en) Semiconductor substrate field effect transistor, and methods for producing the same
JP2004342818A (en) Method of producing semiconductor substrate
JP2005012196A (en) Method for manufacturing strained silicon substrate wafer

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080630

RD04 Notification of resignation of power of attorney

Effective date: 20110624

Free format text: JAPANESE INTERMEDIATE CODE: A7424

RD03 Notification of appointment of power of attorney

Effective date: 20110628

Free format text: JAPANESE INTERMEDIATE CODE: A7423

A977 Report on retrieval

Effective date: 20110825

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20110830

A521 Written amendment

Effective date: 20111012

Free format text: JAPANESE INTERMEDIATE CODE: A523

A131 Notification of reasons for refusal

Effective date: 20111108

Free format text: JAPANESE INTERMEDIATE CODE: A131

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20111222

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20120221