JP2006313771A - Epitaxial substrate for group iii nitride semiconductor element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an epitaxial substrate for a group III nitride semiconductor element which is suitable to manufacturing of a group III nitride semiconductor light-emitting element having excellent light-emitting efficiency, reverse breakdown voltage characteristic, and electrostatic breakdown voltage characteristic. <P>SOLUTION: The epitaxial substrate for a group III nitride semiconductor element consists of a substrate having a surface roughness (Ra) of not more than 1 nm, and a group III nitride semiconductor layer directly laminated on the substrate. In the epitaxial substrate, the group III nitride semiconductor layer consists of a plurality of layers contacting with each other, and at least one of the plurality of layers is a layer having a transition density of not more than 1×10<SP>7</SP>cm<SP>-2</SP>. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an epitaxial substrate for a group III nitride semiconductor and a group III nitride semiconductor light emitting device using the same.

Conventionally, a group III nitride semiconductor formed on a substrate is a group III nitride semiconductor light emitting device having a pn junction structure such as a light emitting diode (LED) or a laser diode (LD) that emits visible light having a short wavelength. It is used as a functional material for constituting (see, for example, Patent Document 1). For example, when configuring an LED that emits light in the near ultraviolet band, blue band, or green band, aluminum nitride gallium (Al _X Ga _Y N: 0 ≦ X, Y ≦ 1, X + Y = 1) is formed on the substrate. The film is formed to have a thickness of several μm (hereinafter referred to as an underlayer), and improves the crystallinity and facilitates light extraction. Furthermore, it is also used to construct an n-type or p-type cladding layer (see, for example, Patent Document 2). On the other hand, gallium nitride indium (Ga _Y In _Z N: 0 ≦ Y, Z ≦ 1, Y + Z = 1) is used to form a light emitting layer (see, for example, Patent Document 3).

In a conventional group III nitride semiconductor light emitting device, the underlying layer is made of gallium nitride (GaN) formed through a GaN or AlN buffer layer or AlGaN having an intermediate lattice constant between the substrate and the underlying layer. In general, aluminum gallium nitride (Al _X Ga _Y N: 0 ≦ X, Y ≦ 1, X + Y = 1) is formed. In this case, the buffer layer plays a role of relaxing the strain between the substrate and the underlayer, and serves to help terminate the dislocation immediately after the start of the underlayer growth. Thereby, propagation of dislocations to the upper part of the underlayer is suppressed. Furthermore, dislocation propagation to the light emitting layer and distortion due to the lattice constant difference are reduced so that the lattice constant difference with the light emitting layer made of Ga _Y In _Z N (0 ≦ Y, Z ≦ 1, Y + Z = 1) or the like becomes small. Reduced.

However, the dislocation density is as high as about 1 × 10 ⁹ cm ⁻² even in the underlayer in which dislocation propagation is suppressed by the buffer layer, and low dislocation is indispensable for improving the characteristics of the group III nitride semiconductor light-emitting device. . Therefore, the formation conditions of the buffer layer and the formation method of the underlayer have been studied.

  Conventionally, as a method therefor, a process for forming irregularities on the substrate is performed (for example, see Patent Document 4), an insulating film is formed on the substrate (for example, see Patent Document 5), or a laminated layer grown on the substrate. An object is processed (for example, refer to Patent Document 6), an insulating film is formed on the deposit (for example, refer to Patent Document 7), and the shape is used to promote lateral crystal growth and dislocation Attempts have been made to terminate. However, since this method processes the substrate or the deposited layer on the substrate, the patterning process such as insulation film formation, photolithography and etching is complicated, and the finally formed film also corresponds to its shape. There was a dislocation distribution.

  In some cases, a processing method for forming pits before epitaxial growth is used in advance (see, for example, Patent Documents 8 and 9). However, even with this method, the crystal once grown is once taken out from the growth furnace, and after processing the pit formation on the growth film, the layer that exhibits the function of the device such as the light emitting layer is grown again. Was cumbersome.

  As a method of not processing the substrate or the deposited layer, a method of flattening the unevenness generated in the undoped underlayer by growing a P-type doping layer or an n-type doping layer thereon (see, for example, Patent Documents 10 and 11). ), Or a method of temporarily stopping growth to fill the pit (for example, see Patent Document 12), forming a pit in the base layer, filling the pit, changing the dislocation direction, and terminating the dislocation, etc. Has been done.

  On the other hand, with respect to pits generated in group III nitride semiconductors, it is known that pits are formed when impurities are doped at a high concentration in addition to growth conditions such as temperature and pressure. (For example, refer nonpatent literature 1). As a method using this, there is a method of forming pits by doping a considerably high concentration of Si (see, for example, Patent Document 13).

  The present invention utilizes this pit formation due to the addition of impurities, but the group III nitride semiconductor laminate having a low dislocation density is controlled by controlling the type of impurity element to be added, the concentration of the impurity to be added, and the layer structure. Is what you get.

JP 2000-332364 A JP 2003-229645 A Japanese Patent Publication No.55-3834 JP 2000-331947 A JP 2002-16001 A JP 2004-35275 A JP 2002-289527 A JP 2003-124128 A Japanese Patent Laid-Open No. 2002-261027 JP 2000-353821 A JP 2000-357820 A JP 2002-367908 A JP 2004-47764 A Japan Journal of Applied Physics Vol.31 (1992) pp.2883-2888

An object of the present invention is to dispose a dislocation density of 1 × 10 ⁷ cm ⁻² by laminating only a semiconductor layer by using a normal epitaxial growth method on a flat substrate without processing the substrate or the deposited layer on the substrate. It is to provide a group III nitride semiconductor layer having a low dislocation density as follows. Another object of the present invention is to provide a group III nitride semiconductor light emitting device and a lamp excellent in luminous efficiency.

The present invention provides the following inventions.
(1) A substrate having a surface roughness (Ra) of 1 nm or less and a group III nitride semiconductor layer directly laminated on the substrate, the group III nitride semiconductor layer comprising a plurality of layers in contact with each other, An epitaxial substrate for a group III nitride semiconductor device, wherein at least one of the plurality of layers is a layer having a dislocation density of 1 × 10 ⁷ cm ⁻² or less.

(2) At least one set of a plurality of layers of the group III nitride semiconductor layer in contact with each other is a high impurity atom concentration layer and a low impurity atom concentration layer, and the high impurity atom concentration layer exists on the substrate side. An epitaxial substrate for a group III nitride semiconductor device as described.

(3) The epitaxial substrate for a group III nitride semiconductor device according to the above item 2, wherein the high concentration layer of impurity atoms and the low concentration layer of impurity atoms are alternately and periodically present.

(4) The epitaxial substrate for a group III nitride semiconductor device according to the above item 3, wherein the number of cycles is 1 to 10.

(5) The III according to any one of the above items 2 to 4, wherein the impurity is one or a combination of two or more selected from the group consisting of Si, Ge, Sn, S, Se, Mg and Zn. Epitaxial substrate for group nitride semiconductor devices.

(6) The epitaxial substrate for a group III nitride semiconductor device as described in 5 above, wherein the impurity is Ge.

(7) Any one of the above items 2 to 6, wherein pits exist in the range of 1 × 10 ⁵ cm ^{−2 to} 5 × 10 ⁸ cm ⁻² on the surface (surface opposite to the substrate) of the impurity atom high concentration layer. An epitaxial substrate for a group III nitride semiconductor device according to Item.

(8) The epitaxial substrate for a group III nitride semiconductor device according to any one of the above items 2 to 7, wherein the impurity concentration of the high impurity atom concentration layer is 5 × 10 ¹⁷ to 4 × 10 ¹⁹ cm ⁻³ .

(9) The epitaxial substrate for a group III nitride semiconductor device according to any one of the above items 2 to 8, wherein the high impurity atom concentration layer has a thickness of 0.1 to 10 μm.

(10) The group III nitriding according to any one of the above items 2 to 9, wherein the impurity concentration of the low impurity atom concentration layer is lower than the impurity concentration of the high impurity atom concentration layer and is 2 × 10 ¹⁹ cm ⁻³ or less. Epitaxial substrate for semiconductor devices.

(11) The epitaxial substrate for a group III nitride semiconductor device according to the above item 10, wherein the impurity atom low concentration layer is not intentionally doped with impurities.

(12) The epitaxial substrate for a group III nitride semiconductor device according to any one of 2 to 11 above, wherein the low-concentration impurity atom layer has a thickness of 0.1 to 10 μm.

(13) The epitaxial substrate for a group III nitride semiconductor device according to any one of the above items 2 to 12, wherein the total thickness of the high impurity atom concentration layer and the low impurity atom concentration layer is 1-1000 μm.

(14) An n-type layer, a light emitting layer, and a p-type layer made of a group III nitride semiconductor in this order on the group III nitride semiconductor element epitaxial substrate according to any one of items 1 to 13 above. A group III nitride semiconductor light-emitting device comprising a negative electrode and a positive electrode provided on the n-type layer and the p-type layer, respectively.

(15) A lamp comprising the light emitting device as described in 14 above.

In the epitaxial substrate for a group III nitride semiconductor device of the present invention, the transition density of the group III nitride semiconductor layer is as extremely low as 1 × 10 ⁷ cm ⁻² or less. Therefore, it is possible to produce a group III nitride semiconductor light emitting device having excellent luminous efficiency using this epitaxial substrate. That is, in the current injection type light emitting element, by reducing the crystal defect that becomes a non-emission center by trapping carriers, for example, in the LED element, the luminous efficiency is improved, the reverse withstand voltage is improved, and the electrostatic withstand voltage is improved. I can expect. In the laser element, the threshold current can be reduced.

  Furthermore, this epitaxial substrate can be obtained by laminating only the semiconductor layer using a normal epitaxial growth method on a flat substrate without processing the substrate or the deposited layer on the substrate. is there.

In the present invention, the substrate on which the group III nitride semiconductor layer is laminated is a sapphire (α-Al ₂ O ₃ single crystal), zinc oxide (ZnO), gallium oxide / lithium (having a relatively high melting point and heat resistance). Examples thereof include an oxide single crystal material such as a composition formula LiGaO ₂ ), a substrate made of a group IV semiconductor single crystal such as silicon single crystal (silicon) and cubic or hexagonal crystal type silicon carbide (SiC). Also, III-V compound semiconductor single crystal materials such as gallium nitride (GaN), aluminum nitride (AlN), and gallium phosphide (GaP) can be used. An optically transparent single crystal material that can transmit light emitted from the light emitting layer can be effectively used as a substrate.

  In addition, the surface of the substrate must be a smooth surface that has been mechanically and / or chemically polished. Usually, those having a surface roughness (Ra) of 1 nm or less, which is used as an index of unevenness, are preferred.

  In the present invention, a flat substrate having a surface roughness (Ra) of 1 nm or less can be used as it is. Further, the present invention is characterized in that the dislocation density of the group III nitride semiconductor layer is reduced in a series of growth processes without taking out the deposited layer once grown from the growth furnace and processing it.

  That is, a layer that generates pits by doping impurities at a high concentration in a part of a semiconductor laminate that is stacked on a substrate having a flat surface, and the pits that are made of an undoped semiconductor with a low impurity concentration It is characterized by having a layer to fill. In the process of growing a low impurity concentration layer or undoped layer while filling a slope that is not parallel to the growth surface formed in the pit portion, dislocations appearing on the slope of the pit are bent laterally and terminate. As a result, dislocations propagating upward are reduced. By repeating this periodically, the dislocation density further decreases.

  By using this method, complicated processing such as processing of the substrate or the deposited layer thereon or processing of the surface by heat treatment during the growth is not necessary, and a simple and large effect of reducing dislocation can be obtained. In addition, this method is effective regardless of the type of impurity element to be doped for forming pits, and can be used with either a conductivity type, an n-type dopant, or a p-type dopant.

  The effect is higher as the area occupied by the pits in the growth surface is larger, and it is more effective that the pits cover almost the entire surface. However, even if the entire surface is covered with pits, if each pit is small, the effect is small and a certain size is required. If the size of the pit is too large, it becomes difficult to fill the pit and make the buried layer flat. Therefore, there is an optimum value for the size and density of the pit.

  However, since the pits are buried by subsequent embedding growth, when the pit formation layer and the pit embedding layer are formed of the same material, the size and density of the pits after the growth cannot be confirmed. Therefore, since the size of the pit depends on the layer thickness of the layer forming the pit, the layer thickness of the pit forming layer, that is, the impurity atom high concentration layer may be defined. In that case, it is important to confirm the pit density in advance and grow under conditions such that the entire surface is covered with pits. In order to control the pit formation state, an in-situ observation apparatus for reflectivity is effective. As the pits are formed, the reflectance decreases, and the reflectance is lowest when almost the entire surface is covered with pits.

  If the entire surface is covered with pits, no further growth occurs in the vertical direction. Therefore, even if epitaxial growth is continued under the same conditions, impurities are deposited on the slopes of the pits and new defects are formed. Therefore, it is preferable to start the formation of the pit buried layer immediately after the pit formation. A reflectance in-situ observation device is important as a means for monitoring this time.

  The dislocation density can be estimated with, for example, a transmission electron microscope (TEM). This is a method of processing a sample into a very thin film and examining the diffraction pattern of the electron beam when it is irradiated with an electron beam, and the state of propagation of dislocations in the crystal and its density can be measured. If only the dislocation density is used, it can be estimated from the measurement of the etch pit density. This is because the epi surface is chemically treated to selectively react with a portion where dislocations exist, and pits having shapes and numbers corresponding to the type and density of dislocations are formed on the surface. Further, cathodoluminescence (CL) can be used. It is a method that utilizes the fact that the crystal is excited by emitting an electron beam and emits light of energy corresponding to the band gap. However, the dislocation position is weaker than other sites, so it depends on the light emission contrast. Know the position of dislocations. In the present invention, a method of measuring dislocation density by forming etch pits is used.

  The impurity atom high-concentration layer for forming pits and the impurity atom low-concentration layer filling them change the supply amount of the impurity doping source to the vapor phase growth reaction system during the vapor phase growth of the group III nitride semiconductor layer. To form. For example, after a large amount of impurity doping source is supplied to the vapor phase growth reaction system for a certain period of time, an undoped layer, that is, a layer where the impurity atom concentration is intentionally added is zero without supplying impurities to the vapor phase growth reaction system. Form by time growth.

  If the supply amount of the impurity doping source to the vapor phase growth reaction system is increased or decreased, the layer where the pit is formed and the layer filling the pit can be formed periodically. In the present invention, the group III nitride semiconductor laminate composed of a high impurity atom concentration layer and a low impurity atom concentration layer is formed by alternately and periodically laminating layers having a high impurity atom concentration and layers having a low impurity atom concentration. Preferably it is.

The group III nitride semiconductor laminate composed of the high impurity atom concentration layer and the low impurity atom concentration layer can be directly provided on the substrate through a conventionally known buffer layer as required. By providing the buffer layer, the density of pits generated in the group III nitride semiconductor laminate can be controlled. The buffer layer can be composed of, for example, aluminum gallium nitride (Al _X Ga _Y In _Z N: 0 ≦ X, Y, Z ≦ 1, and X + Y + Z = 1). Further, a known base layer may be provided on the substrate, and the above group III nitride semiconductor laminate may be provided thereon. Furthermore, the above-mentioned group III nitride semiconductor laminate may be provided on a substrate, and a known base layer may be provided thereon to form the epitaxial substrate of the present invention.

When the underlayer is provided, the underlayer is composed of an Al _x Ga _1-x N layer (0 ≦ x ≦ 1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1). Is preferred. The film thickness is 0.1 μm or more, preferably 0.5 μm or more, more preferably 1 μm or more. An Al _x Ga ₁ -xN layer with good crystallinity is more easily obtained when the film thickness is increased. The upper limit of the thickness of the underlayer is not particularly limited in obtaining the present invention, but if it is too thick, the cost increases, so it is preferably 10 μm or less, more preferably 8 μm or less, and particularly preferably 5 μm or less.

The underlayer may be doped with n-type impurities within the range of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , but undoped (<1 × 10 ¹⁷ / cm ³ ) is a better crystal. It is preferable in terms of maintaining the property. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably it is Si and Ge.

  The thickness of the layer for forming pits containing impurity atoms at a high concentration is suitably from 0.1 μm to 10 μm. Preferably, they are 0.3 micrometer or more and 5 micrometers or less, More preferably, they are 0.5 micrometer or more and 3 micrometers or less. When the film thickness is less than 0.1 μm, the pits are not sufficiently large, and the probability that the dislocation hits that portion becomes low, so the effect of terminating the dislocation is small. On the other hand, when the thickness exceeds 10 μm, the thickness becomes too large, and impurity atoms are not completely filled with the low-concentration layer, resulting in poor flatness. As a result, for example, the flatness of the light emitting layer laminated on the epitaxial substrate of the present invention is also deteriorated, and the characteristics of the light emitting element are deteriorated.

Further, the pit density of the layer for forming pits containing impurity atoms at a high concentration is suitably 1 × 10 ⁵ cm ⁻² or more and 5 × 10 ⁸ cm ⁻² or less. It is preferably 1 × 10 ⁶ cm ⁻² or more and 1 × 10 ⁸ cm ⁻² or less, and more preferably 5 × 10 ⁶ cm ⁻² or more and 5 × 10 ⁷ cm ⁻² or less. Control within this range maximizes the probability that the pits spread over almost the entire surface of the pit forming layer, that is, the high concentration layer of impurity atoms, and that dislocations enter this pit and bend the direction.

  The pit density can be measured, for example, with a differential interference microscope or a fluorescence microscope. The pit density can be calculated by observing the epitaxial film with pits formed in the high concentration layer at 50 to 500 times.

  The thickness of the layer containing impurity atoms at a low concentration is preferably 0.1 μm or more and 10 μm or less, more preferably 0.3 μm or more and 5 μm or less, and more preferably 0.5 μm or more, as in the layer containing impurity atoms at a high concentration. 3 μm or less is particularly preferable. When the film thickness is less than 0.1 μm, the pits formed by the high concentration layer cannot be sufficiently filled and the flatness is impaired. Moreover, the effect does not become large even if it exceeds 10 μm.

  In addition, the layer containing impurity atoms at a low concentration promotes the dislocations to proceed laterally when filling the pits, so that growth parameters such as increasing the growth temperature, decreasing the growth pressure, and decreasing the growth rate are set. It may be changed.

  In the present invention, a set of a high concentration layer and a low concentration layer that are in contact with each other is referred to as one period. The total thickness of the high-concentration layer and the low-concentration layer in each cycle, that is, the thickness of one cycle is preferably 0.2 μm or more and 20 μm or less. Preferably, they are 0.6 micrometer or more and 10 micrometers or less, More preferably, they are 1 micrometer or more and 6 micrometers or less. If it exceeds 20 μm, the pits cannot be filled and the flatness is deteriorated, or the total film thickness is increased when the cycle is repeated, which is disadvantageous for processing. Moreover, in order to make it less than 0.2 micrometer, the supply amount of an n-type impurity raw material must be changed frequently, and working efficiency falls.

  When the high-concentration layer is thicker than the low-concentration layer in one cycle, pit formation is not sufficiently suppressed and flatness cannot be obtained sufficiently. On the other hand, when the low-concentration layer is equal to or thicker than the high-concentration layer in one cycle, the flatness is good. Therefore, the thickness of the low concentration layer is preferably equal to or greater than the thickness of the high concentration layer.

  The total thickness of the high impurity atom concentration layer and the low impurity atom concentration layer is preferably 1 μm to 1000 μm, more preferably 2 μm to 100 μm, and particularly preferably 4 μm to 20 μm. When the layer thickness is 1 μm or less, the probability of dislocation termination is reduced and the effect is reduced, and the effect obtained when the thickness is 1000 μm or more is not significantly different, and only the cost is increased.

  From the thickness of one period and the entire thickness, the number of periods to be laminated is preferably 1 or more and 50 or less, more preferably 1 or more and 10 or less, and particularly preferably 1 or more and 5 or less. For example, a repetition of a high-concentration layer having a thickness of 2 μm and a low-concentration layer having a thickness of 2 μm is set as one cycle, and the layers are laminated over three cycles to form a group III nitride semiconductor laminate having a total thickness of 12 μm. .

  As the number of periods increases, the dislocation density decreases. However, since the generation of pits decreases as the dislocation density decreases, the number of pits formed in the impurity atom high concentration layer also decreases as the number of periods increases. Therefore, as the number of periods increases, the effect of decreasing the dislocation density becomes difficult to obtain. Furthermore, cracks and the like may occur due to the entire layer becoming thick. Therefore, the optimum number of periods can be determined from the relationship between the effective thickness of each layer and the overall thickness.

  Examples of impurities for forming pits include silicon (Si), germanium (Ge), tin (Sn), sulfur (S), Se (selenium), Te (tellurium), magnesium (Mg), and zinc (Zn). Available.

  Among these, Ge is particularly preferable. Pit formation is easier than other impurities, and therefore, the pit density can be easily controlled.

The concentration of impurity atoms in the high-concentration layer varies depending on the type of impurity used and its compound. If the concentration is low, pits cannot be generated and the effect cannot be obtained. Further, if the concentration is too high, there are too many pits and a flat portion does not remain, and flatness may not be recovered when buried with a low concentration layer. Usually, it is preferably 5 × 10 ¹⁷ cm ⁻³ to 4 × 10 ¹⁹ cm ⁻³ . The impurity atom concentration of the high concentration layer does not necessarily have to be constant over the entire group III nitride semiconductor laminate, and the concentration may change continuously or discontinuously for each period. Further, the impurity atom concentration may vary within each layer. Furthermore, the impurity element may not be one kind, and two or more kinds of elements may be combined.

The concentration of impurity atoms in the low concentration layer is preferably lower than the concentration of impurity atoms in the high concentration layer, and 2 × 10 ¹⁹ cm ⁻³ or less. This is because the lower the concentration, the greater the effect of filling the pits. Regarding the lower limit, the lower the better, the more preferably it is not intentionally doped. If the low-concentration layer is composed of an undoped group III nitride semiconductor layer in order to reduce the impurity atom concentration, the effect of filling up the pits generated on the surface of the high-concentration layer is further enhanced, and a semiconductor layer with a flat surface is formed. Preferred to obtain.

  Also, in the low concentration layer, as in the high concentration layer, the impurity atom concentration in the low concentration layer does not necessarily have to be constant over the entire semiconductor layer, and the concentration changes continuously or discontinuously for each period. You may do it. Further, the impurity atom concentration may vary within each layer. Furthermore, the impurity element may not be one kind, and two or more kinds of elements may be combined. In this case, a combination of an n-type impurity and a p-type impurity may be used.

  The concentration of impurity atoms can be measured by, for example, secondary ion mass spectrometry (SIMS). This is a technique for performing mass analysis on an element ionized and ejected by irradiating the surface of a sample with primary ions, and the concentration distribution in the depth direction of a specific element can be observed and quantified. This method is also effective for the Ge element present in the group III nitride semiconductor layer. At that time, the thickness of each layer can also be calculated.

The Group III nitride semiconductor stacked on the substrate, for example, and by the general formula _{Al X Ga Y In Z N 1} -A M A (0 ≦ X ≦ 1,0 ≦ Y ≦ 1,0 ≦ Z ≦ 1, X + Y + Z = 1. A large number of Group III nitride semiconductors represented by the symbol M represents a Group V element different from nitrogen (N), and 0 ≦ A <1, is also known in the present invention. Including those known group III nitride semiconductors, the general formula Al _X Ga _Y In _Z N _1-A M _A (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ Z ≦ 1, and X + Y + Z = 1. The symbol M represents a Group V element different from nitrogen (N), and 0 ≦ A <1.) A Group III nitride semiconductor represented by any number can be used without any limitation.

  The group III nitride semiconductor can contain other group III elements in addition to Al, Ga, and In, and elements such as Ge, Si, Mg, Ca, Zn, Be, P, As, and B as required Can also be contained. Furthermore, it is not limited to elements that are intentionally added, but may include impurities that are inevitably included depending on film forming conditions and the like, as well as trace impurities that are included in the raw materials and reaction tube materials.

The growth method of the group III nitride semiconductor is not particularly limited, and the group III nitride semiconductor such as MOCVD (metal organic chemical vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy) is grown. All methods known to be applied are applicable. A preferred growth method is the MOCVD method from the viewpoint of film thickness controllability and mass productivity. In the MOCVD method, hydrogen (H ₂ ) or nitrogen (N ₂ ) is used as a carrier gas, trimethyl gallium (TMG) or triethyl gallium (TEG) is used as a Ga source as a group III source, and trimethyl aluminum (TMA) or triethyl aluminum is used as an Al source. (TEA), trimethylindium (TMI) or triethylindium (TEI) as an In source, ammonia (NH ₃ ), hydrazine (N ₂ H ₄ ), or the like as an N source that is a group V source.

As a raw material of impurities to be doped, hydrides of respective elements, for example, monosilane (SiH ₄ ), disilane (SiH ₆ ), germane (GeH ₄ ), hydrogen sulfide (H ₂ S), hydrogen selenide (H ₂ Se) ), Hydrogen telluride (H ₂ Te), etc., and organic compounds of the respective elements, such as tetramethyl silicon ((CH ₃ ) ₄ Si), tetraethyl silicon ((C ₂ H ₅ ) ₄ Si), tetramethyl germanium ((CH ₃ ) ₄ Ge), tetraethylgermanium ((C ₂ H ₅ ) ₄ Ge), diethyl selenium ((C ₂ H ₅ ) ₂ Se), diisopropyl selenium ((C ₃ H ₇ ) ₂ Se), diethyl sulfide ((C ₂ H ₅ ) ₂ S), diisopropyl sulfide ((C ₃ H ₇ ) ₂ S), tetramethyltin ((CH ₃ ) ₄ Sn), tetraethyltin ((C ₂ H ₅ ) ₄ Sn), dimethyl tellurium ((CH ₃ ) ₂ Te), diethyl tellurium ((C ₂ H ₅ ) ₂ Te), cyclopentadienyl magnesium (Cp ₂ Mg), diethyl zinc ((C ₂ H ₅₎ available ₂ Zn) and the like. In the MBE method, elemental (metal) can also be used as a doping source.

  In the MOCVD method, it is preferable to grow a group III nitride semiconductor layer according to the purpose in a temperature range of 900 ° C. to 1250 ° C. on the substrate using the above-mentioned raw materials.

When a group III nitride semiconductor device is manufactured using the epitaxial substrate of the present invention, various group III nitride semiconductor layers and electrodes, etc., are formed on the group III nitride semiconductor layer of the substrate according to the target semiconductor device. May be sequentially stacked. As described above, since at least the upper group III nitride semiconductor layer of the epitaxial substrate of the present invention has a dislocation density as very low as 1 × 10 ⁷ cm ⁻² or less, the group III nitride semiconductor layer laminated thereon In addition, a high-performance semiconductor element having excellent crystallinity can be obtained.

  For example, when the target device is a light-emitting device, an n-type layer, a light-emitting layer, and a p-type layer made of a group III nitride semiconductor are stacked in this order on the epitaxial substrate of the present invention. What is necessary is just to provide a negative electrode and a positive electrode in a p-type layer, respectively.

  The n-type layer is usually composed of an n-contact layer and an n-clad layer. The n contact layer can also serve as a cladding layer.

The n contact layer is preferably composed of an Al _x Ga _1-x N layer (0 ≦ x ≦ 1, preferably 0 ≦ x ≦ 0.5, more preferably 0 ≦ x ≦ 0.1). It is preferable that an n-type impurity is doped. When the n-type impurity is contained at a concentration of 1 × 10 ¹⁷ to 1 × 10 ¹⁹ / cm ³ , preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ , a negative electrode From the standpoints of maintaining good ohmic contact with each other, suppressing the occurrence of cracks, and maintaining good crystallinity. Although it does not specifically limit as an n-type impurity, For example, Si, Ge, Sn, etc. are mentioned, Preferably it is Si and Ge. Although a film thickness is not specifically limited, Usually, it is 0.1-10 micrometers, 0.5-8 micrometers is preferable and 1-5 micrometers is more preferable.

The n-clad layer can be formed of AlGaN, GaN, GaInN, or the like. Needless to say, in the case of GaInN, it is desirable to make it larger than the band gap of GaInN in the active layer. The thickness of the n-clad layer is not particularly limited, but is preferably 0.005 to 0.5 μm, more preferably 0.005 to 0.1 μm. The n-type doping concentration of the n-clad layer is preferably 1 × 10 ¹⁷ to 1 × 10 ²⁰ / cm ³ , more preferably 1 × 10 ¹⁸ to 1 × 10 ¹⁹ / cm ³ . A doping concentration within this range is preferable in terms of maintaining good crystallinity and reducing the operating voltage of the device.

As the light emitting layer stacked on the n-type layer, a light emitting layer made of a group III nitride semiconductor, preferably a group III nitride semiconductor of Ga _1-s In _s N (0 <s <0.4) is usually used. It is done. Although it does not specifically limit as a film thickness of a light emitting layer, The film thickness of the grade which can acquire a quantum effect, ie, a critical film thickness, is mentioned, for example, Preferably it is 1-10 nm, More preferably, it is 2-6 nm. A film thickness in the above range is preferable in terms of light emission output. In addition to the single quantum well (SQW) structure as described above, the light emitting layer has Ga _{1 -s} In _s N as a well layer and Al _c Ga _{1 -c} having a larger band gap energy than the well layer. A multiple quantum well (MQW) structure including an N (0 ≦ c <0.3 and b> c) barrier layer may be employed. The well layer and the barrier layer may be doped with impurities.

The p-type layer is usually composed of a p-cladding layer and a p-contact layer. However, the p contact layer may also serve as the p clad layer. The p-cladding layer is not particularly limited as long as it has a composition larger than the band gap energy of the light-emitting layer and can confine carriers in the light-emitting layer, but is preferably Al _d Ga _1-d N (0 < d ≦ 0.4, preferably 0.1 ≦ d ≦ 0.3). When the p-cladding layer is made of such AlGaN, it is preferable in terms of confinement of carriers in the light-emitting layer. The thickness of the p-clad layer is not particularly limited, but is preferably 1 to 400 nm, more preferably 5 to 100 nm. The p-type doping concentration of the p-clad layer is preferably 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , more preferably 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ³ . When the p-type dope concentration is in the above range, a good p-type crystal can be obtained without reducing the crystallinity.

The p-contact layer is a group III comprising at least Al _e Ga _1-e N (0 ≦ e <0.5, preferably 0 ≦ e ≦ 0.2, more preferably 0 ≦ e ≦ 0.1). It is a nitride semiconductor layer. When the Al composition is in the above range, it is preferable in terms of maintaining good crystallinity and good ohmic contact with the positive electrode. When the p-type dopant is contained at a concentration of 1 × 10 ¹⁸ to 1 × 10 ²¹ / cm ³ , preferably at a concentration of 5 × 10 ^{19 to} 5 × 10 ²⁰ / cm ³ , good ohmic contact can be maintained, It is preferable in terms of preventing cracks and maintaining good crystallinity. Although it does not specifically limit as a p-type impurity, For example, Preferably Mg is mentioned. Although a film thickness is not specifically limited, 0.01-0.5 micrometer is preferable, More preferably, it is 0.05-0.2 micrometer. When the film thickness is within this range, it is preferable in terms of light emission output.

  The n-contact layer and the p-contact layer are each provided with a negative electrode and a positive electrode by conventional means well known in the art. As each structure, any structure including a conventionally known structure can be used without any limitation.

  A semiconductor light emitting device can be manufactured using the epitaxial substrate for a group III nitride semiconductor device of the present invention, and a lamp can be manufactured by providing a transparent cover by means well known in the art, for example. In addition, a white lamp can be produced by combining the gallium nitride compound semiconductor light emitting device of the present invention and a cover having a phosphor.

  The present invention will be described in more detail with reference to the following examples, but the present invention is not limited to these examples.

Example 1
FIG. 1 is a diagram schematically showing a cross-sectional structure of an epitaxial substrate for a group III nitride semiconductor device manufactured in this example.

  A structure in which a group III nitride semiconductor was laminated on a sapphire substrate was formed by the following procedure using a general low pressure MOCVD means. First, the substrate 1 made of (0001) -sapphire was placed on a susceptor made of high-purity graphite for semiconductors heated to a film forming temperature by a high-frequency (RF) induction heater. After placing, nitrogen gas was circulated in a stainless steel vapor phase growth reactor to purge the inside of the furnace.

After flowing nitrogen gas through the vapor phase growth reactor for 8 minutes, the induction heating type heater was operated, and the temperature of the substrate 1 was raised from room temperature to 600 ° C. in 10 minutes. While maintaining the temperature of the substrate 1 at 600 ° C., hydrogen gas and nitrogen gas were circulated to set the pressure in the vapor phase growth reactor to 1.5 × 10 ⁴ pascals (Pa). The surface of the substrate 1 was thermally cleaned by being left under this temperature and pressure for 2 minutes. After the thermal cleaning was completed, the supply of nitrogen gas into the vapor phase growth reactor was stopped. The supply of hydrogen gas was continued.

  Thereafter, the temperature of the substrate 1 was raised to 1120 ° C. in a hydrogen atmosphere. After confirming that the temperature was stabilized at 1120 ° C., hydrogen gas accompanied by vapor of trimethylaluminum (TMA) was supplied into the vapor phase growth reactor for 8 minutes and 30 seconds. Thereby, it reacts with nitrogen atoms generated by the decomposition of deposition deposits containing nitrogen that have been attached to the inner wall of the vapor phase growth reactor, and aluminum nitride (AlN) having a thickness of several nm is formed on the sapphire substrate 1. A buffer layer 2 made of a thin film was attached. After stopping the supply of hydrogen gas accompanying the vapor of TMA into the vapor phase growth reactor and terminating the growth of AlN, the process waited for 4 minutes to completely discharge the TMA remaining in the vapor phase growth reactor.

Subsequently, ammonia (NH ₃ ) gas was supplied into the vapor phase growth reactor, and after 4 minutes, the temperature of the susceptor was lowered to 1040 ° C. while continuing the circulation of the ammonia gas. After confirming that the temperature of the susceptor reached 1040 ° C., wait for a while for the temperature to stabilize, and then start supplying trimethylgallium (TMG) into the vapor phase growth reactor, and the bottom made of undoped GaN Formation 3 was grown for 15 minutes. The thickness of the underlayer 3 was 0.5 μm.

Next, hydrogen gas was circulated at 40 sccm (cm ³ / min in standard state conversion) while maintaining the pressure in the stainless steel container containing tetramethylgermanium ((CH ₃ ) ₄ Ge) at 200 kPa (2000 mbar). Tetramethylgermanium was supplied to the reactor. By controlling the supply amount of Ge, the amount of Ge taken into the GaN crystal can be controlled, and as a result, the pit density can be controlled. In this case, a pit formation layer made of Ge-doped GaN, that is, a high impurity atom concentration layer 4 was grown for 2 μm through circulation for 60 minutes. Thereafter, the flow of (CH ₃ ) ₄ Ge was stopped for 1 hour, and a pit buried layer of undoped GaN, that is, a low impurity atom concentration layer 5 was grown by 2 μm to fill the pit. This cycle was repeated twice to form a high impurity atom concentration layer and a low impurity atom concentration layer having a total thickness of 8.0 μm in which the Ge concentration changed periodically.

  After the growth of the impurity atom low concentration layer 5 was finished, energization to the induction heating type heater was stopped, and the temperature of the substrate 1 was lowered to room temperature in about 20 minutes. During the temperature drop, the atmosphere in the vapor phase growth reactor was composed only of nitrogen. After confirming that the temperature of the substrate 1 was lowered to room temperature, the laminated structure was taken out from the vapor phase growth reactor.

The obtained epitaxial substrate was immersed in a mixed solution of sulfuric acid and phosphoric acid at 250 ° C. for 30 minutes. When the density of dislocations observed as etch pits was measured on this surface with an AFM (atomic force microscope), it was 8 × 10 ⁶ cm ⁻² . Furthermore, when the Ge atom concentration of the impurity atom high concentration layer 4 was measured by secondary ion mass spectrometry (SIMS), it was 1 × 10 ¹⁹ cm ⁻³ .

In addition, when the growth of the impurity atom high-concentration layer 4 in the second period was completed, the pit density of the sample taken out from the vapor phase growth reactor was measured with a fluorescence microscope, and it was 1 × 10 ⁷ cm ⁻² . there were.

(Examples 2-3 and Comparative Examples 1-4)
Similar to Example 1, except that the flow rate of hydrogen gas supplied into the stainless steel container containing tetramethylgermanium ((CH ₃ ) ₄ Ge) when the impurity atom high concentration layer 4 is grown is changed. An epitaxial substrate was fabricated.

  The obtained epitaxial substrate was evaluated in the same manner as in Example 1. The results are shown in Table 1 together with the results of Example 1.

  FIG. 2 shows the relationship between the dislocation density of the obtained epitaxial substrate and the pit density formed by the impurity atom high concentration layer 4 in the second period. If the pit density in the impurity atom high concentration layer 4 is small, the probability that the dislocation hits the pit surface and changes its direction is small, so the effect of reducing the dislocation density on the surface of the impurity atom low concentration layer 5 is small. In addition, if the pit density is too high, the pits are combined and the flat portion is lost, so that the burying in the impurity atom low concentration layer 5 is not successful, the flatness is deteriorated, and the effect of reducing dislocations is also achieved. Deteriorate.

Example 4
A group III nitride semiconductor layer was further laminated on the epitaxial substrate prepared in Example 1, and a group III nitride semiconductor light emitting device was manufactured. FIG. 3 is a diagram schematically showing a cross-sectional structure of the group III nitride semiconductor light-emitting device manufactured in this example.

The process up to the formation of the impurity atom high concentration layer 5 is the same as that of the first embodiment. An n-contact layer 6 made of Ge-doped GaN was laminated thereon at 1120 ° C., and then an n-clad layer 7 made of undoped In _0.03 Ga _0.97 N was laminated at 1060 ° C. The thickness of the n-clad layer 7 was 12.5 nm. On the other hand, the n-contact layer 6 has a structure in which a Ge atom high-concentration layer and a Ge atom low-concentration layer are alternately and repeatedly stacked 100 times, and the total layer thickness is 2 μm.

Next, the temperature of the substrate 1 was set to 730 ° C., and the multiple quantum well structure light emitting layer 8 was provided on the n clad layer 7. The multiple quantum well structure light-emitting layer 8 has a repeating structure of a barrier layer 8a made of GaN and a well layer 8b made of In _0.25 Ga _0.75 N, and starts from the barrier layer 8a and ends with the barrier layer 8a. Here, a multi-quantum well structure having six barrier layers 8a and five well layers 8b is employed. That is, in the light emitting layer 8 having the multiple quantum well structure, first, the GaN barrier layer 8a is provided to be bonded to the n-clad layer 7, and the uppermost layer is also the GaN barrier layer 8a.

The GaN barrier layer 8a was grown using triethylgallium (TEG) as a gallium source. The layer thickness was 8 nm and was undoped. The In _0.25 Ga _0.75 N well layer 8b was grown using triethylgallium (TEG) as a gallium source and trimethylindium (TMI) as an indium source. The layer thickness was 2.5 nm and was undoped.

A p-clad layer 9 made of p-type Al _0.07 Ga _0.93 N doped with magnesium (Mg) was formed on the light-emitting layer 8 having a multiple quantum well structure. The layer thickness was 10 nm. On the p-cladding layer 9, a p-contact layer 10 made of p-type GaN doped with Mg was further formed. Bis-cyclopentadienyl Mg was used as the Mg doping source. Mg was added so that the hole concentration of the p-contact layer 10 was 8 × 10 ¹⁷ cm ⁻³ . The layer thickness of the p contact layer 10 was 100 nm.

  After the growth of the p-type GaN contact layer 10 was finished, the energization to the induction heating heater was stopped, and the temperature of the substrate 1 was lowered to room temperature in about 20 minutes. During the temperature drop, the atmosphere in the vapor phase growth reactor was composed only of nitrogen. After confirming that the temperature of the substrate 1 was lowered to room temperature, the laminated structure was taken out from the vapor phase growth reactor. At this time, the p-type GaN contact layer 10 already showed p-type conductivity without performing an annealing process for electrically activating the p-type carrier (Mg).

  Next, the Ge atomic high concentration layer of the Ge-doped n-type GaN layer 6 is exposed only in a region where the n-type ohmic electrode 11 is to be formed by using a known photolithography technique and a general dry etching technique. . A negative electrode 11 in which titanium and gold were stacked (titanium on the semiconductor side) was formed on the surface of the exposed Ge atom high concentration layer. The entire surface of the p-type GaN contact layer 10 that forms the surface of the remaining laminated structure is coated with nickel and gold in order from the semiconductor side using a general vacuum deposition means and a known photolithography means. A laminated positive electrode 12 was formed.

  After that, it was cut into a 350 μm square LED chip, placed on a lead frame, and a gold lead was connected to the lead frame so that an element driving current could flow from the lead frame to the LED chip.

  An element driving current was passed between the negative electrode 11 and the positive electrode 12 through the lead frame in the forward direction. When the forward current was 20 mA, the forward voltage was 3.5V. Further, the central wavelength of emitted blue band light when a forward current of 20 mA was passed was 460 nm. In addition, the intensity of light emission measured using a general integrating sphere reached 6 mW, and a group III nitride semiconductor light-emitting device that gave high intensity light emission was obtained. Furthermore, the voltage at which a reverse current of 10 μA circulates was as good as 30 V or more, and the electrostatic withstand voltage characteristic according to the machine model was as good as 500 V or more.

(Comparative Example 5)
A Group III nitride semiconductor multilayer structure was fabricated in the same manner as in Example 1 except that the thickness of the underlayer was 8.5 μm and the high impurity atom concentration layer and the low impurity atom concentration layer were not provided. The dislocation density on the surface of the obtained laminated structure was 2 × 10 ⁹ cm ⁻² .

  A Group III nitride semiconductor light-emitting device was fabricated on the multilayer structure in the same manner as in Example 4. When the forward and reverse voltages and the emission intensity were measured in the same manner as in Example 4, the forward voltage was 3.5 V, which was the same as in Example 4, but the emission intensity was 5 mW, which is lower than that in Example 4. It was strength. Furthermore, the voltage at which the reverse current flows through 10 μA was about 15 V, and the electrostatic withstand voltage characteristic by the machine model was 200 V, which was inferior to that of Example 4.

  The epitaxial substrate obtained by the present invention has a very low dislocation density of the group III nitride semiconductor layer, and thus is useful for a group III nitride semiconductor device, for example, a group III nitride semiconductor light emitting device.

1 is a diagram schematically showing a cross-sectional structure of an epitaxial substrate of the present invention produced in Example 1. FIG. It is the figure which showed the relationship between the pit density of an impurity atom high concentration layer, and the dislocation density of an impurity atom low concentration layer. 6 is a diagram schematically showing a cross-sectional structure of a group III nitride semiconductor light-emitting device manufactured in Example 4. FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Buffer layer 3 Underlayer 4 High impurity atom concentration layer 5 Low impurity atom concentration layer 6 n contact layer 7 n clad layer 8 light emitting layer 9 p clad layer 10 p contact layer 11 negative electrode 12 positive electrode

Claims (15)

The substrate has a surface roughness (Ra) of 1 nm or less and a group III nitride semiconductor layer directly stacked on the substrate, and the group III nitride semiconductor layer includes a plurality of layers in contact with each other. An epitaxial substrate for a group III nitride semiconductor device, wherein at least one of the layers is a layer having a dislocation density of 1 × 10 ⁷ cm ⁻² or less.   The group III nitride semiconductor layer according to claim 1, wherein at least one set of the plurality of layers in contact with each other of the group III nitride semiconductor layer is a high impurity atom concentration layer and a low impurity atom concentration layer, and the impurity atom high concentration layer exists on the substrate side. Epitaxial substrate for group nitride semiconductor devices.   The epitaxial substrate for a group III nitride semiconductor device according to claim 2, wherein the high impurity atom concentration layer and the low impurity atom concentration layer are present alternately and periodically.   The epitaxial substrate for a group III nitride semiconductor device according to claim 3, wherein the number of periods is 1 to 10.   The group III nitride according to any one of claims 2 to 4, wherein the impurity is one or a combination of two or more selected from the group consisting of Si, Ge, Sn, S, Se, Mg and Zn. Epitaxial substrate for semiconductor devices.   The epitaxial substrate for a group III nitride semiconductor device according to claim 5, wherein the impurity is Ge. 7. The pit is present in the range of 1 × 10 ⁵ cm ^{−2 to} 5 × 10 ⁸ cm ⁻² on the surface (surface opposite to the substrate) of the impurity atom high concentration layer. Epitaxial substrate for group III nitride semiconductor devices. 8. The epitaxial substrate for a group III nitride semiconductor device according to claim 2, wherein the impurity concentration of the high impurity atom concentration layer is 5 × 10 ¹⁷ to 4 × 10 ¹⁹ cm ⁻³ .   The epitaxial substrate for a group III nitride semiconductor device according to any one of claims 2 to 8, wherein the high-concentration impurity atom layer has a thickness of 0.1 to 10 µm. The group III nitride semiconductor device according to any one of claims 2 to 9, wherein the impurity concentration of the low impurity atom concentration layer is lower than the impurity concentration of the high impurity atom concentration layer and is 2 x 10 ¹⁹ cm ^-3 or less. For epitaxial substrate.   The epitaxial substrate for a group III nitride semiconductor device according to claim 10, wherein the impurity atom low concentration layer is not intentionally doped with impurities.   The epitaxial substrate for a group III nitride semiconductor device according to any one of claims 2 to 11, wherein the thickness of the low impurity atom concentration layer is 0.1 to 10 µm.   The epitaxial substrate for a group III nitride semiconductor device according to any one of claims 2 to 12, wherein the total thickness of the high impurity atom concentration layer and the low impurity atom concentration layer is 1-1000 µm.   On the epitaxial substrate for a group III nitride semiconductor device according to any one of claims 1 to 13, an n-type layer, a light emitting layer, and a p-type layer made of a group III nitride semiconductor are provided in this order. A group III nitride semiconductor light emitting device in which a negative electrode and a positive electrode are provided on the n-type layer and the p-type layer, respectively.   The lamp | ramp which consists of a light emitting element of Claim 14.

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