JP2006287127A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an effective length of a parallel pn layer from shortening caused from an impurity diffused from a low resistivity layer in an extreme joining semiconductor device. <P>SOLUTION: An n buffer layer 16 with impurity concentration lower than an n<SP>+</SP>low resistivity layer 11 is located among parallel pn layers 12 where n<SP>+</SP>low resistivity layers, p-type semiconductor areas 13, and n-type semiconductor areas 14 on it are alternately and repeatedly joined. The thickness of the n buffer lyer 16 is made longer than the length diffused when the impurity in the n<SP>+</SP>low resistivity layer 11 thermally diffuses in the n buffer layer 16 toward the parallel pn layers 12 in a high-temperature treatment. Accordingly, the impurity diffused from the n<SP>+</SP>low resistivity layer 11 is prevented from reaching the parallel pn layer 12. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device that can be applied to a MOSFET (insulated gate field effect transistor), an IGBT (insulated gate bipolar transistor), a bipolar transistor, or the like, and that can achieve both high breakdown voltage and large current capacity, and a method for manufacturing the same.

In general, semiconductor devices can be broadly classified into horizontal elements having electrode portions on only one side and vertical elements having electrode portions on both sides. In the vertical element, the direction in which the drift current flows when turned on and the direction in which the depletion layer is extended by the reverse bias voltage when turned off are both in the thickness direction (vertical direction) of the substrate. For example, in a normal planar type n-channel vertical MOSFET, the portion of the high resistance n ⁻ drift layer functions as a region for flowing a drift current in the vertical direction when the MOSFET is in the on state, and is depleted when in the off state. It works to increase pressure resistance.

Reducing the thickness of the high-resistance n ⁻ drift layer, that is, shortening the current path length lowers the drift resistance in the on state, so that the substantial on-resistance (drain-source resistance) of the MOSFET is reduced. It has a lowering effect. However, since the extension width of the drain-base depletion layer extending from the pn junction between the p base region and the n ⁻ drift layer becomes narrow in the off state, the depletion electric field strength is faster than the maximum (critical) electric field strength of silicon. Will reach. That is, breakdown occurs before the drain-source voltage reaches the design value of the device breakdown voltage, and the breakdown voltage (drain-source voltage) is lowered.

On the contrary, when the n ⁻ drift layer is formed thick, it is possible to increase the breakdown voltage, but the on-resistance is inevitably increased, so that the on-loss increases. Thus, there is a trade-off relationship between on-resistance (current capacity) and breakdown voltage. It is known that this relationship is similarly established in semiconductor devices such as IGBTs having a drift layer, bipolar transistors, and diodes. The same applies to a lateral element in which the direction in which the drift current flows when turned on and the direction in which the depletion layer is extended by the reverse bias voltage when turned off. As a solution to this problem, a semiconductor device (hereinafter referred to as a superjunction semiconductor device) in which the drift layer is a parallel pn layer in which n-type regions and p-type regions having an increased impurity concentration are alternately arranged is known. It is.

  The difference in structure between the superjunction semiconductor device and the normal planar type n-channel vertical MOSFET is that the drift portion is not a uniform / single conductive type layer (impurity diffusion layer) but a vertical layer-like n-type. That is, the drift region and the vertical layered p-type partition region are composed of parallel pn layers joined alternately. In this structure, even if the impurity concentration of the parallel pn layer is high, the depletion layer extends in both the lateral directions from each pn junction oriented in the vertical direction of the parallel pn layer in the off state, and the entire drift portion is depleted. High breakdown voltage can be achieved.

  As a method for producing a parallel pn layer, a method of repeatedly performing epitaxial growth of an n-type semiconductor layer and selective ion implantation of a p-type impurity (hereinafter referred to as multistage epitaxial growth method) is known. As another method, a method of forming a plurality of trenches in an n-type semiconductor layer epitaxially grown on a low resistance substrate and filling the trenches with an epitaxial growth layer of a p-type semiconductor (hereinafter referred to as a trench filling method) is known. (For example, refer to Patent Document 1).

  The trench embedding method has an advantage that the cost can be reduced because the number of times of epitaxial growth is smaller than that of the multi-stage epitaxial growth method. In the trench embedding method, a method of forming a trench deeper than the thickness of the epitaxial growth layer of the n-type semiconductor is known (see, for example, Patent Document 2).

  By the way, a PiN diode having a thick low-concentration n-type semiconductor layer for maintaining a withstand voltage between a parallel pn layer and a low specific resistance layer is known as a superjunction semiconductor device (see, for example, Patent Document 3). ). Further, a MOSFET having a withstand voltage class of 600 V having a low-concentration n-type semiconductor layer having a thickness of 30 μm between a parallel pn layer having a thickness of 42 μm and a low specific resistance layer is known (for example, see Patent Document 4). These Patent Documents 3 and 4 both aim at improving the reverse recovery tolerance.

Japanese Patent Laid-Open No. 13-196573 Japanese Patent Laying-Open No. 2003-86800 (FIG. 3) Japanese Patent Laying-Open No. 2003-298072 (FIG. 1) Japanese Patent Laying-Open No. 2004-22716 (FIG. 3)

  The parallel pn layer is usually formed on a high-concentration n-type semiconductor substrate that becomes a low resistivity layer. Therefore, the following problems arise. 23 and 24 are cross-sectional views showing a state where the parallel pn layer 2 is formed on the low resistivity layer 1 by the trench filling method and a state where the MOS structure 5 is formed on the surface of the parallel pn layer 2, respectively. It is. FIG. 25 is a diagram showing the impurity concentration distribution in the depth direction of the cross section shown in FIGS. 23 and 24. FIG. 25 (a) shows the p-type semiconductor from the surface p1 of the parallel pn layer 2 to the parallel pn layer 2. An impurity concentration distribution of p1-p2 passing through the region 3 to the back surface p2 of the low resistivity layer 1 is shown, and FIG. An impurity concentration distribution of n1-n2 passing through the back surface n2 of the low resistivity layer 1 is shown.

  As shown in FIG. 23, when the parallel pn layer 2 is formed by the trench embedding method, the parallel pn layer 2 is formed in substantially the same shape as the shape of the trench. At this time, the effective impurity concentration in the depth direction of the p-type semiconductor region 3 and the n-type semiconductor region 4 of the parallel pn layer 2 (value obtained by subtracting the n-type and p-type impurity amounts) is shown in FIG. ) And (b) as indicated by solid lines. When the MOSFET is manufactured, it is necessary to manufacture the MOS structure 5 on the surface side after the parallel pn layer 2 is formed.

  In the process of manufacturing the MOS structure 5, various high temperature treatments are performed. During the high temperature treatment, n-type impurities diffuse from the low specific resistance layer 1. Therefore, the p-type semiconductor region 3 of the parallel pn layer 2 recedes, and the effective length of the parallel pn layer 2 is shortened as shown in FIG. In FIG. 24, the broken line indicates the parallel pn layer 2 before the high temperature processing. The effective impurity concentrations in the depth direction of the p-type semiconductor region 3 and the n-type semiconductor region 4 of the parallel pn layer 2 after the MOS structure 5 is produced are as shown by broken lines in FIGS. 25A and 25B, respectively. It is.

  Since the withstand voltage in the off state of the MOSFET having the super junction structure is substantially proportional to the effective length of the parallel pn layer 2, the withstand voltage is lowered by reducing the effective length. In order to compensate for this decrease in breakdown voltage, the length of the parallel pn layer 2 is increased in advance by the diffusion length of impurities diffused from the low resistivity layer 1 during the subsequent high temperature processing, and the parallel pn layer after the high temperature processing is processed. It is necessary for the length of 2 to be a length that can provide a desired withstand voltage. Similar problems occur in the multistage epitaxial growth method.

  In the case of the trench embedding method, in order to lengthen the parallel pn layer 2, it is necessary to form the trench deeper, so that the aspect ratio of the trench becomes high. This increases the difficulty of processes such as trench etching and epitaxial growth for filling the trench. In the case of the multistage epitaxial growth method, if the parallel pn layer 2 is lengthened, the number of times of epitaxial growth and selective ion implantation is increased, so that the cost is increased.

  In the above-mentioned four patent documents 1 to 4, the effective length of the parallel pn layer is shortened by the diffusion of the n-type impurity from the low specific resistance layer, the adverse effect thereof, or the means for preventing it, etc. Not listed. In Patent Document 1, a first specific resistance epitaxial growth layer serving as a buffer layer is formed on a high-concentration n-type semiconductor substrate, and a second specific resistance for forming a parallel pn layer is formed thereon. The method for forming the epitaxial growth layer is not described. Further, Patent Document 2 does not describe the relationship between the depth of the trench and the thickness of the epitaxial growth layer for forming the parallel pn layer.

  In order to eliminate the above-described problems caused by the conventional technique, the present invention shortens the effective length of the parallel pn layer due to the diffusion of impurities from the low specific resistance layer after the formation of the parallel pn layer, resulting in a decrease in breakdown voltage. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same that can prevent the above.

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the present invention includes a first conductivity type semiconductor region and a second conductivity type semiconductor region on a first conductivity type low specific resistance layer. A semiconductor device having parallel pn layers that are alternately and repeatedly joined, wherein a buffer layer of a first conductivity type having an impurity concentration lower than that of the low specific resistance layer is provided between the low specific resistance layer and the parallel pn layer. And the buffer layer has a thickness longer than a diffusion length when the impurities in the low resistivity layer thermally diffuse in the buffer layer toward the parallel pn layer during high-temperature processing. And

  A semiconductor device according to a second aspect of the present invention is the semiconductor device according to the first aspect, wherein the buffer layer has a thickness of 8 μm or more.

  A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the buffer layer has a thickness of 10 μm or less.

  According to a fourth aspect of the present invention, there is provided a semiconductor device manufacturing method comprising: a first step of epitaxially growing a first conductivity type semiconductor on a first conductivity type low specific resistance layer; and an epitaxial growth layer of the first conductivity type semiconductor, A second step of forming a plurality of trenches shallower than the thickness of the epitaxial growth layer at predetermined intervals; a third step of filling the trenches by epitaxial growth of a second conductivity type semiconductor; and remaining between the trenches And a fourth step of flattening the surface of the parallel pn layer composed of the first conductive type semiconductor region and the second conductive type semiconductor region embedded in the trench by polishing.

  According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: epitaxially growing a first conductivity type semiconductor with a first specific resistance on a first conductivity type low specific resistance layer; A first step of epitaxially growing a first conductive type semiconductor with a second specific resistance thereon; a second step of forming a plurality of trenches in the epitaxial growth layer of the first conductive type semiconductor at predetermined intervals; A third step of filling the trench by epitaxial growth of the second conductivity type semiconductor; and a parallel pn layer comprising a first conductivity type semiconductor region remaining between the trenches and a second conductivity type semiconductor region buried in the trench. And a fourth step of flattening the surface by polishing.

  According to a sixth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the fifth aspect of the present invention, wherein the gas concentration ratio supplied into the chamber for epitaxial growth is changed during the first step. The epitaxial growth of the first specific resistance and the epitaxial growth of the second specific resistance are continuously performed in the same chamber.

  According to a seventh aspect of the present invention, there is provided the method for manufacturing a semiconductor device according to the fifth or sixth aspect, wherein the first specific resistance is lower than the second specific resistance and the low specific resistance layer is formed. It is characterized by being higher than the specific resistance.

  A method of manufacturing a semiconductor device according to an eighth aspect of the present invention is the method according to any one of the fifth to seventh aspects, wherein in the second step, the thickness is the same as the thickness of the epitaxial growth layer of the second specific resistance. A trench having a depth is formed.

  A method of manufacturing a semiconductor device according to a ninth aspect of the present invention is the method according to any one of the fifth to seventh aspects, wherein, in the second step, the thickness of the epitaxial growth layer of the second specific resistance is greater than A shallow trench is formed.

  According to the first to third aspects of the present invention, the buffer layer is increased in concentration by the impurity diffused from the low resistivity layer, but the impurity can be prevented from diffusing up to the parallel pn layer. The effective length of the parallel pn layer is maintained at the length immediately after the trench formation. Accordingly, it is possible to prevent a decrease in breakdown voltage. According to claim 2, since the diffusion length of the impurity diffused from the low specific resistance layer is about 6.3 μm, it is possible to prevent the impurity from passing through the buffer layer and reaching the parallel pn layer. it can. Furthermore, according to the third aspect, a sufficient breakdown voltage can be obtained without increasing the on-resistance. That is, even if the buffer layer is made thicker than 10 μm, there is almost no effect of increasing the breakdown voltage. On the other hand, as the buffer layer becomes thicker, the on-resistance increases monotonously. The thickness of is suitably 10 μm or less.

  According to the invention of claim 4, in the first conductivity type semiconductor layer epitaxially grown on the low specific resistance layer, the region sandwiched between the bottom of the trench and the low specific resistance layer becomes the buffer layer. According to the fifth to eighth aspects of the present invention, the first conductivity type semiconductor layer having the first specific resistance epitaxially grown on the low specific resistance layer becomes the buffer layer. On the other hand, according to the ninth aspect of the present invention, of the first specific conductivity type semiconductor layer having the first specific resistance epitaxially grown on the low specific resistance layer and the first specific conductivity type semiconductor layer having the second specific resistance thereon, A region including the bottom of the trench and the region sandwiched between the first conductivity type semiconductor layers having the first specific resistance is a buffer layer.

  Since there is such a buffer layer, it is possible to prevent impurities diffused from the low resistivity layer from diffusing up to the parallel pn layer, so that the effective length of the final parallel pn layer is the length immediately after the trench formation. To be kept. Accordingly, the depth of the trench necessary for securing the withstand voltage can be reduced, so that processes such as trench etching and trench-embedded epitaxial growth can be facilitated. In addition, since the time required for trench etching is shortened, the manufacturing cost can be reduced.

  According to the semiconductor device and the method for manufacturing the same according to the present invention, the effective length of the parallel pn layer is shortened by the diffusion of impurities from the low specific resistance layer after the parallel pn layer is formed. There is an effect that it can be prevented. In addition, the manufacturing process can be simplified and the manufacturing cost can be reduced.

  Exemplary embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be explained below in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that electrons or holes are majority carriers in layers and regions with n or p, respectively. Further, + attached to n or p means that the impurity concentration is higher than that of a layer or region where it is not attached. Note that, in the following description of the embodiments and the accompanying drawings, the same reference numerals are given to the same components, and duplicate descriptions are omitted.

Embodiment 1 FIG.
FIG. 1 is a cross-sectional view illustrating a configuration of an active portion of the semiconductor device according to the first embodiment. As shown in FIG. 1, an n buffer layer 16 is provided on the n ⁺ low specific resistance layer 11. The parallel pn layer 12 in which the p-type semiconductor region 13 and the n-type semiconductor region 14 are periodically arranged is provided on the n buffer layer 16. On the surface of the parallel pn layer 12, a MOS structure 15 including a p base region 21, a p ⁺ contact region 22, an n ⁺ source region 23, a gate insulating film 24, a gate electrode 25 and a source electrode 26 is formed. The n ⁺ low specific resistance layer 11 becomes a drain layer of the MOSFET. A drain electrode 17 is formed on the surface of the drain layer.

The impurity concentration of the n buffer layer 16 is lower than the impurity concentration of the n ⁺ low specific resistance layer 11 and preferably equal to the impurity concentration of the parallel pn layer 12 so as not to affect the parallel pn layer 12. Or a concentration close to it. The thickness of the n buffer layer 16 is such that the influence of impurity diffusion from the n ⁺ low specific resistance layer 11 is almost eliminated. That is, the thickness of the n buffer layer 16 is thicker than the diffusion length of the n-type impurity diffused from the n ⁺ low specific resistance layer 11.

FIG. 2 is a diagram showing the influence of impurities diffused from the n ⁺ low specific resistance layer 11 by the heat treatment. In FIG. 2, a region deeper than 8 μm corresponds to the n ⁺ low specific resistance layer 11, and a region shallower than 8 μm corresponds to the n buffer layer 16. FIG. 2 shows that the impurity diffusion length is about 6.3 μm. Thus, if the thickness of the n buffer layer 16 is 8 μm or more, the thermal diffusion of impurities from the n ⁺ low specific resistance layer 11 can be stopped by the n buffer layer 16.

  FIG. 3 is a characteristic diagram showing the relationship between the thickness of the n buffer layer 16 and the breakdown voltage and on-resistance. From FIG. 3, when the thickness of the n buffer layer 16 is 10 μm or more, the increase in breakdown voltage is saturated and the breakdown voltage hardly changes. On the other hand, since the on-resistance continuously increases monotonically as the n buffer layer 16 becomes thicker, it is appropriate that the thickness of the n buffer layer 16 is 10 μm or less.

As an example, the size and concentration of each part of a MOSFET having a withstand voltage class of 600 V are 2 × 10 ¹⁸ cm ⁻³ in the n ⁺ low resistivity layer 11. The depth of the parallel pn layer 12 is 42 μm, and both the p-type semiconductor region 13 and the n-type semiconductor region 14 are 5 μm wide and have a concentration of 4.5 × 10 ¹⁵ cm ⁻³ . The thickness of the n buffer layer 16 is 8 μm, and its concentration is 6 × 10 ¹⁵ cm ⁻³ where the influence of impurity diffusion from the n ⁺ low resistivity layer 11 is sufficiently small (see FIG. 2). .

FIG. 4 is a diagram showing the impurity concentration distribution in the depth direction of the cross section shown in FIG. 1. FIG. 4A shows the surface p 1 of the parallel pn layer 12 through the p-type semiconductor region 13 of the parallel pn layer 12. FIG. 7B shows the impurity concentration distribution of p1-p2 reaching the back surface p2 of the n ⁺ low specific resistance layer 11, and FIG. ⁺ The impurity concentration distribution of n1-n2 reaching the back surface n2 of the low specific resistance layer 11 is shown.

As shown in FIG. 4, by increasing the thickness of the n buffer layer 16 to some extent (8 to 10 μm), the influence of impurity diffusion from the n ⁺ low resistivity layer 11 can be sufficiently reduced by the n buffer layer 16. . That is, impurities diffused from the n ⁺ low specific resistance layer 11 can be prevented from reaching the parallel pn layer 12.

  Therefore, according to the first embodiment, it is possible to prevent the effective length of the parallel pn layer 12 from being shortened by the high-temperature heat treatment, and thus it is possible to prevent the breakdown voltage from being lowered. However, in the first embodiment, since most of the breakdown voltage of the MOSFET is held by the parallel pn layer 12, the n buffer layer 16 is thin enough to hardly hold the breakdown voltage and hardly contribute to the improvement of the reverse recovery resistance. In this respect, the semiconductor device of the first embodiment is different from the invention of Patent Document 3 or 4.

Embodiment 2. FIG.
5 to 10 sequentially show the cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the second embodiment. First, as shown in FIG. 5, an n-type low-resistance silicon substrate having, for example, a (100) plane or a plane equivalent thereto and an impurity concentration of, for example, antimony is about 2 × 10 ¹⁸ cm ^−3. (N ⁺ substrate) is prepared. This n ⁺ substrate becomes the n ⁺ low specific resistance layer 11. Then, an n-type semiconductor 31 having a concentration of about 6 × 10 ¹⁵ cm ⁻³ is epitaxially grown on the n ⁺ substrate (n ⁺ low specific resistance layer 11) to a thickness of about 50 μm, for example.

  Next, as shown in FIG. 6, an insulating film having a thickness of 1.6 μm or more, for example, 2.4 μm, for example, an oxide film (or a nitride film or the like) is formed on the surface of the n-type semiconductor 31. The thickness of the oxide film (or nitride film or the like) is determined even after the trench 33 having a depth of 42 μm, for example, is formed based on the selectivity between the oxide film (or nitride film or the like) and silicon. Alternatively, it is set such that a nitride film or the like remains. Subsequently, the oxide film (or nitride film or the like) is patterned by lithography to form a hard mask 32 for forming trenches.

The width of the oxide film (or nitride film or the like) portion and the opening portion of the hard mask 32 is, for example, 5 μm. That is, for example, hard masks 32 having a width of 5 μm are arranged at intervals of 5 μm. Subsequently, for example, by dry etching, a trench 33 having a depth of, for example, about 42 μm is formed in the n-type semiconductor 31 so that the surface orientation of the trench side wall is, for example, the (010) plane or a plane equivalent thereto. The hard mask 32 is patterned so that the trench 33 having such a plane orientation is formed. After the trench formation, the portion of the n-type semiconductor 31 remaining between the trenches becomes the n-type semiconductor region 14 of the parallel pn layer 12. The portion between the bottom of the trench 33 and the n ⁺ low resistivity layer 11 becomes the n buffer layer 16.

Next, as shown in FIG. 7, a boron-doped p-type semiconductor is epitaxially grown in the trench 33, and the trench 33 is filled with a p-type semiconductor having a concentration of about 6 × 10 ¹⁵ cm ^−3, for example. At this time, the p-type semiconductor is grown with a film thickness of ½ or more of the width of the trench 33. For example, the epitaxial growth is performed in the time required for the growth of a semiconductor film having a thickness of 3 μm on the plane. Thereby, the inside of the trench 33 can be completely buried without generating a void or the like. The p-type semiconductor buried in the trench 33 becomes the p-type semiconductor region 13 of the parallel pn layer 12.

  Next, as shown in FIG. 8, polishing such as CMP (chemical mechanical polishing) is performed using the oxide film or the like of the hard mask 32 as a polishing stopper, and silicon formed on the hard mask 32 by epitaxial growth of the previous p-type semiconductor is performed. Remove the layer. Next, as shown in FIG. 9, the hard mask 32 is removed. And as shown in FIG. 10, the surface of the exposed parallel pn layer 12 is mirror-polished, and the unevenness | corrugation of the surface is eliminated.

The mirror polishing amount here is, for example, about 1.0 μm. This is because the thickness of the oxide film remaining after polishing using the oxide film of the hard mask 32 as a polishing stopper is about 0.5 μm. Therefore, the final length of the parallel pn layer 12 in the depth direction is about 41 μm. The surface of the parallel pn layer 12 may be finished to a mirror surface by polishing the epitaxial growth layer of the p-type semiconductor and the oxide film of the hard mask 32 at the same time. Next, the MOS structure 15 and the breakdown voltage structure are formed on the surface of the parallel pn layer 12, and the drain electrode 17 is formed on the back surface of the n ⁺ low specific resistance layer 11, thereby completing the MOSFET having the configuration shown in FIG.

According to the second embodiment, n ⁺ on the low resistivity layer 11 among the layers of n-type semiconductor 31 is epitaxially grown, the region of a thickness of about 8μm sandwiched bottom and n ⁺ low resistivity layer 11 of the trench 33 Becomes the buffer layer 16. As a result, it is possible to prevent impurities diffused from the n ⁺ low specific resistance layer 11 from diffusing up to the parallel pn layer 12, so that the effective length of the final parallel pn layer 12 is maintained at the length immediately after the trench formation. Be drunk. Accordingly, since the depth of the trench 33 necessary for ensuring the withstand voltage can be reduced, processes such as trench etching and trench-embedded epitaxial growth can be facilitated. In addition, since the time required for trench etching is shortened, the manufacturing cost can be reduced.

Embodiment 3 FIG.
FIGS. 11 to 16 sequentially show cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the third embodiment. First, as shown in FIG. 11, an n-type low resistance silicon substrate (n ⁺ substrate) to be the n ⁺ low specific resistance layer 11 is prepared as in the second embodiment. Then, an n-type semiconductor having a concentration of about 1 × 10 ¹⁶ cm ⁻³ is epitaxially grown on the n ⁺ substrate (n ⁺ low specific resistance layer 11) to a thickness of about 8 μm, for example. This n-type semiconductor layer becomes the n buffer layer 16.

Subsequently, an n-type semiconductor 31 having a concentration of about 6 × 10 ¹⁵ cm ⁻³ is epitaxially grown on the n buffer layer 16 to a thickness of about 42 μm, for example. At that time, the n-type semiconductor to be the n buffer layer 16 and the n-type semiconductor 31 on the n-type semiconductor have different concentrations, but they are continuously grown by changing the gas concentration ratio supplied into the chamber during one epitaxial growth process. You may let them. The subsequent steps are the same as in the second embodiment, and the cross sections in FIGS. 12, 13, 14, 15 and 16 are respectively the same as those in the second embodiment, as shown in FIGS. 6, 7, 8, 8 and 9. This corresponds to the configuration of each cross section of FIG. According to the third embodiment, since the n buffer layer 16 having a thickness of about 8 μm is formed, the same effect as in the second embodiment can be obtained.

Embodiment 4 FIG.
17 to 22 sequentially show the cross-sectional configurations of MOSFETs being manufactured according to the manufacturing method according to the fourth embodiment. First, as shown in FIG. 17, an n-type low resistance silicon substrate (n ⁺ substrate) to be the n ⁺ low specific resistance layer 11 is prepared as in the second embodiment. Then, on the n ⁺ substrate (n ⁺ low specific resistance layer 11), the first n-type semiconductor 34 having a concentration of about 1 × 10 ¹⁶ cm ⁻³ is epitaxially grown to a thickness of about 4 μm, for example. The layer of the first n-type semiconductor 34 becomes a part of the n buffer layer 16.

Subsequently, on the first n-type semiconductor 34, a second n-type semiconductor 31 having a concentration of about 6 × 10 ¹⁵ cm ⁻³ is epitaxially grown to a thickness of about 46 μm, for example. The second n-type semiconductor 31 and the first n-type semiconductor 34 epitaxially grown before the second n-type semiconductor 31 are continuously grown by changing the supply gas concentration ratio into the chamber during one epitaxial growth process. Also good. The subsequent steps are the same as in the second embodiment, but as shown in FIG. 18, about 4 μm sandwiched between the bottom of the trench 33 and the first n-type semiconductor 34 in the layer of the second n-type semiconductor 31. The region 35 having a thickness of 2 becomes a part of the buffer layer 16.

  18, 19, 20, 21, and 22 correspond to the configurations of the cross sections of FIGS. 6, 7, 8, 9, and 10 of the second embodiment, respectively. According to the fourth embodiment, a region having a thickness of about 8 μm is formed by combining a region 35 having a thickness of about 4 μm among the layers of the first n-type semiconductor 34 having a thickness of about 4 μm and the second n-type semiconductor 31. Since it becomes the n buffer layer 16, the same effect as in the second embodiment is obtained.

  As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made. For example, the dimensions and concentrations described in the embodiments are examples, and the present invention is not limited to these values. In each embodiment, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. It holds.

  As described above, the semiconductor device and the manufacturing method thereof according to the present invention are useful for a high-power semiconductor device, and in particular, increase the breakdown voltage and increase the voltage of a MOSFET, IGBT, bipolar transistor, or the like having a parallel pn layer in the drift portion. It is suitable for a semiconductor device that can achieve both current capacity.

2 is a cross-sectional view showing a configuration of an active part of the semiconductor device according to the first embodiment; FIG. It is a figure which shows the mode of the diffusion of the impurity from the low specific resistance layer by heat processing. It is a characteristic view showing the relationship between the thickness of the buffer layer, withstand voltage and on-resistance. FIG. 3 is a diagram illustrating an impurity concentration distribution in a depth direction of the semiconductor device according to the first embodiment; FIG. 6 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the second embodiment; FIG. 6 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the second embodiment; FIG. 6 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the second embodiment; FIG. 6 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the second embodiment; FIG. 6 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the second embodiment; FIG. 6 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the second embodiment; FIG. 10 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the third embodiment; FIG. 10 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the third embodiment; FIG. 10 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the third embodiment; FIG. 10 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the third embodiment; FIG. 10 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the third embodiment; FIG. 10 is a cross-sectional view showing a semiconductor device being manufactured by the manufacturing method according to the third embodiment; FIG. 6 is a sectional view showing a semiconductor device being manufactured by the manufacturing method according to the fourth embodiment; FIG. 6 is a sectional view showing a semiconductor device being manufactured by the manufacturing method according to the fourth embodiment; FIG. 6 is a sectional view showing a semiconductor device being manufactured by the manufacturing method according to the fourth embodiment; FIG. 6 is a sectional view showing a semiconductor device being manufactured by the manufacturing method according to the fourth embodiment; FIG. 6 is a sectional view showing a semiconductor device being manufactured by the manufacturing method according to the fourth embodiment; FIG. 6 is a sectional view showing a semiconductor device being manufactured by the manufacturing method according to the fourth embodiment; It is sectional drawing which shows the principal part of the conventional semiconductor device. It is sectional drawing which shows the principal part of the conventional semiconductor device. It is a figure which shows the impurity concentration distribution of the depth direction of the conventional semiconductor device.

Explanation of symbols

11 n ⁺ low specific resistance layer 12 parallel pn layer 13 p-type semiconductor region 14 n-type semiconductor region 16 n buffer layer 31, 34 n-type semiconductor 33 trench

Claims (9)

A semiconductor device having a parallel pn layer in which a first conductivity type semiconductor region and a second conductivity type semiconductor region are alternately and repeatedly joined on a first conductivity type low specific resistance layer,
Between the low specific resistance layer and the parallel pn layer, there is a first conductivity type buffer layer having an impurity concentration lower than that of the low specific resistance layer, and the buffer layer is the low specific resistance layer during high temperature processing. The semiconductor device has a thickness that is longer than a diffusion length when the impurity therein thermally diffuses in the buffer layer toward the parallel pn layer.   The semiconductor device according to claim 1, wherein the buffer layer has a thickness of 8 μm or more.   The semiconductor device according to claim 1, wherein a thickness of the buffer layer is 10 μm or less. A first step of epitaxially growing a first conductivity type semiconductor on the first conductivity type low specific resistance layer;
A second step of forming, in the epitaxial growth layer of the first conductivity type semiconductor, a plurality of trenches shallower than the thickness of the epitaxial growth layer at predetermined intervals;
A third step of filling the trench by epitaxial growth of a second conductivity type semiconductor;
A fourth step of flattening by polishing the surface of the parallel pn layer comprising the first conductive type semiconductor region remaining between the trenches and the second conductive type semiconductor region embedded in the trench;
A method for manufacturing a semiconductor device, comprising: A first conductivity type semiconductor is epitaxially grown on the first conductivity type low specific resistance layer with a first specific resistance, and then the first conductivity type semiconductor is epitaxially grown on the first specific resistance epitaxial growth layer with a second specific resistance. A first step of epitaxial growth;
A second step of forming a plurality of trenches at predetermined intervals in the epitaxial growth layer of the first conductivity type semiconductor;
A third step of filling the trench by epitaxial growth of a second conductivity type semiconductor;
A fourth step of flattening the surface of the parallel pn layer comprising the first conductive type semiconductor region remaining between the trenches and the second conductive type semiconductor region embedded in the trenches by polishing;
A method for manufacturing a semiconductor device, comprising:   By changing the gas concentration ratio supplied into the chamber for epitaxial growth during the first step, the epitaxial growth of the first specific resistance and the epitaxial growth of the second specific resistance are continuously performed in the same chamber. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the method is performed.   7. The method of manufacturing a semiconductor device according to claim 5, wherein the first specific resistance is lower than the second specific resistance and higher than a specific resistance of the low specific resistance layer.   The method for manufacturing a semiconductor device according to claim 5, wherein in the second step, a trench having the same depth as the thickness of the epitaxial growth layer having the second specific resistance is formed. .   8. The method of manufacturing a semiconductor device according to claim 5, wherein a trench shallower than the thickness of the epitaxial growth layer having the second specific resistance is formed in the second step.

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