JP2006216717A - Wafer level electro-optical semiconductor assembly structure and its manufacturing method - Google Patents

Wafer level electro-optical semiconductor assembly structure and its manufacturing method Download PDF

Info

Publication number
JP2006216717A
JP2006216717A JP2005026967A JP2005026967A JP2006216717A JP 2006216717 A JP2006216717 A JP 2006216717A JP 2005026967 A JP2005026967 A JP 2005026967A JP 2005026967 A JP2005026967 A JP 2005026967A JP 2006216717 A JP2006216717 A JP 2006216717A
Authority
JP
Japan
Prior art keywords
electro
wafer
optic semiconductor
assembly structure
optic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2005026967A
Other languages
Japanese (ja)
Inventor
Bily Wang
ビリー ワング
Jonnie Chuang
ジョニー チュアング
Chuan-Fa Lin
チュアン−ファ リン
Chi-Wen Hung
チ−ウェン ユング
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Harvatek Corp
Original Assignee
Harvatek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Harvatek Corp filed Critical Harvatek Corp
Priority to JP2005026967A priority Critical patent/JP2006216717A/en
Publication of JP2006216717A publication Critical patent/JP2006216717A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12041—LED

Landscapes

  • Led Device Packages (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein the conventional light-emitting diode sealing structure has an influence on the sealing size and optional functions in actual application, and also gives an adverse impact on a sealing yield since the entire size is too large, and there is a lack of precision and an additional circuit has too large a volume. <P>SOLUTION: The structure includes a wafer (10) which has a front surface and a rear surface, with the front surface having predetermined positions (18) for joining coated crystal grains; an electro-optical semiconductor crystal grain (12) having crystal grain contacts (11) for jointing the crystal grain to a predetermined positions (18) on the front surface of the wafer (10); and a conductive material (13) which is located on the front surface of the wafer (10) so as to connect the electro-optical semiconductor crystal grain (12) to the wafer (10). <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明はウエハーレベル電気光学半導体組立構造に関し、従来の電気光学半導体結晶粒封止技術を改善する能力を有し、ペーストをウエハーの正面で塗布する方法により、銀ペーストを塗布しかつ半田付けペーストをウエハー上に印刷し、スクリーン印刷または鋼板印刷方式で行うことができ、ボンディング（被覆）、ワイヤボンディング、封止とダイシングを行い、その後、従来の結晶粒封止技術生産ラインを通過し、結晶粒をウエハーの基材上に設置するため、その細線（ｆｉｎｅ ｌｉｎｅ）の性能が従来のＰＣＢよりも優れ、ディバイスの特性を向上するようにディバイスの密度を縮小し、ひいては良品率をもっと向上でき、工数コストを節約し、生産プロセスを簡素化でき、生産効率を向上し、低コスト化による改善を伴う大きな効果を有する発明である。特に、大寸法の発光ダイオード結晶粒やセンサー封止生産ラインの場合に適用される。   The present invention relates to a wafer level electro-optic semiconductor assembly structure, which has the ability to improve the conventional electro-optic semiconductor crystal grain sealing technology, and applies a silver paste and solder paste by a method of applying the paste on the front surface of the wafer. Can be printed on the wafer, screen printing or steel plate printing method, bonding (coating), wire bonding, sealing and dicing, then passed through the conventional crystal grain sealing technology production line, crystal Since the grains are placed on the substrate of the wafer, the performance of the fine line is superior to that of the conventional PCB, and the density of the device can be reduced to improve the device characteristics, and thus the yield rate can be further improved. , Saves man-hour costs, simplifies production process, improves production efficiency, and greatly improves with lower costs Is an invention having the results. In particular, the present invention is applied to large-sized light emitting diode crystal grains and sensor sealed production lines.

一般の関連する業界では知られているように、電気光学半導体結晶粒封止生産ラインの量産能力の向上は、近年、各種の結晶粒封止関連業界およびその下請け代行業界において、積極的に研究及び生産する際の課題であり、そこで使用する技術方式が例えば生産フローの改善や新材料の使用などを各種の結晶粒封止に適用できる場合に、コスト低減および工数削減の要求を達成できる。しかし、生産フローの改善が非常に重要な目前の改善項目と言え、結晶粒封止の機器が精密機械であることが多いため、わずかな変更があればいつもコストが増加するが、固有の機器特性に対応して周辺フローの改善を行うことによって、コストがより低くなり、かつ生産フローの改善効果が著しい。   As is known in the general related industry, the improvement of the mass production capacity of the electro-optic semiconductor grain sealing production line has been actively researched in various grain sealing related industries and subcontracting agency industries in recent years. When the technical method used there is applicable to, for example, improvement of production flow or use of new materials for various types of crystal grain sealing, the demand for cost reduction and man-hour reduction can be achieved. However, improvement of the production flow is a very important improvement item in the near future, and since the grain sealing equipment is often a precision machine, a slight change always increases the cost. By improving the peripheral flow in accordance with the characteristics, the cost becomes lower and the improvement effect of the production flow is remarkable.

ＩＣ基板分野（ＢＧＡ（ボールグリッドアレー）、ＣＳＰ（チップサイズパッケージ）とＦｌｉｐ Ｃｈｉｐ（フリップチップ）の３大類を含む）において、なかでもＩＣ基板は、近年成長幅が大きく、近年台湾、韓国と中国大陸などの地域に積層基板の生産量を積極的に拡充し、かつ、レーザー穴あけ機設備を投資し続けており、基板の生産上における競争力を増加させている。将来における携帯式電子製品の軽薄短小化の需要傾向のために、回路基板は細線化およびビア技術へ向けて発展し、小型封止技術の進歩を加え、高品位ＩＣ基板の需要も向上し、ひいては小寸法結晶粒封止技術の広範な進歩が予測される。すなわち、携帯電話基板、通信製品および自動車産業の需要を満たすために、将来にわたり小寸法結晶粒封止が再び発展し続けるものと予期される。   In the field of IC substrates (including three types of BGA (Ball Grid Array), CSP (Chip Size Package) and Flip Chip (Flip Chip)), IC substrates have grown greatly in recent years, and in recent years Taiwan, Korea and China. Actively expanding the production volume of multilayer substrates in continents and other regions, and continuing to invest in laser drilling equipment, increasing the competitiveness in substrate production. Due to the trend of demand for lighter, thinner and smaller portable electronic products in the future, circuit boards have evolved toward thinning and via technology, and in addition to advances in miniature encapsulation technology, the demand for high-quality IC substrates has also improved. As a result, a wide range of advances in small-size grain sealing technology is expected. That is, it is expected that small sized grain seals will continue to evolve again in the future to meet the demands of mobile phone substrates, communications products and the automotive industry.

図６は従来の発光ダイオード封止構造１ａであり、基材１０ａに発光ダイオード結晶粒１２ａを貼付け、またリード線１４ａに接続し、封止材料１６ａで封止される構造であり、特に組立時に、従来の発光ダイオード封止構造１ａは、より煩雑な製造プロセスの問題および効率（工程を簡単化する）の問題に直面し、例えば基材を貼付ける時に、全体の寸法過大や精度不足に加え、付加回路（基材上の回路）の体積があまり大きく、実際の応用時に、封止寸法と付加機能に影響を及ぼし、また封止の良品率に対しても、悪い影響を及ぼす。従って、封止寸法の縮小に寄与しかつ高機能を付加しやすく精度が制御されやすい封止結構を研究する必要があり、実際、それは応用上の要求と一致する。さらに、図７に示すように、従来のＲＧＢの３色結晶粒（１１１−１１３）が発光して白光を混成する際には、封止基材と回路設計により細線化できないという制限から、当該ＲＧＢの３色結晶粒（１１１−１１３）が近接できなく、結晶粒間の距離が遠く分散する。同様な状況がフォトセンサー封止領域にも発生する。   FIG. 6 shows a conventional light-emitting diode sealing structure 1a, in which light-emitting diode crystal grains 12a are attached to a base material 10a, connected to a lead wire 14a, and sealed with a sealing material 16a. The conventional light emitting diode sealing structure 1a faces more complicated manufacturing process problems and efficiency (simplifies the process). For example, when pasting a base material, the overall size is too large and the accuracy is insufficient. The volume of the additional circuit (circuit on the substrate) is so large that it affects the sealing dimensions and additional functions during actual application, and also adversely affects the yield rate of sealing. Therefore, it is necessary to study a sealing structure that contributes to the reduction of the sealing dimension and that is easy to add a high function and whose accuracy is easily controlled. In fact, it matches the application requirements. Furthermore, as shown in FIG. 7, when the conventional RGB three-color crystal grains (111-113) emit light and mix white light, the restriction cannot be made thin due to the sealing substrate and circuit design. The RGB three-color crystal grains (111-113) cannot be close to each other, and the distances between the crystal grains are long and dispersed. A similar situation occurs in the photosensor sealing region.

そこで、生産のプロセスを改善でき且つ高品質および高効率を連続的に確保できるために、実際の状態に対応して新たな生産フローと新たな構造を研究し、印刷導電ペースト方式により、ウエハー上に導電ペーストを印刷方式で直接に塗布し、或いは導電バンプをレイアウトし、さらに電気光学半導体結晶粒をウエハー上に貼付ける必要がある。すると、封止生産ラインにおいて、組立の品質と機能が向上するが、電気光学半導体結晶粒をウエハーに貼付けるのは、その貼付け方式または印刷方式を使用して、ペーストを塗布し或いは導電バンプをレイアウトするため、アラインメント精度が高く、コストが低く、コストと良品率を共に向上でき、ひいては各周辺機具の生産にも対応し、また工業エンジニアリングにおけるフロー配置原理と符合することから、より便利な技術を見出し、本発明は各方面と各種の状況を処理する能力を具備でき、従って本発明を研究して前述の要求を達成する。特に大寸法の電気光学半導体（発光ダイオード、フォトセンサーやパワーチップ）が本発明に適用でき、大寸法の電気光学半導体は、予めウエハー中に所要のモジュール回路を注入でき、電気光学装置体積を縮小するが、他の種類の配合構成は、半導体結晶粒を応用しまた当該電気光学半導体の付近に被覆することに対応できる。ほかに、熱の集積による熱効果があるため、大寸法の場合、従来の回路基板（例えばエポキシ基板）では放熱効果が悪く、製品の寿命に対し、ある程度の影響を及ぼす。   Therefore, in order to be able to improve the production process and continuously ensure high quality and high efficiency, research on a new production flow and a new structure corresponding to the actual state, and on the wafer by the printed conductive paste method It is necessary to directly apply a conductive paste by a printing method or to lay out conductive bumps and to paste electro-optic semiconductor crystal grains on the wafer. Then, in the sealed production line, the quality and function of the assembly are improved, but the electro-optic semiconductor crystal grains are pasted on the wafer by applying the paste or the conductive bumps using the pasting method or the printing method. Because the layout is high, the alignment accuracy is high, the cost is low, the cost and the yield rate can be improved, and the production of each peripheral equipment is supported. The present invention can be equipped with the ability to handle various situations and various situations, and thus the present invention is studied to achieve the aforementioned needs. In particular, large-sized electro-optic semiconductors (light-emitting diodes, photosensors, and power chips) can be applied to the present invention. Large-sized electro-optic semiconductors can inject required module circuits into a wafer in advance, reducing the volume of electro-optic devices However, other types of blending configurations can accommodate the application of semiconductor crystal grains and coating near the electro-optic semiconductor. In addition, since there is a thermal effect due to heat integration, in the case of a large size, a conventional circuit board (for example, an epoxy board) has a poor heat dissipation effect and has some influence on the life of the product.

発明者は前述の欠点を減じるため、鋭意研究をし、かつ学理の運用に対応し、設計が合理的でまた広範かつ有効に前述の欠点を改善する本発明を提出する。   In order to reduce the above-mentioned drawbacks, the inventor submits the present invention which has been intensively studied and corresponds to the operation of science, and the design is rational and extensively and effectively improves the above-mentioned drawbacks.

すなわち、本発明の主要な目的は、ウエハーレベル電気光学半導体組立構造、即ち新たな生産フロー方法を生成する構造を提供し、そして、コストの安価な構成および対応関連するより便利な専用周辺自動機器により実施でき、電気光学半導体結晶粒封止製品の応用場所に使用でき、低コストかつ高品質の効果を提供できるものである。   That is, the main object of the present invention is to provide a wafer level electro-optic semiconductor assembly structure, i.e. a structure for generating a new production flow method, and a cheaper configuration and corresponding more convenient dedicated peripheral automation equipment. And can be used in an application place of an electro-optic semiconductor crystal grain sealing product, and can provide a low-cost and high-quality effect.

本発明の次の目的は、ウエハーレベル電気光学半導体組立構造を提供し、細線とマイクロ組立構造を提供できるものである。   Another object of the present invention is to provide a wafer level electro-optic semiconductor assembly structure, and to provide a fine wire and a micro assembly structure.

本発明の他の目的は、ウエハーレベル電気光学半導体組立構造を提供し、電気光学装置体積を縮小するように予めウエハー中に必要なモジュール回路を注入でき、単一のチップを、モジュール化チップとしたり直接に封止してディバイスにすることができるものである。   Another object of the present invention is to provide a wafer level electro-optic semiconductor assembly structure, in which necessary module circuits can be injected into the wafer in advance to reduce the electro-optic device volume, and a single chip is used as a modular chip. Or can be directly sealed to form a device.

本発明のさらに他の目的は、ウエハーレベル電気光学半導体組立構造を提供し、ウエハー基板を利用して良好な放熱性を提供するものである。   Still another object of the present invention is to provide a wafer level electro-optic semiconductor assembly structure and to provide good heat dissipation using a wafer substrate.

前述の目的を達成するために、本発明は全枚数のウエハーに導電物質を印刷方式により塗布でき、従来の基材寸法の縮小の困難さと回路機能の弱化のような問題を避け、電気光学半導体結晶粒封止専用機器の使用に対応して結晶粒封止を完了し、実際の応用に寄与する結晶粒封止構造をより経済的となるように定義し、また従来の技術よりも実用上の価値を有する。そして本発明は、ＥＳＤ（Ｅｌｅｃｔｒｏ Ｓｔａｔｉｃ Ｄｉｓｃｈａｒｇｅ、静電放電保護）機能付加保護能力を更に有し、ひいては過電圧保護、電圧安定度、電流安定度、ノイズフィルタなどの機能を含むことを可能にし、予めウエハー中に注入できる。   In order to achieve the above-mentioned object, the present invention can apply a conductive material to all the wafers by a printing method, avoids problems such as conventional difficulty in reducing the size of a substrate and weakening of circuit function, and avoids problems such as electro-optic semiconductors. Complete crystal grain sealing in response to the use of dedicated equipment for crystal grain sealing, define the crystal grain sealing structure that contributes to actual applications to be more economical, and is more practical than conventional technology Of value. The present invention further has an ESD (Electro Static Discharge) function addition protection capability, and further includes functions such as overvoltage protection, voltage stability, current stability, and noise filter. Can be injected into the wafer.

本発明の構造は、正面と裏面を有しかつ当該正面が被覆結晶粒接合の予定位置を有するウエハーと、結晶粒コンタクトを有し当該ウエハーの正面の予定位置に接合しあうようにする電気光学半導体結晶粒と、当該ウエハーの正面に位置し当該電気光学半導体結晶粒および当該ウエハーを接続するようにする導電材料とを含む。
本発明の構造の製造方法は、被覆結晶粒接合の予定位置を備えるウエハーを用意すること、導電材料を当該予定位置に塗布すること、電気光学半導体結晶粒を当該ウエハーの導電材料上に積層すること、当該電気光学半導体を高分子材料で封止して半製品を形成すること、および当該高分子材料封止後の半製品を切削して電気光学半導体組立構造になることのようなステップを含む。 The structure of the present invention includes a wafer having a front surface and a back surface, the front surface having a predetermined position for covering crystal grain bonding, and an electro-optic that has a crystal grain contact and is bonded to the predetermined position on the front surface of the wafer. A semiconductor crystal grain; and a conductive material positioned in front of the wafer and connecting the electro-optic semiconductor crystal grain and the wafer.
The structure manufacturing method of the present invention includes preparing a wafer having a predetermined position for covering crystal grain bonding, applying a conductive material to the predetermined position, and laminating electro-optic semiconductor crystal grains on the conductive material of the wafer. Steps such as sealing the electro-optic semiconductor with a polymer material to form a semi-finished product and cutting the semi-finished product after sealing the polymer material into an electro-optic semiconductor assembly structure. Including.

本発明の特徴および技術内容をもっと理解できるように、以下の本発明に関する詳細な説明を参照するものであるが、記載する内容は、参考と説明用にだけ供し、本発明を限定するものではない。   For a better understanding of the features and technical contents of the present invention, reference is made to the following detailed description of the invention, which is provided for reference and description only and is not intended to limit the invention. Absent.

本発明は以下のメリットを有する。すなわち、
１．アラインメントの精度と良品率の向上を図ることができる。すなわち、本発明はウエハーに導電材を印刷しまた電気光学半導体結晶粒（発光ダイオード）をウエハー上にラミネートすることにより実施し、アラインメントの誤差を減少でき、ひいては取出し機の良品率を向上し、経済的な効果を達成する。
２．封止寸法の縮小を図ることができる。すなわち、電気光学半導体結晶粒（発光ダイオード）はウエハーにラミネートされ、本発明の封止寸法がウエハーレベル封止と見なすことを可能にし、封止寸法がより小さい。
３．工程機器設備の低コストを図ることができる。すなわち、工程は適切に実施され、設備のコストを自然に減少して設備を取得しやすい（例えば導電ペーストを印刷する設備）。
４．機能の向上を図ることができる。すなわち、ウエハーの集積回路に機能を予め注入でき、例えば過電流を増加してダイオードを保護する。 The present invention has the following merits. That is,
1. It is possible to improve alignment accuracy and yield rate. That is, the present invention is carried out by printing a conductive material on a wafer and laminating electro-optic semiconductor crystal grains (light-emitting diodes) on the wafer, thereby reducing alignment errors and thus improving the yield rate of the unloader. Achieve economic benefits.
2. The sealing dimension can be reduced. That is, the electro-optic semiconductor crystal grains (light emitting diodes) are laminated to the wafer, allowing the sealing dimensions of the present invention to be considered wafer level sealing, with smaller sealing dimensions.
3. Low cost of process equipment can be achieved. That is, the process is appropriately performed, and it is easy to acquire equipment by reducing the cost of equipment naturally (for example, equipment for printing a conductive paste).
4). The function can be improved. That is, functions can be pre-injected into the integrated circuit on the wafer, for example, increasing the overcurrent to protect the diode.

本発明の動作原理は以下の記述を参照するものである。本発明は、導電ペーストを利用してウエハーの上に印刷し塗布したり、金（または錫）バンプを被覆するステップであり、電気光学半導体が結晶粒の貼付けをウエハー上に実施するための生産フローである。ひいては、簡単な方式で述べられる本発明のフローは、即ちウエハーの製作、導電材料の設置、電気光学半導体結晶粒をウエハー上に積層すること（ワイヤボンディングと略することができ、一般は金線である）、封止およびダイシングであり、かつ、印刷アラインメントにより累積アラインメント誤差を減少し、アラインメント精度に寄与するため、電気光学半導体結晶粒はウエハーに対し、位置アラインメントが容易であり、周辺対応補助機器を加えてコストを節約するように実際の応用に寄与する結晶粒封止生産システムを定義するものである。また、ウエハー上に、予め簡単な電圧安定ダイオード（例えばｚｅｎｅｒ ｄｉｏｄｅ、ゼナダイオード）を設けて過電圧保護、電流安定度、制御、ノイズフィルタ機能を付与したり、静電防止構造をウエハー中に注入でき、電気光学半導体全体の機能の向上に寄与する。   The operating principle of the present invention refers to the following description. The present invention is a step in which a conductive paste is printed and applied on a wafer or a gold (or tin) bump is coated, and an electro-optic semiconductor is produced for applying crystal grains on a wafer. It is a flow. As a result, the flow of the present invention described in a simple manner is, that is, the fabrication of the wafer, the installation of the conductive material, and the lamination of the electro-optic semiconductor crystal grains on the wafer (which can be abbreviated as wire bonding, generally a gold wire) The electro-optic semiconductor crystal grains are easy to position align with the wafer because it is sealing and dicing, and the cumulative alignment error is reduced by printing alignment, contributing to alignment accuracy. It defines a grain-encapsulated production system that contributes to actual application so as to save cost by adding equipment. In addition, a simple voltage stabilization diode (eg, Zener diode) can be provided on the wafer in advance to provide overvoltage protection, current stability, control and noise filter functions, and an antistatic structure can be injected into the wafer. This contributes to improving the function of the entire electro-optic semiconductor.

本発明の構造は、正面と裏面を有するウエハー（当該ウエハーの当該正面が被覆結晶粒接合の予定位置を有する）と、結晶粒コンタクトを有し当該ウエハーの正面の予定位置に接合しあうようにする電気光学半導体結晶粒（単にパワー半導体や発光ダイオードできる）と、当該ウエハーの正面に位置する導電材料とを含む。当該導電材料は、当該電気光学半導体と当該ウエハーを接続する。当該電気光学半導体は、発光ダイオードまたは画像センサーとすることができる。   The structure of the present invention is such that a wafer having a front surface and a back surface (the front surface of the wafer has a predetermined position for covering crystal grain bonding) and a crystal grain contact are bonded to the predetermined position on the front surface of the wafer. An electro-optic semiconductor crystal grain (which can simply be a power semiconductor or a light-emitting diode) and a conductive material located in front of the wafer. The conductive material connects the electro-optic semiconductor and the wafer. The electro-optic semiconductor can be a light emitting diode or an image sensor.

本発明の構造の製造方法は、被覆結晶粒接合の予定位置（１８）を備えるウエハー（１０）を用意すること、導電ペースト（１３）（導電材料）を当該予定位置（１８）に塗布すること、電気光学半導体結晶粒（１２）（単にパワー半導体または発光ダイオードとすることができる）を当該ウエハー（１０）の導電ペースト（１３）上に積層すること、当該電気光学半導体結晶粒（１２）を高分子材料で封止し半製品を形成することおよび当該高分子材料封止後の半製品を切削し、電気光学半導体結晶粒の組立構造になること、のようなステップを含む。   The manufacturing method of the structure of the present invention is to prepare a wafer (10) having a predetermined position (18) for covering crystal grain bonding, and to apply a conductive paste (13) (conductive material) to the predetermined position (18). Laminating the electro-optic semiconductor crystal grains (12) (which can be simply a power semiconductor or a light-emitting diode) on the conductive paste (13) of the wafer (10); It includes steps such as encapsulating with a polymer material to form a semi-finished product and cutting the semi-finished product after encapsulating the polymer material into an assembly structure of electro-optic semiconductor crystal grains.

本発明の実施例のウエハーレベル電気光学半導体組立構造の平面図である図１を参照すると、ウエハー（１０）の正面が複数個の電気光学半導体結晶粒（１２）を有する。また、すべての電気光学半導体結晶粒（１２）とウエハー（１０）を貼付ける断面構造である図２を参照すると、正面と裏面を有しかつ当該正面がフリップチップ接合の予定位置（１８）を有するウエハー（１０）と、複数個のフリップチップコンタクト（１１）を有し当該ウエハー（１０）の正面の予定位置（１８）に接合しあうようにする当該電気光学半導体結晶粒（１２）と、当該ウエハーの正面に位置し当該電気光学半導体結晶粒（１２）と当該ウエハー（１０）を接続するようにする導電ペースト（１３）とを含む。   Referring to FIG. 1, which is a plan view of a wafer level electro-optic semiconductor assembly structure according to an embodiment of the present invention, the front surface of a wafer (10) has a plurality of electro-optic semiconductor crystal grains (12). Further, referring to FIG. 2, which is a cross-sectional structure for attaching all the electro-optic semiconductor crystal grains (12) and the wafer (10), the front surface has a front surface and a back surface, and the front surface has a predetermined position (18) for flip chip bonding. A wafer (10) having a plurality of flip-chip contacts (11), the electro-optic semiconductor crystal grains (12) being bonded to a predetermined position (18) on the front surface of the wafer (10); A conductive paste (13) located in front of the wafer and connecting the electro-optic semiconductor crystal grains (12) and the wafer (10);

図２ないし図５を参照して本発明の実施例を詳細に述べる。本実施例においては、当該ウエハーがアラインメントマーク（１７）を具備できる。当該導電ペースト（１３）は、スクリーン印刷により形成でき、鋼板印刷によっても形成でき、そして、この導電ペースト（１３）（または導電材料）の厚さは１０−５０μｍである。当該フリップチップコンタクト（１１）は、電気光学半導体結晶粒の中央、エッジまたは全面領域に位置できる。当該ウエハー（１０）の正面には、過電圧保護回路（１５）を形成しており、当該電気光学半導体結晶粒（１２）に並列して過電圧を防ぐためのものであり、当該過電圧保護回路（１５）は、２位相の過電圧保護ダイオード（１６）が直列することにより形成される。当該導電ペースト（１３）は、半田付けペーストまたは銀ペーストにより形成される。当該電気光学半導体結晶粒（１２）は、発光ダイオード方式により実施され、その設置方式が、複数の赤、緑、青の３色または紫外線、赤外線などのＲ、Ｇ、Ｂの３色の結晶粒を、特定のブロック内（図３の通り）に組合せることを可能にしている。本実施例において、３色の結晶粒がフリップチップ方式（Ｆｌｉｐ−ｃｈｉｐ）により生産でき、ＲＧＢ結晶粒のモジュールを直接に製作し、ボンディングが基材（１０’）上にワイヤボンディング方式（ｂｏｎｄｉｎｇ ｗｉｒｅ）により電気的に接続される（図４の通り）。あるいは、直接に封止してディバイスになり（図２の通り）、当該ウエハーの底部に溶接部（２２）を直接に設け、即ち直接に当該ウエハーを基材とし、ワイヤボンディングの必要がない。あるいは、例えば補助制御集積回路結晶粒をある領域内に設置して多結晶粒形式（例えば図５に示すように）を呈する。本発明は、高分子封止構造（１４）をさらに含み、当該電気光学半導体結晶粒（１２）を囲むことを可能にする。当該ウエハーの当該電気光学半導体に対する接合方式は、金属に対する金属の共晶（ｅｕｔｅｃｔｉｃ）または異なる金属の溶接接合、例えば金に対する金の共晶、錫に対する金の接合または錫に対する錫の共晶や溶接ができる。   An embodiment of the present invention will be described in detail with reference to FIGS. In this embodiment, the wafer can have an alignment mark (17). The said conductive paste (13) can be formed by screen printing, can also be formed by steel plate printing, and the thickness of this conductive paste (13) (or conductive material) is 10-50 micrometers. The flip chip contact (11) can be located at the center, edge or entire surface area of the electro-optic semiconductor crystal grains. An overvoltage protection circuit (15) is formed on the front surface of the wafer (10), and is used to prevent overvoltage in parallel with the electro-optic semiconductor crystal grains (12). The overvoltage protection circuit (15 ) Is formed by serially connecting two-phase overvoltage protection diodes (16). The conductive paste (13) is formed of a soldering paste or a silver paste. The electro-optic semiconductor crystal grain (12) is implemented by a light-emitting diode method, and the installation method is a plurality of red, green, and blue three-color crystal grains such as R, G, and B such as ultraviolet and infrared. Can be combined in a specific block (as shown in FIG. 3). In this embodiment, three color crystal grains can be produced by flip-chip method, and a module of RGB crystal grains is directly manufactured, and bonding is performed on a substrate (10 ') by a wire bonding method (bonding wire). ) For electrical connection (as shown in FIG. 4). Alternatively, the device is directly sealed to form a device (as shown in FIG. 2), and the welded portion (22) is directly provided at the bottom of the wafer, that is, the wafer is directly used as a base material, and there is no need for wire bonding. Alternatively, for example, auxiliary control integrated circuit crystal grains are placed in a certain region to exhibit a polycrystalline grain format (for example, as shown in FIG. 5). The present invention further includes a polymer encapsulating structure (14), allowing the electro-optic semiconductor crystal grain (12) to be surrounded. The method of joining the wafer to the electro-optic semiconductor may be metal eutectic to metal or welded joint of different metals, eg gold eutectic to gold, gold to tin or tin eutectic or weld to tin. Can do.

ゆえに、従来のように回路基板を封止搭載板とすると細線に限定されやすく、もっとファインピッチ化できないことに対し（従来の封止搭載板の線間の幅が０．０５ｍｍであることが多い）、本発明のようにウエハーを搭載板とすれば、線間の幅が０．００５ｍｍ以下であることを可能にし、ディバイスの寸法を大幅に縮小し、かつ、発光ダイオードについては、その発光特性を向上するために結晶粒間の距離を著しく縮小し、さらに、ウエハー基板の放熱性が従来のエポキシ樹脂基板よりも優れ、集積熱による熱効果については、放熱性能がより高く、より長いの製品寿命を提供できる。   Therefore, when a circuit board is used as a sealing mounting board as in the prior art, it is likely to be limited to fine lines, and a finer pitch cannot be achieved (the width between lines of the conventional sealing mounting board is often 0.05 mm. ) If the wafer is a mounting plate as in the present invention, the width between the lines can be 0.005 mm or less, the size of the device is greatly reduced, and the light emitting diode has its light emission characteristics. The distance between crystal grains is remarkably reduced to improve the heat resistance, and the heat dissipation of the wafer substrate is better than that of the conventional epoxy resin substrate. Can provide a lifetime.

以上の叙述は、本発明の好ましい可能な実施例にすぎず、発明者の権益を保障するように本発明の明細書または図面の内容を適用するための種々の変化構成は、同様に本発明の範囲内に含まれることを、ここに陳述する。   The above descriptions are merely preferred embodiments of the present invention, and various modifications for applying the contents of the specification or the drawings of the present invention so as to guarantee the rights of the inventor are similarly applicable to the present invention. It is stated here that it falls within the scope of

本発明の実施例のウエハーレベル電気光学半導体組立構造の平面図である。It is a top view of the wafer level electro-optic semiconductor assembly structure of the Example of this invention. 本発明のすべての電気光学半導体結晶粒とウエハーを貼付ける断面構造模式図である。It is a cross-sectional structure schematic diagram which affixes all the electro-optic semiconductor crystal grains and a wafer of this invention. 本発明がＲＧＢ結晶粒モジュールを直接に製作する平面図である。It is a top view which manufactures an RGB grain module directly by the present invention. 本発明がＲＧＢ結晶粒モジュールを直接に製作する断面構造模式図である。FIG. 3 is a schematic cross-sectional structure diagram in which the present invention directly manufactures an RGB crystal grain module. 本発明の他の実施例の平面図である。It is a top view of the other Example of this invention. 従来の発光ダイオード封止構造の断面模式図である。It is a cross-sectional schematic diagram of the conventional light emitting diode sealing structure. 従来の発光ダイオード封止構造の平面図である。It is a top view of the conventional light emitting diode sealing structure.

符号の説明Explanation of symbols

１０ ウエハー
１１ 結晶粒コンタクト
１２ 電気光学半導体結晶粒
１３ 導電材料
１４ 高分子封止構造
１８ 予定位置
２０ 特定のブロック
DESCRIPTION OF SYMBOLS 10 Wafer 11 Crystal grain contact 12 Electro-optic semiconductor crystal grain 13 Conductive material 14 Polymer sealing structure 18 Predetermined position 20 Specific block

Claims (9)

ウエハーレベル電気光学半導体組立構造において、その構造が、
正面と裏面を有しかつ当該正面が被覆結晶粒接合の予定位置（１８）を有するウエハー（１０）と、
結晶粒コンタクト（１１）を有し、当該ウエハー（１０）の正面の予定位置（１８）に接合しあうようにする電気光学半導体結晶粒（１２）と、
当該ウエハー（１０）の正面に位置し、当該電気光学半導体結晶粒（１２）及び当該ウエハー（１０）を接続するようにする導電材料（１３）とを含むことを特徴とするウエハーレベル電気光学半導体組立構造。 In the wafer level electro-optic semiconductor assembly structure, the structure is
A wafer (10) having a front surface and a back surface, the front surface having a predetermined position (18) for covering grain bonding;
An electro-optic semiconductor crystal grain (12) having a crystal grain contact (11) and joining to a predetermined position (18) on the front surface of the wafer (10);
A wafer level electro-optic semiconductor, which is located in front of the wafer (10) and includes the electro-optic semiconductor crystal grains (12) and a conductive material (13) for connecting the wafer (10). Assembly structure. 前記電気光学半導体結晶粒（１２）に対する前記ウエハー（１０）の接合方式は、金属に対する金属の共晶または異なる金属間溶接であることを特徴とする請求項１に記載のウエハーレベル電気光学半導体組立構造。   The wafer level electro-optic semiconductor assembly according to claim 1, wherein the bonding method of the wafer (10) to the electro-optic semiconductor crystal grain (12) is eutectic of metal to metal or welding between different metals. Construction. 前記導電材料（１３）は、スクリーンまたは鋼板印刷により形成されることを特徴とする請求項１に記載のウエハーレベル電気光学半導体組立構造。   The wafer level electro-optic semiconductor assembly structure according to claim 1, wherein the conductive material (13) is formed by screen or steel plate printing. 前記結晶粒コンタクト（１１）は、電気光学半導体結晶粒（１２）の中央、エッジまたは全面領域に位置することを特徴とする請求項１に記載のウエハーレベル電気光学半導体組立構造。   The wafer level electro-optic semiconductor assembly structure according to claim 1, wherein the crystal grain contact (11) is located at a center, an edge or an entire area of the electro-optic semiconductor crystal grain (12). 前記導電材料（１３）は、半田付けペーストまたは銀ペーストにより形成されることを特徴とする請求項１に記載のウエハーレベル電気光学半導体組立構造。   The wafer level electro-optic semiconductor assembly structure according to claim 1, wherein the conductive material (13) is formed of a soldering paste or a silver paste. 前記電気光学半導体結晶粒（１２）の設置方式は、複数組の赤、緑、青の３色または紫外線、赤外線などのＲＧＢ発光ダイオードを含み、ある特定のブロック（２０）内に設けられることを特徴とする請求項１に記載のウエハーレベル電気光学半導体組立構造。   The electro-optic semiconductor crystal grains (12) are installed in a specific block (20) including a plurality of sets of red, green, and blue colors or RGB light emitting diodes such as ultraviolet rays and infrared rays. 2. The wafer level electro-optic semiconductor assembly structure according to claim 1, wherein 高分子封止構造（１４）をさらに含み、前記電気光学半導体結晶粒（１２）を囲むことを特徴とする請求項１に記載のウエハーレベル電気光学半導体組立構造。   The wafer level electro-optic semiconductor assembly structure according to claim 1, further comprising a polymer sealing structure (14) and surrounding the electro-optic semiconductor crystal grains (12). ウエハーレベル電気光学半導体組立構造の製造方法において、そのステップが、
被覆結晶粒接合の予定位置（１８）を備えるウエハー（１０）を用意すること、
導電材料（１３）を当該予定位置（１８）に塗布すること、
電気光学半導体結晶粒（１２）を当該ウエハー（１０）の導電材料（１３）上に積層すること、
当該電気光学半導体結晶粒（１２）を高分子材料で封止し、半製品を形成すること、
当該高分子封止後の半製品を切削し、電気光学半導体結晶粒（１２）の組立構造になることを含むことを特徴とするウエハーレベル電気光学半導体組立構造の製造方法。 In the method of manufacturing a wafer level electro-optic semiconductor assembly structure, the steps include:
Providing a wafer (10) with a predetermined position (18) for covering grain bonding;
Applying a conductive material (13) to the expected position (18);
Laminating the electro-optic semiconductor crystal grains (12) on the conductive material (13) of the wafer (10);
Sealing the electro-optic semiconductor crystal grains (12) with a polymer material to form a semi-finished product;
A method for producing a wafer level electro-optic semiconductor assembly structure, comprising cutting the semi-finished product after the polymer encapsulation to form an assembly structure of electro-optic semiconductor crystal grains (12). 前記ウエハー（１０）は、過電圧保護、電圧安定度、電流安定度、制御、ノイズフィルタ機能または静電気防止構造を有し、該機能または構造をウエハー（１０）中に注入し、当該予定位置（１８）に接続しあうようにすることを特徴とする請求項８に記載のウエハーレベル電気光学半導体組立構造の製造方法。
The wafer (10) has overvoltage protection, voltage stability, current stability, control, noise filter function or antistatic structure, and the function or structure is injected into the wafer (10), and the predetermined position (18 9. The method of manufacturing a wafer level electro-optic semiconductor assembly structure according to claim 8, wherein the wafer level electro-optic semiconductor assembly structure is connected to each other.
JP2005026967A 2005-02-02 2005-02-02 Wafer level electro-optical semiconductor assembly structure and its manufacturing method Pending JP2006216717A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2005026967A JP2006216717A (en) 2005-02-02 2005-02-02 Wafer level electro-optical semiconductor assembly structure and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005026967A JP2006216717A (en) 2005-02-02 2005-02-02 Wafer level electro-optical semiconductor assembly structure and its manufacturing method

Publications (1)

Publication Number Publication Date
JP2006216717A true JP2006216717A (en) 2006-08-17

Family

ID=36979681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005026967A Pending JP2006216717A (en) 2005-02-02 2005-02-02 Wafer level electro-optical semiconductor assembly structure and its manufacturing method

Country Status (1)

Country Link
JP (1) JP2006216717A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101197778B1 (en) 2010-08-09 2012-11-06 엘지이노텍 주식회사 Wafer level chip scale package for electrostatic discharg protection and the manufacturing method thereof
JP2013042166A (en) * 2007-12-14 2013-02-28 Cree Inc Textured encapsulant surface in led packages
US8858004B2 (en) 2005-12-22 2014-10-14 Cree, Inc. Lighting device
US8901585B2 (en) 2003-05-01 2014-12-02 Cree, Inc. Multiple component solid state white light
US9142734B2 (en) 2003-02-26 2015-09-22 Cree, Inc. Composite white light source and method for fabricating
US9666772B2 (en) 2003-04-30 2017-05-30 Cree, Inc. High powered light emitter packages with compact optics
US10615324B2 (en) 2013-06-14 2020-04-07 Cree Huizhou Solid State Lighting Company Limited Tiny 6 pin side view surface mount LED

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9142734B2 (en) 2003-02-26 2015-09-22 Cree, Inc. Composite white light source and method for fabricating
US9666772B2 (en) 2003-04-30 2017-05-30 Cree, Inc. High powered light emitter packages with compact optics
US8901585B2 (en) 2003-05-01 2014-12-02 Cree, Inc. Multiple component solid state white light
US8858004B2 (en) 2005-12-22 2014-10-14 Cree, Inc. Lighting device
JP2013042166A (en) * 2007-12-14 2013-02-28 Cree Inc Textured encapsulant surface in led packages
US9431589B2 (en) 2007-12-14 2016-08-30 Cree, Inc. Textured encapsulant surface in LED packages
KR101197778B1 (en) 2010-08-09 2012-11-06 엘지이노텍 주식회사 Wafer level chip scale package for electrostatic discharg protection and the manufacturing method thereof
US10615324B2 (en) 2013-06-14 2020-04-07 Cree Huizhou Solid State Lighting Company Limited Tiny 6 pin side view surface mount LED

Similar Documents

Publication Publication Date Title
KR101900352B1 (en) Semiconductor device and fabrication method for same
US6552419B2 (en) Semiconductor device and liquid crystal module using the same
US6424050B1 (en) Semiconductor device
JP5096782B2 (en) Semiconductor device
US20150179623A1 (en) Method for manufacturing semiconductor device
JP2000243775A (en) Method and apparatus for prolonging fatigue lifetime of solder joint in semiconductor element
US7755188B2 (en) Method and apparatus for stacking electrical components using via to provide interconnection
JP2002208656A (en) Semiconductor device
JP2008166373A (en) Semiconductor device and its manufacturing method
CN101582395B (en) Wiring board
US20070069350A1 (en) Method and apparatus for stacking electrical components using via to provide interconnection
JP2007123595A (en) Semiconductor device and its mounting structure
TW201250942A (en) Integrated circuit packaging system with routed circuit lead array and method of manufacture thereof
US8633499B2 (en) Light emitting device
US20060261488A1 (en) Wafer level electro-optical simiconductor manufacture fabrication mechanism and a method for the same
US20040227223A1 (en) Semiconductor device, electronic device, electronic apparatus, and methods for manufacturing semiconductor device and electronic device
JP2006196709A (en) Semiconductor device and manufacturing method thereof
US20050110166A1 (en) Semiconductor device, electronic device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic device
JP2006216717A (en) Wafer level electro-optical semiconductor assembly structure and its manufacturing method
US20040222519A1 (en) Semiconductor device, electronic device, electronic apparatus, method of manufacturing semiconductor device, and method of manufacturing electronic device
TWI313500B (en)
CN100547772C (en) Assembling structure of photoelectric semiconductor wafer and manufacture method thereof
JP3110240U (en) Wafer level electro-optic semiconductor assembly structure
US20170053856A1 (en) Semiconductor die attachment with embedded stud bumps in attachment material
JP4777692B2 (en) Semiconductor device

Legal Events

Date Code Title Description
A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070911

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20071211

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20080129