JP2005065184A - Solid state image sensor and its driving method, and video camera and still camera using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid state image sensor which can perform the timing of the signal storage start and end of all pixels to a simultaneous reset switch Q102 without the deterioration of SN in an output. <P>SOLUTION: The solid state image sensor is provided with a photodiode PD in pixels, a PD reset switch Q105 which resets the photodiode, a transfer switch Q101, a selection switch Q104, a input transistor Q103 of a source follower, and a reset switch Q102 which resets the input of the source follower. Moreover, gate electrodes of the PD reset switch Q105 and the transfer switch Q101 are arranged so as to contact with the same side of the n-layer 303 of the photodiode PD. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a solid-state imaging device widely used as an image input device for a video camera or a digital still camera, a driving method thereof, and a video camera and a still camera using the solid-state imaging device.

  In recent years, the cell size of photoelectric conversion elements using a miniaturization process has been vigorously reduced for high resolution, while the photoelectric conversion signal output has been reduced, and the photoelectric conversion signal is amplified and output. An amplifying photoelectric conversion device capable of this is attracting attention. Such amplification type photoelectric conversion devices include MOS type, AMI, CMD, BASIS and the like.

  Among these, the MOS type stores light carriers generated in the photodiode in the gate electrode of the MOS transistor, and amplifies the potential change to the output unit according to the drive timing from the scanning circuit and outputs it. In recent years, a CMOS type photoelectric conversion device that is realized by a CMOS process, including the photoelectric conversion unit and its peripheral circuit unit, of the MOS type has attracted particular attention.

  However, while the CMOS type photoelectric conversion device amplifies the signal charge with the charge amplification amplifier in the pixel, there is a problem that the variation of the Vth of the input MOS of the charge amplification amplifier and the variation of the amplifier gain causes the SN of the signal to deteriorate. .

  Accordingly, the inventors of the present application have proposed a solid-state imaging device that solves this problem in Japanese Patent Laid-Open No. 11-274454 (see Patent Document 1). FIG. 10 is an equivalent circuit diagram showing the pixel configuration of the publication, and FIG. 11 is an equivalent circuit diagram showing a photoelectric conversion device using the pixel of FIG.

  First, as shown in FIG. 10, the publication includes a photodiode PD and a transfer switch Q1 composed of a MOS transistor. Q2 is a reset switch of a reset MOS transistor for resetting the diffusion floating region, and Q3 is an input MOS of a source follower amplifier circuit in which the diffusion floating region is connected to the gate and a constant current source 812 is connected as a load on the source side. The transistor Q4 is a selection switch for selecting a readout pixel.

  FIG. 11 is an equivalent circuit diagram showing a solid-state imaging device using this pixel cell. For simplicity, the pixels are shown in 3 rows and 3 columns. The operation will be described. First, a reset operation for inputting a reset voltage to the input gate of the source follower amplifier circuit by the reset switch Q2 and row selection by the selection switch Q4 are performed.

  Next, the gate of the diffusion floating region at the input node of the source follower amplifier circuit is floated, and a noise component consisting of reset noise and fixed pattern noise such as variations in the threshold voltage of the source follower input MOS transistor Q3 is read out. Is temporarily held in the signal storage unit 805. Thereafter, the transfer switch Q1 is opened and closed, the accumulated charge of the photodiode PD generated by the optical signal is transferred to the input node of the source follower amplification circuit, the sum of the noise component and the optical signal component is read, and the signal accumulation unit 805 Hold on.

  Next, the signal of the noise component and the signal of the sum of the noise component and the optical signal component are read out to the common signal lines 809 and 809 ′ via the transfer switches 808 and 808 ′, respectively, and are output via the output amplifiers 810 and 810 ′. Output as outputs 811 and 811 ′. Thereafter, the difference between the outputs 811 and 811 ′ is taken to remove the reset noise and the fixed pattern noise, and only the optical signal component is taken out, so that an image signal with a high SN can be obtained.

Also, Japanese Patent Laid-Open No. 2002-320141 has proposed a method in which the accumulation timings of all rows of the solid-state imaging device are simultaneously set (see Patent Document 2). The method of the publication starts signal accumulation by simultaneously releasing the reset of the photodiodes in all rows, and ends the signal accumulation by simultaneously transferring the accumulated charges of the photodiodes in all rows to the input node of the source follower amplifier circuit. To do. After that, the output of the source follower amplifier circuit is read for each row, and then the reset voltage is input to the input gate of the source follower amplifier circuit to perform the reset operation, and then the variation in threshold voltage of the source follower input MOS transistor is fixed. A noise component consisting of pattern noise is read out, and a signal is obtained by taking the difference between the two output values.
JP-A-11-274454 JP 2002-320141 A

  The solid-state imaging device disclosed in Patent Document 1 sequentially reads out line by line. In such a solid-state imaging device, when the accumulated charge of the photodiode generated by the optical signal is transferred to the input node of the source follower amplifier circuit, the next signal charge accumulation is started, so the signal accumulation starts for each row. The timing of termination will be shifted. For this reason, when the subject to be imaged moves quickly, the shape of the subject may be distorted and the flicker of the fluorescent lamp may appear in the image.

  Further, the method of Patent Document 2 is not based on a reset before a signal charge is transferred to a reset output that takes a difference. Accordingly, there is a problem that the reset noise when resetting the diffusion floating region cannot be subtracted and the SN of the obtained output is deteriorated.

  The present invention has been made in view of the above-described conventional problems, and an object of the present invention is to provide a solid-state imaging device capable of simultaneously performing signal accumulation start and end timings of all pixels without degradation of output SN. It is an object of the present invention to provide a driving method and a video camera and a still camera using the driving method.

  In order to achieve the above object, the solid-state imaging device of the present invention converts photoelectric signals into signal charges and accumulates them, and first reset means that resets the signal charges accumulated in the photoelectric conversion means, A reading means for reading out the signal charge; an amplifying means for amplifying the signal charge read through the reading means; a second reset means for resetting the signal charge of the amplifying means; and a selection for selecting a specific pixel And the first reset means and the readout means are arranged in contact with the same side of the photoelectric conversion means.

The solid-state imaging device driving method of the present invention includes a photoelectric conversion unit that converts an optical signal into a signal charge and stores the signal, a first reset unit that resets the signal charge stored in the photoelectric conversion unit, Read means for reading signal charges, amplification means for amplifying signal charges read through the read means, second reset means for resetting signal charges of the amplification means, and selection means for selecting a specific pixel A solid-state imaging device including a pixel as a component of a pixel,
After resetting the input of the amplifying means by the second reset means, the noise signal is read out from the pixels sequentially in a row with the input of the amplifying means floating,
Simultaneously resetting the photoelectric conversion means of all pixels by the first reset means;
After a certain accumulation period, the signal charges accumulated in the photoelectric conversion means by the readout means are simultaneously read out to the input of the amplification means,
Read out the optical signal superimposed on the noise signal from the pixels row by row,
Difference processing between the noise signal and the optical signal is performed.

  According to the present invention, it is possible to make the accumulation start and end timings of all the pixels at the same time without degrading the output SN. Therefore, even when capturing a fast-moving subject, it is possible to capture a high-quality image without distorting and capturing the shape of the subject or causing flicker of a fluorescent lamp to appear in the image.

  Next, the best mode for carrying out the invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is an equivalent circuit diagram showing a first embodiment of a solid-state imaging device according to the present invention. FIG. 1 shows the configuration of the pixel portion. In the figure, PD is a photodiode, and Q101 is a transfer switch composed of a MOS transistor. Q102 is a reset switch composed of a MOS transistor for resetting the diffusion floating region, Q104 is a selection switch composed of a MOS transistor for selecting a readout pixel, Q103 is connected to the gate of the diffusion floating region, and the source is the selection switch Q104. A source follower input MOS transistor Q105 connected to the drain is a PD reset switch composed of a MOS transistor for resetting the photodiode PD.

  Reference numeral 101 denotes a PD reset switch line that drives the PD reset switch Q105, 102 denotes a transfer switch line that drives the transfer switch Q101, 103 denotes a reset switch line that drives the reset switch Q102, and 104 denotes a selection switch that drives the selection switch Q104. A line 105 indicates a signal output line for reading out signals from the pixel portion.

  Next, the operation of the pixel portion will be described. First, by turning on the reset switch Q102 by driving the reset switch line 103, a reset operation for inputting a reset voltage to the input gate of the source follower and row selection by the selection switch Q104 are performed in accordance with driving of the selection switch line 104. Next, the diffusion floating region of the input node of the source follower is made floating, and a noise component composed of fixed noise such as reset noise and threshold voltage variation of the input MOS transistor Q103 of the source follower is read.

  Further, the PD reset switch Q105 is turned on by driving the PD reset switch line 101 to reset the photodiode PD and start accumulation. When the desired accumulation time elapses, the transfer switch Q101 is opened and closed, the accumulated charge of the photodiode PD generated by the optical signal is transferred to the input node of the source follower, and the sum of the noise component and the optical signal component is read out. Thereafter, by taking the difference between the two signals, the reset noise and the fixed pattern noise are removed, and the optical signal component is extracted to obtain an image signal having a high SN.

  According to the configuration of the present embodiment, since the start of signal charge accumulation in the photodiode PD and the transfer of accumulated charge from the photodiode PD to the input node of the source follower can be controlled independently, the start and end of accumulation are completely controlled. Lines can be done simultaneously.

  2 is a plan view of a pixel portion showing the arrangement of each element of the pixel of FIG. 1, and FIG. 3 is a cross-sectional view of FIG. 2 taken along the line AA. The same parts as those in FIG. 1 are denoted by the same reference numerals. In the figure, reference numeral 301 denotes an n substrate. A p-type well 302 is formed on the n substrate 301, and an n layer 303 of a photodiode is formed thereon. Further, a p-layer 304 of the photodiode is formed thereon with a deep surface, gate regions 305 and 307 of the transfer switch Q101 and the PD reset switch Q105 are formed on the side surface of the photodiode via an insulating layer 316, and A gate region 306 of the reset switch Q102 is formed via an insulating layer 316.

  Between the gate regions 305 and 307 of the transfer switch Q101 and the PD reset switch Q105 and the side surface of the photodiode, bypass regions 308 and 309 continuing from the n-layer 303 of the photodiode are formed. A diffusion floating region 310 is formed below the side surfaces of the gate regions 305 and 306 of the transfer switch Q101 and the reset switch Q102. The diffusion floating region 310 is a source follower input MOS transistor Q103 via a contact 311 and a wiring layer 312. The drain of the selection switch Q104 is connected to the source.

  Further, an n-type source / drain region 313 is formed below the side surfaces of the gate regions 307 and 306 of the PD reset switch Q105 and the reset switch Q102, and the source / drain region 313 is connected to the power supply VDD via the contact 314 and the wiring layer 315. ing. Note that the gate regions 305 and 307 preferably have at least one of the gate length and the gate width equal to make the characteristics of the two MOS transistors uniform.

  Next, features of the present embodiment will be described based on the read operation described above. The feature of this embodiment is that the output signal Vr1 immediately after resetting the diffusion floating region 310 is once held, and then a positive voltage is applied to the gate region 305 of the transfer switch Q101 to thereby store the accumulated charge in the n layer 303 of the photodiode PD. Most of reset noise in the diffusion floating region 310 is transferred to the diffusion floating region 310 and a difference (Vsig1−Vr1) from the signal Vsig1 superimposed on the reset signal by the transfer charge Qsig / the diffusion floating region capacitance Cfd is obtained. Is to remove. In particular, it is important to reset the charge accumulated in the n layer 303 of the photodiode PD at a higher rate and transfer it to the diffusion floating region 310.

  The reset operation of the n-layer 303 of the photodiode will be further described. If the PD reset switch Q105 is in a sufficiently ON state, the n-type layer 303 of the photodiode PD includes the GND of the p-type well 302 and the deep p-layer 304 of the surface. A reverse bias of the power supply voltage VDD is applied to the potential. At this time, in the n layer 303 of the photodiode PD, a depletion layer extends from the p-type well 302 and the dense p layer 304 on the surface, and the entire n layer 303 of the photodiode PD is depleted, whereby the signal charge is supplied to the photodiode PD. Can be reset with almost no leftover. Similarly, for the transfer from the n layer 303 of the photodiode PD to the diffusion floating region 310, the signal charge can be read out with almost no signal charge remaining in the photodiode PD.

  In order to realize such an operation, it is necessary to turn on the PD reset switch Q105 and the transfer switch Q101 sufficiently. In this embodiment, as a technique for that purpose, bypass regions 308 and 309 are formed between the transfer switch Q101 and the PD reset switch Q105 and the embedded photodiode.

  As a method of forming the bypass region, the n layer 303 of the photodiode PD and the p layer 304 having a thick surface are used as gate regions of the transfer switch Q101 and the PD reset switch Q105, for example, polycrystalline silicon as a mask material, and ions are obliquely formed. There is a method of forming by injection. Further, the n layer 303 of the photodiode PD is formed by self-alignment using the gate regions of the transfer switch Q101 and the PD reset switch Q105 as a mask material, and the dark p layer 304 is exposed with an offset with respect to the gate region. And the like.

  When the former method is used, the positional relationship between the gate region 305 and the bypass region 308 of the transfer switch Q101 and the positional relationship between the gate region 307 and the bypass region 309 of the PD reset switch Q105 are the same direction (that is, photodiodes). It is important that the alignment direction of the n layer 303, the gate region 305, and the contact 311 is the same as the alignment direction of the n layer 303, the gate region 307, and the contact 314 of the photodiode. Even when the latter method is adopted, since the width of the bypass region changes in the same way with respect to misalignment of the exposure apparatus by arranging both in the same direction, the management of the manufacturing process becomes easy.

  FIG. 4 is a block diagram showing an embodiment of a solid-state imaging device using the pixel cells of FIGS. In FIG. 4, pixel cells are arranged in 3 rows and 3 columns for simplicity. In the figure, 406 is a horizontal shift register, 407 is a vertical shift register, 408 is a transfer switch to the common signal output line 415, and 408_1, 408_2, and 408_3 are drive pulses from the horizontal shift register 406 to the transfer switch 408. Reference numeral 409 denotes a constant current source, 410 denotes an output amplifier, 411 denotes an output, 412 denotes an AD converter, 413 denotes a signal storage unit, and 414 denotes a frame memory.

  Reference numeral 401 denotes a PD reset line, 402 denotes a transfer switch line, 403 denotes a reset switch line, 404 denotes a selection switch line, and 405 denotes a signal output line. These PD reset line 401, transfer switch line 402, reset switch line 403, selection switch line 404, and signal output line 405 are the PD reset line 101, transfer switch line 102, reset switch line 103, and selection switch line in FIG. 1, respectively. 104, corresponding to the signal output line 105.

  Next, the basic operation of the solid-state imaging device of this embodiment will be described with reference to the timing chart of FIG. First, prior to reading, PD reset switch lines 401 in all rows are set to high level, transfer switch line 402 is set to low level, reset switch line 403 is set to high level, PD reset switch Q105 and reset switch Q102 are turned on, and transfer switch Q101 is set. By turning off, the diffusion floating regions of the photodiode PD of all the pixels and the input node of the source follower are reset. The PD reset switch line 101, the transfer switch line 102, the reset switch line 103, and the selection switch line 404 are driven by the vertical shift register 407.

  Next, as shown in FIG. 5, the reset switch lines 403 of all rows (403_1 in FIG. 5 is the first row, 403_2 is the second row, 403_3 is the third row reset switch line) are set to the low level, and the reset switch Q102 is turned on. By turning off, the diffusion floating region of the input node of the source follower is made floating. Thereafter, the selection switch line 404_1 in the first row (404_2 in FIG. 5 is the second row and 404_3 is the selection switch line in the third row) is set to the high level, and the selection switch Q104 in the first row is turned on to perform row selection. Then, noise components including fixed pattern noise such as reset noise and threshold voltage variation of the input follower input MOS transistor Q103 are read out to the signal storage unit 413.

  Next, as shown in FIG. 5, the drive pulses 408_1 to 408_3 from the horizontal shift register 406 are sequentially set to the high level, and the MOS transistor transfer switch 408 is sequentially turned on, so that the noise in the first row is output to the output 411 via the amplifier 410. Read components sequentially. The read noise component is AD (Analog to Digital) converted by an AD (Analog to Digital) converter 412 and held in the frame memory 414. The second and subsequent rows are similarly read out as shown in FIG. 5 and the noise components for all the pixels are held in the frame memory 414.

  Next, as shown in FIG. 5, the PD reset switch lines 401 of all the rows are set to the low level, and the PD reset switch Q105 is turned off to start accumulation of the signal charges photoelectrically converted into the n layer 303 of the photodiode PD. When a desired accumulation time elapses, the charge stored in the photodiode PD is transferred to the input node of the source follower by opening and closing the transfer switch Q101 by driving the transfer switch lines 402 of all rows. The range indicated by the arrow in FIG. 5 is the accumulation period.

  Next, the row selection is performed by setting the selection switch line 404_1 of the first row to the high level in the same manner as the reading of the noise component, and the sum of the noise component and the optical signal component is read out to the signal storage unit 413. Next, the drive pulses 408_1, 408_2, and 408_3 from the horizontal shift register 406 are sequentially set to the high level, and the transfer switch 408 is sequentially turned on, whereby the noise component and the optical signal in the first row are output to the output 411 via the output amplifier 410. Read the sum of components sequentially. The sum of the read noise component and the optical signal component is AD-converted by the AD converter 412, and the difference from the noise component in the first row held in advance in the frame memory 414 is taken, thereby reset noise and fixed pattern noise. And only the optical signal component is extracted. The second and subsequent rows are similarly read out and an image signal with a high SN is obtained.

  According to the above operation, the signal accumulation start and end timings of all rows are the same, and even when the subject is moving fast, the shape of the subject is distorted or the flicker of the fluorescent lamp appears in the image. A high-quality image can be taken without appearing.

  In addition, since the PD reset switch lines 401 of all rows are at the high level and the PD reset switch Q105 of all the pixels is in the on state except for the accumulation period, light is incident during the period other than the accumulation, and the accumulated charge is stored in the photodiode PD. Even if the saturation charge amount of the n layer 303 is exceeded, the blooming phenomenon that overflows and enters the adjacent diffusion floating region or the photodiode PD does not occur.

  Furthermore, the time when the diffusion floating area of each row is floating is determined when the noise component is read (period from when the reset switch is closed until the transfer switch is opened) and when the signal component is read (the signal is output after the transfer switch is closed). The period until the data is read out by the storage unit) is equal, so that the influence of photoelectric charges and dark current due to light leakage into the diffusion floating region can be removed by the above-described differential processing. In the present embodiment, the case where the pixels are arranged in 3 rows and 3 columns has been described, but the present invention is not limited to this.

(Second Embodiment)
FIG. 6 is a block diagram showing another embodiment of the solid-state imaging device using the pixels of FIGS. In FIG. 6, the same parts as those in FIG. 4 are denoted by the same reference numerals. For simplicity, the pixel cells are arranged in 3 rows and 3 columns. The reading method is different from the embodiment of FIG. 4 as described later. In the figure, 408 is a transfer switch for reading out noise components, 408 'is a transfer switch for reading out the sum of noise components and optical signal components, 410 and 410' are output amplifiers, and 411 and 411 'are outputs.

  Next, the basic operation of this embodiment will be described with reference to the timing chart of FIG. First, prior to reading, the PD reset switch lines 401 of all rows are set to the high level, the transfer switch line 402 is set to the low level, and the reset switch line 403 is set to the high level. The diffusion floating region is reset.

  Next, as shown in FIG. 7, the reset switch line 403_1 in the first row is set to a low level, and the reset switch Q102 is turned off to make the diffusion floating region of the input node of the source follower floating. Thereafter, the selection switch line 404_1 in the first row is set to a high level to perform row selection, and noise components including reset pattern noise and fixed pattern noise such as threshold voltage variations of input MOS transistors of the source follower are read out to the signal storage unit 413.

  Next, the reset switch lines 403_2 and 403_3 in the second row and the third row are sequentially set to a low level, and the selection switch lines 404_2 and 404_3 are sequentially set to a high level to perform row selection, and noise components are sequentially read out to the signal storage unit 413. At this time, the signal accumulation unit 413 holds noise components for three rows. Next, as shown in FIG. 7, the PD reset switch lines 401 in all rows are set to the low level, and the PD reset switch Q105 is turned off to start accumulation of signal charges photoelectrically converted into the n layer 303 of the photodiode PD.

  When a desired accumulation time elapses, as shown in FIG. 7, the transfer switch Q101 is opened / closed by driving the transfer switch lines 402 in all rows to transfer the accumulated charge of the photodiode PD to the input node of the source follower. A range indicated by an arrow in FIG. 7 is an accumulation period.

  Next, similarly to the readout of the noise component, the selection switch line 404_1 in the first row is set to the high level to perform row selection, and the sum of the noise component and the optical signal component is read out to the signal storage unit 413. Next, by sequentially setting the drive pulses 408_1 to 408_3 and the drive pulses 408′_1 to 408′_3 from the horizontal shift register 406 to a high level, the transfer switch 408 and the transfer switch 408 ′ are sequentially turned on. The transfer switch 408 is used to transfer a noise component, and the transfer switch 408 ′ is used to transfer the sum of the noise component and the optical signal component. The drive pulse 408_1, the drive pulse 408′_1, and the drive pulse 408_2 from the horizontal shift register 106 are driven. The pulse 408′_2, the drive pulse 408_3, and the drive pulse 408′_3 are simultaneously set to the high level.

  By driving the transfer switches 408 and 408 ′ in this way, the noise component in the first row previously stored in the signal storage unit 413 is sequentially read to the output 411, and the sum of the noise component and the signal component is sequentially read to the output 411 ′. It is. FIG. 7 shows only the drive pulses 408_1 to 408_3, but the high level and low level timings of the drive pulses 408′_1 to 408′_3 are the same as those of the drive pulses 408_1 to 408_3.

  Next, in the second and subsequent rows, the selection switches are turned on in the same manner, and the drive pulses 408_1 to 408_3 and the drive pulses 408′_1 to 408′_3 are sequentially set to the high level, so that the transfer switch 408 and the transfer switch 408 ′ are turned on. Turn on sequentially. As a result, the noise component stored in the signal storage unit 413 is sequentially read to the output 411, and the sum of the noise component and the signal component is sequentially read to the output 411 ′. Further, by removing the reset noise and the fixed pattern noise by taking the difference between the two signals and extracting only the optical signal component, an image signal with a high SN can be obtained.

  According to the above operation, the signal accumulation start and end timings of all rows are the same, and even when the subject to be imaged moves quickly, the shape of the subject is not distorted and flickering of the fluorescent lamp Does not appear in the image.

  In addition, since the PD reset switch lines 401 of all rows are at the high level and the PD reset switch Q105 of all the pixels is in the on state except for the accumulation period, light is incident during the period other than the accumulation, and the accumulated charge is stored in the photodiode PD. Even if the saturation charge amount of the n layer 303 is exceeded, a blooming phenomenon that overflows and enters the adjacent diffusion floating region 310 or the photodiode PD does not occur. In the present embodiment, the pixels are simply arranged in 3 rows and 3 columns, but the present invention is not limited to this. In addition, it is desirable that the signal storage unit 413 of this embodiment be disposed on the same semiconductor substrate as the pixel unit in order to simplify wiring connection.

  In the embodiment of FIG. 6, a frame memory and a signal storage unit for holding noise components of all pixels are required. On the other hand, a mode that requires the signal accumulation start and end timings of all rows to be simultaneous is often a mode for capturing a moving image. In this case, unnecessary rows are thinned out without reading all the rows. Thus, the number of pixels to be read can be reduced and the frame rate can be improved. Further, when thinning out unnecessary rows and reading them out, it suffices if there are as many frame memories and signal storage units as necessary.

  Further, in such a thinning-out operation, the charge accumulated in the n layer 303 of the photodiode PD in the unnecessary row is saturated by always setting the PD reset switch line 401 and the reset switch line 403 in the row that is not read out to the high level. Even if the charge amount is exceeded, the blooming phenomenon that overflows and mixes into the adjacent diffusion floating region or photodiode does not occur.

(Third embodiment)
FIG. 8 is a block diagram showing an embodiment when the solid-state imaging device of the present invention is used in a video camera. In the figure, reference numeral 1A denotes a focus lens for adjusting the focus with a photographing lens, 1B denotes a zoom lens for performing a zoom operation, and 1C denotes a lens for image formation. 2 is a solid-state imaging device that photoelectrically converts an object image formed on the imaging surface into an electrical imaging signal, and is described in the embodiment of FIG. 4 or FIG. Shall be used.

  Reference numeral 4 denotes a sample and hold circuit (S / H circuit) that samples and holds an imaging signal output from the solid-state imaging device 3 and further amplifies the level, and outputs a video signal. A process circuit 5 performs predetermined processing such as gamma correction, color separation, and blanking processing on the video signal output from the sample hold circuit 4, and outputs a luminance signal Y and a chroma signal C.

  The chroma signal C output from the process circuit 5 is subjected to white balance and color balance correction by the color signal correction circuit 21 and output as color difference signals RY and BY. Also, the luminance signal Y output from the process circuit 5 and the color difference signals RY and BY output from the color signal correction circuit 21 are modulated by an encoder circuit (ENC circuit) 24, and are used as standard television signals. Is output. This television signal is supplied to a monitor EVF such as a video recorder or an electronic viewfinder (not shown). Further, the color difference signals RY and BY output from the color signal correction circuit 21 are gated by the gate circuit 22, and the integration value is detected by the integration circuit 25 and input to the logic control circuit 17. This signal is mainly used for white balance adjustment (not shown).

  Reference numeral 6 denotes an iris control circuit that controls the iris drive circuit 7 based on the video signal supplied from the sample and hold circuit 4 and controls the aperture of the diaphragm 2 so that the level of the video signal becomes a predetermined value. The ig meter 8 is automatically controlled as much as possible. Reference numerals 13 and 14 denote different band-limited bandpass filters (BPFs) for extracting high-frequency components necessary for performing focus detection from the video signal output from the sample hold circuit 4.

  The signals output from the first bandpass filter 13 (BPF1) and the second bandpass filter 14 (BPF2) are gated by the gate circuit 15 and the focus gate frame signal, respectively, and the peak detection circuit 16 detects the peak value. And held and input to the logic control circuit 17. This signal is called a focus voltage, and the focus is adjusted by this focus voltage.

  Reference numeral 18 denotes a focus encoder that detects the moving position of the focus lens 1A, 19 denotes a zoom encoder that detects the focal length of the zoom lens 1B, and 20 denotes an iris encoder that detects the opening amount of the diaphragm 2. The detection values of these encoders are supplied to a logic control circuit 17 that performs system control. The logic control circuit 17 detects the focus on the subject based on the video signal corresponding to the set focus detection area and adjusts the focus.

  That is, the peak value information of the high frequency components supplied from the respective band pass filters 13 and 14 is taken in, and the focus motor 10 is supplied to the focus drive circuit 9 to drive the focus lens 1A to the position where the peak value of the high frequency components is maximized. Control signals such as a rotation direction, a rotation speed, and rotation / stop are supplied and controlled.

(Fourth embodiment)
FIG. 9 is a block diagram showing an embodiment when the solid-state imaging device of the present invention is used in a still camera. In the figure, 31 is a barrier that serves as a lens protect and main switch, 32 is a lens that forms an optical image of a subject on the solid-state imaging device 34, 33 is a diaphragm for changing the amount of light that has passed through the lens 32, and 34 is a lens 32. It is assumed that the solid-state imaging device for taking in the imaged subject as an image signal is the one described in the embodiment of FIG. 4 or FIG.

  An A / D converter 36 performs analog-digital conversion of an image signal output from the solid-state imaging device 34, and 37 performs various corrections on the image data output from the A / D converter 36 and compresses the data. A signal processing unit 38 is a timing generation unit that outputs various timing signals to the solid-state imaging device 34, the imaging signal processing circuit 35, the A / D converter 36, and the signal processing unit 37.

  Also, 39 is an overall control / arithmetic unit for controlling various calculations and the entire still camera, 40 is a memory unit for temporarily storing image data, and 41 is a recording medium control I for recording or reading on a recording medium. An / F (interface) unit, 42 is a removable recording medium such as a semiconductor memory for recording or reading image data, and 43 is an external I / F (interface) unit for communicating with an external computer or the like.

  Next, the operation at the time of shooting with the still camera will be described. First, when the barrier 31 is opened, the main power supply is turned on, then the control system power supply is turned on, and the power supply of the imaging system circuit such as the A / D converter 36 is turned on. Then, in order to control the exposure amount, the overall control / arithmetic unit 39 opens the diaphragm 33, and the signal output from the solid-state imaging device 34 is converted by the A / D converter 36 and then sent to the signal processing unit 37. Entered.

  The overall control / calculation unit 39 calculates exposure based on the data. The brightness is determined based on the result of the photometry, and the overall control / calculation unit 39 controls the diaphragm 32 according to the result. Next, a high-frequency component is extracted based on the signal output from the solid-state imaging device 34, and the distance to the subject is calculated by the overall control / calculation unit 39. Thereafter, the lens 32 is driven to determine whether or not it is in focus. When it is determined that the lens is not in focus, the lens 32 is driven again to perform distance measurement.

  Then, after the in-focus state is confirmed, the main exposure starts. When the exposure is completed, the image signal output from the solid-state imaging device 34 is A / D converted by the A / D converter 36, passes through the signal processing unit 37, and is written in the memory unit 40 by the overall control / calculation unit 39. Thereafter, the data stored in the memory unit 40 is recorded on a removable recording medium 42 such as a semiconductor memory through the recording medium control I / F unit 41 under the control of the overall control / arithmetic unit 39. Further, the image may be processed by directly entering the computer or the like through the external I / F unit 43.

It is an equivalent circuit diagram which shows the pixel part of the solid-state imaging device which concerns on this invention. It is a top view which shows the element arrangement | positioning of the pixel part of FIG. It is sectional drawing in the AA of FIG. 1 is an equivalent circuit diagram showing an embodiment of a solid-state imaging device of the present invention. FIG. 5 is a timing diagram illustrating an operation of the solid-state imaging device of FIG. 4. It is an equivalent circuit diagram which shows other embodiment of the solid-state imaging device of this invention. FIG. 7 is a timing diagram illustrating an operation of the solid-state imaging device of FIG. 6. It is a block diagram which shows the structure of one Embodiment at the time of using the solid-state imaging device of this invention for a video camera. It is a block diagram which shows the structure of one Embodiment at the time of using the solid-state imaging device of this invention for a still camera. It is an equivalent circuit diagram which shows the pixel part of the solid-state imaging device of a prior art example. It is an equivalent circuit diagram which shows the solid-state imaging device using the pixel part of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1A Focus lens 1B Zoom lens 1C Imaging lens 2 Aperture 3 Solid-state imaging device 4 Sample hold circuit 5 Process circuit 6 Iris control circuit 7 Iris drive circuit 8 ig meter 9 Focus drive circuit 10, 12 Motor 11 Zoom drive circuit 13, 14 BPF
DESCRIPTION OF SYMBOLS 15, 22 Gate circuit 16 Peak detection circuit 17 Logic control circuit 18 Focus encoder 19 Zoom encoder 20 Iris encoder 21 Color signal correction circuit 23 Gate pulse generation circuit 24 ENC circuit 25 Integration circuit 31 Barrier 32 Lens 33 Diaphragm 34 Solid-state imaging device 35 Imaging Signal processing circuit 36 A / D converter 37 Signal processing circuit 38 Timing generation unit 39 Overall control / calculation unit 40 Memory unit 41 Recording medium control I / F unit 42 Recording medium 43 External I / F unit 101, 401 PD reset switch line 102, 402 transfer switch line 103, 403 reset switch line 104, 404 selection switch line 105, 405 signal output line 301 n substrate 302 p type well 303 photodiode n layer 304 dark p layer 305 surface transfer Switch gate region 306 Reset switch gate region 307 PD reset switch gate region 308, 309 Bypass region 310 Diffusion floating region 311, 314 Contact 312, 315 Wiring layer 313 Source drain region 316 Insulating layer 406 Horizontal shift register 407 Vertical shift register 408, 408 ′ transfer switch 409 constant current source 410, 410 ′ output amplifier 411, 411 ′ output 412 A / D converter 413 signal storage unit 414 frame memory 415, 415 ′ common signal output line PD photodiode Q101 transfer switch Q102 reset switch Q103 Input MOS transistor Q104 Selection switch Q105 PD reset switch

Claims (11)

A photoelectric conversion unit that converts an optical signal into a signal charge and stores it, a first reset unit that resets the signal charge stored in the photoelectric conversion unit, a read unit that reads the signal charge, and a read unit that reads the signal charge. The first reset includes amplifying means for amplifying the output signal charge, second resetting means for resetting the signal charge of the amplifying means, and selecting means for selecting a specific pixel as the constituent elements of the pixel. The solid-state imaging device is characterized in that the means and the reading means are disposed in contact with the same side of the photoelectric conversion means. 2. The photoelectric conversion means is a photodiode, and a bypass region continuous from an n layer of the photodiode is formed between the first reset means and the reading means and the photodiode. The solid-state imaging device described in 1. The first reset unit and the readout unit are MOS transistors having a source region as a signal charge accumulation region of the photoelectric conversion unit, and gate electrodes of two MOS transistors of the first reset unit and the readout unit are The solid-state imaging device according to claim 1, wherein the solid-state imaging device is arranged in the same direction. The solid-state imaging device according to claim 3, wherein at least one of a gate length or a gate width of the two MOS transistors is equal. A first signal holding unit for holding noise signals read from pixels in a row sequence and a second signal holding unit for holding optical signals read from pixels in a row sequence are the same semiconductor as the pixels The solid-state imaging device according to claim 1, wherein the solid-state imaging device is provided on a substrate. The solid-state imaging device according to claim 5, further comprising: the first signal holding unit that holds a plurality of rows of noise signals; and the second signal holding unit that holds an optical signal for one row. A photoelectric conversion unit that converts an optical signal into a signal charge and stores it, a first reset unit that resets the signal charge stored in the photoelectric conversion unit, a read unit that reads the signal charge, and a read unit that reads the signal charge. A solid-state imaging device driving method including amplification means for amplifying the output signal charge, second reset means for resetting the signal charge of the amplification means, and selection means for selecting a specific pixel as constituent elements of the pixel Because
After resetting the input of the amplifying means by the second reset means, the noise signal is read out from the pixels sequentially in a row with the input of the amplifying means floating,
Simultaneously resetting the photoelectric conversion means of all pixels by the first reset means;
After a certain accumulation period, the signal charges accumulated in the photoelectric conversion means by the readout means are simultaneously read out to the input of the amplification means,
Read out the optical signal superimposed on the noise signal from the pixels row by row,
A method of driving a solid-state imaging device, wherein difference processing between the noise signal and the optical signal is performed. The noise signal read out from the pixels in a row sequence is held in the first signal holding unit, the optical signal for one row read out from the pixel is held in the second signal holding unit, The solid-state imaging device according to claim 7, wherein differential processing of both signals is performed while sequentially reading to a plurality of common signal lines together with the noise signals in the same row as the optical signals held by the signal holding means. Driving method. The noise signals read out from the pixels in the row sequence are sequentially read out to the common signal line, A / D converted and held in the signal holding means, and the optical signals read out from the pixels in the row sequence are sequentially read out to the common signal line. 9. The method of driving a solid-state imaging device according to claim 8, wherein difference processing with the noise signal held in the signal holding means after AD conversion is performed in a row sequential manner. The solid-state imaging device according to claim 1, a lens that forms a subject image on the solid-state imaging device, and a video signal from the solid-state imaging device is subjected to predetermined signal processing to obtain a luminance signal And a signal processing means for generating a chroma signal. The solid-state imaging device according to claim 1, a lens that forms a subject image on the solid-state imaging device, and a signal processing unit that processes a signal from the solid-state imaging device. A feature still camera.

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