JP2005057042A - Thin film transistor, its manufacturing method, liquid crystal display device, and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable thin film transistor, its manufacturing method, a liquid crystal display device, and its manufacturing method. <P>SOLUTION: The liquid crystal display device is provided with a capacitive element 8, an n-type thin film transistor 11, and a p-type thin film transistor 12 on a glass substrate 1. Each thin film transistor 11 and 12 is provided with island-like crystalline polysilicon films 4b and 4c which are formed on the glass substrate 1 through a base film 2, and in which a channel region and a source/drain region are respectively formed and gate electrodes 6a and 6b formed on the polysilicon films 4b and 4c through insulating films 5. The angles between the bottom faces and side faces of the polysilicon films 4b and 4c are adjusted to 15-80°, and the thicknesses of the portions of the base film 2 on which the polysilicon films 4b and 4c are not formed are made thinner than those of the portions of the base film 2 immediately under the polysilicon films 4b and 4c. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a thin film transistor, a manufacturing method thereof, a liquid crystal display device, and a manufacturing method thereof, and more specifically, a thin film transistor of a type using crystallized silicon, a manufacturing method thereof, a liquid crystal display device having the thin film transistor, and a manufacturing method thereof. About.

  Conventionally, in a thin film transistor using polysilicon, as a crystallization method, a method of melting an amorphous silicon film by irradiating an excimer laser, and then crystallizing at cooling is adopted. According to this method, since the substrate itself hardly receives heat, a thin film transistor can be formed on a glass substrate having a low heat-resistant temperature.

An example of a liquid crystal display device having such a thin film transistor is described in, for example, JP-A-8-255915. The thin film transistors are described in, for example, Japanese Patent Application Laid-Open Nos. 2002-343976, 2000-174284, 9-213961, and 2002-299234.
JP-A-8-255915 JP 2002-343976 A JP 2000-174284 A Japanese Patent Laid-Open No. 9-239661 JP 2002-299234 A

  However, in the thin film transistors described in any of the above-described documents, the thickness of the base film under the active layer or the semiconductor film is substantially equal between the portion located under the active layer or the semiconductor film and the other portion. .

  Therefore, when an insulating film is formed so as to cover the active layer or the semiconductor film, cracks are likely to occur in the insulating film near the portion where the peripheral portion of the active layer or the semiconductor film is in contact with the base film. As a result, there is a problem in that the reliability of the thin film transistor is lowered, which becomes one of the causes of a decrease in the reliability of the liquid crystal display device having the thin film transistor.

  SUMMARY An advantage of some aspects of the invention is that it provides a highly reliable thin film transistor, a manufacturing method thereof, a liquid crystal display device, and a manufacturing method thereof.

  A thin film transistor according to the present invention includes an insulating substrate, an island-shaped crystallized silicon film formed on the insulating substrate via a base film, and having a channel region and a source / drain region, and a crystallized silicon film A portion where the angle between the bottom surface and the side surface of the crystallized silicon film is not less than 15 degrees and not more than 80 degrees, and the crystallized silicon film is not formed on the surface. The thickness of the base film is made thinner than the thickness of the base film located immediately below the crystallized silicon film. The liquid crystal display device according to the present invention includes the thin film transistor as described above.

  In the present invention, while adjusting the angle formed between the bottom surface and the side surface of the crystallized silicon film within the above range, the thickness of the base film in the portion where the crystallized silicon film is not formed on the surface is adjusted to be just below the crystallized silicon film. Therefore, when the gate insulating film is formed so as to cover the crystallized silicon film, it is positioned near the portion where the peripheral part of the crystallized silicon film is in contact with the base film. The stress generated in the gate insulating film can be reduced. Therefore, it is possible to suppress the generation of cracks in the gate insulating film located in the vicinity of the portion where the peripheral portion of the crystallized silicon film and the base film are in contact with each other, and to effectively suppress the deterioration of the reliability of the thin film transistor. it can.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

(Embodiment 1)
FIG. 1 is a partial cross-sectional view of the liquid crystal display device according to Embodiment 1 of the present invention. As shown in FIG. 1, the liquid crystal display device includes a display pixel region in which display pixels are formed and a peripheral circuit region in which peripheral circuits are formed.

  In the display pixel region, a capacitor element 8 and an n-type thin film transistor (TFT) 11 are formed on a glass substrate 1 which is an insulating substrate. In the peripheral circuit region, various circuit elements including the p-type thin film transistor 12 are formed. The capacitor element 8 includes a polysilicon film 4a that is a crystallized silicon film and a common electrode 7, and the n-type thin film transistor 11 includes a polysilicon film 4b that is a crystallized silicon film and a gate electrode 6a. The p-type thin film transistor 12 includes a polysilicon film 4c that is a crystallized silicon film and a gate electrode 6b.

  The polysilicon films 4a to 4c are formed in an island shape on the base film 2 at intervals. An n-type impurity such as phosphorus is introduced into the polysilicon film 4a. In the polysilicon film 4b, a channel region 16a of the n-type thin film transistor 11 and n-type source / drain regions 9a and 9b are formed on both sides of the channel region 16a. A channel region 16b of the p-type thin film transistor 12 and n-type source / drain regions 10a and 10b are formed on both sides of the channel region 16b in the polysilicon film 4c.

  A recess is formed on the surface of the base film 2 positioned between the polysilicon films 4a to 4c, and the thickness of the base film 2 positioned between the polysilicon films 4a to 4c due to the presence of the recess is determined to be the polysilicon film 4a. It is thinner than the thickness of the base film 2 located immediately below -4c.

  An insulating film 5 is formed so as to cover the polysilicon films 4a, 4b and 4c. The insulating film 5 is composed of a silicon oxide film formed by using, for example, TEOS (Tetra Etyle Ortho Silicate) or PECVD (Plasma Enhanced Chemical Vapor Deposition), and in the capacitive element 8, a dielectric between electrodes (capacitance electrodes). The n-type thin film transistor 11 and the p-type thin film transistor 12 function as a gate insulating film. The common electrode 7 is formed on the polysilicon film 4a via the insulating film 5, the gate electrode 6a is formed on the polysilicon film 4b via the insulating film 5, and the gate electrode 6b is formed on the polysilicon film 4c. Are formed via an insulating film 5.

  A protective film 13 made of a silicon oxide film or the like is formed so as to cover the common electrode 7 and the gate electrodes 6a and 6b. A contact hole 14a is formed through the protective film 13 and the insulating film 5 so as to reach the polysilicon film 4a, and a source / drain region of the polysilicon film 4b is formed through the protective film 13 and the insulating film 5. Contact holes 14b and 14c are formed so as to reach 9a and 9b, and contact holes 14d and 14e are formed so as to penetrate the protective film 13 and the insulating film 5 and reach the source / drain regions 10a and 10b of the polysilicon film 4c. Form. An electrode 15a is formed so as to extend from the contact holes 14a, 14b onto the protective film 13, and an electrode 15b is formed so as to extend from the contact hole 14c onto the protective film 13, and within the contact holes 14d, 14e. The electrodes 15c and 15d are formed so as to extend on the protective film 13 respectively. The electrodes 15a to 15d are configured by a conductive film having a three-layer structure in the example of FIG. 1, but may be configured by a single-layer structure or a stacked structure of a plurality of conductive films other than three layers.

  An insulating film 17 such as a silicon nitride film is formed so as to cover the electrodes 15a to 15d. A planarizing film 18 made of a photosensitive resin or the like is formed on the insulating film 17. A contact hole 19 reaching the electrode 15 a is formed in the planarizing film 18, and a pixel electrode 20 is formed in the contact hole 19. The pixel electrode 20 is made of, for example, ITO (tin-added indium oxide).

  Next, characteristic structures of the thin film transistor and the liquid crystal display device in this embodiment will be described with reference to FIGS. In the following description, an n-type thin film transistor will be described, but the same applies to a p-type thin film transistor.

  FIG. 7 is a partially enlarged view of the n-type thin film transistor 11 in FIG. As shown in FIG. 7, the end of the polysilicon film 4b has a tapered shape, and the angle (taper angle) θ between the side surface 26 and the bottom surface 25 of the polysilicon film 4b is 15 degrees or more and 80 degrees or less. is there.

  Since the end portion of the polysilicon film 4b has the above tapered shape, the coverage of the insulating film 5 on the end portion of the polysilicon film 4b can be improved. When the insulating film 5 is formed by a plasma CVD (Chemical Vapor Deposition) method or the like, it cannot be said that the coverage of the vertical end face is excellent. Therefore, for example, as shown in FIG. 8A, the side surface (end surface) of the polysilicon film 4b extends in a direction substantially perpendicular to the main surface of the glass substrate 1, and the taper angle of the end portion of the polysilicon film 4b is 80 degrees. In the case of exceeding the thickness, the thickness of the insulating film 5 located on the side surface of the polysilicon film 4b becomes thin, and cracks 22 or streaks such as cracks are likely to occur in the insulating film 5.

  If a thin film transistor or a capacitor element is formed in the state shown in FIG. 8A, there is a high possibility of causing an initial failure due to a breakdown voltage failure or a reliability failure. Further, when the conductive film 23 to be a wiring is formed thereon as shown in FIG. 8B, the conductive film 23 is interrupted on the crack 22 and may cause a disconnection failure of the wiring. However, by setting the taper angle of the end portion of the polysilicon film 4b to 80 degrees or less as described above, it is possible to avoid the occurrence of various defects such as the above-mentioned breakdown voltage breakdown.

  On the other hand, if the taper angle at the end of the polysilicon film 4b is too small, the following problem in characteristics may occur. FIG. 9A shows a schematic diagram of the vicinity of the silicon end surface when the taper angle θ1 at the end of the polysilicon film 4b is small, and FIG. 9B shows the taper angle θ2 at the end of the polysilicon film 4b. The schematic diagram of the silicon | silicone end surface vicinity in the case of being comparatively large is shown.

  On the surface of the side surface (tapered surface) 26 of the polysilicon film 4b, damage during etching usually remains and is in a relatively rough state. For this reason, the leakage current is increased or the on-characteristics are deteriorated at or near the side surface 26 of the polysilicon film 4b. Further, since the effective film thickness of silicon is thin at the tapered portion of the polysilicon film 4b, the state is equivalent to the case where the transistor (TFT1) in the tapered portion and the transistor (TFT2) in the tapered portion are arranged side by side. It becomes. In other words, the parasitic transistor corresponding to TFT2 is formed on both sides of the transistor corresponding to TFT1.

  As shown in FIG. 9B, when the taper angle θ2 at the end of the polysilicon film 4b is relatively large, the TFT2 portion corresponding to the parasitic transistor is small, and can be neglected as compared with the length of the effective portion of the transistor. It will be about. Therefore, by increasing the taper angle θ2 at the end of the polysilicon film 4b, adverse effects due to the parasitic transistor can be reduced.

  Further, when the taper angle θ1 is reduced, the substantial size (channel width) of the transistor cannot be ignored. If the thickness of the polysilicon film 4b is t1, the channel width is t1 / tan (θ1), the taper angle θ1 is 5 degrees, and the thickness of the polysilicon film 4b is 50 nm, the channel width is 0. It becomes about 6 μm. Therefore, considering that there are two parasitic transistors on both sides of the transistor TFT1, the total channel width of the parasitic transistors is 1 μm or more.

  In general, the channel width of a pixel transistor or a transistor constituting a driving circuit is about 5 to 10 μm. Therefore, when the taper angle θ1 is reduced, the channel width of the parasitic transistor is 1 of the channel width of the transistor constituting the pixel transistor or the driving circuit. The adverse effects of parasitic transistors cannot be ignored. In particular, in the case of a small transistor, the ratio of the channel width of the parasitic transistor can be as high as about 30%. In this case, there is a concern that the parasitic transistor may have a serious adverse effect.

  FIG. 10 shows the relationship between the taper angle θ and the channel width of the parasitic transistor (parasitic TFT) when the channel thickness (the thickness of the polysilicon film 4b) is 50 nm.

  As shown in FIG. 10, by setting the taper angle θ to 10 degrees or more, preferably 15 degrees or more, where the value of 1 / tan θ does not increase, the influence of the parasitic transistor formed at the end of the silicon film is reduced. It can be suppressed to a level that can be almost ignored.

  As described above, the characteristics, yield, and reliability of the thin film transistor can be improved by controlling the taper angle of the end portion of the polysilicon film to 10 degrees or more (preferably 15 degrees or more) and 80 degrees or less.

  Next, the structure of the base film in the vicinity of the end of the polysilicon film in the thin film transistor of this embodiment will be described.

  In the first embodiment, as shown in FIG. 7, a recess 24 is formed on the surface of the base film 2 located near the end (periphery) of the polysilicon film 4b, thereby forming the polysilicon film 4b. The thickness t4 of the base film 2 in the unexposed portion is thinner than the thickness t3 of the base film 2 located immediately below the polysilicon film 4b.

  As shown in FIG. 12, when the thickness of the base film 2 is equal between the portion where the polysilicon film 4b is not formed and the portion located immediately below the polysilicon film 4b, the end portion of the polysilicon film 4b Cracks frequently occur in the insulating film 5 in the vicinity of the portion in contact with the base film 2.

  Accordingly, as shown in FIG. 7, the thickness t4 of the base film 2 where the polysilicon film 4b is not formed is made thinner than the thickness t3 of the base film 2 located immediately below the polysilicon film 4b, thereby forming polysilicon. The insulating film 5 can be gently extended from the side surface (tapered surface) 26 of the film 4 b to the base film 2, and the occurrence of cracks in the insulating film 5 can be effectively suppressed.

  The recess 24 reaches the end of the polysilicon film 4b or the vicinity thereof without entering under the polysilicon film 4b, and has a gently inclined slope. As a result, the entire bottom surface of the polysilicon film 4 b comes into contact with the base film 2.

  As shown in FIG. 11A, when the recess 24a is formed so as to enter under the polysilicon film 4b, the coverage of the insulating film 5 is deteriorated, and the possibility of occurrence of a coverage failure is increased. When the conductive film 23 is formed on the insulating film 5 as shown in FIG. 11B, an initial failure due to a breakdown voltage failure or a reliability failure occurs between the conductive film 23 and the polysilicon film 4b. obtain.

  Therefore, as described above, the recess 24 shown in FIG. 7 reaches the end of the polysilicon film 4b or the vicinity thereof without entering under the polysilicon film 4b, so that the coverage defect can be effectively suppressed, and the insulation is prevented. An initial failure due to a breakdown voltage failure or a reliability failure can be avoided.

  Further, the surface roughness (for example, Rmax) of the base film 2 in the portion where the recess 24 is formed is larger than the surface roughness of the base film 2 located immediately below the polysilicon film 4b. Thereby, even when the distance between the polysilicon patterns is short, the surface leakage current between the polysilicons can be reduced.

  Further, as described later, a polysilicon film having a large grain size (for example, an average grain size of about 0.3 μm) obtained by crystallization using a YAG (Yttrium-Aluminum-Garnet) laser or the like is used, and the insulating film 5 By making the thickness of 300 nm or less, although the gate insulating film is thick, the crystallinity of the channel region is improved, so that a thin film transistor having a sufficient level for normal use can be obtained in terms of characteristics. Further, by adopting the above-described structure as the structure around the polysilicon film, and making the thickness t2 of the insulating film 5 more than twice the thickness t1 of the polysilicon film 4b, a high breakdown voltage exceeding a normal level, A highly reliable thin film transistor can be obtained. By adopting the thin film transistor, it is possible to obtain a liquid crystal display device that is effective even in the fields of special applications such as industrial, military, and medical use, which are particularly required to have a long life and high durability.

  Next, a method for manufacturing the thin film transistor and the liquid crystal display device in the present embodiment having the above-described structure will be described with reference to FIGS.

  As shown in FIG. 2, a base film 2 having a thickness of about 250 nm is formed on a glass substrate 1 (insulating substrate) by, for example, PECVD. As the base film 2, a silicon nitride film, a silicon oxide film, or a laminated film thereof can be used. On this base film 2, an amorphous silicon film 3 for forming channel regions of the p-type thin film transistor and the n-type thin film transistor is formed with a thickness of about 50 nm.

  Next, the amorphous silicon film 3 is annealed using a solid-state laser such as a YAG laser, so that the amorphous silicon film 3 is melted, and the melted amorphous silicon film 3 is cooled and crystallized to become a polysilicon film.

In addition to the YAG laser, a YVO ₄ laser can be used as the solid-state laser, and a YAG laser doped with Nd (neodymium) ions or Yb (ytterbium) ions or a crystal doped with Nd ions can be used. preferable. More preferably, a pulse laser beam of the second harmonic (wavelength 532 nm) of the YAG laser doped with Nd ions, a pulse laser beam of the second harmonic (wavelength 532 nm) of the YVO ₄ laser doped with Nd ions, Yb A pulsed laser beam of the second harmonic (wavelength 515 nm) of a YAG laser doped with ions is used.

Next, a mask film (not shown) is formed by photolithography on the polysilicon film formed as described above, and dry etching is performed using the mask film. Thereby, the polysilicon film can be selectively etched, and island-like polysilicon films 4a to 4c can be formed as shown in FIG. At this time, etching conditions are employed such that the ends of the polysilicon films 4a to 4c are tapered. Specifically, etching is performed under conditions of a pressure of 5 Pa and a power of 800 W while supplying CF ₄ as an etching gas at 0.15 liter / minute (150 sccm) and O ₂ at 0.03 liter / minute (30 sccm). The etching time is 60 seconds. Thereby, the end portions of the polysilicon films 4a to 4c can be tapered, and in this embodiment, the taper angle θ can be set to about 20 degrees. Note that the taper angle θ can be set to an arbitrary angle of 10 degrees or more and 80 degrees or less by appropriately adjusting the etching conditions.

  Thereafter, UV (ultraviolet) irradiation having an effect of oxidizing the exposed surfaces of the polysilicon films 4a to 4c is performed. 6A and 6B are schematic views near the polysilicon film 4b. As shown in FIG. 6A, an oxide film 21 can be formed on the surface of the polysilicon film 4b by UV irradiation. At the same time, oxide films are also formed on the surfaces of the polysilicon films 4a and 4c. Further, as shown in FIG. 6A, a recess 24 is formed on the surface of the base film 2 located in the vicinity of the polysilicon films 4a to 4c when the polysilicon films 4a to 4c are patterned.

  Next, as shown in FIG. 6B, wet etching is performed using an etchant containing hydrofluoric acid, thereby etching the exposed surface of the base film 2 and removing the oxide film 21. At this time, the oxide films on the surfaces of the polysilicon films 4a to 4c are also etched together with the surface of the base film 2, so that the side surfaces (end faces) of the polysilicon films 4a to 4c are retracted and below the polysilicon films 4a to 4c. It is possible to suppress the recess 24 from entering. This effect becomes more conspicuous when the base film 2 has an etching rate slower than that of a natural oxide film of silicon by an etching solution containing hydrofluoric acid.

As the etching solution containing hydrofluoric acid, for example, buffered hydrofluoric acid (a mixed solution of HF and NH ₄ F) can be used. It is preferable to use a HF / NH ₄ F mixing ratio of 1: 100 and an HF concentration of 1% or less. In this case, the etching amount of the base film 2 can be easily controlled. In addition, by slowing the film formation rate of the base film 2 and making the base film 2 a dense film, the etching rate of the base film 2 by the etching solution containing hydrofluoric acid is made higher than the etching rate of the normal natural oxide film. It can be slow enough.

  In the present embodiment, an example in which UV irradiation is performed as an oxidation method for the polysilicon films 4a to 4c has been described. However, an oxygen plasma treatment, an oxidation treatment using oxygen gas in a range from normal pressure to high pressure, or a steam treatment. In addition, at least one of oxidation treatment using an oxidizing liquid (sulfuric acid, hydrogen peroxide, nitric acid, amine resist stripping solution, etc.) and oxidation treatment using a solution in which ozone gas is dissolved may be employed. .

  Thereafter, the insulating film 5 is formed using a PECVD method or the like. The insulating film 5 has t2 ≧ 2 × t1-3 × t1 (t2 is 2 to 3 times t1) when the thickness of the polysilicon films 4a to 4c is t1 and the thickness of the insulating film 5 is t2. And a thickness of about 200 nm so as to satisfy t2 ≦ 300 nm.

  Next, with the polysilicon films 4b and 4c covered with a resist film (not shown), phosphorus (P) ions, which are n-type conductive impurities, are implanted into the polysilicon film 4a. Thereby, the lower electrode of the capacitive element is formed.

  Next, a conductive film made of Cr (chromium) or the like is formed on the insulating film 5 by sputtering, and the conductive film is patterned into an island shape by photolithography and etching techniques. Thereby, gate electrodes 6a and 6b and a common electrode 7 are formed as shown in FIG.

  Thereafter, a portion other than the polysilicon film 4b is covered with a resist film (not shown), and P (phosphorus) ions which are n-type impurities are implanted into both ends of the polysilicon film 4b using the resist film as a mask. Thereby, source / drain regions (n-type impurity diffusion regions) 9a and 9b are formed at both ends of the polysilicon film 4b. Further, a portion other than the polysilicon film 4c is covered with a resist film (not shown), and B (boron) ions are implanted into both ends of the polysilicon film 4c through the insulating film 5 using this resist film as a mask. As a result, source / drain regions (p-type impurity diffusion regions) 10a and 10b are formed at both ends of the polysilicon film 4c.

  Next, a protective film 13 is formed on the insulating film 5 so as to cover the gate electrodes 6a and 6b and the common electrode 7 by using a CVD method or the like. As the protective film 13, for example, a TEOS or silicon oxide film having a thickness of about 600 nm is used. Thereafter, activation annealing is performed at a temperature of about 400.degree. Thereby, the impurities implanted into the polysilicon film are activated. A thin film transistor can be manufactured by the above method.

  Next, as shown in FIG. 5, the insulating film 5 and the protective film 13 are selectively etched by adopting the photoengraving technique and the etching technique, thereby penetrating the insulating film 5 and the protective film 13 to form polysilicon. Contact holes 14a to 14e are formed so as to reach the films 4a to 4c. A three-layer film of Mo (molybdenum) film, Al (aluminum) film, and Mo film is formed in the sputtering apparatus so as to fill the contact holes 14a to 14e. Electrodes 15a to 15d are formed by patterning the above-mentioned three-layer film using a photoengraving technique and an etching technique.

  Thereafter, hydrogen plasma is used to hydrogenate the channel regions 16a and 16b of the thin film transistors. Thus, the characteristics of each thin film transistor are improved and the operation is stabilized. Then, as shown in FIG. 1, an insulating film 17 made of, for example, a silicon nitride film is formed on the electrodes 15a to 15d. A planarizing film 18 made of, for example, a photosensitive resin is formed thereon.

  Next, contact holes 19 are formed in the insulating film 17 and the planarizing film 18 by performing exposure and development. A transparent conductor film is formed so as to extend from the inside of the contact hole 19 onto the planarizing film 18. As the transparent conductor film, for example, ITO can be used. The pixel electrode 20 can be formed by partially removing the transparent conductor film by photolithography and etching techniques.

  In the peripheral circuit region, an n-type thin film transistor is formed by the above-described method in addition to the p-type thin film transistor 12 shown in FIG. 1, and a peripheral circuit is formed by combining the p-type thin film transistor and the n-type thin film transistor. In the display pixel region, a display pixel is formed by electrically connecting the n-type thin film transistor 11 and a separately formed transparent electrode. Further, the glass substrate on which these elements are formed as a semiconductor device is bonded to the other glass substrate on which the color filter and the counter electrode are formed. And a liquid crystal display device is obtained by performing predetermined processes, such as injecting and sealing a liquid crystal in a gap formed between these glass substrates.

  In this embodiment, a transmissive liquid crystal display device using an ITO film as a pixel electrode has been described. However, a reflective liquid crystal display device using a reflective electrode such as Al, or a half provided with both. The idea of this embodiment can be applied to a transmissive liquid crystal display device, an organic EL (Electro-Luminescence) display device, and the like.

(Embodiment 2)
Next, Embodiment 2 of the present invention will be described with reference to FIG.

  In the second embodiment, the thickness of the insulating film 5 is set so that the thickness t1 of the polysilicon film 4b and the thickness t2 of the insulating film 5 shown in FIG. 13 satisfy a predetermined relationship. That is, the thickness of the insulating film 5 is set so as to satisfy the relationship of t2 ≧ t1 and t2 ≦ 150 nm. Specifically, in the second embodiment, the thickness of the insulating film 5 is about 70 nm. Other configurations are basically the same as those in the first embodiment.

  According to the second embodiment, a polysilicon film having a large particle size (for example, an average particle size of about 0.3 μm) obtained by crystallization using a YAG laser or the like is used, and the thickness of the insulating film 5 is 150 nm. By making the following, the gate insulating film has a standard thickness, but since the crystallinity of the channel region becomes good, the characteristics exceed the normal level, high mobility, low threshold voltage, etc. An realized thin film transistor can be obtained.

  Further, by adopting the optimized structure as in the first embodiment as the structure around the polysilicon film, and making the thickness t2 of the insulating film 5 equal to or greater than the thickness t1 of the polysilicon film 4b, a normal level is achieved. Due to the synergistic effect with the film thickness, it is possible to obtain a thin film transistor having a sufficient withstand voltage and reliability for normal use. As a result, a high-performance liquid crystal display device with a built-in advanced peripheral circuit that requires particularly high transistor characteristics can be obtained.

(Embodiment 3)
Next, Embodiment 3 of the present invention will be described with reference to FIG.

  In the third embodiment, the amorphous silicon film is annealed and crystallized using a gas laser such as an excimer laser instead of the solid-state laser to form a polysilicon film. Specifically, a polysilicon film is formed using a XeCl excimer laser (308 nm). Further, the thickness of the insulating film 5 is set so that the thickness t2 of the insulating film 5 shown in FIG. 14 and the thickness t1 of the polysilicon film 4b satisfy the relationship of t2 ≧ (t1 / 2) and t2 ≦ 150 nm. Specifically, in the third embodiment, the thickness of the insulating film 5 is about 70 nm. Other configurations are basically the same as those in the first embodiment.

  According to the third embodiment, by setting the thickness of the insulating film 5 to 150 nm or less, the gate insulating film has a standard thickness, and is a normal level channel region crystallized by using a gas laser such as an excimer laser. Therefore, a thin film transistor having a sufficient level for normal use can be obtained in terms of characteristics.

  Further, by adopting the optimized structure as in the first embodiment as the structure around the polysilicon film, the thickness t2 of the insulating film 5 is set to 1/2 or more of the thickness t1 of the polysilicon film 4b. Even in a relatively thin film thickness range, it is possible to obtain a thin film transistor having a sufficient breakdown voltage and reliability for normal use. As a result, a high-performance liquid crystal display device having a built-in peripheral circuit operable with normal level transistor characteristics can be obtained in a form that is compatible with sufficient withstand voltage and reliability for normal use.

  Further, in the range satisfying t2 ≧ (t1 / 2), for example, when the thickness of the insulating film 5 is set to about 40 nm so that the thickness of the insulating film 5 is 50 nm or less, even when an excimer laser is used. As in the case of Form 2, it is possible to obtain a thin film transistor that achieves a high mobility, a low threshold voltage, etc. exceeding the normal level.

(Embodiment 4)
Next, Embodiment 4 of the present invention will be described with reference to FIG.

  In the fourth embodiment, a polysilicon film 4b having a large grain size (for example, a maximum grain size of about 0.3 μm) obtained by crystallization using a YAG laser or the like is used, and as shown in FIG. The taper angle θ at the end of the polysilicon film 4b is increased to about 85 degrees.

In this way, in order to make the side surface (end surface) of the polysilicon film 4b substantially perpendicular to the main surface of the glass substrate 1, for example, CF ₄ is used as an etching gas at 0.25 liters / minute (250 sccm), and O ₂ is set at 0.00. Etching may be performed under the conditions of a pressure of 10 Pa and a power of 1500 W while supplying 02 liter / min (20 sccm). The etching time may be 40 seconds. Other configurations are basically the same as those in the first embodiment.

  According to the fourth embodiment, the gate insulating film is formed by using the large-grain-size polysilicon film 4b obtained by crystallization using a YAG laser or the like and reducing the thickness of the insulating film 5 to 300 nm or less. Although it is relatively thick, since the crystallinity of the channel region is good, a thin film transistor having a level sufficient for normal use can be obtained in terms of characteristics.

  On the other hand, although the structure around the polysilicon film is not optimized, the gate insulating film has a thickness of a standard level or more, that is, t2 ≧ (2 × t1) to (3 × t1): t2 is 2 to 3 of t1 Since it has a thickness that satisfies the relationship of at least twice, it is possible to obtain a thin film transistor with sufficient withstand voltage and reliability sufficient for normal use. As a result, a high-performance liquid crystal display device having a built-in peripheral circuit operable with normal level transistor characteristics can be obtained in a form that is compatible with sufficient withstand voltage and reliability for normal use.

  As described above, the embodiments of the present invention have been described. However, it should be considered that the embodiments are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, and includes meanings equivalent to the terms of the claims and all modifications within the scope.

It is a fragmentary sectional view of the liquid crystal display device in Embodiment 1 of this invention. It is sectional drawing which shows the 1st process of the manufacturing process of the liquid crystal display device shown in FIG. It is sectional drawing which shows the 2nd process of the manufacturing process of the liquid crystal display device shown in FIG. It is sectional drawing which shows the 3rd process of the manufacturing process of the liquid crystal display device shown in FIG. It is sectional drawing which shows the 4th process of the manufacturing process of the liquid crystal display device shown in FIG. FIG. 5A is a schematic diagram illustrating an example of a polysilicon film after oxidation and a structure example in the vicinity thereof, and FIG. 5B is a schematic diagram illustrating a structure example of the polysilicon film after etching the oxide film and the vicinity thereof. It is the elements on larger scale of the thin-film transistor in FIG. (A) is a schematic diagram which shows the state which the crack has generate | occur | produced in the insulating film when the taper angle of the edge part of a polysilicon film is large, (b) is a conductive film on the insulating film shown to (a). It is a schematic diagram which shows the state which formed. (A) is a schematic diagram of a polysilicon film and its vicinity when the taper angle at the end is small, and (b) is a schematic diagram of the polysilicon film and its vicinity when the taper angle at the end is relatively large. FIG. It is a figure which shows the relationship between the taper angle of the edge part of a polysilicon film when a channel thickness is 50 nm, and the channel width of a parasitic transistor (TFT). (A), (b) is a schematic diagram which shows the case where a recessed part is formed so that it may penetrate under a polysilicon film. It is a schematic diagram of a polysilicon film and its vicinity when the thickness of a base film is uniform. It is the elements on larger scale of the thin-film transistor in the liquid crystal display device of Embodiment 2 of this invention. It is the elements on larger scale of the thin-film transistor in the liquid crystal display device of Embodiment 3 of this invention. It is the elements on larger scale of the thin-film transistor in the liquid crystal display device of Embodiment 4 of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Glass substrate, 2 Underlayer film, 3 Amorphous silicon film, 4a-4c Polysilicon film, 5, 17 Insulating film, 6a, 6b Gate electrode, 7 Common electrode, 8 Capacitance element, 9a, 9b, 10a, 10b Source / drain Region, 11 n-type thin film transistor, 12 p-type thin film transistor, 13 protective film, 14a-14c, 19 contact hole, 15a-15d electrode, 16a, 16b channel region, 18 planarization film, 20 pixel electrode, 21 oxide film, 22 crack , 23 conductive film, 24, 24a recess, 25 bottom surface, 26 side surface.

Claims (16)

An insulating substrate;
An island-like crystallized silicon film formed on the insulating substrate via a base film, in which a channel region and a source / drain region are formed;
A gate electrode formed on the crystallized silicon film via a gate insulating film,
The angle formed between the bottom surface and the side surface of the crystallized silicon film is 15 degrees or more and 80 degrees or less,
A thin film transistor in which the thickness of the base film on which the crystallized silicon film is not formed is made thinner than the thickness of the base film located immediately below the crystallized silicon film. An insulating substrate;
An island-like crystallized silicon film formed on the insulating substrate via a base film, in which a channel region and a source / drain region are formed;
A gate electrode formed on the crystallized silicon film via a gate insulating film,
The angle formed between the bottom surface and the side surface of the crystallized silicon film is 15 degrees or more and 80 degrees or less,
A thin film transistor, wherein a recess reaching the periphery of the crystallized silicon film or the vicinity thereof without entering under the crystallized silicon film is provided on the surface of the base film located in the vicinity of the periphery of the crystallized silicon film.   The thin film transistor according to claim 1, wherein an entire bottom surface of the crystallized silicon film is in contact with the base film.   4. The thin film transistor according to claim 1, wherein the base film is made of a material having an etching rate smaller than an etching rate of the oxide film of the crystallized silicon film.   5. The thin film transistor according to claim 1, wherein the crystallized silicon film is made of silicon crystallized by irradiation with a YAG laser.   When the thickness of the crystallized silicon film is t1 and the thickness of the gate insulating film is t2, the thickness t2 of the gate insulating film is set so as to satisfy the relationship of t2 ≧ t1 / 2 and t2 ≦ 150 nm. The thin film transistor according to any one of claims 1 to 5.   The thin film transistor according to claim 6, wherein the gate insulating film has a thickness of 50 nm or less.   When the thickness of the crystallized silicon film is t1 and the thickness of the gate insulating film is t2, the thickness t2 of the gate insulating film is set so as to satisfy the relationship of t2 ≧ (3 × t1) and t2 ≦ 300 nm. The thin film transistor according to any one of claims 1 to 5.   The thickness t2 of the gate insulating film is set so as to satisfy the relationship of t2 ≧ t1 and t2 ≦ 150 nm, where t1 is the thickness of the crystallized silicon film and t2 is the thickness of the gate insulating film. The thin film transistor according to any one of claims 1 to 5.   A liquid crystal display device comprising the thin film transistor according to claim 1. An insulating substrate;
A base film formed on the insulating substrate;
A first crystallized silicon film formed on the first portion of the base film and forming a channel region and source / drain regions of the thin film transistor;
A first electrode formed on the first crystallized silicon film via an insulating film and functioning as a gate electrode of the thin film transistor;
A second crystallized silicon film formed on the second portion of the base film and spaced apart from the first crystallized silicon film;
A second electrode formed on the second crystallized silicon film via the insulating film,
The angles formed by the bottom and side surfaces of the first and second crystallized silicon films are 15 degrees or more and 80 degrees or less, respectively.
A liquid crystal display device, wherein a thickness of the base film located between the first and second crystallized silicon films is made thinner than a thickness of the base film located immediately below the first and second crystallized silicon films. An insulating substrate;
A base film formed on the insulating substrate;
A first crystallized silicon film formed on the first portion of the base film and forming a channel region and source / drain regions of the thin film transistor;
A first electrode formed on the first crystallized silicon film via an insulating film and functioning as a gate electrode of the thin film transistor;
A second crystallized silicon film formed on the second portion of the base film and spaced apart from the first crystallized silicon film;
A second electrode formed on the second crystallized silicon film via the insulating film;
The angles formed by the bottom and side surfaces of the first and second crystallized silicon films are 15 degrees or more and 80 degrees or less, respectively.
Peripheral portions of the first and second crystallized silicon films without entering under the first and second crystallized silicon films on the surface of the base film located between the first and second crystallized silicon films or A liquid crystal display device provided with a recess reaching the vicinity thereof. Forming a base film on an insulating substrate;
Forming an amorphous silicon film on the base film;
Irradiating the amorphous silicon film with a laser to form a crystallized silicon film;
Processing the crystallized silicon film into an island shape;
Forming an oxide film by oxidizing the surface of the crystallized silicon film;
Etching the oxide film and the exposed surface of the base film;
Forming a gate insulating film so as to cover the crystallized silicon film;
Forming a gate electrode on the gate insulating film;
A method of manufacturing a thin film transistor, comprising:   The oxidation step is at least one of ultraviolet irradiation treatment, oxygen plasma treatment, oxidation treatment using oxygen gas, water vapor treatment, oxidation treatment using an oxidizing liquid, and oxidation treatment using a solution in which ozone gas is dissolved. The method for manufacturing a thin film transistor according to claim 13, wherein the method is performed using treatment.   The method of manufacturing a thin film transistor according to claim 13 or 14, wherein the etching of the oxide film and the base film is performed using a solution having a hydrofluoric acid concentration of 1% or less. Forming a base film on an insulating substrate;
Forming an amorphous silicon film on the base film;
Irradiating the amorphous silicon film with a laser to form a crystallized silicon film;
Forming the first and second crystallized silicon films at an interval on the base film by processing the crystallized silicon film into an island shape;
Forming first and second oxide films by oxidizing the surfaces of the first and second crystallized silicon films;
Etching the first and second oxide films and the surface of the base film located between the first and second crystallized silicon films;
Forming an insulating film so as to cover the first and second crystallized silicon films;
Forming first and second electrodes on the insulating film,
A method for manufacturing a liquid crystal display device.

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