JP2004088576A - Digital signal transmitting device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a digital signal transmitting device to make normal transmission by reducing the strains of receiving waveforms caused by the increase of the connected number of digital signal transmitting devices. <P>SOLUTION: The digital signal transmitting device is provided with a threshold setting circuit which can set a threshold by means of a voltage dividing circuit in which a resistor and a speed-up capacitor are connected in parallel with each other to the input of a difference input type receiver circuit for controlling an input threshold, by switching with a binary value by reducing the number of difference input type receivers circuits from two to one; a differential driver circuit which supplies a DC voltage or outputs transmitting data to the power supply terminal of the threshold setting circuit; and a driver output control circuit which controls the output of the differential driver circuit with the outputs of a carrier detecting circuit, when a transmission requesting signal is outputted for the transmitting data. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a transmission / reception circuit system of a digital signal transmission device applied to digital baseband transmission.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, when digital signals are transmitted and received between digital signal transmission apparatuses having a built-in DPLL, they are connected to, for example, a half-duplex transmission system as shown in FIG.
This system has a configuration in which digital signal transmission devices (hereinafter, referred to as stations) 12, 13 to 15 for transmitting data are connected to a two-wire transmission line 11. This configuration shows an example in which four stations are connected, but more stations are actually connected. In this half-duplex transmission system, data is exchanged between stations by a mechanism occupying the transmission line 11 and having the right to transmit by one station.
In this example, the station 12 obtains the transmission right and transmits the data, and the other stations 13 to 15 receive the data through the transmission line 11. A period from the end of the reception operation to the start of the transmission operation corresponds to a transmission suspension period, and the transmission line is in a no-signal state. In the transmission pause state, if noise equal to or higher than the reception detection level of the receiving circuit enters, erroneous data will be received, and normal reception will not be possible. In general, in an electric transmission system, a transmission cable is easily affected by external noise, so that it is necessary to devise a receiving circuit.
FIG. 4 shows a functional block diagram of a conventional digital signal transmission device. In FIG. 4, reference numeral 51 denotes a threshold value setting circuit for setting an input threshold value of the differential squelch receiver 52, which will be described later. Reference numeral 52 denotes a differential squelch receiver that identifies received data at or above the voltage level of the threshold setting circuit, converts the data into a digital signal, and outputs the digital signal. Reference numeral 53 denotes a differential zero-cross receiver that identifies data received from a transmission line near 0 V, converts the data into a digital signal, and outputs the digital signal. 54 detects that the leading preamble bit of the received data has a regular pulse width, detects a change point of the received data, turns on the state signal during that period, and outputs the signal. This is a reception carrier detection circuit that turns off the state signal and outputs the signal N bits after N bits or when the pulse width of the reception data is violated. An AND gate 55 outputs data received by the differential zero-cross receiver 53 under the condition that the output of the carrier detection circuit is ON. Reference numeral 56 denotes a DPLL circuit for extracting a reception clock from reception data. Reference numeral 57 denotes a communication LSI for controlling transmission / reception data. Reference numeral 58 denotes a differential driver having a control input function for outputting data transmission.
Next, the reception operation of FIG. 4 will be described. Here, the transmission signal code is a Manchester code, and the transmission frame is described below as an HDLC format.
In the HDLC format, a preamble bit is added to the beginning of a frame, and is used for pulling in the synchronization of the DPLL of the receiving unit. The preamble bit has a 1-bit pulse width as a repeating pattern of "1" and "0". Since the data thereafter becomes a random pattern, repetition of "1" or "0" may be continued. Since the pulse width becomes 1/2 bit length, the repetition frequency becomes twice as large as the preamble bit. Obviously, as the signal frequency increases, the signal loss of the cable increases and the transmission waveform distortion increases. The threshold setting circuit 51 increases the reception detection level of the differential squelch receiver 52 so that noise higher than the reception detection level of the reception circuit may not enter the transmission circuit in the transmission pause state and receive erroneous data. Obviously, when the signal loss increases due to the extension of the transmission cable and the number of connected stations, the distortion of the transmission signal waveform also increases. Since the data received from the differential squelch receiver 52 has a greater pulse width distortion than the data received from the differential zero cross receiver 53, the differential squelch receiver 52 only detects the leading preamble bit of the received data. Then, the subsequent received data is received by the differential zero-cross receiver 53 to improve the waveform distortion. The data received from the differential squelch receiver 52 is input to a carrier detection circuit 54 to determine whether or not there is received data. While the output of the carrier detection circuit is ON, the received data of the differential zero-cross receiver 53 becomes valid and is input to the DPLL 56 to extract the received clock.
FIG. 5 shows a specific example of a circuit diagram of the transmission / reception circuit unit of FIG. The circuit of FIG. 5 will be described.
The differential squelch receiver 52 and the differential zero cross receiver 53 are differential input type receivers. The threshold of the differential input type receiver switches near 0V. A threshold setting circuit 51 is added as a circuit for setting a large differential input threshold in order to prevent reception of erroneous data due to a transmission line short circuit accident or external noise in a non-communication state. The threshold value setting circuit 51 sets a threshold value by the voltage division of the resistance. Since the threshold value of the differential squelch receiver 52 is large, if the rising / falling edge of the transmission waveform is large, the received pulse width distortion becomes large and normal reception cannot be performed, so that only the first preamble bit of the received data is received. . Subsequent received data is received from the differential zero-cross receiver 53 having a small threshold value.
[0003]
[Problems to be solved by the invention]
One of the causes of waveform distortion of a transmission line is a receiver circuit. In the conventional digital signal transmission device, two receivers, a differential squelch receiver 52 and a differential zero cross receiver 53, are required as shown in the receiver circuit diagram of FIG. Assuming that the equivalent input resistance of the receiver is Zi, the equivalent input resistance of the receiver circuit viewed from the transmission line is の of Zi. When the number of connected stations increases, the characteristic impedance on the transmission line greatly fluctuates, and the distortion of the transmission waveform increases, so that normal transmission cannot be performed.
SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a digital signal transmission device capable of performing normal transmission by reducing received waveform distortion due to an increase in the number of connected digital signal transmission devices. With the goal.
[0004]
[Means for Solving the Problems]
In order to solve the above-mentioned problem, the present invention reduces the number of differential input type receiver circuits of two to one and controls the input threshold value by switching the threshold value between two levels. And a voltage setting circuit in which a speed-up capacitor is connected in parallel to set a threshold, and a differential type for supplying a DC voltage to a power terminal of the threshold setting circuit or outputting transmission data. A digital signal transmission device comprising: a driver circuit; and a driver output control circuit that controls the output of the differential driver circuit based on the output of a carrier detection circuit and the output of a transmission request signal for transmission data.
The digital signal transmission apparatus of the present invention having such a function is improved so that the reception waveform distortion due to an increase in the number of connected digital signal transmission systems can be reduced and normal transmission can be performed.
[0005]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a description will be given based on examples of the present invention.
FIG. 1 shows a functional block diagram of the digital signal transmission device of the present invention.
FIG. 2 shows a specific circuit example of the transmission / reception circuit unit in FIG. The same components as those of the prior art are denoted by the same reference numerals and the description thereof will be omitted, and only different points will be described.
The differences between the present invention and the prior art are as follows.
In FIG. 1, the supply of the DC power supply voltage and the transmission of data of the threshold value setting circuit 51 are performed by the same differential driver 58, and the output signal of the carrier detection circuit 54 and the OR gate 59 to which the RTS output signal of the communication LSI 57 is input. The output controls the output of the differential driver 58. In the threshold setting circuit 51 shown in FIG. 2, speed-up capacitors C3 and C4 are added in parallel with R1 and R2. The speed-up capacitors C3 and C4 prevent the data transmission signal from being attenuated by the voltage dividing resistors R1 and R2. By using a circuit system in which the DC power supply voltage of the threshold value setting circuit 51 is supplied from the differential driver 58, common mode noise invading from the transmission line occurs while the output of the differential driver 58 is OFF. The flow out of the threshold value setting circuit 51 to the power supply circuits VC and GND via the output terminal of the differential driver 58 and the internal output circuit of the differential driver 58 is prevented to prevent the balance of the receiving circuit from lowering. are doing.
The operation of the binary control of the threshold value will be described with reference to FIG.
During the data receiving operation, the output of the differential driver 58 is controlled by the output signal of the carrier detection circuit 54. When the output signal of the carrier detection circuit 54 is OFF ("1"), a DC voltage is output to the output of the differential driver 58, and a current flows through the voltage dividing resistors R1 to R4 of the threshold value setting circuit 51. , A threshold voltage is generated. That is, squelch reception becomes possible. When the output signal of the carrier detection circuit 54 is ON (“0”), the output of the differential driver 58 becomes no voltage and the current flowing through the voltage dividing resistors R1 to R4 is cut off, so that the threshold voltage Also has no voltage, and zero-cross reception is possible.
The operation of data transmission will be described with reference to FIG. The output of the differential driver 58 is controlled by the RTS output signal of the communication LSI 57. When the RTS output signal is ON (“1”), a pulse voltage of transmission data is output from the output of the differential driver 58 and passes through the speed-up capacitors C3, C4 and C1, C2 of the threshold value setting circuit 51. Output to the transmission line.
Next, the receiving operation will be described with reference to FIG.
The data received from the differential squelch receiver 52 is input to a carrier detection circuit 54 to determine whether or not there is received data. In the non-communication state, the output of the carrier detection circuit 54 is turned off (“”), so that a DC voltage is output to the output of the differential driver 58 and a current flows through the threshold setting circuit 51 to generate a threshold voltage. Then, the threshold value of the differential squelch receiver 52 is set to be larger than 0V. When the received data exceeds the threshold value of the differential squelch receiver 52 and the output of the carrier detection circuit 54 is turned on (“0”), the output of the differential driver 58 becomes no voltage, Since the current of the setting circuit 51 is cut off, the threshold value of the differential squelch receiver 52 is set low near 0V. The differential squelch receiver 52 outputs the received data switched around 0 V, and is input to the DPLL 56 during the period when the output of the carrier detection circuit 54 is ON (“0”), and the reception clock is extracted. This is equivalent to the receiving operation of the conventional digital signal transmission device.
[0006]
【The invention's effect】
As described above, according to the present invention, the differential driver can be configured by using the output signal of the carrier detection circuit and the threshold setting circuit which can set the input threshold value to two values with one differential input type receiver. By using a digital signal transmission device including a receiving unit that switches to a binary threshold value by a driver output control circuit that controls the output, the conventional two-circuit differential input type receiver can be reduced to one circuit, and the transmission can be reduced. The equivalent input resistance of the differential input type receiver circuit viewed from the line is improved by a factor of two, and the effect of preventing an increase in the distortion of the transmission waveform due to an increase in the number of connected stations is obtained. Further, by using a circuit system for supplying power from the differential driver to the power supply of the threshold setting circuit of the differential input type receiver circuit, during the period in which the output of the differential driver 58 is OFF, the common voltage that invades from the transmission line. This has the effect of suppressing intrusion of mode noise and preventing the balance of the receiving circuit from lowering.
[Brief description of the drawings]
FIG. 1 shows a functional block diagram of a digital signal transmission device of the present invention.
FIG. 2 shows a specific example of a transmission / reception circuit of the present invention.
FIG. 3 shows a configuration of a half-duplex transmission system to which a digital signal transmission device is connected.
FIG. 4 shows a functional block diagram of a conventional digital signal transmission device.
FIG. 5 shows a specific circuit example of a conventional transmitting / receiving circuit.
[Explanation of symbols]
11 Transmission Line 12-15 Station 51 Threshold Setting Circuit 52 Differential Squelch Receiver 53 Differential Zero Cross Receiver 54 Carrier Detection Circuit 55 AND Gate 56 DPLL
57 Communication LSI
58 Differential driver 59 OR gates R1 to R4 Voltage dividing resistors C1 to C4 Speed-up capacitor VC Power supply voltage for circuit + side GND Power supply voltage for circuit-side (0 V)
RT Termination resistance of transmission cable

Claims (1)

A differential input type receiver circuit for level-converting a transmission data signal to a digital signal via a transmission line in a digital baseband transmission and outputting the digital signal;
A threshold setting circuit capable of setting a threshold by a voltage dividing circuit in which a resistor and a speed-up capacitor are connected in parallel to the input of the differential input type receiver circuit;
A differential driver circuit for supplying a DC voltage to a power supply terminal of the threshold value setting circuit or outputting transmission data,
A digital signal transmission device comprising: a driver output control circuit that controls an output of the differential driver circuit by an output of a carrier detection circuit or an output of a transmission request signal for transmission data.

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