JP2003318579A - Heat radiation method for fet with heat sink plate - Google Patents
Heat radiation method for fet with heat sink plateInfo
- Publication number
- JP2003318579A JP2003318579A JP2002121865A JP2002121865A JP2003318579A JP 2003318579 A JP2003318579 A JP 2003318579A JP 2002121865 A JP2002121865 A JP 2002121865A JP 2002121865 A JP2002121865 A JP 2002121865A JP 2003318579 A JP2003318579 A JP 2003318579A
- Authority
- JP
- Japan
- Prior art keywords
- fet
- heat
- wiring board
- printed wiring
- heat dissipation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/27—Manufacturing methods
- H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
- H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
Landscapes
- Cooling Or The Like Of Electrical Apparatus (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、放熱板付きＦＥＴ
の放熱方法に関し、特に、放熱板付きＦＥＴが実装され
るプリント配線板を利用して放熱促進を図る放熱板付き
ＦＥＴの放熱方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a FET with a heat sink.
The present invention particularly relates to a heat radiation method for a FET with a heat sink, which promotes heat radiation by using a printed wiring board on which the FET with a heat sink is mounted.
【０００２】[0002]
【従来の技術】従来、放熱板付きＦＥＴの放熱方法は、
図４に示すように、絶縁基材１１（例えば、ガラス繊維
布にエポキシ樹脂、フェノール樹脂などを結合剤とした
積層板）の表面に導電箔１２（通常は銅箔）がパターン
形成されてなるプリント配線板１に、ＦＥＴ本体部２１
のドレイン電極から延在し下面を除いて樹脂で覆われた
放熱板２２をはんだ付けし、ＦＥＴ本体部２１で発生し
た熱を放熱板２２からプリント配線板１を介して下面側
空間へ放熱させるとともに放熱板から直接的に上面側空
間へ放熱させるようにしていた。2. Description of the Related Art Conventionally, the heat radiation method for a FET with a heat sink is
As shown in FIG. 4, a conductive foil 12 (usually a copper foil) is patterned on the surface of an insulating base material 11 (for example, a laminated board using glass fiber cloth with epoxy resin, phenol resin, or the like as a binder). On the printed wiring board 1, the FET body 21
A heat radiation plate 22 extending from the drain electrode of the FET and covered with a resin except for the lower surface is soldered, and the heat generated in the FET body 21 is radiated from the heat radiation plate 22 to the lower surface side space via the printed wiring board 1. At the same time, heat is radiated directly from the heat sink to the upper space.
【０００３】[0003]
【発明が解決しようとする課題】しかしながら、プリン
ト配線板１の絶縁基材の熱伝導率が低いため、ＦＥＴ本
体部２１で発生した熱がプリント配線板１の下面側空間
へ効率良く放熱されず、ＦＥＴ２の温度上昇を十分に抑
制することが困難であるという問題があった。However, since the thermal conductivity of the insulating base material of the printed wiring board 1 is low, the heat generated in the FET body 21 is not efficiently radiated to the space on the lower surface side of the printed wiring board 1. However, there is a problem that it is difficult to sufficiently suppress the temperature rise of the FET2.
【０００４】本発明は、上記のような従来技術の問題点
を解決し、きわめて簡単な構成によってＦＥＴの温度上
昇を抑制することが可能な放熱板付きＦＥＴの放熱方法
を提供することを目的とする。An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a heat radiation method for a FET with a heat radiation plate, which is capable of suppressing the temperature rise of the FET with an extremely simple structure. To do.
【０００５】[0005]
【課題を解決するための手段】請求項１に係る放熱板付
きＦＥＴの放熱方法は、絶縁基材の表面に導電箔がパタ
ーン形成されてなるプリント配線板に実装される放熱板
付きＦＥＴの放熱方法において、前記プリント配線板の
ＦＥＴ実装位置に予めめっきスルーホールを設けてお
き、該めっきスルーホール内にはんだを充填させるよ
う、前記放熱板付きＦＥＴの放熱板を前記プリント配線
板にはんだ付けすることを特徴とする。According to a first aspect of the present invention, there is provided a heat dissipation method for a FET with a heat dissipation plate, which is mounted on a printed wiring board having a conductive foil patterned on a surface of an insulating base material. In the method, a plated through hole is provided in advance in the FET mounting position of the printed wiring board, and a heat sink of the FET with a heat sink is soldered to the printed wiring board so that the plated through hole is filled with solder. It is characterized by
【０００６】請求項１に係る加熱板付きＦＥＴの放熱方
法において、ＦＥＴの発熱は、図４に示した従来例と同
様、放熱板から、プリント配線板におけるＦＥＴ実装位
置においてめっきスルーホールの形成されていない部位
を介して下面側空間へ放熱されるが、この放熱ルート以
外に、ＦＥＴ直下のめっきスルーホール内のはんだを通
る熱伝導率に優れた放熱ルートを経て下面側空間へ放熱
される。このため、放熱量が増大し、ＦＥＴの温度上昇
を抑制し得るようになる。In the method for radiating heat from a FET with a heating plate according to the first aspect of the present invention, as in the conventional example shown in FIG. 4, heat generated by the FET causes a plated through hole to be formed from the heat radiating plate at the FET mounting position on the printed wiring board. Heat is radiated to the lower surface side space through the unopened portion, but in addition to this heat radiating route, heat is radiated to the lower surface side space through a heat radiating route having excellent thermal conductivity that passes through the solder in the plated through hole directly under the FET. Therefore, the amount of heat radiation increases, and the temperature rise of the FET can be suppressed.
【０００７】請求項２に係る放熱板付きＦＥＴの放熱方
法は、絶縁基材の表面に導電箔がパターン形成されてな
るプリント配線板に実装される放熱板付きＦＥＴの放熱
方法において、前記プリント配線板のＦＥＴ実装位置か
ら延在するドレインパット領域に予めめっきスルーホー
ルを設けておき、前記放熱板付きＦＥＴの放熱板を前記
プリント配線板にはんだ付けするとともに前記めっきス
ルーホール内にはんだを充填させることを特徴とする。According to a second aspect of the present invention, there is provided a method for radiating heat from a FET with a heat radiating plate, which is mounted on a printed wiring board having a conductive foil pattern formed on a surface of an insulating base material. A plated through hole is provided in advance in a drain pad region extending from the FET mounting position of the board, and the heat sink of the FET with a heat sink is soldered to the printed wiring board and the plated through hole is filled with solder. It is characterized by
【０００８】請求項２に係る放熱板付きＦＥＴの放熱方
法において、ＦＥＴの発熱は、図４に示した従来例と同
様、放熱板から、プリント配線板におけるＦＥＴ実装位
置を介して下面側空間へ放熱されるが、この放熱ルート
以外に、ドレインパット及びとめっきスルーホール内の
はんだを通る熱伝導率に優れた放熱ルートを経て下面側
空間へ放熱される。このため、放熱量が増大し、ＦＥＴ
の温度上昇を抑制し得るようになる。In the method for radiating heat from a FET with a heat radiating plate according to a second aspect of the present invention, heat generated by the FET is from the heat radiating plate to the space on the lower surface side through the FET mounting position on the printed wiring board, as in the conventional example shown in FIG. In addition to this heat radiation route, the heat is also radiated to the space on the lower surface side via the drain pad and the heat radiation route having excellent thermal conductivity through the solder in the plated through hole. Therefore, the amount of heat radiation increases, and the FET
It becomes possible to suppress the temperature rise.
【０００９】[0009]
【発明の実施の形態】以下、本発明の実施形態を図面に
基づいて説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.
【００１０】図１は、本発明の第１実施形態に係る放熱
板付きＦＥＴの放熱方法を使用したプリント配線板にＦ
ＥＴを実装した状態を表す断面図を示す。FIG. 1 shows a printed wiring board using the heat radiation method for the FET with heat radiation plate according to the first embodiment of the present invention.
The sectional view showing the state which mounted ET is shown.
【００１１】図１において、１はプリント配線板、２は
放熱板付きＦＥＴをそれぞれ表す。プリント配線板１
は、絶縁基材１１（例えば、ガラス繊維布にエポキシ樹
脂、フェノール樹脂などを結合剤とした積層板）の表面
に導電箔１２（通常は銅箔）がパターン形成されてな
る。さらに、プリント配線板１には、ＦＥＴ２の実装位
置に予め１つ又は複数のめっきスルーホール１３が設け
られており、このめっきスルーホール１３内に、はんだ
１４が充填されている。ＦＥＴ２は、ＦＥＴ本体部２１
のドレイン電極（図示せず）から延在し下面を除いて樹
脂で覆われた放熱板２２をプリント配線板１の上面には
んだ付けすることによって実装されている。なお、上記
めっきスルーホール１３内のはんだ１４は、このはんだ
付け作業の際にめっきスルーホール１３内に充填され
る。In FIG. 1, 1 is a printed wiring board and 2 is a FET with a heat sink. Printed wiring board 1
Is formed by patterning a conductive foil 12 (usually a copper foil) on the surface of an insulating base material 11 (for example, a laminated plate using glass fiber cloth with an epoxy resin, a phenol resin, or the like as a binder). Further, the printed wiring board 1 is provided with one or a plurality of plated through holes 13 in advance at the mounting position of the FET 2, and the plated through holes 13 are filled with solder 14. FET2 is the FET body 21
The heat dissipation plate 22 extending from the drain electrode (not shown) and covered with a resin except for the lower surface is mounted on the upper surface of the printed wiring board 1 by soldering. The solder 14 in the plated through hole 13 is filled in the plated through hole 13 during this soldering work.
【００１２】次に、動作中のＦＥＴ２が発した熱の放熱
ルートについて説明する。ＦＥＴ２の発熱は、図４に示
した従来例と同様、放熱板２２から、プリント配線板１
におけるＦＥＴ実装位置においてめっきスルーホール１
３の形成されていない部位を介して下面側空間へ放熱さ
れる。さらに、ＦＥＴ２の発熱は、上記従前からの放熱
ルート以外に、ＦＥＴ２直下のめっきスルーホール１３
内のはんだ１４を通る熱伝導率に優れた放熱ルートを経
て下面側空間へ放熱されることになる。このため、放熱
量は増大し、ＦＥＴ２の温度上昇を抑制し得るようにな
る。Next, a heat radiation route of heat generated by the operating FET 2 will be described. As in the conventional example shown in FIG. 4, heat generated by the FET 2 is transferred from the heat sink 22 to the printed wiring board 1
Through hole 1 at the FET mounting position in
Heat is radiated to the space on the lower surface side through a portion where 3 is not formed. Further, the heat generated by the FET 2 is generated by the plating through hole 13 directly below the FET 2 in addition to the above-described heat radiation route.
The heat is dissipated to the space on the lower surface side through a heat dissipation route having excellent thermal conductivity that passes through the solder 14 inside. Therefore, the amount of heat radiation increases, and the temperature rise of the FET 2 can be suppressed.
【００１３】図２は、第２実施形態に係る放熱板付きＦ
ＥＴの放熱方法を使用したプリント配線板にＦＥＴを実
装した状態を表す外観斜視図、図３は、その断面図をそ
れぞれ示す。FIG. 2 shows an F with a radiator plate according to the second embodiment.
FIG. 3 is an external perspective view showing a state in which an FET is mounted on a printed wiring board using the heat dissipation method of ET, and FIG. 3 is a sectional view thereof.
【００１４】図２及び図３において、プリント配線板１
は、基本的には上記第１実施形態のプリント配線板１と
同様に構成されている。さらに、プリント配線板１に
は、ＦＥＴ実装位置からドレインパット１５が延在して
おり、このドレインパット領域１５に予め１つ又は複数
のめっきスルーホール１３が設けられており、このめっ
きスルーホール１３内に、はんだ１４が充填されてい
る。ＦＥＴ２は、ＦＥＴ本体部２１のドレイン電極(図
示せず)から延在し下面を除いて樹脂で覆われた放熱板
２２をプリント配線板１の上面にはんだ付けすることに
よって実装されている。また、このはんだ付け作業の
際、ドレインパット領域１５のめっきスルーホール１３
内にはんだ１４が充填される。図中の他の符号１６及び
１７はゲートパット及びソースパッド、１８及び１９は
リードを表す。2 and 3, the printed wiring board 1 is shown.
Is basically configured similarly to the printed wiring board 1 of the first embodiment. Further, the drain pad 15 extends from the FET mounting position on the printed wiring board 1, and one or more plated through holes 13 are provided in advance in the drain pad region 15. Solder 14 is filled therein. The FET 2 is mounted by soldering a heat radiating plate 22 extending from a drain electrode (not shown) of the FET body 21 and covered with a resin except the lower surface to the upper surface of the printed wiring board 1. Also, during this soldering work, the plated through hole 13 in the drain pad region 15 is
Solder 14 is filled inside. Other reference numerals 16 and 17 in the drawing represent gate pads and source pads, and 18 and 19 represent leads.
【００１５】次に、動作中のＦＥＴ２が発した熱の放熱
ルートについて説明する。ＦＥＴ２の発熱は、図４に示
した従来例と同様、放熱板２２から、プリント配線板１
を介して下面側空間へ放熱される。さらに、ＦＥＴ２の
発熱は、上記従前からの放熱ルート以外に、ドレインパ
ット１５及びめっきスルーホール１３内のはんだ１４を
通る熱伝導率に優れた放熱ルートを経て下面側空間へ放
熱されることになる。このため、放熱量は増大し、ＦＥ
Ｔの温度上昇を抑制し得るようになる。Next, the heat radiation route of the heat generated by the operating FET 2 will be described. As in the conventional example shown in FIG. 4, heat generated by the FET 2 is transferred from the heat sink 22 to the printed wiring board 1
Heat is radiated to the space on the lower surface side via. Further, the heat generated by the FET 2 is radiated to the space on the lower surface side through a heat radiation route having excellent thermal conductivity that passes through the drain pad 15 and the solder 14 in the plated through hole 13, in addition to the above-described heat radiation route. . Therefore, the amount of heat radiation increases and FE
The temperature rise of T can be suppressed.
【００１６】[0016]
【発明の効果】本発明によるＦＥＴの放熱方法による
と、きわめて簡単な構成によってＦＥＴの温度上昇を抑
制することが可能になる。According to the heat dissipation method of the FET of the present invention, the temperature rise of the FET can be suppressed with an extremely simple structure.
【図１】本発明の第１実施形態に係る放熱板付きＦＥＴ
の放熱方法を使用したプリント配線板にＦＥＴを実装し
た状態を表す断面図である。FIG. 1 is a FET with a heat sink according to a first embodiment of the present invention.
FIG. 6 is a cross-sectional view showing a state in which an FET is mounted on a printed wiring board using the heat radiation method of FIG.
【図２】第２実施形態に係る放熱板付きＦＥＴの放熱方
法を使用したプリント配線板にＦＥＴを実装した状態を
表す外観斜視図である。FIG. 2 is an external perspective view showing a state in which an FET is mounted on a printed wiring board using the heat dissipation method for the FET with a heat dissipation plate according to the second embodiment.
【図３】その断面図である。FIG. 3 is a sectional view thereof.
【図４】従来のＦＥＴの放熱方法を説明するための断面
図である。FIG. 4 is a cross-sectional view for explaining a conventional heat dissipation method of an FET.
１ プリント配線板 １１ 絶縁基材 １２ 導電箔 １３ めっきスルーホール １４ はんだ １５ ドレインパット領域 ２ 放熱板付きＦＥＴ ２１ ＦＥＴ本体部 ２２ 放熱板 1 printed wiring board 11 Insulating material 12 Conductive foil 13 plated through holes 14 Solder 15 Drain pad area 2 FET with heat sink 21 FET body 22 Heat sink
───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5E322 AA01 AA02 AA11 AB02 5F036 AA01 BA23 BB03 BC06 BC33 BE03 ─────────────────────────────────────────────────── ─── Continued front page F-term (reference) 5E322 AA01 AA02 AA11 AB02 5F036 AA01 BA23 BB03 BC06 BC33 BE03
Claims (2)
されてなるプリント配線板に実装される放熱板付きＦＥ
Ｔの放熱方法において、前記プリント配線板のＦＥＴ実
装位置に予めめっきスルーホールを設けておき、該めっ
きスルーホール内にはんだを充填させるよう、前記放熱
板付きＦＥＴの放熱板を前記プリント配線板にはんだ付
けすることを特徴とする放熱板付きＦＥＴの放熱方法。1. An FE with a heat dissipation plate mounted on a printed wiring board having a conductive foil patterned on the surface of an insulating base material.
In the heat dissipation method of T, a plated through hole is provided in advance in the FET mounting position of the printed wiring board, and the heat dissipation plate of the FET with the heat dissipation plate is attached to the printed wiring board so that the plated through hole is filled with solder. A heat dissipation method for a FET with a heat dissipation plate, which is characterized by soldering.
されてなるプリント配線板に実装される放熱板付きＦＥ
Ｔの放熱方法において、前記プリント配線板のＦＥＴ実
装位置から延在するドレインパット領域に予めめっきス
ルーホールを設けておき、前記放熱板付きＦＥＴの放熱
板を前記プリント配線板にはんだ付けするとともに前記
めっきスルーホール内にはんだを充填させることを特徴
とする放熱板付きＦＥＴの放熱方法。2. An FE with a heat dissipation plate, which is mounted on a printed wiring board in which a conductive foil is patterned on the surface of an insulating base material.
In the heat dissipation method of T, a plated through hole is provided in advance in a drain pad region extending from the FET mounting position of the printed wiring board, and the heat dissipation plate of the FET with the heat dissipation plate is soldered to the printed wiring board and A heat dissipation method for a FET with a heat dissipation plate, characterized in that solder is filled in the plated through holes.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002121865A JP2003318579A (en) | 2002-04-24 | 2002-04-24 | Heat radiation method for fet with heat sink plate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002121865A JP2003318579A (en) | 2002-04-24 | 2002-04-24 | Heat radiation method for fet with heat sink plate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003318579A true JP2003318579A (en) | 2003-11-07 |
Family
ID=29537639
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002121865A Pending JP2003318579A (en) | 2002-04-24 | 2002-04-24 | Heat radiation method for fet with heat sink plate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003318579A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007184455A (en) * | 2006-01-10 | 2007-07-19 | Hitachi Kokusai Electric Inc | Electronic circuit board |
| KR100768235B1 (en) * | 2006-06-13 | 2007-10-18 | 삼성에스디아이 주식회사 | Heat dissipation structure of printed circuit board having surface mounted power device and plasma display module including the same |
| JP2008078271A (en) * | 2006-09-20 | 2008-04-03 | Sumitomo Wiring Syst Ltd | Printed-circuit board equipped with heat dissipating structure, and its manufacturing method |
| US7381905B2 (en) | 2004-05-31 | 2008-06-03 | Calsonic Kansei Corporation | Structure for fixing an electronic device to a substrate |
| WO2016013362A1 (en) * | 2014-07-22 | 2016-01-28 | 株式会社オートネットワーク技術研究所 | Circuit structure |
| JP2016122679A (en) * | 2014-12-24 | 2016-07-07 | 株式会社オートネットワーク技術研究所 | Circuit constitution body and manufacturing method for the same |
| DE102019215523A1 (en) * | 2019-10-10 | 2021-04-15 | Vitesco Technologies GmbH | Power semiconductor component and method for manufacturing a power semiconductor component |
-
2002
- 2002-04-24 JP JP2002121865A patent/JP2003318579A/en active Pending
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7381905B2 (en) | 2004-05-31 | 2008-06-03 | Calsonic Kansei Corporation | Structure for fixing an electronic device to a substrate |
| JP2007184455A (en) * | 2006-01-10 | 2007-07-19 | Hitachi Kokusai Electric Inc | Electronic circuit board |
| KR100768235B1 (en) * | 2006-06-13 | 2007-10-18 | 삼성에스디아이 주식회사 | Heat dissipation structure of printed circuit board having surface mounted power device and plasma display module including the same |
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| WO2016013362A1 (en) * | 2014-07-22 | 2016-01-28 | 株式会社オートネットワーク技術研究所 | Circuit structure |
| CN106471870A (en) * | 2014-07-22 | 2017-03-01 | 株式会社自动网络技术研究所 | Circuit structure |
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| JP2016122679A (en) * | 2014-12-24 | 2016-07-07 | 株式会社オートネットワーク技術研究所 | Circuit constitution body and manufacturing method for the same |
| DE102019215523A1 (en) * | 2019-10-10 | 2021-04-15 | Vitesco Technologies GmbH | Power semiconductor component and method for manufacturing a power semiconductor component |
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