JP2003245278A - Ultrasonic diagnostic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow an ultrasonic diagnostic apparatus to flexibly deal with its change by alleviating a designing load. <P>SOLUTION: Modules 14 to 26 are connected to a bus 12. Data are DMA- transferred between the modules. A high-speed general-purpose bus is used as the bus 12. Control data is transferred, in addition to ultrasonic data by utilizing the bus 12. A transfer unit is a data block, which includes an attribute and data. Since the high-speed bus is used, even when the modules are increased or decreased, the change of designing is facilitated. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultrasonic diagnostic apparatus, and more particularly to a system architecture of the ultrasonic diagnostic apparatus.

[0002]

2. Description of the Related Art An ultrasonic diagnostic apparatus is composed of a plurality of processing units such as a beam processing unit, a scan conversion unit and an image processing unit. These processing units are individually connected to each other by a dedicated bus along the flow of processing received signals. Further, a dedicated control bus is provided between the host CPU and each processing unit for controlling those processing units.

Recently, the number of processing units mounted on an ultrasonic diagnostic apparatus is increasing due to the high functionality of the ultrasonic diagnostic apparatus. Similarly, the increase in digital signal processing has led to an increase in the number of signal lines on the backplane on which each processing unit is mounted. There is also a circumstance that it is frequently necessary to redesign the system due to the specification change.

As described above, the conventional apparatus configuration has a problem in that it cannot flexibly cope with an increase in functions and a change in specifications. In particular, the increase in data amount and transfer rate has spurred the problem.

An object of the present invention is to reduce the design load of an ultrasonic diagnostic apparatus and to flexibly cope with changes in the apparatus configuration.

[0006]

In order to achieve the above object, the present invention includes a plurality of processing modules and at least one system internal bus to which the plurality of processing modules are commonly connected. The first data block including ultrasonic data and the second data block including control data are transferred between the processing modules of the above 1 through the internal bus.

According to the above configuration, a plurality of processing modules are connected to each other via a common internal bus (many-to-many transmission is performed), that is, the first data block and the first data block are transmitted via the internal bus. Two data blocks are transferred.
That is, ultrasonic data and control data are exchanged using the same internal bus. Each processing module is preferably configured as a module board mounted on a backplane board, in which case the internal bus is arranged on the backplane board.

In the above structure, ultrasonic data and control data are transmitted by the same internal bus. Therefore, according to the present invention, basically the same internal bus can be used as it is even if the number of modules is increased or decreased, so that the design can be easily changed. Incidentally, it is desirable to use various general-purpose buses used in computers as the internal bus.

Preferably, the first and second data blocks are DMA (Direct Memory Access) transferred. This is to transfer each data in burst without passing through the host CPU. In order to avoid contention for using the internal bus, it is desirable to separately provide a circuit for performing bus control. In this case, by entrusting complicated bus control (arbitration) to the general-purpose bus bridge, the designer of the ultrasonic diagnostic apparatus can concentrate on the design of each processing unit. D
Even when the internal bus is occupied between the specific processing modules by the MA transfer, the host CPU is generally disconnected from the internal bus by the bus bridge, so that the load on the host CPU does not occur. In DMA transfer, the processing module of the transfer source serves as an initiator, and data transfer is performed in data block units.

Preferably, the ultrasonic data is transferred in units of ultrasonic beams or display lines.

Preferably, the first data block includes an attribute in addition to the ultrasonic data,
The attributes include a frame identifier and an ultrasonic beam identifier or a display line identifier.

Preferably, a plurality of systems of internal buses are provided as the internal bus, and the internal buses are used properly according to the type of the ultrasonic data. Preferably, a first internal bus and a second internal bus are provided as the internal buses, the first internal bus is used for transferring pre-beam processing data, and the second internal bus is used for post-beam processing data and images. Used for data transfer.

Preferably, the plurality of processing modules include a host module having a host CPU, and the host module executes software processing of ultrasonic data.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a preferred embodiment of the ultrasonic diagnostic apparatus according to the present invention, and FIG. 1 is a block diagram showing the overall configuration of the apparatus.

In FIG. 1, the bus 12 as an internal bus
A plurality of modules 14 to 26 are connected to.
In the example shown in FIG. 1, the memory module 14, the beam processing module 16, the beam processing module 18, the scan conversion module 20, the scan conversion module 22, the image processing module 24, and the host module 26 are connected to the bus 12. .

The internal bus 12 is formed on a backplane board in the ultrasonic diagnostic apparatus, and each of the modules 14 to 26 constitutes a module board (board).

As the bus 12 described above, a high-speed general-purpose bus used in a computer or the like in this embodiment is used. Specifically, for example, a compact PC
I-bus is used. Although one bus 12 is shown in the example shown in FIG. 1, a plurality of buses may be provided depending on the type of data to be transmitted, as will be described later with reference to FIG.

In FIG. 1, a probe 10 is an ultrasonic probe that transmits and receives ultrasonic waves. The probe 10 is provided with an array transducer including a plurality of vibrating elements. An ultrasonic beam is formed by the array transducer, and the ultrasonic beam is electronically scanned. A transmitter module and a receiver module (not shown) are provided for forming the ultrasonic beam and for electronic scanning. The transmission module functions as a transmission beam former and supplies a driving signal to the plurality of vibrating elements. The reception module functions as a reception beam former, and performs phasing addition processing on the reception signals from the plurality of vibrating elements. By the way, the receiving module is also equipped with an A / D converter provided for each channel.

The memory module shown in FIG. 1 stores the received signal after the above phasing addition, and transfers the received signal to the subsequent module. Specifically, the memory module 14 has a beam memory 14A and an output unit 14C. The beam memory 14A is a memory that stores a reception signal (that is, echo data) in units of one ultrasonic beam. The beam memory 14A may store only the reception signal corresponding to one ultrasonic beam, or may store the reception signal for one frame, for example. The output unit 14C outputs the received signal (data before beam processing) on the beam memory 14A to the subsequent predetermined module.
It is a circuit for MA transfer.

The data block 60 transferred between the modules will be described with reference to FIG. The data block 60 is roughly divided into a data block for transferring ultrasonic data and a data block for transferring control data. In any case, the data block 60 consists of attributes 64 and data 66 as shown in FIG. Of course, this data structure is an example.

The attribute 64 is attribute information such as a data type, a frame identifier, a beam identifier, frame synchronization information, and a data size. Of course, the attribute 64 is set according to the content of the data 66. The data 66 is roughly classified into ultrasonic data and control data. When the data 66 is ultrasonic data, it is pre-beam processing data, post-beam processing data, or image data. The pre-beam processing data is the data before the beam processing described later, the post-beam processing data is the pre-scan conversion data after the beam processing, and the image data is the image data formed by the scan conversion. is there.

As described above, data is transferred in units of data blocks between the modules shown in FIG. Therefore, when a data block is transferred from the above-mentioned memory module 14 to, for example, the beam processing modules 16 and 18, necessary data such as an attribute is added to the pre-beam processing data, whereby the data block is configured. , That data block will be burst-transferred.

The beam processing module 16 is composed of an echo processing section 16A, an input section 16B and an output section 16C. The echo processing unit 16A executes various processes necessary for forming, for example, a B-mode image, such as detection and logarithmic compression processing. Input unit 16B and output unit 16
C is a unit necessary for performing the DMA transfer of the data block. In this beam processing module 16, the data block DMA-transferred is input unit 16B.
The pre-beam processing data received in the data block is processed by the echo processing unit 16A, and the post-beam processing data, that is, the post-beam processing data is processed by the output unit 1.
The data block is reconstructed by the 6C, and the data block is DMA-transferred to, for example, the scan conversion module 20 in the subsequent stage. The basic flow of the above processing is the same in each module.

The beam processing module 18 comprises a Doppler processing section 18A, an input section 18B and an output section 18C. The Doppler processing unit 18A has a quadrature detection circuit, an autocorrelation circuit, and the like, and executes processing necessary for forming a color Doppler image. Input unit 18B and output unit 1
8C DM data block with other modules
This is a circuit for A transfer.

The scan conversion module 20 includes a scan conversion unit 2
0A, an input unit 20B and an output unit 20C. The scan conversion unit 20A executes coordinate conversion and interpolation processing necessary for forming a B-mode image. Input section 2
The 0B and the output unit 20C are circuits for DMA transfer of data blocks with other modules.

The scan conversion module 22 includes the scan conversion unit 2
2A, an input unit 22B and an output unit 22C. The scan conversion unit 22A executes coordinate conversion and interpolation processing for forming a color Doppler image. Input unit 22
B and the output unit 22C are circuits for performing DMA transfer of data blocks with other modules.

The image processing module 24 includes the image processing unit 2
4A, an input unit 24B and an output unit 24C. The image processing unit 24A executes a process of combining a B-mode image with a color Doppler image and various image processes. Input section 24B
The output unit 24C is a circuit for performing a DMA transfer of the data block with another module. A display device that displays a display image obtained as a result of image processing is connected to the image processing module 24.

The host module 26 is the host CPU 3
2 and a bus bridge circuit 34. Host CPU3
2 controls the operation of each processing unit and executes necessary software processing for ultrasonic data. For example, when a specific image process is performed by software instead of hardware, the image data is passed to the host CPU 32 to perform the process, and the result is returned to the image processing module 24.

The bus bridge circuit 34 is a circuit for controlling data transfer on the bus 12. For example, if a data block is from one module to another module D
When MA transfer is performed, the host CPU 32 is disconnected from the bus 12 by the bus bridge circuit 34.
Further, the bus bridge circuit 34 arbitrates transfer so that DMA transfer does not conflict. The external storage device 30 is connected to the host module 26, and necessary programs and data are stored on the external storage device 30. When image processing is performed by the host CPU, the image data as the processing result may be stored in the external storage device 30. The external storage device 30 exhibits the same function as the external storage installed in a normal computer or the like. The external storage device 30 may be, for example, a hard disk device.

In the above description, the transfer of ultrasonic data has been described in particular, but when the host CPU 32 gives a parameter value to each module or when the necessary control information is passed from one module to the other module. , The data block including the control data shown in FIG. 2 is DMA-transferred. By the way, when the register setting for each module is completed first, the set value is not changed in real time after that, so the number of DMA transfer of the data block including the control data is not so large. That is, during the real-time processing operation, the bus 12 can be fully dedicated to the transfer of ultrasonic data.

As an example, the rate required to transfer the pre-beam processing data is 8 MB / s, and the rate required to transfer the post-beam processing data is 2 MB / s. The required rate is 8MB /
s. On the other hand, if the bus 12 is composed of, for example, a compact PCI bus which is a general-purpose high-speed bus, the bus has a transfer capacity of 133 MB / s at the maximum, and therefore it is necessary for bus arbitration. Even if the overhead time is taken into consideration, each data can be sufficiently transferred by one bus.

FIG. 3 shows the basic structure of the modules 14 to 24 connected to the bus 12. The module 40 includes the processing unit 42 and the input unit 4 as described above.
4 and an output section 46, and the input section 44 and the output section 46 have the configurations shown in the drawing. That is, the bus interface 56 is connected to the bus 12, the input section memory 48 and the input section register 50 are provided between the bus interface 56 and the processing section 42 on the data input side, and the output on the data output side. A copy memory 52 and an output register 54 are provided. The input unit memory 48 and the output unit memory 52 are storage units for storing ultrasonic data, respectively.
0, the output unit register 54 is a storage unit for storing parameter values as control information. DMA controller 58
Is a circuit for forming the above-mentioned data block and performing DMA transfer thereof under the control of the processing unit 42. Of course, the configuration shown in FIG. 3 is an example, and other configurations can be adopted.

FIG. 4 shows the configuration of an ultrasonic diagnostic apparatus according to another embodiment. Here, module 64-
74 corresponds to the modules 14 to 24 shown in FIG. The host module 76 shown in FIG. 4 corresponds to the host module 26 shown in FIG.

In the configuration example shown in FIG. 4, both the first bus 60 and the second bus 62 are connected to each module from the beam processing module 66 to the scan conversion module 72. In addition, the memory module 64 is the first bus 6
0, and the image processing module 74 is connected to the second bus 62. Furthermore, the host module 7
Two buses 60 and 62 are connected to the bus 6.

The first bus 60 and the second bus 62 are constituted by, for example, the above PCI bus. First bus 60
Is used to transfer pre-beam processing data,
The bus 62 is mainly used for transferring post beam processing data and image data. Incidentally, for the control data, either or both of the first bus 60 and the second bus 62 are used for the transfer.

The host module 76 has a first bus bridge 80 for the first bus 60 and a second bus bridge 78 for the second bus 62, which are the host CPU 82.
Controlled by. An external storage device 86 is connected to the host module 76, and the image processing module 74
A display device 84 is connected to the.

In the configuration shown in FIG. 4, the memory module 6
The data block including the pre-beam processing data output from No. 4 is transferred to, for example, the beam processing module 66 via the first bus 60. Then, the data block including the post-beam processing data generated in the beam processing module 66 is transferred to, for example, the scan conversion module 70 via the second bus 62. Then, the data block including the image data generated by the scan conversion module 70 is transferred to the image processing module 74 via the second bus 62.

As described above, depending on the type of data, the first
Since the bus 60 and the second bus 62 are used properly, it is possible to handle a larger amount of data.
For example, when forming an ultrasonic three-dimensional image, etc., it is necessary to process a large amount of data acquired in the three-dimensional echo data acquisition space. Although processing is necessary, according to the configuration example shown in FIG. 4, since two data transmission lines are prepared, it is possible to realize data transfer with a margin. Also in the configuration shown in FIG. 4, each bus 60, 6
Since 2 composes a common bus, the degree of freedom in changing the design of the device is increased.

In FIG. 1, when DMA transfer is performed from one module to the next module, information such as data size is stored in the attribute 64 in which data is transferred in a predetermined data unit (one record unit) as described above. Is also stored, and the module side receiving the data block can know the end of the DMA transfer by referring to such information. Of course, the end of data transfer may be determined by another method. In any case, by writing the information of the frame identifier and the identifier of the beam or line in the attribute 64, even if each data block is transferred separately, it is possible to reconfigure them, and asynchronous transfer is possible. While performing, it is possible to obtain the same result as when the synchronous transfer is performed.

[0041]

As described above, according to the present invention,
It is possible to reduce the design load of the ultrasonic diagnostic apparatus and flexibly cope with changes in the apparatus configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a preferred embodiment of an ultrasonic diagnostic apparatus according to the present invention.

FIG. 2 is a conceptual diagram showing the structure of a data block.

FIG. 3 is a block diagram for explaining a basic configuration of a module.

FIG. 4 is a block diagram showing an overall configuration of an ultrasonic diagnostic apparatus according to another embodiment.

[Explanation of symbols]

10 probes, 12 buses, 14 memory modules, 16 beam processing modules, 18 beam processing modules, 20 scan conversion modules, 22 scan conversion modules, 24 image processing modules, 26 host modules.

Claims (7)

[Claims] 1. A plurality of processing modules, and an internal bus of at least one system to which the plurality of processing modules are commonly connected, between the plurality of processing modules, ultrasonic data is transmitted via the internal bus. An ultrasonic diagnostic apparatus is characterized in that a first data block including the above and a second data block including the control data are transferred. 2. The ultrasonic diagnostic apparatus according to claim 1, wherein the first and second data blocks are DMA-transferred. 3. The ultrasonic diagnostic apparatus according to claim 1, wherein the ultrasonic data is transferred in ultrasonic beam units or display line units. 4. The apparatus according to claim 3, wherein the first data block includes an attribute in addition to the ultrasonic data, and the attribute includes a frame identifier and an ultrasonic beam identifier or a display line. An ultrasonic diagnostic apparatus including an identifier. 5. The ultrasonic diagnostic apparatus according to claim 1, wherein a plurality of systems of internal buses are provided as the internal buses, and the internal buses are used properly according to the type of the ultrasonic data. 6. The apparatus according to claim 1, wherein a first internal bus and a second internal bus are provided as the internal buses, the first internal bus is used for transferring pre-beam processing data, and 2. The ultrasonic diagnostic apparatus, wherein the internal bus is used for transferring post-beam processing data and image data. 7. The apparatus according to claim 1, wherein the plurality of processing modules include a host module including a host CPU, and the host module executes software processing of ultrasonic data. Ultrasonic diagnostic equipment.