JP2003188263A - Method for producing semiconductor integrated circuit chip and semiconductor package using semiconductor integrated circuit chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for producing a semiconductor integrated circuit chip having fine side face electrodes (fine pitch electrodes) in which occupation area of electrode pads for I/O signal (through electrodes) on the surface of the semiconductor integrated circuit chip can be reduced and the side face of the semiconductor integrated circuit chip can be utilized effectively. <P>SOLUTION: When a semiconductor wafer 11 is separated individually (diced) into semiconductor integrated circuit chips, through holes 1 are made on the border line 8 of a semiconductor integrated circuit region 10 becoming the semiconductor integrated circuit chip and a scribe region 2 being cut out formed between the semiconductor integrated circuit regions 10, and through hole electrodes are formed in the through holes 1 such that they are exposed to the side face of the semiconductor integrated circuit chips at the time of dicing. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing method (manufacturing process) of a semiconductor integrated circuit chip (semiconductor device) having side electrodes and a semiconductor package.

[0002]

2. Description of the Related Art Conventionally, when a semiconductor wafer provided with a semiconductor integrated circuit (IC) is singulated to form a semiconductor integrated circuit chip (IC chip), electrode pads for input / output signals (electrodes for input / output signals) Pad),
The input / output signal electrode pads are adjacent ICs.
It is formed so as to cover the line width of the cut region on the chip surface.
As a result, input / output signal electrode pads are formed around the IC chip.

In the assembly of a general plastic package, the input / output signal electrode pad on the IC chip and the inner lead of the lead frame or the electrode pad (substrate electrode pad) on the substrate are connected by a gold wire. Connect and assemble.

Here, an example of a package using gold wires will be described with reference to FIGS. 11 and 12.

FIG. 11 shows a Q using an IC chip 212 having a conventional surface electrode 217 (chip surface electrode 217).
The FP233 is shown.

As shown in this figure, QFP233 (Quad
Flat Package 233) is a die bond material 21 on the lead frame die pad 219 (die pad 219).
The surface electrode IC chip 212 is bonded with 3 and the gold wire 2
After the surface electrode 217 and the inner lead 221a are connected (wire bonded) at 18, they are resin-sealed with a sealing member 216.

Incidentally, FIG. 11A is a plan view of the QFP 233 using the front surface electrode IC chip 212, and FIG.
11 shows a sectional view taken along the line PP ′ of FIG.

FIG. 12 shows a C using an IC chip 212 having a conventional surface electrode 217 (chip surface electrode 217).
SP234 (Chip Size Package 234) is shown.

As shown in this figure, the CSP 234 connects the surface electrode 217 and the substrate electrode pad 220 to the gold wire 2.
After connecting (wire bonding) at 18, the sealing member 216
It is sealed with resin. Further, reference numeral 251 indicates a solder ball.

12A is a plan view of the CSP 234 using the surface electrode IC chip 212, and FIG. 12B is a sectional view taken along the line QQ 'of FIG. 12A.

11 and 12, the input / output signal wiring 105, which will be described later, is omitted in order to make the contents of the drawing easy to understand. Further, in the plan views of FIGS. 11 and 12, the IC chip 212 and the surface electrode 217 incorporated therein are shown.
Etc. are shown by a solid line for easy understanding.

In the package as shown in FIGS. 11 and 12, the wire height region on the IC chip necessary for the wire bond (connection using the gold wire 218) is required inside the package. Become. That is, when wire bonding is used in assembly, the sealing member 216 on the surface of the IC chip needs to have a sufficient thickness (wire height region) to protect the gold wire 218.

Since a region for connecting the gold wire 218 to the lead frame 221 and the substrate 214 is also required inside the package, a region of the inner lead 221a of the lead frame 221 and the electrode pad 22 of the substrate.
This is because a region of 0 (substrate electrode pad 220) is required (for example, the connection position (wire bond position) of the gold wire 218 to the electrode pad 220 on the substrate requires a certain distance from the IC chip). ).

Therefore, there is a problem that the thinning and miniaturization of the semiconductor package, which is highly demanded in the market, is limited.

In order to increase the capacity and function of the device by using such an assembly, for example, a stacked chip package or a multi-chip package is used. In these packages,
Wire bonding, flip chip bonding and the like are used for bonding IC chips to each other and bonding an IC chip to a lead frame. However, for example, in a stacked chip package, if the number of stacked IC chips increases, I
There is a problem that the signal transmissibility between C chips deteriorates, and there is also a problem that the number of stacked IC chips and the size of IC chips to be combined are largely restricted.

Further, since the input / output signal electrode pad is formed on the surface of the IC chip, a large part of the surface area of the IC chip is used as an electrode area, and one sheet is used for the purpose of cost reduction and rationalization. There is also a problem that there is a limit to the promotion of IC chip size reduction for increasing the number of chips mounted on the semiconductor wafer.

As a measure against these problems, Japanese Patent Laid-Open No. 6-5
In the technology of Japanese Patent No. 665, by forming an input / output signal electrode pad (side electrode) on a side surface portion of a conventional IC chip, the area occupied by the input / output signal electrode pad on the surface of the IC chip is reduced, and Achieved chip miniaturization.

An IC chip having this side electrode (side terminal) and its manufacturing method will be described with reference to FIG.

FIG. 13B shows a semiconductor wafer 111 on which a large number of semiconductor integrated circuits are formed. FIG.
(A) is a detailed view of the semiconductor wafer 111, which is diced (cut) into individual semiconductor integrated circuit regions 110 which are semiconductor integrated circuit chips (IC chips).

In the manufacturing method of the publication, a through hole 101 is provided in a scribe region 102 (a region that is cut and removed by a dicing blade) where dicing is performed in order to separate the IC chips from the semiconductor wafer 111.

Then, as shown in FIG. 14A (enlarged view of the vicinity of the through hole 101), the inner hole of the through hole 101 is
An insulating film 103 is deposited, and a conductive material 104 is further deposited on the insulating film 103.

After that, the input / output signal wiring 105 is provided on the conductive material 104 to form the through electrode 106, and then the scribe region 102 is cut and removed to divide the IC chip into individual pieces.

As a result, as shown in FIG. 15, the through electrode 106 is exposed on the side surface of the IC chip, and the exposed portion is used as the side electrode 107 (side terminal).

It should be noted that FIG. 14 (b) shows X of FIG. 14 (a).
-X 'line sectional view, FIG.14 (c) has shown the YY' line sectional view of FIG.14 (a).

[0025]

However, according to this method, a plurality of through electrodes 106 are formed in a row on the cutting region formed of the scribe region 102, and the center of the through electrode 106 is further cut. The side electrode 107 is obtained. Therefore, when cutting by dicing,
It is necessary to form the through electrode 106 that is larger than the width of the dicing blade.

As a result, there is a limit in providing fine side surface electrodes and increasing the number of side surface electrodes corresponding to high integration and multifunction of devices. That is, there arises a problem that it is difficult to form fine side surface electrodes (fine pitch electrodes).

The present invention has been made to solve the above problems. And the purpose is to reduce the area occupied by the input / output signal electrode pads on the surface of the IC chip, and to manufacture an IC chip having fine side surface electrodes (fine pitch electrodes) capable of effectively utilizing the side surface of the IC chip, and It is to provide a semiconductor package using the IC chip.

[0028]

In order to solve the above-mentioned problems, a method of manufacturing a semiconductor integrated circuit chip according to the present invention comprises dicing a cutting region for cutting a semiconductor integrated circuit chip on a semiconductor wafer, and then the semiconductor A method of manufacturing a semiconductor integrated circuit chip in which a wafer is divided into semiconductor integrated circuit chips, wherein a penetrating hole for forming an electrode is provided at a boundary line between a semiconductor integrated circuit region which becomes a semiconductor integrated circuit chip by the above dividing and the cutting region. A hole is provided, a through electrode is formed in the through hole, and the semiconductor wafer is divided so that the through electrode is exposed at a side surface of the semiconductor integrated circuit chip.

According to the above invention, the through hole for forming the electrode is not provided on the cut region as in the conventional case, but the through hole is provided on the boundary line between the semiconductor integrated circuit region and the cut region. There is.

Therefore, when the above cutting region is cut and removed by dicing, it is not necessary to form a through hole larger than the width of the dicing blade (width of the cutting region) as in the conventional case. That is, it is possible to reduce the size of the through electrode, and as a result, the area of the through electrode (side electrode) exposed on the divided surface of the semiconductor wafer, that is, the side surface of the semiconductor integrated circuit chip becomes fine.

Therefore, compared to the conventional case, even in the same area (area) of the semiconductor integrated circuit, it is possible to effectively use the side surface of the semiconductor integrated circuit chip (for example, increase the number of side surface electrodes).

Further, since the area occupied by the penetrating electrodes on the surface of the semiconductor integrated circuit chip can be reduced, the semiconductor integrated circuit chip can be downsized.

That is, by using this manufacturing method, it is possible to manufacture a semiconductor integrated circuit chip having a reduced size and a semiconductor integrated circuit chip that effectively utilizes the side surface of the semiconductor integrated circuit chip. The cost can be further reduced by further reducing the chip size.

The semiconductor package of the present invention is a semiconductor package in which the semiconductor integrated circuit chip manufactured by the method for manufacturing a semiconductor integrated circuit chip is mounted on a substrate, wherein the semiconductor integrated circuit chip is Having a side surface electrode on the side surface, the side surface electrode and the substrate electrode pad provided on the substrate are connected by a curable conductive agent,
Further, it is preferable that the semiconductor integrated circuit chip is sealed with resin.

According to the above invention, the connection between the electrode (side electrode) of the semiconductor integrated circuit chip and the substrate electrode pad of the substrate is made by a curable conductive agent (for example, conductive adhesive or solder).
Can be easily connected by applying. for that reason,
For example, it is not necessary to form bumps used in conventional connection using wire bond or flip chip bond.
That is, in the semiconductor package of the present invention, the assembly process can be rationalized (simplified).

Further, since the semiconductor integrated circuit chip having the above-mentioned side surface electrodes is made smaller than the conventional semiconductor integrated circuit chip, it is possible to make the semiconductor package thinner and smaller.

Further, in the semiconductor package of the present invention, for example, the electrode (side electrode) can be connected to the substrate electrode pad without using wire bond, so that the wire height region on the chip necessary for wire bond is unnecessary. Therefore, the semiconductor package can be made thinner and smaller.

In other words, according to the present invention, it is possible to reduce the thickness and size of the semiconductor package and to rationalize the assembly process of the semiconductor package in response to the market demand.

The bumps are projecting connection electrodes formed on the semiconductor integrated circuit chip.

Further, in the semiconductor package of the present invention, in addition to the above structure, semiconductor integrated circuit chips having the above-mentioned side surface electrodes are mounted in an overlapping manner, and the side surface electrodes are connected to each other by a curable conductive agent. Is preferred.

According to the above-described invention, since the stacked semiconductor integrated circuit chips are connected to each other, that is, the wiring between the semiconductor integrated circuit chips is performed by the side electrodes, the bumps between the front and back surfaces of the semiconductor integrated circuit chips are, for example, bumps. It becomes unnecessary to connect it with the like. As a result, the thickness between the semiconductor integrated circuit chips can be minimized, and the overall thickness of the semiconductor package can be further reduced in thickness and size.

Further, like the conventional semiconductor package,
For example, it is not necessary to connect the side electrodes to each other using a metal rod.

That is, in the semiconductor package of the present invention,
By applying a curable conductive agent without using a metal rod, it is possible to easily and directly connect the side surface electrodes to each other and the side surface electrodes to the substrate electrode pads. As a result, the process of assembling the semiconductor package can be rationalized (simplified) and the cost can be reduced.

In order to further increase the capacity and multifunction of the semiconductor package device, it is possible to reduce the thickness and size of the semiconductor package while stacking the semiconductor integrated circuit chips (stacked chip mounting). it can.

Further, it is possible to reduce the cost by thinning and miniaturizing the semiconductor package and simplifying the assembling process.

[0046]

BEST MODE FOR CARRYING OUT THE INVENTION [First Embodiment] Fine side surface electrodes (fine pitch electrodes) according to an embodiment of the present invention.
A method of manufacturing a semiconductor integrated circuit chip having the above (main manufacturing method) will be described.

FIG. 2 shows a semiconductor wafer 1 in which a large number of semiconductor integrated circuit regions 10 to be semiconductor integrated circuit chips are collected.
1 is shown. That is, the semiconductor wafer 11 is a collection of the semiconductor integrated circuit regions 10 that are individualized (cut) into semiconductor integrated circuit chips (IC chips).

FIG. 1 is an enlarged plan view of a semiconductor wafer 11 in which semiconductor integrated circuit regions 10 are gathered. As shown in this figure, between the semiconductor integrated circuit regions 10 is a region (scribe region 2) that is cut and removed when the semiconductor wafer 11 is diced (diced).

In this manufacturing method, first, as shown in FIG. 1, a boundary line 8 (for example, a boundary line between two columns) on the boundary between the semiconductor integrated circuit region 10 and the scribe region 2 is used as a center for etching and laser processing. The through hole 1 is provided by machining or machining with a drill [through hole drilling step].

The through holes 1 are provided in a larger number than the required number of input / output signal electrode pads. Although the size of the through hole 1 is not particularly limited,
100 μm is preferable.

Next, as shown in FIG. 3A, the through hole 1
A silicon oxide film or an organic material film is formed on the inner wall surface of the substrate by a CVD (Chemical Vapor Deposition) method to form an electrically insulating film 3 [insulating film forming step].

After that, the conductive material 4 (conductive portion 4) is embedded inside the insulating film 3 by plating deposition [conductive material forming step]. The material of the conductive material 4 is not particularly limited, but copper, aluminum (Al), or gold (Au) is preferable.

Next, the conductive material 4 inside the through hole 1 and I
The input / output signal wiring 5 to / from the C chip 12 is connected to the IC chip 1
Connect on the surface of 2 [wiring connection step].

In order to clearly show this connected state, a sectional view taken along the line AA 'of FIG. 3 (a) is shown in FIG. 3 (b).
3C shows a sectional view taken along the line BB ′ of FIG.
Further, the electrode composed of the insulating film 3, the conductive material 4, and the input / output signal wiring 5 is referred to as a penetrating electrode 6.

Thereafter, as shown in FIG. 4, the scribe area 2 is removed by grinding (dicing) using a dicing blade, and the ground cross section of the conductive material 4 inside the through hole 1 (see FIG. 3) is subjected to IC chip. The wafer is cut (separated) so as to be exposed on the side surface of the wafer [wafer cutting step]. In this figure, the area removed in the scribe area 2 is shown by the shaded area. Further, in FIG. 4, the input / output signal wiring 5 is omitted in order to make the contents of the drawing easy to understand.

As a result of the above steps [through hole drilling step, insulating film forming step, conductive material forming step, wiring connecting step, wafer cutting step], as shown in FIG. Causes the conductive material 4 of the through electrode 6 to be exposed. That is, the conductive material 4 is formed on the side surface of the IC chip 12.
IC chip 12 provided with the side surface electrode 7 formed of the exposed portion of
Can be manufactured. Note that FIG.
The side view of (a) is represented.

As described above, when the IC chip 12 having the side surface electrode 7 is manufactured by using this manufacturing method, the conventional IC is manufactured.
When cutting by dicing as in the chip manufacturing method, it is not necessary to form the through hole 1 (through electrode 6) larger than the width of the dicing blade (FIG. 13A).
Through hole 101). That is, it is possible to reduce the size of the through electrode 6 that serves as an electrode pad for input / output signals,
As a result, the dividing surface of the semiconductor wafer, that is, I
The area of the through electrode 6 (side electrode 7) exposed on the side surface of the C chip 12 is also minute.

Here, an IC manufactured by this manufacturing method has the same region (area) of the semiconductor integrated circuit as the IC chip 112 (side electrode IC chip 112) provided with the conventional side electrode 107 as shown in FIG. Chip 12 (side electrode I
The C chip 12) is shown in FIG.

As shown in FIG. 6, when the side electrode IC chip 12 is manufactured using this manufacturing method, the side electrode 7
Is the side electrode 107 of the conventional side electrode IC chip 112.
It becomes finer (fine electrode), and the number of side surface electrodes 7 can be increased even in the same region (area) of the semiconductor integrated circuit.

Further, since the size of the through electrode 6 is reduced, the area occupied by the input / output signal electrode pad (through electrode 6) on the surface of the IC chip 12 can be reduced, and the IC chip 12 can be downsized (downsized). Can be planned.

That is, using this manufacturing method, it is possible to manufacture the IC chip 12 having a reduced size and the IC chip 12 having an increased number of terminals (fine side surface electrodes 7). As a result, it is possible to reduce the cost by further downsizing the chip size than ever before.

6 and 15, the input / output signal wiring 5 or the input / output signal wiring 105 is omitted in order to make the contents of the drawing easy to understand.

[Second Embodiment] The following will describe another embodiment of the present invention. Members having the same functions as those used in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted. In addition,
7 to 10, the input / output signal wiring 5 is omitted in order to make the contents of the drawings easy to understand. In addition, in the plan views of FIGS.
2, the side electrodes 7 and the like are shown by solid lines for easy understanding.

In the second embodiment, an example of mounting a semiconductor package using the IC chip 12 (side electrode IC chip 12) manufactured in the first embodiment will be described.

Layered chip package 3 as shown in FIG.
1 (semiconductor package) further adheres the die bond material 13 on the side surface electrode IC chip 12 adhered to the substrate 14 by the die bond material 13 (sheet 13) to form the second side surface electrode IC chip 12 of the same kind. It is configured by insulating adhesion. Further, third, fourth, or more side electrode IC chips 12 are further stacked on the second side electrode IC chip 12.

Since each of the above chips is the same kind of side electrode IC chip 12, the positions of the side electrodes 7 are arranged in a line on a vertical straight line.

Then, by applying a conductive adhesive 15 (curable conductive agent) to the side electrodes 7 in one row, after the side electrodes 7 are connected to each other (after electrical connection), And the side surface electrode 7 and the electrode pad 20 on the substrate 14.
After the connection with the (substrate electrode pad 20), the layered chip package 31 is resin-sealed by the sealing member 16 (resin).
Is completed.

As described above, the side electrode IC chip 12
In the layered chip package 31 using the (IC chip 12 of the present invention), the side electrodes 7 are connected to each other by applying the conductive adhesive 15, and the side electrodes 7 and the substrate electrode pad 2 are connected.
The connection with 0 can be easily connected. That is,
The assembly process of the semiconductor package can be rationalized (simplified).

Further, in the semiconductor package of the present invention, since the side surface electrode 7 and the substrate electrode pad 20 can be connected without using the conventional wire bond, for example, the wire height region on the chip necessary for the wire bond. Is unnecessary, the semiconductor package can be made thinner and smaller.

Further, since there is no need to connect a wire to the uppermost chip, there is no limit to the number of stacked chips,
You can stack any number of layers.

Moreover, since wiring (connection) between the side surface electrode IC chips 12 is performed on the side surface (side surface electrode 7), connection between the front and back surfaces of the side surface electrode IC chip 12, for example, connection by bumps or the like is unnecessary. become.

As a result, the thickness of the insulating adhesive sheet 13 (die bond material 13) between the side electrode IC chips 12 can be minimized, and the overall thickness of the semiconductor package can be further thinned and miniaturized.

Therefore, in order to further increase the capacity and multifunction of the device of the semiconductor package, the thickness of the semiconductor package can be reduced while mounting the stacked chips (even when the side electrode IC chips 12 are mounted for stacking). It can be made thinner and smaller.

Further, the side electrode IC chip 12 has the conventional I
Since it is smaller than the C chip, it is possible to reduce the thickness and size of the semiconductor package.

Further, by reducing the thickness and size of the semiconductor package and simplifying the assembly process, the cost of the semiconductor package can be reduced.

In addition, a conventional semiconductor package (for example,
Unlike the multi-IC chip disclosed in JP-A-6-5665), it is not necessary to use metal rods to connect the side surface electrodes 7 to each other.

That is, in the semiconductor package of the present invention,
By applying the conductive adhesive 15 without using a metal rod, it is possible to easily and directly connect the side surface electrodes 7 to each other and the side surface electrodes 7 and the substrate electrode pads 20.
As a result, the process of assembling the semiconductor package can be rationalized (simplified) and the cost can be reduced.

The conductive adhesive 15 which is one of the curable conductive agents used for the connection between the side surface electrodes 7 and the connection between the side surface electrodes 7 and the substrate electrode pads 20 on the substrate 14 is particularly limited. Although not a thing, an epoxy resin containing Ag (silver) filler is preferably used. However, the material is not limited to these, and for example, solder (curable conductive agent) may be used.

The bump is a protruding connection electrode formed on the IC chip. Further, reference numeral 51 in FIG. 7 indicates a solder ball which functions as a connection terminal.

Side electrode ICs having different chip sizes
The chip 12 can also be used to manufacture a multi-chip package 32 (semiconductor package) as shown in FIG.

FIG. 8A shows a multi-chip package 32.
8A and FIG. 8B are sectional views taken along the line CC ′ of FIG. 8A.

As shown in FIG. 8B, in the multi-chip package 32, the side electrode IC chips 12 are arranged adjacent to each other by the die bonding material 13 on the substrate 14. At the time of this bonding, the side electrodes 7 facing each other of the side electrode IC chip 12 are connected by the conductive adhesive 15. Furthermore, after the side surface electrode 7 and the electrode pad 20 (substrate electrode pad 20) on the substrate 14 are connected by the conductive adhesive 15, resin is sealed by the sealing member 16 (sealing resin), and this multi-chip The package 32 is completed (assembled).

In this multi-chip package 32, for example, bumps for conventional wire bonding and flip chip bonding are not required, so that the semiconductor package can be thinned.

In addition, the connection between the side electrodes 7 facing each other,
Also, the side surface electrode 7 and the substrate electrode pad 20 on the substrate 14
The conductive adhesive 15 can be used to easily connect to. That is, the process of assembling the semiconductor package can be rationalized (simplified).

Further, in this multi-chip package 32, for example, the side electrode 7 and the substrate electrode pad 20 can be connected without using a wire bond as in the prior art, so that the wire height region on the chip necessary for the wire bond can be obtained. Since it is unnecessary, the semiconductor package can be made thinner and smaller.

Further, in order to further increase the capacity and multifunction of the device of the semiconductor package, even though the multi-chip mounting is performed (even if the side electrode IC chip 12 is mounted adjacent to the substrate 14), the semiconductor The package can be made thinner and smaller.

The side electrode IC chip 12 is a conventional I
Since it is smaller than the C chip, it is possible to reduce the thickness and size of the semiconductor package.

Further, the semiconductor package can be made thinner and smaller, and the assembling process can be simplified to realize cost reduction.

The conductive adhesive 15 used for connecting the side surface electrodes 7 to each other and for connecting the side surface electrodes 7 to the electrode pads on the substrate 14 is not limited to this, and is, for example, solder. It doesn't matter.

Further, by using the side electrode IC chip 12,
As shown in FIG. 9, a QFP 33 (Quad Flat Package 33), which is one of peripheral lead packages, can be manufactured.

FIG. 9A is a plan view of the QFP 33.
9B is a sectional view taken along the line DD ′ of FIG. 9A.

As shown in these figures, in the QFP 33, the inner leads 21a (2
By directly sandwiching the side electrode 7 of the side electrode IC chip 12 from the periphery with the tip of 1), the side electrode IC chip 12 is supported by the lead frame 21. After that, the sealing member 1
This QF is resin-sealed with 6 (sealing resin 16).
P33 is completed (assembled).

Instead of directly sandwiching the side electrode 7, the tip of the inner lead 21a and the side electrode 7 may be connected by a slight amount of the conductive adhesive 15.

Here, QFP33.2 of FIG. 9 and FIG.
As can be seen by comparing 33 with each other, in the QFP 33 of FIG. 9, since the die bond material 213, the die pad 219, and the gold wire 218 (see FIG. 11) are not used, the thickness of the semiconductor package is the thickness of the chip (IC chip 12). Will only depend on it. Therefore, the semiconductor package can be made thinner.
It can be sufficiently miniaturized.

Since the side surface electrode IC chip 12 is made smaller than the conventional IC chip, the semiconductor package can be made thinner and smaller.

In addition, the step of attaching the die bonding material 213 (die bonding step), which must be performed by the QFP 233 of FIG. 11, the surface electrode 21 by the gold wire 218.
The step of connecting (7) and the inner lead 221a (wire bonding step) is not necessary.

That is, in the QFP 33 of FIG. 9, the die-bonding step and wire-bonding step described above are combined with the step of collectively connecting the inner lead 21a and the side surface electrode 7. Therefore, the process of assembling the semiconductor package can be rationalized.

Further, the semiconductor package can be made thinner and smaller, and the assembling process can be simplified to realize cost reduction.

The numbers 21b (21) and 221b
(221) shows the outer leads of the lead frames 21 and 221.

Further, using the side electrode IC chip 12,
As shown in FIG. 10, CSP34 (Chip Size Package
34) can also be produced.

FIG. 10A is a plan view of the CSP 34, and FIG. 10B is a sectional view taken along the line EE ′ of FIG. 10A.

As shown in FIG. 10B, the side surface electrode 7 of the side surface electrode IC chip 12 adhered to the substrate 14 by the die bond material 13 (sheet 13) and the electrode pad on the substrate 14 arranged immediately below the side surface electrode 7. 20 (substrate electrode pad 20)
After being connected by applying the conductive adhesive 15 to and, the resin is sealed by the sealing member 16 to complete (assemble) the CSP 34.

The conductive adhesive 15 used for connecting the side surface electrode 7 and the substrate electrode pad 20 is not limited to this, and may be solder, for example.

Here, the CSP 34 of FIG. 10 and FIG.
As can be seen by comparing 234, CSP3 in FIG.
In 4, the connection from the surface of the side surface electrode IC chip 12 to the substrate electrode pad 20 by wire bonding is unnecessary. Therefore, the thickness of the sealing member 16 corresponding to the wire height on the side surface electrode IC chip 12 can be reduced, and the thickness of the semiconductor package can be thinned (thinner package can be thinned and downsized). .

The side electrode IC chip 12 is a conventional I
Since it is smaller than the C chip, it is possible to reduce the thickness and size of the semiconductor package.

Moreover, since the side surface electrode IC chip 12 is fixed by the die bond material 13, even if the amount of the electrode connecting adhesive or solder is extremely small, it can function as a conductive material. As a result, the electrode pad 20 of the substrate 14
The (substrate electrode pad 20) portion can be reduced, and the semiconductor package can be further downsized.

Further, the semiconductor package can be made thinner and smaller, and the assembling process can be simplified to realize cost reduction.

Further, in the case of the semiconductor package of this embodiment, even if the layered chip package 31 and the multi-chip package 32 are used, it is not necessary to use the conventional wire bond or flip bond, and therefore, the number of chip layers and the combined chip size. It is possible to realize a large capacity and multi-functionality as a one-package device without any limitation.

Further, as the effect of this embodiment, it is possible to further reduce the cost and rationalize by further reducing the chip size than before, and to respond to the market demand and rationalize the assembly process by thinning and miniaturizing the semiconductor package. Becomes
In addition, due to the structure and process that uses the side electrode IC chip for laminated chip mounting and multi-chip mounting, the device capacity and functionality are further increased, the semiconductor package is made thinner and smaller, and the assembly process (manufacturing process) It can be said that cost reduction can be realized by simplifying the above.

The method for manufacturing a semiconductor integrated circuit chip and the semiconductor package using the semiconductor integrated circuit chip can be expressed as follows.

In the method for manufacturing a semiconductor integrated circuit chip, a through hole is formed in a cutting region between adjacent chips in a semiconductor wafer having a semiconductor integrated circuit formed, an inner wall of the hole is covered with an electrically insulating film, and Fill the inside with an electrically conductive material (conductive portion) made of copper, aluminum or gold, connect the input / output signal wiring of the integrated circuit to this electrically conductive material, cut along the cutting area, and fill the through hole. A method of manufacturing a semiconductor chip in which a conductive material is exposed as an input / output electrode on a side surface of a chip, wherein through holes are formed in two rows on a boundary between a scribe region and a semiconductor integrated circuit region, and a scribe line is removed by dicing. It can be said that there is.

In the semiconductor package using the semiconductor integrated circuit chip, the side surface electrode semiconductor integrated circuit chip (side surface electrode IC chip) is electrically connected to the electrode pad of the substrate with a conductive adhesive or solder. It can be said that the side electrode IC chip is a resin package and a semiconductor package having a solder ball-shaped terminal electrically connected to the electrode pad on the lower side of the substrate.

Further, in the semiconductor package using the semiconductor integrated circuit chip, the side surface electrode IC chips are joined together by a conductive adhesive or solder between the side surface electrodes between two or more vertically stacked side surface electrode IC chips. It can be said that it is an assembled semiconductor package.

[0114]

As described above, according to the method of manufacturing a semiconductor integrated circuit chip of the present invention, the cutting region for cutting the semiconductor integrated circuit chip on the semiconductor wafer is diced, and the semiconductor wafer is divided into the semiconductor integrated circuit chips. A method for manufacturing a semiconductor integrated circuit chip, comprising: a semiconductor integrated circuit region that becomes a semiconductor integrated circuit chip by the above division; and a boundary line between the cutting region and a through hole for forming an electrode. A through electrode is formed, and the semiconductor wafer is divided so that the through electrode is exposed at the side surface of the semiconductor integrated circuit chip.

According to this, when the cutting region is cut and removed by dicing, it is not necessary to form a through hole larger than the width of the dicing blade (width of the cutting region) as in the conventional case. That is, it is possible to reduce the size of the through electrode, and as a result, the area of the through electrode (side electrode) exposed on the divided surface of the semiconductor wafer, that is, the side surface of the semiconductor integrated circuit chip becomes fine.

Therefore, it is possible to effectively use the side surface of the semiconductor integrated circuit chip (for example, to increase the number of side surface electrodes) even in the same area (area) of the semiconductor integrated circuit as compared with the related art. Produce an effect.

Further, since the area occupied by the through electrode on the surface of the semiconductor integrated circuit chip can be reduced, the semiconductor integrated circuit chip can be downsized.

That is, by using this manufacturing method, it is possible to manufacture a semiconductor integrated circuit chip having a reduced size and a semiconductor integrated circuit chip that effectively utilizes the side surface of the semiconductor integrated circuit chip, and as a result, it is possible to manufacture a semiconductor integrated circuit chip more than ever before. The cost can be further reduced by further reducing the chip size.

The semiconductor package of the present invention is a semiconductor package in which the semiconductor integrated circuit chip manufactured by the above method for manufacturing a semiconductor integrated circuit chip is mounted on a substrate. Having a side surface electrode on the side surface, the side surface electrode and the substrate electrode pad provided on the substrate are connected by a curable conductive agent,
Further, it is preferable that the semiconductor integrated circuit chip is sealed with resin.

According to this, the connection between the electrode (side electrode) of the semiconductor integrated circuit chip and the substrate electrode pad of the substrate is
The connection can be easily made by applying a curable conductive agent (for example, a conductive adhesive or solder). Therefore, for example, it is not necessary to form bumps used in conventional connection using wire bonding or flip chip bonding. That is, the semiconductor package of the present invention has an effect that the assembly process can be rationalized (simplified).

Further, since the semiconductor integrated circuit chip having the above-mentioned side surface electrodes is made smaller than the conventional semiconductor integrated circuit chip, the semiconductor package can be made thinner and smaller. .

Further, in the semiconductor package of the present invention, for example, the electrode (side electrode) and the substrate electrode pad can be connected without using wire bond, so that the wire height region on the chip necessary for wire bond is unnecessary. Therefore, it is possible to reduce the thickness and size of the semiconductor package.

In other words, the present invention has an effect that it is possible to reduce the thickness and size of the semiconductor package and to rationalize the assembly process of the semiconductor package in response to the market demand.

Further, in the semiconductor package of the present invention, in addition to the above structure, semiconductor integrated circuit chips having the above-mentioned side surface electrodes are stacked and attached, and the side surface electrodes are connected by a curable conductive agent. Is preferred.

According to this, since the stacked semiconductor integrated circuit chips are connected to each other, that is, the wiring between the semiconductor integrated circuit chips is performed by the side electrodes, the front and back surfaces of the semiconductor integrated circuit chips are connected by, for example, bumps. Becomes unnecessary. As a result, there is an effect that the thickness between the semiconductor integrated circuit chips can be suppressed to a minimum and the overall thickness of the semiconductor package can be further reduced in thickness and size.

Further, like the conventional semiconductor package,
For example, it is not necessary to connect the side electrodes to each other using a metal rod.

That is, in the semiconductor package of the present invention,
By applying a curable conductive agent without using a metal rod, it is possible to easily and directly connect the side surface electrodes to each other and the side surface electrodes to the substrate electrode pads. As a result, the process of assembling the semiconductor package can be rationalized (simplified) and the cost can be reduced.

Further, in order to further increase the capacity and multifunction of the device of the semiconductor package, it is possible to reduce the thickness and size of the semiconductor package while stacking the semiconductor integrated circuit chips (stacked chip mounting). It has the effect of being able to.

Further, the semiconductor package can be made thin and compact, and the assembling process can be simplified to realize cost reduction.

[Brief description of drawings]

FIG. 1 is a plan view showing a semiconductor wafer used in a method for manufacturing a semiconductor integrated circuit chip of the present invention (this manufacturing method).

FIG. 2 is an enlarged view showing the semiconductor wafer shown in FIG.

3 (a) is a plan view showing a through electrode formed in the through hole shown in FIG. 1, and FIG. 3 (b) is an A- of FIG.
It is an A'line arrow sectional view, (c) is a BB 'line arrow sectional view of (a).

FIG. 4 is a schematic plan view showing a process of cutting (dicing) the semiconductor wafer of FIG. 1 using a dicing blade.

5A is a plan view showing the IC chip after the step of FIG. 4, and FIG. 5B is a side view of FIG.

FIG. 6 is a plan view showing an IC chip manufactured by this manufacturing method.

FIG. 7 is a cross-sectional view showing a layered chip package using an IC chip manufactured by this manufacturing method.

FIG. 8A is a plan view showing a multi-chip package using an IC chip manufactured by this manufacturing method,
(B) is a CC 'line sectional view taken on the line of (a).

9A is a plan view showing a QFP using an IC chip manufactured by this manufacturing method, and FIG. 9B is a D-of FIG.
It is a D'line arrow sectional view.

10A is a plan view showing a CSP using an IC chip manufactured by this manufacturing method, and FIG. 10B is an E of FIG.
FIG. 6 is a sectional view taken along the line E ′ of FIG.

FIG. 11A is a conventional surface electrode (chip surface electrode).
It is a top view which shows QFP using the IC chip which has, and (b) is a PP 'line sectional view taken on the line of (a).

FIG. 12 (a) is a conventional surface electrode (chip surface electrode).
It is a top view which shows CSP using the IC chip which has, and (b) is a QQ 'line sectional view taken on the line of (a).

13A is an enlarged view showing a semiconductor wafer used in a conventional IC chip manufacturing method (conventional manufacturing method), and FIG. 13B is a semiconductor integrated circuit region of the semiconductor wafer shown in FIG. It is a top view showing the state where many were gathered.

14A is a plan view showing a through electrode formed in the scribe region shown in FIG. 13B, FIG.
FIG. 7A is a sectional view taken along the line XX ′ of FIG. 7A, and FIG.

FIG. 15 is a plan view showing an IC chip manufactured by a conventional manufacturing method.

[Explanation of symbols]

1 through hole 2 Scribing area (cutting area) 3 insulating film 4 Conductive material 5 signal wiring 6 Through electrode 7 Side electrode 8 border 10 Semiconductor integrated circuit area 11 Semiconductor wafer 12 Semiconductor integrated circuit chip 14 board 15 Conductive adhesive 16 Sealing member (resin) 20 Substrate electrode pad 31 Layered chip package (semiconductor package) 32 Multi-chip package (semiconductor package) 33 QFP (semiconductor package) 34 CSP (semiconductor package)

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Claims (3)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit chip, wherein a cutting region for cutting a semiconductor integrated circuit chip on a semiconductor wafer is diced, and the semiconductor wafer is divided into semiconductor integrated circuit chips. A semiconductor integrated circuit area to be a chip and a boundary line between the cutting area are provided with a through hole for electrode formation, and a through electrode is formed in the through hole, and the through electrode is formed on the side surface of the semiconductor integrated circuit chip. A method of manufacturing a semiconductor integrated circuit chip, characterized in that the semiconductor wafer is divided so as to be exposed. 2. A semiconductor package in which a semiconductor integrated circuit chip manufactured by the method for manufacturing a semiconductor integrated circuit chip according to claim 1 is mounted on a substrate, wherein the semiconductor integrated circuit chip has side electrodes on side surfaces. A semiconductor characterized in that the side electrode and the substrate electrode pad provided on the substrate are connected by a curable conductive agent, and the semiconductor integrated circuit chip is sealed with resin. package. 3. The semiconductor package according to claim 2, wherein the semiconductor integrated circuit chips having the side surface electrodes are stacked and attached, and the side surface electrodes are connected by a curable conductive agent.