JP2003167542A - Device and method for image display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image display device which can correct changes of driving conditions with the electric resistance that the matrix wiring of a display panel has with a small number of hardware and has superior gradations. <P>SOLUTION: The device is equipped with a modulating means 8 of outputting a modulated signal according to corrected image data CData of inputted image data obtained by correcting changes of driving conditions for an image forming element due to the electric resistance of line wiring and a corrected image data computing means having a function of updating computation parameters for calculating the corrected image data Dout according to characteristics of the image forming means as a corrected image data computing means of generating the corrected image data Dout for the input image data Data in one horizontal scanning period. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device provided with an element for forming an image, such as a cold cathode element, which is wired in a matrix, and in particular, irradiation of an electron beam emitted from the image forming element. The present invention relates to an image display device such as a television receiver or a display device that receives a television signal or a display signal of a computer or the like and displays an image by providing a fluorescent screen that receives and emits light, or an image display method.

More specifically, for example, an image display device and an image display device for displaying an image by correcting and driving a decrease in the cold cathode element drive voltage caused by the electric resistance of the matrix wiring (scanning wiring) of the display panel. It relates to a display method.

[0003]

2. Description of the Related Art In order to correct a decrease in brightness due to a voltage drop due to a wiring resistance of a wiring for electrically connecting to a cold cathode element, the correction data is calculated by a statistical calculation, An image display device having a configuration for combining a line demand value and a correction value is disclosed in Japanese Patent Laid-Open No. 8-248920.

The configuration of the image display device described in this publication is shown in FIG.
6 shows. The structure relating to the correction of data in this device is roughly as follows. First, the brightness data for one line of the digital image signal is added up by the adder 206, and the correction rate data corresponding to the added value is read from the memory 207.

On the other hand, the digital image signal is serial / parallel converted in the shift register 204, held in the latch circuit 205 for a predetermined time, and then input to a multiplier 208 provided for each column wiring at a predetermined timing. In the multiplier 208, the luminance data is multiplied by the correction data read from the memory 207 for each column wiring, and the obtained corrected data is transferred to the modulation signal generator 209, and the modulated data corresponding to the corrected data is modulated. A signal is generated in the modulation signal generator 209, and an image is displayed on the display panel 201 based on this modulation signal.

Here, a statistical calculation process such as calculating a sum or an average is performed on the digital image signals, like the summing process of the luminance data for one line of the digital image signals in the adder 206, Correction is performed based on this value.

[0007]

However, in the above-mentioned conventional structure, a large-scale device such as a multiplier for each column wiring, a memory for outputting correction data, and a summing device for giving an address signal to the memory is required. I needed hardware.

The present invention has been made in order to solve the above-mentioned problems of the prior art. The object of the present invention is to make the driving conditions based on the electric resistance of the matrix wiring of the display panel simpler than the conventional one. An object of the present invention is to provide an image display device and an image display method capable of correcting fluctuations.

[0009]

In order to achieve the above object, in an image display device according to the present invention, the image display devices are arranged in a matrix and driven through a plurality of row wirings and column wirings to form an image. An image forming element to be used, a scanning unit for sequentially selecting and scanning the row wirings, and input image data are corrected to compensate for variations in driving conditions for the image forming elements due to electric resistance of the row wirings. A correction image data calculation unit that calculates correction image data and a modulation unit that outputs a modulation signal based on the correction image data, wherein the correction image data calculation unit includes the input image data for one horizontal scanning period. On the other hand, the correction image data is generated, and the calculation parameter for calculating the correction image data is updated according to the characteristics of the image forming element.

It is preferable that the image display device has a measuring means for measuring the element characteristic of the image forming element, and the calculation parameter is updated according to the change of the element characteristic.

It is preferable that the measuring means measures the element current of the image forming element and updates the calculation parameter according to the change of the element current.

The correction image data calculation means has an image pattern output means for outputting a predetermined measurement image pattern and a drive current measurement means for measuring a drive current when driven by the measurement image pattern. It is preferable that the calculation parameter is updated according to the drive current measured by the drive current measuring means.

The drive current measuring means is preferably provided in the scanning means.

The drive current measuring means is preferably provided in the modulating means.

It is preferable that the calculation parameters are updated when the image display device is powered on.

It is preferable that the calculation parameters are updated at the time of power-off operation of the image display device.

It is preferable that the calculation parameters are updated at an arbitrary time point requested by the user.

The modulation means is preferably pulse width modulation means for modulating the pulse width of the pulse output by the modulation means based on the corrected image data.

The corrected image data calculation means predicts the amount of voltage drop in the row wiring with respect to the input image data, and the amount of decrease in luminance due to the voltage drop from the amount of voltage drop. It is preferable to include a brightness reduction amount calculation unit that performs the correction, and a correction amount calculation unit that calculates a correction amount for correcting the input image data from the brightness reduction amount.

It is preferable that the voltage drop amount calculation means updates the element current, which is a calculation parameter used when calculating the voltage drop amount in the row wiring, in response to a change in the characteristic of the image forming element. is there.

The voltage drop amount calculating means sets a plurality of reference times during one horizontal scanning period corresponding to the input image data, and sets a plurality of reference points along the selected row wiring,
It is preferable to predictively calculate the voltage drop amount at the reference point that should occur at the plurality of reference times.

It is preferable that the brightness reduction amount calculation means predictively calculates the horizontal position where the voltage drop amount calculation means calculates the voltage drop amount and the brightness reduction amount corresponding to a plurality of reference times.

The correction amount calculation means calculates the brightness reduction amounts generated at the plurality of reference times at the plurality of reference points calculated by the brightness reduction amount calculation means from the plurality of discrete horizontal display positions of the reference points. It is preferable to calculate the corrected image data for a plurality of preset image data values.

The corrected image data calculation means interpolates the discrete corrected image data calculated by the correction amount calculation means and calculates an corrected image data corresponding to the size of the input image data and its horizontal display position. It is preferable to provide.

The electron emitting device is preferably a cold cathode device.

The cold cathode device is preferably a surface conduction type emission device.

The cold cathode device is preferably a field emission device.

It is preferable to provide a fluorescent member that emits fluorescence by collision of electrons emitted from the image forming element.

It is preferable that the calculation parameters are updated in a state where high voltage is not applied.

The image forming element is preferably an EL element.

Further, in the image display method according to the present invention, the image forming elements arranged in a matrix form, driven through a plurality of row wirings and column wirings, and used for image formation are inputted and input. The row wirings are sequentially selected and scanned in accordance with the image data, and the input image data and the corrected image data corrected to compensate the variation of the driving condition for the image forming element due to the electric resistance of the row wirings are obtained. An image display method of a display device for displaying an image by applying a modulation signal to the column wiring based on the corrected image data for generating the corrected image data for the input image data in one horizontal scanning period. The method includes a calculation step, and the correction image data calculation step updates the calculation parameter for calculating the correction image data according to the characteristics of the image forming element. Characterized in that it comprises a computation parameter updating step of.

The calculation parameter updating step includes a step of detecting power-on, a step of outputting a predetermined measurement image pattern, and a step of measuring a drive current when driven by the measurement image pattern. It is preferable that the step of updating the calculation parameter according to the measured drive current.

The calculation parameter updating step includes a step of detecting a power-off instruction, a step of stopping application of high voltage, a step of outputting a predetermined measurement image pattern, and a step of driving with the measurement image pattern. It is preferable that the step of measuring the drive current is included, and the step of updating the calculation parameter according to the measured drive current.

The calculation parameter updating step includes a step of detecting a parameter updating instruction from a user,
Stopping the application of high voltage, outputting a predetermined measurement image pattern, measuring the drive current when driven by the measurement image pattern, the calculation parameter according to the measured drive current Preferably, and the step of restarting the application of high voltage.

[0035]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be illustratively described in detail below with reference to the drawings. However, the dimensions of the components described in this embodiment,
Unless otherwise specified, the material, the shape, the relative arrangement, and the like are not intended to limit the scope of the present invention thereto.

(First Embodiment) In the present invention, in a display device in which cold cathode elements are arranged in a simple matrix, a voltage drop occurs due to a current flowing into a scanning wiring and a wiring resistance of the scanning wiring, and a display image is displayed. Considering the phenomenon of deterioration,
The present invention relates to an image display device provided with a processing circuit that corrects the influence of a voltage drop in the scanning wiring on a display image, and particularly, it is realized with a relatively small circuit scale.

The correction circuit of the present invention calculates the deterioration of the display image caused by the voltage drop according to the input image data,
The correction data for correcting it is obtained, and the image data is corrected.

Further, in the course of studying the image display device of the method described below, the correction circuit of the present invention can appropriately perform correction even when the element characteristics change due to aging or the like. There is a history of further improving the image display device.

At this time, since the device current flowing through the cold cathode device changes with the passage of time, the influence of the voltage drop in the scanning wiring also changes.

Therefore, it is necessary to calculate the correction data according to the change over time, and it was confirmed that the correction can be preferably performed by preparing the image display device having the structure described below.

In describing the present invention below,
Overview of a display panel of an image display device according to an embodiment of the present invention, electrical connection of the display panel, characteristics of a surface conduction electron-emitting device, a method of driving the display panel, and when displaying an image by such a display panel. After the mechanism of the reduction of the driving voltage due to the electric resistance of the scanning wiring is described, the correction method and apparatus for the influence of the voltage drop, which is the feature of the present invention, will be described.

(Overview of Image Display Device) FIG. 1 is a perspective view of a display panel used in the image display device according to this embodiment, in which a part of the panel is cut away to show the internal structure. . In the figure, 1005 is a rear plate, 1006 is a side wall, 1007 is a face plate, and 1005-
1007 forms an airtight container for maintaining a vacuum inside the display panel.

The rear plate 1005 has a substrate 1001.
, But the cold cathode device 1002 is fixed on the substrate.
Are formed by N × M. Row wiring (scan wiring) 100
3, the column wiring (modulation wiring) 1004 and the cold cathode element (image forming element) are connected as shown in FIG.

Such a connection structure is called a simple matrix.

A fluorescent film 1008 is formed on the lower surface of the face plate 1007. Since the image display device according to the present embodiment is a color display device, the fluorescent film 1
Red, green, which is used in the field of CRT
Phosphors of three primary colors of blue are painted separately.

The phosphor is a pixel (picture element) on the rear plate.
Cold cathode elements 10 formed in a matrix corresponding to
A pixel is formed at a position where the emission electron (emission current) from 02 is irradiated.

A metal back 1 is formed on the lower surface of the fluorescent film 1008.
009 is formed.

Hv is a high voltage terminal and is a metal back 100.
9 is electrically connected. By applying a high voltage to the Hv terminal, a high voltage is applied between the rear plate 1005 and the face plate 1007.

In this embodiment, a surface conduction electron-emitting device was manufactured as a cold cathode device in the above display panel. A field emission type element can also be used as the cold cathode element. The present invention can also be applied to an image display device in which an element that emits light by itself such as an EL element other than the cold cathode element is connected to a matrix wiring and driven.

(Characteristics of Surface Conduction Type Emitting Element) In the surface conduction type emitting element, as shown in FIG. 3, (emission current Ie) vs. (element applied voltage Vf) characteristics, and (element current If) vs. (element applied voltage Vf). ) Has characteristics. Since the emission current Ie is significantly smaller than the device current If and it is difficult to draw the same current scale, the two graphs are shown on different scales.

That is, the emission current Ie has the following three characteristics.

First, a certain voltage (this is the threshold voltage Vth
When the above voltage is applied to the element, the emission current Ie rapidly increases, while the emission current Ie is hardly detected at a voltage lower than the threshold voltage Vth.

That is, the nonlinear element has a clear threshold voltage Vth with respect to the emission current Ie.

Secondly, since the emission current Ie changes depending on the voltage Vf applied to the element, the magnitude of the emission current Ie can be controlled by changing the voltage Vf.

Thirdly, since the cold cathode element has a high-speed response, the emission current I depends on the application time of the voltage Vf.
The release time of e can be controlled.

Due to the above-mentioned characteristics, the surface conduction electron-emitting device can be preferably used in a display device.

For example, in the image display device using the display panel shown in FIG. 1, if the first characteristic is used, it is possible to sequentially scan the display screen for display. That is, a voltage equal to or higher than the threshold voltage Vth is appropriately applied to the driven element according to the desired light emission luminance, and a voltage lower than the threshold voltage Vth is applied to the non-selected element. By sequentially switching the elements to be driven, it is possible to sequentially scan the display screen for display.

By utilizing the second characteristic,
By the voltage Vf applied to the element, the emission brightness of the phosphor can be controlled and an image can be displayed.

By utilizing the third characteristic,
The light emission time of the phosphor can be controlled by the time for which the voltage Vf is applied to the element, and an image can be displayed.

In the image display device of the present invention, the amount of the electron beam of the display panel is modulated by using the above third characteristic.

(Display Panel Driving Method) The display panel driving method of the present invention will be specifically described with reference to FIG.

FIG. 4 shows an example of voltages applied to the voltage supply terminals of the scanning wiring and the modulation wiring when the display panel of the present invention is driven.

Now, the horizontal scanning period I is a period in which the pixels in the i-th row emit light.

Now, the horizontal scanning period I is a period in which the pixels in the i-th row emit light. In order to cause the pixels in the i-th row to emit light, the scanning wiring in the i-th row is brought into a selected state, and the selection potential Vs is applied to its voltage supply terminal Dxi. In addition, the voltage supply terminals Dxk (k = 1,
2 ,. ． ． N, but k ≠ i) is in the non-selected state, and the non-selected potential Vns is applied.

In this example, the selection potential Vs is set to -0.5V _SEL, which is half the voltage V _SEL shown in FIG. 3, and the non-selection potential Vs is set.
ns is the GND potential.

A pulse width modulation signal having a voltage amplitude Vpwm was supplied to the voltage supply terminal of the modulation wiring. Here, the voltage amplitude applied to the modulation wiring is the potential difference between the modulation wiring potential and the modulation potential Vpwm at the time of off.

Conventionally, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring depends on the size of the image data of the pixel at the i-th row and the j-th column of the image to be displayed when no correction is performed conventionally. Then, the pulse width modulation signal according to the size of the image data of each pixel is supplied to all the modulation wirings.

In the present invention, as will be described later, the pulse width of the pulse width modulation signal supplied to the j-th modulation wiring is the image to be displayed in order to correct the decrease in luminance due to the influence of the voltage drop. Is determined according to the size of the image data of the pixel at the i-th row and the j-th column and the correction amount thereof, and the pulse width modulation signal is supplied to all the modulation wirings.

In this embodiment, the voltage Vpwm is +
It was set to 0.5V _SEL .

As shown in FIG. 3, the surface conduction electron-emitting device emits electrons when a voltage V _SEL is applied across the device, but does not emit electrons at a voltage lower than Vth.

Further, the voltage Vth is as shown in FIG.
It is characterized by being larger than 0.5V _SEL .

Therefore, no electrons are emitted from the surface conduction electron-emitting device connected to the scanning wiring to which the non-selection potential Vns is applied.

Similarly, during a period in which the output of the pulse width modulation means is at the ground potential (hereinafter, referred to as a period in which the output is "L"), both ends of the surface conduction electron-emitting device on the selected scanning wiring are connected. Since the applied voltage is Vs, no electrons are emitted.

From the surface conduction electron-emitting device on the scanning wiring to which the selection potential Vs is applied, the output of the pulse width modulation means is V.
Pwm period (hereinafter referred to as "H" period of output)
The electrons are emitted according to the. When the electrons are emitted, the above-mentioned phosphor emits light in accordance with the amount of the emitted electron beam, so that it is possible to emit the brightness corresponding to the emitted time.

The image display apparatus according to the present invention also displays an image by line-sequential scanning and pulse width modulation of such a display panel.

(Regarding Voltage Drop in Scan Line) As described above, the fundamental problem of the present invention is that the potential on the scan line increases due to the voltage drop in the scan line of the display panel, and thus the surface conduction type This means that the voltage applied to the emission element is reduced, so that the emission current from the surface conduction type emission element is reduced. The mechanism of this voltage drop will be described below.

Although depending on the design specifications and manufacturing method of the surface conduction electron-emitting device, the device current for one device of the surface conduction electron-emitting device is about several hundred μA when the voltage V _SEL is applied.

Therefore, when only one pixel on the selected scanning line is made to emit light and the other pixels are not made to emit light in a certain horizontal scanning period, the element current flowing from the modulation wiring to the scanning wiring of the selected row is 1. Since it is only the current for the pixel (that is, the above-mentioned several 100 μA), there is almost no voltage drop, and the emission brightness does not decrease.

However, in the case where all the pixels in the selected row are made to emit light in a certain horizontal scanning period, the current for all the pixels flows from all the modulation wirings to the scanning wirings in the selected state. The sum is several hundred mA
The number was several A, and a voltage drop occurred on the scanning wiring due to the wiring resistance of the scanning wiring.

If a voltage drop occurs on the scanning wiring, the voltage applied across the surface conduction electron-emitting device will decrease. For this reason, the emission current emitted from the surface conduction electron-emitting device is reduced, and as a result, the emission brightness is reduced.

Specifically, consider a case where a white cross pattern is displayed on a black background as shown in FIG. 5A as a display image.

Then, when the row L in the figure is driven, since the number of lit pixels is small, almost no voltage drop occurs on the scanning wiring of that row. As a result, a desired amount of emission current is emitted from the surface conduction electron-emitting device of each pixel, and light can be emitted with a desired brightness.

On the other hand, when driving the row L'in the figure, all the pixels are turned on at the same time, so that a voltage drop occurs on the scanning wiring, and the emission current from the surface conduction electron-emitting device of each pixel is generated. Decrease. As a result, the luminance of the line of row L'is reduced.

As described above, the influence of the voltage drop changes due to the difference in the image data for each horizontal line. Therefore, when the cross pattern as shown in FIG. 5A is displayed, as shown in FIG. An image like this had been displayed.

This phenomenon is not limited to the cross pattern, but occurs even when a window pattern or a natural image is displayed.

Further, more complicatedly, the magnitude of the voltage drop has the property of changing within one horizontal scanning period by performing modulation by pulse width modulation.

The pulse width modulation signal supplied to each column is shown in FIG.
In the case of outputting a pulse width modulation signal whose pulse width depends on the size of the input data and whose rising edge is synchronized with respect to the input data as shown in, it depends on the input image data Since the number of pixels that are lit is large at the beginning of one horizontal scanning period and then the pixels are turned off in order from a place with low brightness, the number of lit pixels decreases with time in one horizontal scanning period. .

Therefore, the magnitude of the voltage drop that occurs on the scan wiring also tends to decrease gradually toward the beginning of one horizontal scanning period.

Since the output of the pulse width modulation signal changes at each time corresponding to one gradation of modulation, the temporal change of the voltage drop also changes at each time corresponding to one gradation of the pulse width modulated signal.

The voltage drop in the scanning wiring has been described above.

Next, a method of correcting the influence of the voltage drop, which is a feature of the present invention, will be described in detail.

(Calculation Method of Voltage Drop) In order to obtain the correction amount for reducing the influence of the voltage drop, the inventors first predict the magnitude of the voltage drop and its time change in real time as the first step. I thought it was necessary to develop hardware that would

However, the display panel of the image display device according to the present invention is generally provided with several thousand modulation wirings, and the voltage drop at the intersection of all the modulation wirings and the scanning wirings is calculated. Is very difficult and
It was not realistic to create hardware that calculates it in real time.

On the other hand, as a result of the examination of the voltage drop by the inventors, it has been found that the following features are provided.

I) At a certain point in one horizontal scanning period, the voltage drop generated on the scan wiring is a spatially continuous amount on the scan wiring, which is a very smooth curve.

Ii) Although the magnitude of the voltage drop varies depending on the display image, it changes at each time corresponding to one gradation of pulse width modulation. Either becomes smaller or maintains its size.

That is, in the driving method as shown in FIG. 4, the magnitude of the voltage drop does not increase within one horizontal scanning period.

Therefore, in consideration of the above-mentioned characteristics, the inventors examined whether the calculation amount can be reduced by performing simplification by the following approximate model.

First, from the characteristic of i), when calculating the magnitude of the voltage drop at a certain time, it is approximated by a degenerate model in which thousands of modulation wirings are concentrated into several to several tens of modulation wirings. We examined whether it could be simplified and calculated (this will be explained in detail in the calculation of the voltage drop by the following degenerate model).

Further, from the characteristics mentioned in ii), it is possible to roughly predict the time change of the voltage drop by providing a plurality of times in one horizontal scanning period and calculating the voltage drop at each time. did.

Concretely, the time change of the voltage drop was roughly predicted by calculating the voltage drop by the degenerate model described below for a plurality of times.

(Calculation of voltage drop by degenerate model) FIG. 6
(A) is a figure for demonstrating the block and node at the time of performing degeneration of this invention.

In the figure, for simplification of the drawing, only the selected scanning wiring, each modulation wiring, and the surface conduction electron-emitting device connected to the intersection thereof are shown.

Now, at a certain time in one horizontal scanning period, the lighting state of each pixel on the selected scanning wiring (that is, whether the output of the modulating means is "H" or "L"). ) Is known.

In this lighting state, the element current flowing from each modulation wiring to the selected scanning wiring is set to Ifi (i =
1, 2 ,. ． ． N and i are defined as column numbers).

As shown in the figure, a block is defined by grouping the n modulation wirings, the intersections of the selected scanning wirings and the surface conduction electron-emitting devices arranged at the intersections thereof. . In this example, the blocks are divided into four blocks.

Further, a position called a node is set at the boundary position of each block. A node is a horizontal position (reference point) for discretely calculating the amount of voltage drop that occurs on the scanning wiring in the degenerate model. Here, the divided blocks are constituted by surface conduction electron-emitting devices connected to the regions of the scanning wiring divided by the nodes (reference points).

In this example, node 0 is set at the block boundary position.
~ 5 nodes of node 4 were set.

FIG. 6B is a diagram for explaining the degenerate model.

In the degenerate model, the n modulation wirings included in one block in FIG. 10A were degenerated into one, and the scanning wirings were connected so as to be located at the center of the block.

Further, a current source is connected to the centralized modulation wiring of each block, and the sum total (statistical amount) IF0 to IF3 of the current in each block flows from each current source.

That is, IFj (j = 0, 1, ... 3)
Is

[Equation 1] Is the current expressed as

Further, the potentials at both ends of the scanning wiring are shown in FIG.
In the example of FIG. 5B, the GND potential is the potential difference between two points in the same figure (b), and in the degenerate model, it flows into the scanning wiring selected from the modulation wiring. This is because by modeling the current with the current source, the voltage drop amount of each part on the scanning wiring can be calculated by calculating the voltage (potential difference) of each part with the feeding part as a reference potential.

Further, the surface conduction electron-emitting device is omitted regardless of the presence or absence of the surface conduction electron-emitting device as long as an equivalent current flows from the column wiring when viewed from the selected scanning wiring. This is because the generated voltage drop itself does not change. Therefore, here, the surface conduction electron-emitting device is omitted by setting the current value flowing from the current source of each block to the total current value of the device currents in each block (Equation 1).

Further, the wiring resistance of the scanning wiring of each block is set to n times the wiring resistance r of the scanning wiring of one section (here, one section is the intersection of the scanning wiring with a certain column wiring and its adjacent portion. In this example, the wiring resistance of the scanning wiring in one section is assumed to be uniform.

In such a degenerate model, the amount of voltage drop DV0 to DV generated at each node on the scanning wiring.
4 can be easily calculated by the following product-sum formula.

[0117]

[Equation 2] That is,

[Equation 3] Is.

However, aij is a voltage generated at the i-th node when a unit current is injected into only the j-th block in the degenerate model. (Hereinafter, this is aij
And the definition. ).

The above aij can be easily derived as follows according to Kirchhoff's law.

That is, in FIG. 6B, the wiring resistance from the current source of the block i to the supply terminal on the left side of the scanning wiring is rli (i = 0, 1, 2, 3) to the supply terminal on the right side. The wiring resistance is defined as rri (i = 0, 1, 2, 3), and the wiring resistance between the block 0 and the left supply terminal and the wiring resistance between the block 4 and the right supply terminal are both defined as rt. If

[Equation 4] further,

[Equation 5] Then, aij is

[Equation 6] Can be derived easily.

However, in (Equation 3), A // B is
A symbol representing the resistance value of the resistance A and the resistance B in parallel,
// B = A × B / (A + B).

Even if the number of blocks is not four, (Equation 2) can be easily calculated by Kirchhoff's law, considering the definition of aij. Further, even in the case where the power supply terminals are not provided on both sides of the scanning wiring as in this example and only one side is provided, the calculation can be easily performed by performing calculation according to the definition of aij.

The parameter aij defined by (Equation 3) does not have to be recalculated each time, and
It should be calculated once and stored as a table.

Further, with respect to the total currents IF0 to IF3 of each block defined by (Equation 1),

[Equation 7] The approximation as shown in (Equation 4) is performed.

However, in the above equation, Count i is a variable that takes 1 when the i-th pixel on the selected scanning line is in the lighting state and takes 0 when it is in the unlit state.

IFS is the amount obtained by multiplying the device current IF flowing when the voltage V _SEL is applied across the one surface conduction electron-emitting device by a coefficient α taking a value between 0 and 1.

That is,

[Equation 8] Was defined.

In (Equation 4), the element current proportional to the number of lights in the block flows into the selected scan wiring from the column wiring of each block. At this time, a value obtained by multiplying the element current IF of one element by a coefficient α is the element current I of one element.
The reason why FS is taken into consideration is that the amount of the device current is reduced due to the increase in the voltage of the scanning wiring due to the voltage drop.

FIG. 6C shows an example of the result of calculation of the voltage drop amounts DV0 to DV4 of each node by the degeneration model in a certain lighting state.

Since the voltage drop has a very smooth curve, it is assumed that the voltage drop between the nodes approximately takes the value shown by the dotted line in the figure.

By using this degenerate model as described above, it is possible to calculate the voltage drop for each node at a desired time point with respect to arbitrary image data.

As described above, the amount of voltage drop in a certain lighting state was simply calculated using the degeneration model.

The voltage drop that occurs on the selected scan wiring changes with time within one horizontal scanning period, but as described above, this occurs at some times (reference times) during one horizontal scanning period. For the lighting state at that time,
It was predicted by calculating the voltage drop for the lighting state using a degeneration model.

The number of lights in each block at a certain point in one horizontal scanning period can be easily obtained by referring to the image data of each block.

Now, as an example, assume that the number of bits of input data to the pulse width modulation circuit is 8 bits, and the pulse width modulation circuit outputs a linear pulse width with respect to the size of the input data. And

That is, when the input data is 0, the output is "L", when the input data is 255, "H" is output during one horizontal scanning period, and when the input data is 128, one horizontal scanning period. It is assumed that "H" is output in the first half period and "L" is output in the second half period.

In such a case, the number of lights at the rise time (start time) of the pulse width modulation signal can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than zero.

Similarly, the number of lights at the center time of one horizontal scanning period can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than 128.

In this way, by comparing the image data with a certain threshold value and counting the number of true outputs of the comparator, the number of lightings at any time can be easily calculated.

Here, in order to simplify the following description, a time amount called a time slot is defined.

That is, the time slot represents the time from the rise of the pulse width modulation signal in one horizontal scanning period, and the time slot = 0 means the start time of the pulse width modulation signal (in this case, the rise time). ) Defined as representing the time immediately after.

Time slot = 64 is defined as a time when 64 gradations have elapsed from the start time of the pulse width modulation signal.

Similarly, time slot = 128 is defined as a time when 128 gradations have elapsed from the start time of the pulse width modulation signal.

In this example, the pulse width modulation has been described in which the rising time is used as a reference and the pulse width from it is modulated. Similarly, when the pulse width is modulated using the falling time of the pulse as a reference. However, it goes without saying that the same can be applied, although the advancing direction of the time axis is opposite to the advancing direction of the time slot.

(Calculation of Correction Data from Voltage Drop Amount) As described above, the time change of the voltage drop during one horizontal scanning period is approximately and discretely calculated by repeatedly performing the degeneracy model. I was able to.

FIG. 7 shows an example in which the voltage drop is repeatedly calculated for a certain image data, and the time change of the voltage drop in the scan wiring is calculated (the voltage drop shown here and its time change are , An example for one image data, and it is natural that the voltage drop for another image data has another change.

In the figure, time slots = 0, 64, 12
The degenerate model was applied to each of the four time points of 8 and 192 to perform the calculation, and the voltage drop at each time was calculated discretely.

In FIG. 7, the voltage drop amount at each node is connected by a dotted line, but the dotted line is shown to make the diagram easier to see, and the voltage drop calculated by this degenerate model is □, ○, Δ. It was calculated discretely at the position of each node shown in.

The inventors examined a method of calculating correction data for correcting image data from the amount of voltage drop as the next step after the magnitude of voltage drop and its change over time can be calculated.

FIG. 8 is a graph in which the emission current emitted from the surface conduction electron-emitting device in the lighting state is estimated when the voltage drop shown in FIG. 7 occurs on the selected scanning wiring.

The vertical axis represents the amount of the emission current at each position at each time in percentage, with the magnitude of the emission current emitted when there is no voltage drop being 100%, and the horizontal axis represents the horizontal position. There is.

As shown in FIG. 8, the horizontal position of node 2
At (reference point), the emission current at time slot = 0 is Ie0, the emission current at time slot = 64 is Ie1, the emission current at time slot = 128 is Ie2, and the emission current at time slot = 192 is Let the current be Ie3.

FIG. 8 is calculated from the graph of the voltage drop amount of FIG. 7 and the “driving voltage vs. emission current” of FIG. Specifically, it is simply a mechanical plot of the value of the emission current when a voltage obtained by subtracting the voltage drop amount from the voltage V _SEL is applied.

Therefore, FIG. 8 means only the current emitted from the surface conduction electron-emitting device in the lighting state, and the surface conduction electron-emitting device in the off state does not emit current.

A method of calculating correction data for correcting image data from the amount of voltage drop will be described below.

FIGS. 9A, 9B and 9C are diagrams for explaining a method of calculating correction data of the voltage drop amount from the time change of the emission current of FIG. The figure is 64
It is an example of calculating the correction data for the image data.

The emission amount of luminance is nothing but the emitted charge amount obtained by temporally integrating the emission current by the emission current pulse.
Therefore, in the following, when considering the variation of the brightness due to the voltage drop, the description will be given based on the amount of the emitted charges.

Now, when there is no influence of the voltage drop, the emission current is IE, and the time corresponding to one gradation of the pulse width modulation is Δt.
Then, when the image data is 64, the emission charge amount Q0 to be emitted by the emission current pulse is obtained by multiplying the amplitude IE of the emission current pulse by the pulse width (64 × Δt).

[Equation 9] Can be represented as

However, in reality, a phenomenon occurs in which the emission current decreases due to the voltage drop on the scanning wiring.

The amount of charge emitted by the emission current pulse considering the influence of the voltage drop can be approximately calculated as follows. That is, if the emission currents of the time slots = 0 and 64 of the node 2 are Ie0 and Ie1, respectively, and if the emission current between 0 and 64 is approximated to linearly change between Ie0 and Ie1, the emission during this period is approximated. The charge amount Q1 is shown in FIG.
Area of the trapezoid of

[Equation 10] Can be calculated as

Next, as shown in FIG. 9C, it is assumed that the influence of the voltage drop can be removed when the pulse width is extended by DC1 in order to correct the decrease in the emission current due to the voltage drop.

When the voltage drop is corrected and the pulse width is extended, it is considered that the amount of emission current in each time slot changes, but here, for simplification,
As shown in FIG. 9C, it is assumed that the emission current is Ie0 at time slot = 0 and the emission current at time slot = (64 + DC1) is Ie1.

Further, the emission current between the time slot 0 and the time slot (64 + DC1) is approximated to take a value on a line connecting the emission currents at two points with a straight line.

Then, the amount of charge Q2 emitted by the corrected emission current pulse is

[Equation 11] Can be calculated as

If this is equal to Q0, then

[Equation 12] Becomes

If this is solved for DC1,

[Equation 13] Becomes

In this way, the correction data when the image data was 64 was calculated.

That is, the size of the position of node 2 is 6
For the image data of 4, as shown in (Equation 9), C
The correction amount may be added by Data = DC1.

FIG. 10 shows an example in which correction data for image data of size 128 is calculated from the calculated voltage drop amount.

Now, when there is no influence of the voltage drop, when the image data is 128, the emission charge amount Q3 emitted by the emission current pulse is

[Equation 14] Is.

On the other hand, the input charge amount due to the actual emission current pulse, which is affected by the voltage drop, can be approximately calculated as follows.

That is, the time slot of node 2 =
Emission current amounts of 0, 64, and 128 are Ie0 and Ie, respectively.
1 and Ie2. The emission current between 0 and 64 is I
If it is approximated to change linearly between e0 and Ie1 and change on a line connecting Ie1 and Ie2 with a straight line between 64 and 128, the emitted charge during the time slot from 0 to 128 is approximated. The quantity Q4 is the sum of the areas of the two trapezoids in FIG.

[Equation 15] Can be calculated as

On the other hand, the correction amount of the voltage drop was calculated as follows.

The period corresponding to time slots 0 to 64 is defined as period 1, and the period corresponding to 64 to 128 is defined as period 2.

When the correction is applied, the portion of the period 1 is DC1.
Is extended to period 1'and the portion of period 2 is DC2
I think that it will be extended only in the period 2 '.

At this time, it is assumed that the amount of emitted charges becomes the same as Q0 described above by performing the correction in each period.

It is needless to say that the emission currents at the beginning and the end of each period change due to the correction, but here it is assumed that they do not change in order to simplify the calculation.

That is, the emission current at the beginning of the period 1'is I
e0, the emission current at the end of period 1'is Ie1, period 2 '
The emission current at the beginning of the period is Ie1 and the emission current at the end of the period 2'is Ie2.

Then, DC1 can be calculated in the same manner as (Equation 9).

DC2 is also based on the same idea.

[Equation 16] Can be calculated as

As a result, the size of the position of node 2 is 12
For the image data of 8,

[Equation 17] Only the correction amount needs to be added.

FIG. 11 is an example in which correction data for image data of size 192 is calculated from the calculated voltage drop amount.

Now, when the image data is 192, the emission charge amount Q5 expected by the emission current pulse is

[Equation 18] Is.

On the other hand, the amount of electric charge emitted by the actual emission current pulse, which is affected by the voltage drop, can be approximately calculated as follows.

That is, the time slot of node 2 = 0
Let Ie0 be the emission current at time, Ie1 be the emission current at time slot = 64, Ie2 be the emission current at time slot = 128, and Ie3 be the emission current at time slot = 192. Emission currents of Ie0 and Ie
1 linearly changes, and between 64 and 128 changes on a line connecting Ie1 and Ie2 with a straight line, 128 to 19
2 can be approximated as changing on a line connecting Ie2 and Ie3 with a straight line, the injected charge amount Q6 during the time slot from 0 to 192 is the area of the three trapezoids in FIG. 11B. , That is,

[Formula 19] Can be calculated as

On the other hand, the correction amount of the voltage drop was calculated as follows.

The period corresponding to the time slots 0 to 64 is the period 1, and the period corresponding to the time slots 64 to 128 is the period 2,128.
The period corresponding to 192 is defined as period 3.

Similarly to the above, after the correction, the portion of the period 1 is extended by DC1 and extended to the period 1 ', and the portion of period 2 is extended by DC2 and extended to the period 2',
It is assumed that the part of the period 3 is extended by DC3 and then extended to the period 3 ′.

At this time, it is assumed that the amount of emitted charges becomes the same as Q0 described above by being corrected in each period.

Further, it is assumed that the emission currents at the beginning and the end of each period do not change before and after the correction.

That is, the emission current at the beginning of the period 1'is
Ie0, the emission current at the end of the period 1'is Ie1, the emission current at the beginning of the period 2'is Ie1, the emission current at the end of the period 2'is Ie2, and the emission current at the beginning of the period 3'is Ie.
2, the emission current at the end of the period 3 ′ is Ie3.

Then, DC1 and DC2 can be calculated similarly to (Equation 9) and (Equation 12), respectively.

For DC3,

[Equation 20] Can be calculated as

As a result, the size of the position of node 2 is 19
As the correction data CData to be added to the image data of 2,

[Equation 21] And it is sufficient.

As described above, the correction data CDat of the image data 64, 128, 192 for the position of the node 2 is obtained.
a was calculated.

When the pulse width is 0, of course, there is no influence of the voltage drop on the emission current, so the correction data is set to 0 and the correction data CData is added to the image data.
Is also 0.

Incidentally, as described above, 0, 64, 128, 19
The reason why correction data is calculated for discrete image data as in 2 is to reduce the amount of calculation.

That is, if the same calculation is performed on all arbitrary image data, the calculation amount becomes very large.
The amount of hardware for calculation becomes very large.

On the other hand, at a certain node position, the larger the image data, the larger the correction data tends to be. As a result, when calculating correction data for arbitrary image data, if the points near the image data for which correction data has already been calculated and the points are interpolated by linear approximation, the amount of calculation will be greatly reduced. This is because you can Note that this interpolation will be described in detail when the discrete correction data interpolation means is described.

If the same idea is applied to the positions of all the nodes, the correction data of image data = 0, 64, 128, 192 can be calculated at the positions of all the nodes.

The image data for which the correction data is calculated in this way is called an image data reference value.

In this example, the time slots are 0, 64, 12
By applying the degenerate model to the four points of 8, 192 and calculating the voltage drop amount at each time, 0, 64, 12
The correction data for the four image data reference values of 8,192 could be obtained.

However, as described above, preferably, the time interval for calculating the voltage drop by the degenerate model is made fine,
By increasing the reference value of the image data, the time change of the voltage drop can be handled more accurately, and the error in the approximation calculation can be reduced.

At that time, based on the same idea,
Calculations may be performed by modifying (Equation 6) to (Equation 16).

FIG. 12A shows an example of the result of discretely calculating correction data for image data = 0, 64, 128, 192 at the position of each node with respect to certain input data by the above method. Is.

Incidentally, in the same drawing, the discrete correction data for the same image data are shown by connecting them with a dotted curve in order to make the drawing easier to see.

(Interpolation Method of Discrete Correction Data) The correction data calculated discretely is discrete with respect to the position of each node and does not give the correction data at an arbitrary horizontal position (column wiring number). Absent. At the same time, it is correction data for image data having some predetermined reference image data size at each node position and does not give correction data according to the actual image data size. .

Therefore, the inventors calculated the correction data suitable for the size of the input image data in each column wiring by interpolating the correction data calculated discretely.

FIG. 12B shows the image data Dat at the position x located between the node n and the node n + 1.
It is the figure which showed the method of calculating the correction data equivalent to a.

As a premise, it is assumed that the correction data has already been discretely calculated at the positions Xn and Xn + 1 of the nodes n and n + 1.

Data as input image data is assumed to take a value between two image data reference values Dk and Dk + 1 for which correction data has already been calculated discretely.

Now, the correction data for the reference value Dk of the kth image data of the node n is set to CData [k] [n].
The correction data CA for the image data Dk at the position x is CData [k] [n] and CD
The value of ata [k] [n + 1] can be used to calculate as follows by linear approximation.

[0213]

[Equation 22] Can be calculated.

Also, the image data Dk + 1 at the position x
The correction data CB of

[Equation 23] Can be calculated.

By linearly approximating the correction data of CA and CB, the correction data CD for the image data Data at the position x is as follows.

[Equation 24] Can be calculated.

As described above, in order to calculate the correction data suitable for the actual position and the size of the image data from the discrete correction data, the calculation is simply performed by the method described in (Equation 17) to (Equation 19). it can.

If the correction data thus calculated is added to the image data to correct the image data and the pulse width modulation is performed according to the corrected image data, the image quality due to the voltage drop, which has been a problem in the past, has been solved. Can be reduced and the image quality can be improved.

The hardware for correction, which has been a problem in the future, can be reduced in a very small scale by introducing the approximation such as degeneracy described above so that the calculation amount can be reduced. It has an excellent merit that it can be configured with various hardware.

(Explanation of Function of Entire System and Each Part) Next, the hardware of the image display device incorporating the correction data calculating means will be explained.

FIG. 13 is a block diagram showing an outline of the circuit configuration. In the figure, 1 is the display panel of FIG. 1, Dx1
˜DxM and Dx1 ′ to DxM ′ are voltage supply terminals of the scanning wiring of the display panel, Dy1 to DyN are voltage supply terminals of the modulation wiring of the display panel, and Hv is for applying an acceleration voltage between the face plate and the rear plate. High voltage supply terminal,
Va is a high voltage power supply, 2 is a scanning circuit (scanning means), 3 is a synchronization signal separation circuit, 4 is a timing generation circuit, 7 is a conversion circuit for converting the YPbPr signal into RGB by the synchronization separation circuit 3, and 17 is a reverse γ. A processing unit, 5 is a shift register for one line of image data, 6 is a latch circuit for one line of image data, 8 is pulse width modulation means (modulation means) for outputting a modulation signal to the modulation wiring of the display panel, and 12 is addition. Device (arithmetic processing unit, addition processing unit), 14 correction data calculation unit, 19 delay circuit, 20 test pattern generator, 2
Reference numeral 1 is a device parameter measurement control CPU, and 22 and 23 are changeover switches.

Further, in the figure, R, G and B are RGB parallel input video data, Ra, Ga and Ba are RGB parallel video data subjected to an inverse γ conversion process which will be described later, and D.
ata is image data subjected to parallel / serial conversion by the data array conversion unit, CD is correction data calculated by the correction data calculating unit, and Dout is image data corrected by adding the correction data to the image data by the adder. Is.

(Synchronous Separation Circuit, Timing Generation Circuit) The image display device according to the present embodiment uses NTSC, PAL, SE.
Television signals such as CAM and HDTV, and VGA output from a computer can be displayed together.

In FIG. 13, in order to simplify the drawing, HDTV
Only the method is described.

In the HDTV system video signal, the synchronization signals Vsync and Hsync are first separated by the synchronization separation circuit 3 and supplied to the timing generation circuit. The video signals separated by synchronization are supplied to the RGB conversion means. Inside the RGB conversion means, a YPbPr-to-RGB conversion circuit, a low-pass filter (not shown), an A / D converter, and the like are provided. The YPbPr is converted into a digital RGB signal, and the inverse γ processing is performed. Supply to the department.

(Timing Generation Circuit) The timing generation circuit is a circuit which has a built-in PLL circuit, generates timing signals synchronized with the synchronization signals of various video sources, and generates operation timing signals for each section.

The timing signal generated by the timing generating circuit 4 is T _SFT for controlling the operation timing of the shift register 5, the shift register 5 to the latch circuit 6.
Control signal Dataalo for latching data to
d, pulse width modulation start signal Pwmstar of the modulation means 8
t, a clock Pwmclk for pulse width modulation, Tscan for controlling the operation of the scanning circuit 2, and the like.

(Scanning Circuit) The scanning circuits 2 and 2 ′ output the selection potential Vs or the non-selection potential Vns to the connection terminals Dx1 to DxM in order to sequentially scan the display panel row by row in one horizontal scanning period. Circuit (FIG. 14).

As shown in the figure, the scanning circuit 2 is equipped with a power supply 24 for outputting the selection potential Vs and a power supply 25 for outputting the non-selection potential Vns. The power supply 24 has a current value monitor function, and outputs the current current value in response to a current value read request from the outside.

The scanning circuits 2 and 2 ′ are circuits that perform scanning by sequentially switching the selected scanning wiring in each horizontal period in synchronization with the timing signal Tscan from the timing generation circuit 4.

Note that Tscan is a timing signal group made up of a vertical synchronizing signal, a horizontal synchronizing signal, and the like.

The scanning circuits 2 and 2'are each composed of M switches and shift registers as shown in FIG. These switches are preferably composed of transistors or FETs.

In order to reduce the voltage drop in the scanning wiring, it is preferable that the scanning circuit is connected to both ends of the scanning wiring of the display panel and driven from both ends as shown in FIG.

On the other hand, the present invention is effective even when the scanning circuit is not connected to both ends of the scanning wiring, and can be applied only by changing the parameter of Expression 3.

(Inverse γ processing section) The CRT has a light emission characteristic of approximately 2.2 to the input (hereinafter referred to as an inverse γ characteristic).

Such characteristics of the CRT are taken into consideration in the input video signal, and the input video signal is generally converted according to the .gamma. Characteristic of 0.45 so as to have a linear emission characteristic when displayed on the CRT.

On the other hand, when the display panel of the image display device of the present invention is modulated by the application time of the drive voltage, it has a substantially linear light emission characteristic with respect to the length of the application time.
It is necessary to convert the input video signal based on the inverse γ characteristic (hereinafter referred to as inverse γ conversion).

The inverse γ processing section 17 shown in FIG. 13 is a block for performing inverse γ conversion on the input video signal.

The inverse γ processing section 17 of this embodiment uses the inverse γ
The conversion process is composed of memory.

The inverse γ processing unit 17 sets the number of bits of the video signals R, G, B to 8 bits, and the number of bits of the video signals Ra, Ga, Ba output from the inverse γ processing unit is also 8 bits, and sets the address 8 It is configured by using a memory of 8 bits and data of 8 bits for each color (FIG. 15).

The inverse γ characteristic shown in FIG. 16 is stored in each memory. It should be noted that the figure shows the data described in the table when the input video signal of this conversion table is in the range of 0 to 255.

(Data Array Converter) Data Array Converter 9
Is a circuit for performing parallel / serial conversion of RGB parallel video signals Ra, Ga, Ba according to the pixel array of the display panel. The configuration of the data array converter 9 is shown in FIG.
As shown in, the FIFO (First
In First Out) memory 2021R, 20
21G, 2021B and a selector 2022.

Although not shown in the figure, the FIFO memory includes two horizontal pixel memory words for odd lines and even lines. When the video data of the odd line is input, the data is written in the FIFO for the odd line, while the image data accumulated in the previous horizontal scanning period is read from the FIFO memory for the even line. When the video data of the even-numbered lines is input, the data is written in the FIFO for the even-numbered lines, while the image data accumulated in the previous horizontal period is read from the FIFO memory for the odd-numbered lines.

The data read from the FIFO memory is parallel-serial converted by the selector according to the pixel array of the display panel and output as RGB serial image data SData. Although not described in detail, it operates based on the timing control signal from the timing generation circuit 4.

(Adder 12) The adder 12 is means for adding the correction data CD and the image data Data from the correction data calculating means. Image data D can be obtained by adding
ata is corrected and transferred to the shift register as image data Dout.

The image data Data and the correction data C
Although overflow may occur in the adder when D is added, in contrast to this, in this example, as a configuration for preventing overflow, the maximum value when the image data Data and the correction data CD are added is set. Accordingly, the bit width of the adder and the bit width of the subsequent modulation means were determined.

More specifically, in the case of the image display apparatus of this example, the maximum correction value is 120 when the image data is all 255 screens, so the maximum value of the output of the adder = 2.
Since 55 + 120 = 375, the number of bits output from the adder is 9 bits, and the number of bits of the modulation means is also 9 bits.

As another structure for preventing overflow, the maximum value of the correction data to be added is roughly estimated and overflow is prevented when the maximum value is added. The range of image data may be reduced in advance.

In order to reduce the size of the image data, for example, the input image data may be limited when it is A / D converted, or a multiplier may be provided to reduce the input image data to 0. The magnitude may be limited by multiplying the gain by 1 or more.

(Delay Circuit 19) The image data SData rearranged by the data array converter is input to the correction data calculation means and the delay circuit (delay means) 19. The correction data interpolation unit of the correction data calculation means 14 is provided with the horizontal position information x from the timing control circuit and the image data SData.
The correction data CD suitable for them is calculated with reference to the value of.

The delay circuit 19 is provided to absorb the time required for calculating the correction data. When the adder 12 adds the correction data to the image data, the correction data corresponding to the correct correction data is correctly added to the image data. It is a means for delaying the addition. The same means can be configured by using a flip-flop.

(Shift Register, Latch Circuit) The image data Dout, which is the output of the correction data interpolating section, is transferred from the serial data format by the shift register 5 to
The parallel image data ID1 to IDN for each modulation wiring are serial / parallel converted and output to the latch circuit. The latch circuit latches the data from the shift register by the timing signal Dataload immediately before the start of one horizontal period. The output of the latch circuit 6 is supplied to the modulation means as parallel image data D1 to DN.

In this embodiment, the image data ID1
-IDN and D1-DN are 8-bit image data. These operation timings are the timing control signals T _SFT and Da from the timing generation circuit 4 (FIG. 13).
It operates based on taload.

(Details of Modulating Means) The parallel image data D1 to DN output from the latch circuit 6 are supplied to the modulating means 8.

As shown in FIG. 18A, the modulation means is a pulse width modulation circuit (PWM circuit) including a PWM counter, a comparator and a switch (FET in the figure) for each modulation wiring.

The relationship between the image data D1 to DN and the output pulse width of the modulating means has a linear relationship as shown in FIG. 18 (b).

FIG. 3C shows an example of the output waveform of the modulator 3
Show one.

In the figure, the upper waveform is the waveform when the input data to the modulating means is 0, the central waveform is the waveform when the input data to the modulating means is 256, and the lower waveform is the modulating means. This is a waveform when the input data to 511 is 511.

In this example, the input data D1 to the modulation means is
As described above, the number of bits of DN is 9 bits in consideration of the fact that overflow does not occur (in the above description, when the input data of the modulating means is 511, a pulse corresponding to one horizontal scanning period). Although there is a part where it is described that the width modulation signal is output, in detail, as shown in FIG. 7C, although it is a very short time, the period before the pulse rises and the period during which the pulse does not drive after the fall are provided. I have a certain margin.).

FIG. 19 is a timing chart showing the operation of the modulation means of the present invention.

In the figure, the Hsync horizontal synchronizing signal,
Dataload is a load signal to the latch circuit 6, D1
-DN are the input signals to the columns 1-N of the aforementioned modulation means, Pw
mstart is a PWM counter synchronization clear signal, Pw
mclk is the clock of the PWM counter. Also, X
D1 to XDN represent outputs of the first to Nth columns of the modulation means.

When one horizontal scanning period starts as shown in the figure, the latch circuit 6 latches the image data and transfers the data to the modulating means.

The PWM counter, as shown in FIG.
Counting is started based on Pwmstart and Pwmclk, and when the count value reaches 511, the counter is stopped and the count value 511 is held.

The comparator provided for each column is
The count value of the PWM counter is compared with the image data of each column, and when the value of the PWM counter is greater than or equal to the image data, High
h is output, and Low is output during the other periods.

The output of the comparator is connected to the gates of the switches in each column, and the output of the comparator is Low.
During the period, the switch on the upper side (VPWM side) in the figure is ON,
The lower (GND side) switch is turned off, and the modulation wiring is connected to the voltage VPWM.

On the contrary, while the output of the comparator is High, the upper switch in the figure is turned off and the lower switch is turned on, and the voltage of the modulation wiring is connected to the GND potential.

The pulse width modulation signal output from the modulating means is D1, D in FIG. 19 as a result of the operation of each section as described above.
2, a waveform in which the rising edges of the pulses are synchronized as shown by DN.

(Element parameter measurement control CPU, test pattern generator) Element parameter measurement control CPU 21
Is for measuring the characteristics of the image forming element.
The element characteristics are measured as a current flowing through the power supply 24 of the scanning circuit 2 when a predetermined test pattern is output from the test pattern generator 20 to the panel when the power of the panel is turned on. This current value is sent to the correction data calculation means 14 as the reference current value IFr, and is used to select the element current table to be used when calculating the voltage drop correction data.

The device characteristic measuring operation when the power is turned on will be described with reference to the flowchart of FIG. 24 and FIG.

When the power-on is detected, the element parameter measurement control CPU 21 starts the element characteristic measurement operation before applying the high voltage to the display panel.

First, the signal S is sent to the changeover switches 22 and 23.
By sending el, the inputs to the timing generation circuit 4 and the shift register 5 are switched to those from the test pattern generator 20 (S31).

Next, a signal is sent to the test pattern generator to generate a test pattern (S32). In this embodiment, this is the data of the maximum pulse width of the entire screen.

Next, the current value reading signal RData is sent to the power supply 24 of the scanning circuit 2 (S33).

The power supply 24 outputs the average amount of current in one vertical synchronizing period when the panel is driven by the test pattern according to RData as the reference current value IFr and sends it to the correction data calculating means (S34).

When the reference current value IFr is output, the device parameter measurement control CPU switches the changeover switches 22 and 23.
Then, the signal Sel is sent to switch the input to the timing generation circuit 4 and the shift register 5 from the video data (S35), and the device characteristic measuring operation is completed.

After that, a high voltage is applied to the panel to display an image. By performing the element characteristic measuring operation before applying the high voltage, the test pattern is not displayed on the screen and does not bother the user.

(Correction Data Calculation Means) The correction data calculation means 14 is a circuit for calculating the voltage drop correction data by the above-mentioned correction data calculation method. The correction data calculation means 14 is composed of two blocks, a discrete correction data calculation unit and a correction data interpolation unit, as shown in FIG.

The discrete correction data calculation unit is means for calculating the voltage drop amount from the input video signal and discretely calculating the correction data from the voltage drop amount. In order to reduce the amount of calculation and the amount of hardware, the means introduces the concept of the above-mentioned degenerate model and calculates correction data discretely.

The correction data calculated discretely is interpolated by the correction data interpolating section (correction data interpolating means), and the correction data CD suitable for the size of the image data and its horizontal display position x is calculated.

(Discrete Correction Data Calculation Unit) FIG. 21 shows a discrete correction data calculation unit for calculating the discrete correction data of the present invention.

As will be described below, the discrete correction data calculation unit divides the image data into blocks, calculates a statistic (number of lights) for each block, and calculates the voltage drop amount at each node position from the statistic. A function as a voltage drop amount calculation unit that calculates a time change, a function that converts the voltage drop amount for each time into a light emission brightness amount, and a function that integrates the light emission brightness amount in the time direction to calculate a total light emission brightness amount. , And correction data for the reference values of the image data at discrete reference points.

In the figure, 100a to 100d are lighting number counting means, 101a to 101d are a group of registers for storing the number of lighting at each time for each block, and 10
2 is a CPU, 103 is a table memory (voltage drop amount storage means) for storing the parameters aij described in equations 2 and 3, 104 is a temporary register for temporarily storing the calculation result, and 105 is a program for the CPU. Program memory, 113 is a register in which a reference current value IFr indicating the device characteristic of the panel is stored, 1
Reference numeral 12 is a table memory for calculating the element current amount for calculating the voltage drop amount from the reference current value IFr.
Reference numeral 1 is a table memory in which conversion data for converting a voltage drop amount into an emission current amount is described, and 106 is a register group for storing the calculation result of the discrete correction data described above.

Lighting number counting means 100a to 100d
Is composed of a comparator and an adder as shown in FIG. The video signals Ra, Ga, and Ba are input to the comparators 107a to 107c, respectively, and sequentially C
It is compared with the value of val.

Cval corresponds to the reference value set for the image data described above.

The comparators 107a to 107c compare Cval with the image data, and if the image data is larger, Hi.
gh is output, and Low is output if it is small.

The output of the comparator is the adders 108 and 1
09, and the addition is performed for each block by the adder 110, and the addition result for each block is set as the lighting number for each block in the register group 1
01a-c are stored.

In the lighting number counting means 100a to 100d, 0, 64 and 1 are respectively set as the comparison value Cval of the comparator.
28 and 192 are input.

As a result, the lighting number counting means 100a
Counts the number of image data larger than 0 among the image data, and registers the total for each block in the register 101.
Store in a.

Similarly, the lighting number counting means 100b counts the number of image data larger than 64 among the image data, and the total for each block is registered in the register 101b.
To store.

Similarly, the lighting number counting means 100c counts the number of the image data larger than 128 among the image data, and the total for each block is registered in the register 101.
Store in c.

Similarly, the number-of-lights counting means 100d counts the number of image data larger than 192 among the image data, and the total for each block is registered in the register 101.
Store in d.

When the number of times of lighting for each block is counted, the CPU reads the parameter table aij stored in the table memory 103 at any time, and calculates the voltage drop amount according to (Equation 2) to (Equation 5). Then, the calculation result is stored in the temporary register 104.

At this time, the CPU 102 first sets the register 1
The value of the reference current value IFr is read with reference to the contents of 13.

Further, in order to obtain the element current amount used for the voltage drop from the reference current value IFr, the table memory 3
Refer to the content of (112). In the table memory 3,
The relationship between the reference current value IFr and the element current IF is stored, and when the reference current value IFr is input, the element current amount IF corresponding thereto is output.

The element current amount IF thus obtained
Is substituted into (Equation 5), and the amount of voltage drop is calculated.

In this example, the CPU is provided with a product-sum operation function for smoothly performing the calculation of (Equation 2).

As a means for realizing the operation shown in (Equation 2), the CPU does not have to perform the product-sum operation.
The calculation result may be stored in the memory.

That is, the number of lighting of each block may be used as an input and the voltage drop amount at each node position may be stored in the memory for all possible input patterns.

When the calculation of the voltage drop amount is completed, C
The PU reads out the voltage drop amount for each block from the temporary register 104 at each time, and outputs the table memory 2
With reference to (111), the voltage drop amount was converted into the emission current amount, and the discrete correction data was calculated according to (Equation 6) to (Equation 16).

The calculated discrete correction data is stored in the register group 1
It was stored in 06.

(Correction Data Interpolation Unit) The correction data interpolation unit is means for calculating the correction position data (horizontal position) at which the image data is displayed and the correction data suitable for the size of the image data. This means interpolates the correction data calculated discretely to display the image data (horizontal position).
Also, correction data corresponding to the size of the image data is calculated.

FIG. 22 is a diagram for explaining the correction data interpolation unit.

In the figure, 123 is a decoder for determining the node numbers n and n + 1 of the discrete correction data used for interpolation from the display position (horizontal position) x of the image data, and 124 is the size of the image data. (Equation 17) ~
It is a decoder for determining k and k + 1 in (Equation 19).

Further, the selectors 125 to 128 are selectors for selecting the discrete correction data and supplying it to the linear approximation means.

Further, 121 to 123 are respectively expressed by the formula (1
It is a linear approximation means for performing the linear approximation of 7) to (19).

FIG. 23 shows a configuration example of the linear approximation means 121. Generally, the linear approximation means is represented by the operators of the equations (17) to (19), as shown in the subtractor, the integrator, the adder,
It can be configured by a divider or the like.

However, it is desirable that the number of column wirings between the nodes for calculating the discrete correction data and the interval of the image data reference value for calculating the discrete correction data (that is, the time interval for calculating the voltage drop) be a power of two. There is a merit that the hardware can be configured very easily if it is configured as follows. If you set them to a power of 2,
In the divider shown in FIG. 3, Xn + 1-Xn becomes a power of 2 and bit shift is required.

If the value of Xn + 1-Xn is always a constant value and a value represented by a power of 2, it suffices to shift the addition result of the adder by the multiplier of the power and output it. There is no need to make a divider.

In addition, by setting the intervals of the nodes for calculating the discrete correction data and the intervals of the image data to the powers of 2 at other locations, for example, the decoders 123 to 124 can be easily manufactured, and There are many merits such as that the operation performed by the subtractor in FIG. 23 can be replaced with a simple bit operation.

(Operation Timing of Each Part) FIG. 25 shows a timing chart of the operation timing of each part.

In the figure, Hsync is a horizontal synchronizing signal and DotCLK is a PLL in the timing generation circuit.
A clock generated by the circuit from the horizontal synchronizing signal Hsync, R, G, B are digital image data from the input switching circuit, Data is image data after data array conversion,
Dout is image data that has been subjected to voltage drop correction, TSF
T is a shift clock for transferring the image data Dout to the shift register 5, Dataload is a load pulse for latching data in the latch circuit 6, and Pwms
start is the start signal of the above-mentioned pulse width modulation, the modulation signal X
D1 is an example of a pulse width modulation signal supplied to the modulation wiring 1.

With the start of one horizontal period, the digital image data RGB is transferred from the input switching circuit. In the figure, in the horizontal scanning period I, when the input image data is represented by R_I, G_I, and B_I, the image data is stored in the data array conversion circuit 9 for one horizontal period, and in the horizontal scanning period I + 1. , Is output as digital image data Data_I according to the pixel arrangement of the display panel.

R_I, G_I and B_I are input to the correction data calculating means in the horizontal scanning period I. With this means, the number of times of lighting described above is counted, and at the end of counting, the voltage drop amount is calculated.

Subsequent to the calculation of the voltage drop amount, the discrete correction data is calculated, and the calculation result is stored in the register.

In the scanning period I + 1, the correction data interpolating means interpolates the discrete correction data in synchronization with the output of the image data Data_I one horizontal scanning period before from the data array conversion unit, and the correction data is calculated. To be done. The interpolated correction data is supplied to the adder 12.

The adder 12 sequentially adds the image data Data and the correction data CD to obtain the corrected image data Do.
Transfer ut to the shift register. The shift register is T
Image data Dou for one horizontal period according to SFT
t is stored, serial-parallel conversion is performed, and parallel image data ID1 to IDN are output to the latch circuit 6.

The latch circuit 6 latches the parallel image data ID1 to IDN from the shift register at the rising edge of Dataload, and transfers the latched image data D1 to DN to the pulse width modulation means 8.

The pulse width modulation means 8 outputs a pulse width modulation signal having a pulse width according to the latched image data. In the image display device of the present embodiment, as a result, the pulse width output by the modulation means is displayed with a delay of two horizontal scanning periods with respect to the input image data.

When an image was displayed by such an image display device, it was possible to correct the amount of voltage drop in the scanning wiring, which had been a problem in the past, and it was possible to display a very good image. .

Further, the correction data can be calculated very easily by calculating the correction data discretely and interpolating between the points calculated discretely. It was very effective, as it could be achieved with simple hardware.

Further, even when the element characteristics change due to aging or the like, the correction circuit of the present invention appropriately corrects the change in the element current, so that a good image can be displayed, which is very preferable. .

In this embodiment, the current of the power source of the scanning circuit when the test pattern is output in order to measure the characteristics of the element is measured, but the present invention is not limited to this. It is also possible to provide a current measuring means to measure the amount of current that can be associated with the characteristics of the device, such as measuring the device current.

In this embodiment, the device characteristics are measured when the power is turned on. However, the device characteristics may be measured when the power is turned off. In that case, the device characteristics measurement operation is performed after turning off the high voltage power supply, and then The main power may be turned off.

It is also possible to separately provide a measurement mode and measure the element characteristics at any time according to the user's request. In that case, it is preferable that the application of high voltage is stopped during the device characteristic measuring operation so that the test pattern is not displayed, since it does not bother the user.

(Second Embodiment) In the first embodiment, the correction data calculation means calculates the correction data from the RGB parallel image data, but the present invention is not limited to this.

That is, the data array converter converts the RGB
It goes without saying that the correction data can be obtained by using the image data converted from parallel to RGB serial.

In this case, a register or memory for delaying the RGB serial image data is necessary to secure the time required to calculate the correction data, but similar correction can be performed. Needless to say.

In the first embodiment, the result calculated by the correction data calculation means is converted into the data array RGB.
An example of applying it to serial image data has been shown, but there is no particular limitation to this.

That is, the data array conversion unit is replaced with a simple line memory, parallel image data is input,
Even if the parallel image data is output, it goes without saying that the correction can be performed by a simple modification of the hardware.

Of course, the configuration shown in the first embodiment positively utilizes the line memory necessary for performing the data array conversion (parallel / serial conversion) of image data and the delay time there. Needless to say, the correction amount is calculated during the delay time and the correction is performed on the serial image data, which has the effect of reducing the amount of hardware.

Also in the present embodiment, even when the element characteristics change due to aging or the like, the correction circuit of the present invention appropriately corrects the change in the element current, so that a good image can be displayed. I was able to do it very much.

(Third Embodiment) In the first embodiment,
With respect to the input image data, the reference value of the discrete image data is set, the reference point is set on the row wiring, and the correction data for the image data having the size of the image data reference value at the reference point is calculated. Was there.

Further, the correction data calculated in accordance with the horizontal display position of the input image data and its size is calculated by interpolating the correction data calculated discretely, and the correction data is added to the image data to make the correction. Was realized.

On the other hand, the same correction can be performed by the following configuration in addition to the above configuration.

The correction result of the image data (that is, the sum of the discrete correction data and the image data reference value) with respect to the discrete horizontal position and the image data reference value is calculated, and the correction result calculated discretely is interpolated. However, a correction result corresponding to the horizontal display position of the input image data and its size may be calculated, and modulation may be performed according to the correction result.

With this configuration, since the image data and the correction data are added when discretely calculating the correction result, it is not necessary to add the image data and the correction data after the interpolation.

Also in the present embodiment, even when the element characteristics change due to aging or the like, the correction circuit of the present invention appropriately corrects the change in the element current to obtain a good image display. I was able to do it very much.

[0337]

As described above, according to the image display device and the image display method of the present invention, it is possible to improve the deterioration of the display image due to the voltage drop on the scanning wiring, which has been a problem in the past. It was

By introducing several approximations, the correction amount of the image data for correcting the voltage drop can be easily calculated, and it can be realized by very simple hardware. It had a very good effect.

Further, even when the element characteristics are changed due to a change with time or the like, it is possible to perform an appropriate correction corresponding to the change.

[Brief description of drawings]

FIG. 1 is a diagram showing an overview of an image display device of the present invention.

FIG. 2 is a diagram showing an electrical connection of a display panel.

FIG. 3 is a diagram showing characteristics of a surface conduction electron-emitting device.

FIG. 4 is a diagram showing a driving method of a display panel.

FIG. 5 is a diagram illustrating an influence of a voltage drop.

FIG. 6 is a diagram illustrating a degenerate model of the present invention.

FIG. 7 is a graph showing a discretely calculated voltage drop amount.

FIG. 8 is a graph showing the amount of change in emission current calculated discretely.

FIG. 9 is a diagram for explaining a method of calculating correction data according to the present invention.

FIG. 10 is a diagram showing an example of calculation of correction data when the size of image data is 128.

FIG. 11 is a diagram showing an example of calculation of correction data when the size of image data is 192.

FIG. 12 is a diagram for explaining a correction data interpolation method of the present invention.

FIG. 13 is a block diagram showing a schematic configuration of an image display device incorporating a correction circuit of the present invention.

FIG. 14 is a block diagram showing a configuration of a scanning circuit of the image display device of the present invention.

FIG. 15 is a block diagram showing a configuration of an inverse γ processing unit of the image display device of the present invention.

FIG. 16 is a diagram showing input / output characteristics of the inverse γ processing unit of the image display device of the present invention.

FIG. 17 is a block diagram showing a configuration of a data array conversion unit of the image display device of the present invention.

FIG. 18 is a diagram illustrating the configuration and operation of the modulation means of the image display device of the present invention.

FIG. 19 is a timing chart of the modulation means of the image display device of the present invention.

FIG. 20 is a block diagram showing a configuration of a correction data calculation unit of the image display device of the present invention.

FIG. 21 is a block diagram showing a configuration of a discrete correction data calculation unit of the image display device of the present invention.

FIG. 22 is a block diagram showing a configuration of a correction data interpolation unit of the present invention.

FIG. 23 is a block diagram showing a configuration of a linear approximation means of the present invention.

FIG. 24 is a flowchart of the device characteristic measuring operation of the present invention.

FIG. 25 is a timing chart of the image display device of the present invention.

FIG. 26 is a block diagram showing a configuration of a conventional image display device.

[Explanation of symbols]

1 Display panel 2 scanning circuit 4 Timing generation circuit 5 shift registers 6 latch 8 Pulse width modulation means 9 Data array converter 12 adder 14 Correction data calculation means 17 Reverse γ processing unit 19 Delay circuit 20 test pattern generator 21 Element parameter measurement control CPU 22,23 selector switch 100a-100d lighting number counting means 101a-101g register group 102 CPU 103 table memory 104 Temporary register 105 program memory 106 registers 107a-c comparator 108-110 adder 123-124 decoder 1001 substrate 1002 cold cathode device 1003 row wiring (scan wiring) 1004 Column wiring (modulation wiring) 1007 face plate 1008 fluorescent film

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 G09G 3/20 642P 670 670D 3/22 3/22 E H 3/30 3/30 K H01J 31/12 H01J 31/12 C (72) Inventor Naoto Abe 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (72) Yutaka Saito 3-30-2 Shimomaruko, Ota-ku, Tokyo Kya Non-Corporation (72) Inventor Takeshi Ikeda 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. F-term (reference) 5C036 EF06 EG47 EG48 5C080 AA06 BB05 BB10 DD05 EE29 JJ02 JJ04 JJ05 JJ06

Claims (26)

[Claims] 1. An image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings, and used for image formation, and a scanning unit for sequentially selecting and scanning the row wirings. Corrected image data calculating means for calculating corrected image data, in which the image data is corrected to compensate for a change in driving conditions for the image forming element due to electric resistance of the row wiring, and a modulation signal based on the corrected image data. And a correction means for outputting the corrected image data, the corrected image data calculation means generates the corrected image data for the input image data in one horizontal scanning period, and outputs the corrected image data according to the characteristics of the image forming element. An image display device characterized by updating calculation parameters for calculation. 2. The image display device according to claim 1, further comprising a measuring unit for measuring element characteristics of the image forming element, and updating the calculation parameter according to a change in the element characteristics. Image display device. 3. The image display device according to claim 2, wherein the measuring means measures the element current of the image forming element and updates the calculation parameter according to the change of the element current. 4. An image pattern output means for outputting a predetermined measurement image pattern, and a drive current measurement means for measuring a drive current when driven by the measurement image pattern. 3. The image display device according to claim 2, wherein the means updates the calculation parameter according to the drive current measured by the drive current measuring means. 5. The image display device according to claim 4, wherein the drive current measuring means is provided in the scanning means. 6. The image display device according to claim 4, wherein the drive current measuring means is provided in a modulating means. 7. The image display device according to claim 1, wherein the calculation parameters are updated when the power of the image display device is turned on. 8. The image display device according to claim 1, wherein the update of the calculation parameter is performed during a power-off operation of the image display device. 9. The image display device according to claim 1, wherein the calculation parameter is updated at an arbitrary time point requested by a user. 10. The image display device according to claim 1, wherein the modulation means is pulse width modulation means for modulating the pulse width of the pulse output from the modulation means based on the corrected image data. 11. The corrected image data calculation means is a voltage drop amount calculation means for predicting a voltage drop amount in a row wiring with respect to the input image data, and a luminance decrease amount due to a voltage drop from the voltage drop amount. 2. The image display according to claim 1, further comprising: a brightness decrease amount calculating unit for predicting the brightness reduction amount; and a correction amount calculating unit for calculating a correction amount for correcting the input image data from the brightness decrease amount. apparatus. 12. The voltage drop amount calculating means updates the element current, which is a calculation parameter used when calculating the voltage drop amount in the row wiring, in response to a change in the characteristic of the image forming element. The image display device according to claim 11, which is characterized in that. 13. The voltage drop amount calculating means sets a plurality of reference times during one horizontal scanning period corresponding to input image data, and sets a plurality of reference points along a selected row wiring, The image display device according to claim 12, wherein the amount of voltage drop at the reference point that should occur at the plurality of reference times is predicted and calculated. 14. The brightness decrease amount calculation means predictively calculates the horizontal position where the voltage drop amount calculation means calculates the voltage drop amount and the brightness decrease amount corresponding to a plurality of reference times. The image display device according to claim 12. 15. The correction amount calculating means calculates a plurality of discrete horizontal display of reference points from the luminance decrease amounts generated at the plurality of reference times at the plurality of reference points calculated by the luminance decrease amount calculating means. The image display device according to claim 12, wherein corrected image data for a plurality of preset image data values at a position is calculated. 16. The corrected image data calculating means interpolates the discrete corrected image data calculated by the correction amount calculating means,
16. The image display device according to claim 11, further comprising an interpolation circuit that calculates corrected image data corresponding to a size of input image data and a horizontal display position thereof. 17. The image display device according to claim 1, wherein the electron-emitting device is a cold cathode device. 18. The image display device according to claim 17, wherein the cold cathode device is a surface conduction electron-emitting device. 19. The image display device according to claim 17, wherein the cold cathode device is a field emission device. 20. The image display device according to claim 17, further comprising a fluorescent member that emits fluorescence when electrons emitted from the image forming element collide with each other. 21. The update of the calculation parameter is performed in a state where a high voltage is not applied.
0. Image display device 22. The image display device according to claim 1, wherein the image forming element is an EL element. 23. An image forming element arranged in a matrix, driven through a plurality of row wirings and column wirings, and used for image formation, wherein the row wirings are sequentially selected and scanned according to input image data. At the same time, a modulation signal is applied to the column wiring based on the input image data and the corrected image data that has been corrected by the electric resistance of the row wiring to compensate for the variation of the driving condition for the image forming element. An image display method of a display device for displaying an image, comprising: a correction image data calculation step of generating the correction image data for the input image data in one horizontal scanning period, the correction image data calculation step comprising: , Including a calculation parameter updating step of updating a calculation parameter for calculating the corrected image data according to the characteristics of the image forming element An image display method characterized by the above. 24. The calculation parameter updating step includes a step of detecting power-on, a step of outputting a predetermined measurement image pattern, and a step of measuring a drive current when driven by the measurement image pattern. The image display method according to claim 23, further comprising: updating the calculation parameter according to the measured drive current. 25. The calculation parameter updating step includes a step of detecting a power-off instruction, a step of stopping application of high voltage, a step of outputting a predetermined measurement image pattern, and a step of driving with the measurement image pattern. 24. The image display method according to claim 23, further comprising the step of measuring the drive current at the time, the step of updating the calculation parameter according to the measured drive current. 26. The calculation parameter updating step includes a step of detecting a parameter update instruction by a user, a step of stopping application of high voltage, a step of outputting a predetermined measurement image pattern, and a step of outputting the measurement image pattern. 24. The method according to claim 23, further comprising: a step of measuring a driving current when driven, a step of updating the calculation parameter according to the measured driving current, and a step of restarting application of high voltage. Image display method.