JP2003092362A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent leakage defect of a normal breakdown strength MOS transistor and a high breakdown strength MOS transistor made on the same semiconductor substrate. SOLUTION: This method is provided with a process for removing an etching damaged layer 11 which occurs in a source/drain formation region when dry- etching the first thick oxide film 9 of the high breakdown strength MOS transistor. SCI cleaning (RCA cleaning) is applied, and a silicon substrate 1 where the etching damaged layer 11 is made is etched by 10 Å-20 Å.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having two types of MOS transistors having different gate oxide film thicknesses on the same semiconductor substrate.

[0002]

2. Description of the Related Art For example, an LSI for driving a display device such as an LCD or an organic EL has a logic section which operates at a power supply voltage of 3V to 5V and a driver section which operates at a high power supply voltage of 15V to 45V. is doing. Some microcomputers also have an input terminal (for example, a test terminal) to which a voltage signal of about 15V is input.

In such an LSI, a high breakdown voltage MOS transistor which operates under the condition that a high power supply voltage is applied or a high voltage signal is input, has its gate oxide film formed in order to secure a gate withstand voltage. It must be formed thick. On the other hand, the normal withstand voltage MO that operates under the condition of low power supply voltage
In order to enable high speed operation and miniaturization of the S transistor, it is necessary to form a thin gate oxide film according to the scaling rule of the MOS transistor.

Therefore, in order to integrate such a driving LSI and a microcomputer into one chip, a high breakdown voltage MOS transistor and a normal breakdown voltage MOS transistor having different gate oxide films are integrated on the same semiconductor substrate.

Hereinafter, a method of manufacturing a semiconductor device according to a conventional example will be described with reference to FIGS.

First, as shown in FIG. 4, 120 n is formed on a P-type semiconductor substrate 1 (for example, a silicon substrate) by thermal oxidation.
A first oxide film 2 (SiO2 film) having a film thickness of m is formed.

Next, as shown in FIG.
The first oxide film 2 in the transistor formation region is selectively removed by using known photolithography. On the other hand, the first oxide film 2 is left in the adjacent high breakdown voltage MOS transistor formation region.

Next, as shown in FIG. 6, the second oxide film 3 is formed in the normal breakdown voltage MOS transistor formation region by thermal oxidation.
(SiO2 film) is formed. The second oxide film 3 is formed thinner than the first oxide film 2. The film thickness is, for example, 33n
It is about m. The first oxide film 2 is slightly thickened by this thermal oxidation process.

Next, as shown in FIG. 7, the LPCV is formed on the entire surface.
The polysilicon layer 4 is formed by the D method. The film thickness is, for example, about 440 nm. Instead of the polysilicon layer 4, an amorphous silicon layer may be formed.

Next, as shown in FIG. 8, a first photoresist layer 5 is formed on the polysilicon layer 4 in the formation region of the high breakdown voltage MOS transistor. The first photoresist layer 5 is a mask for forming a gate electrode when the polysilicon layer is etched later. Further, the first photoresist layer 6 is formed on the polysilicon layer 4 in the formation region of the normal breakdown voltage MOS transistor. This first photoresist layer 6 is a mask for forming a gate electrode used when etching a polysilicon layer later. Here, the first photoresist layer 5 is formed wider than the first photoresist layer 6. This is to increase the channel length of the high breakdown voltage MOS transistor and secure the source / drain breakdown voltage.

Next, as shown in FIG. 9, the polysilicon layer 4 is etched by using the first photoresist layers 5 and 6 as a mask, and the first gate electrode 7 of the high breakdown voltage MOS transistor and the normal breakdown voltage are formed. The second gate electrode 8 of the MOS transistor is formed.

Next, as shown in FIG.
In preparation for the ion implantation step for forming the drain layer, the first oxide film 2 is dry-etched. The film thickness of the residual film 2A after this dry etching is aimed at about 20 nm. As a result, a first gate oxide film 9 having a film thickness of 120 nm is formed under the first gate electrode 7. A second gate oxide film 10 having a film thickness of 33 nm is formed under the second gate electrode 8.

Next, as shown in FIG. 11, the first photoresist layers 5 and 6 are removed by a resist stripping solution.

Then, as shown in FIG. 12, an n − type source layer 12 and an n − type drain layer 13 are formed on the surface of the semiconductor substrate 1 adjacent to the first gate electrode 7 by low-concentration ion implantation. To do. Further, the n + type source layer 14 and the n + type drain layer 15 are formed on the surface of the semiconductor substrate 1 adjacent to the second gate electrode 8 by high-concentration ion implantation. At the same time, the n + type source layer 16 and the n + type drain layer 17 are formed on the surface of the semiconductor substrate 1 away from the first gate electrode 7.

Here, in the high breakdown voltage MOS transistor formation region, only the thin residual film 2A is formed except for the region where the first gate oxide film 9 is formed, so that the ion implantation is performed at low acceleration energy. Can be done by

As a result, a high breakdown voltage MOS transistor having the first gate oxide film 9 having a thickness of about 120 nm,
A normal breakdown voltage MOS transistor having a second gate oxide film 10 having a thin thickness of about 33 nm is formed.

[0017]

However, as a result of the study by the present inventor, the above-described method for manufacturing a semiconductor device has two drawbacks.

First, dry etching is used in the step of etching the first oxide film 2 shown in FIG. At this time, the second oxide film 3 having a thin thickness of 33 nm is used.
Since it is over-etched in the polysilicon etching step before that, most of it is etched and does not remain.

Therefore, while the first oxide film 2 is dry-etched, the source and
The drain formation region is exposed to etching plasma with the semiconductor substrate 1 exposed. Therefore, the etching damage layer 11 is formed on the surface of the source / drain formation region.
Is formed. As a result, the normal breakdown voltage MOS transistor has a problem that a leak failure occurs due to the influence of the etching damage layer 11.

Secondly, in the step of etching the first oxide film 2 shown in FIG. 10, the remaining film 2A of, for example, 20 nm is aimed as an etching end point. However, due to variations in etching, the semiconductor substrate 1 in the high breakdown voltage MOS transistor formation region is locally exposed, and an etching damage layer (not shown) is formed on the surface of the source / drain formation region. was there. Therefore, also in the high breakdown voltage MOS transistor, there is a problem that a crystal defect occurs in the source / drain layer and a leak defect is caused.

Therefore, an object of the present invention is to provide a normal withstand voltage MOS transistor in a semiconductor device having two types of MOS transistors having different gate oxide film thicknesses, that is, a high withstand voltage MOS transistor and a normal withstand voltage MOS transistor on the same semiconductor substrate. The purpose of this is to prevent a leak defect between a transistor and a high-voltage MOS transistor, improve reliability, and improve yield.

[0022]

The present invention has been made to solve the above-mentioned problems, and is characterized in that the first MOS having a different gate oxide film thickness on the same semiconductor substrate. In a method of manufacturing a semiconductor device including a transistor and a second MOS transistor, a step of forming a first oxide film in the first MOS transistor formation region, and a step of forming the first oxide film in the second MOS transistor formation region. Forming a second oxide film thinner than the oxide film of
Forming a silicon layer on the first and second oxide films; forming a photoresist layer on the gate electrode formation regions of the first and second MOS transistors;
Forming a first gate electrode of the first MOS transistor and a second gate electrode of the second MOS transistor by etching the silicon layer using the photoresist layer as a mask; A step of dry etching the first and second oxide films using the resist layer as a mask; and a step of removing the etching damage layer generated at least in the source / drain formation region of the second MOS transistor by the dry etching. A step of forming source / drain layers of the first and second MOS transistors by an ion implantation method.

Since the first oxide film to be the first gate oxide film is formed thick on the source / drain layer formation region,
It becomes an obstacle when forming the source / drain layer by the ion implantation method. That is, high acceleration energy is required for ions to penetrate the thick first oxide film and reach the semiconductor substrate. As a result, there are problems that the ion implantation is damaged and that an inexpensive low-acceleration ion implantation apparatus cannot be used.

Therefore, it is conceivable to etch the first oxide film thin to some extent.
Since the etching damage layer is formed on the surface of the source / drain formation region of the MOS transistor, the leak failure of the MOS transistor occurs.

Therefore, the present invention has solved the problem by introducing a step of removing the etching damage layer generated at least in the source / drain formation region of the second MOS transistor by dry etching.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a method of manufacturing a semiconductor device according to an embodiment of the semiconductor device of the present invention will be described with reference to FIGS. 4 to 10 and FIGS.

In the present embodiment, “a semiconductor substrate 1 (for example, a P-type silicon substrate) is thermally oxidized to 120 n
a step of forming a first oxide film 2 having a thickness of m (FIG.
From step 1) to "the step of dry etching the first oxide film 2 in preparation for the subsequent ion implantation step for forming the source / drain layer (shown in FIG. 10)" is the same as in the conventional example. The description is omitted.

In the embodiment of the present invention, the process shown in FIG. 10 is followed by the process shown in FIG. As described above, FIG.
By the dry etching step of the first oxide film 2 shown in FIG. 1, the source / drain formation region of the normally-withstanding voltage MOS transistor is etched while the semiconductor substrate 1 is exposed.
Exposed to plasma. Therefore, the etching damage layer 11 is formed on the surface of the source / drain formation region.

Further, due to the above-mentioned variation in dry etching, the semiconductor substrate 1 in the formation region of the high breakdown voltage MOS transistor is locally exposed, and an etching damage layer (not shown) is formed on the surface of the source / drain formation region. In some cases, even in a high breakdown voltage MOS transistor, a crystal defect occurs in the source / drain layer, resulting in a leak defect.

Therefore, it is decided to provide a process for removing the etching damage layer 11 (FIG. 1). Specifically, SC1 cleaning (RCA cleaning) at about 70 ° C. is performed, and the silicon substrate 1 on which the etching / damage layer 11 is formed is etched by 10Å to 20Å.
The time required for the SC1 cleaning treatment is about 5 minutes. Here, the SC1 cleaning is a cleaning process, but it is also a kind of wet etching. The composition of the SC1 cleaning solution is
For _{example, NH 4 OH: H 2 O} 2: H 2 O = 1: 1: 5~10
Is.

Another method for removing the etching damage layer 11 is a dry damage layer removing method using an oxide film dry etcher. This is a method of removing the etching damage layer 11 by dry etching using an oxide film dry etcher (for example, AME8310) and a mixed gas of nitrogen trifluoride gas (NF ₃ ) and argon gas (Ar). . According to the experiment, 20mT
Under pressure of -40 mT, nitrogen trifluoride gas (NF
₃ ) Flow rate of 5 to 20 sccm, argon gas (Ar)
It is preferable that the flow rate is 50 to 100 sccm.

It is also effective to combine the above-mentioned SC1 cleaning with the dry type damage layer removing method. That is, this is a method in which after the etching damage layer 11 is removed to some extent by the dry damage layer removal method, it is completely removed by SC1 cleaning.

If only the SC1 cleaning is performed, it may take a long processing time or the effect of removing the damaged layer may be insufficient. On the other hand, the dry type damage layer removal method has a short treatment time but may cause a new damage layer. Therefore, by combining these two, the processing time is relatively short and the damage can be reliably removed.

Next, as shown in FIG. 2, the first photoresist layers 5 and 6 are removed by a resist stripping solution.

Then, by the low concentration ion implantation, the first
On the surface of the semiconductor substrate 1 adjacent to the gate electrode 7 of
The type source layer 12 and the n− type drain layer 13 are formed.
Phosphorus is used as the ion species, and the implantation amount is 1 × 10 ¹³ / cm ² to 1 × 10 ¹⁴ / cm ^{2, although} it depends on the target breakdown voltage. As a result of etching the first oxide film 2, a low energy of, for example, 30 KeV to 70 KeV is sufficient as the ion acceleration energy.

Further, by the high-concentration ion implantation, the second
On the surface of the semiconductor substrate 1 adjacent to the gate electrode 8 of
The type source layer 14 and the n + type drain layer 15 are formed.
At the same time, the n + type source layer 16 and the n + drain layer 1 are formed on the surface of the semiconductor substrate 1 away from the first gate electrode 7.
Form 7.

Arsenic is used as the ion species, and the implantation amount is 1 × 1.
It is about 0 ¹⁵ / cm ² . The acceleration energy of the ions is, for example, 30 KeV as a result of etching the first oxide film 2.
Energy as low as ~ 80 KeV is sufficient.

Thus, the high breakdown voltage MOS transistor having the first gate oxide film 9 with a thickness of about 120 nm and 3
A normal voltage MOS transistor having a second gate oxide film 10 having a thin thickness of about 3 nm is formed.

Since this high voltage MOS transistor has a thick gate oxide film 9, it can withstand a gate voltage of about 30V. In addition, the n + type source layer 16 and the n +
An offset region is provided between the mold drain layer 17 and the first gate electrode 7, and n− is formed in the offset region.
Since the type source layer 12 and the n − type drain layer 13 are formed, high source breakdown voltage and drain breakdown voltage can be obtained.

However, the present invention is not limited to the method of manufacturing such a high breakdown voltage MOS transistor, and when only the gate breakdown voltage is required, the n-type source layer 12 and the n-type source layer 12 and
The n + type source layer 16 and the n + type drain layer 17 may be adjacent to the first gate electrode 7 without forming the − type drain layer 13.

Further, the normal voltage MOS transistor has the thin second gate oxide film 10 and is therefore suitable for speeding up, and also suitable for miniaturization by preventing the short channel effect. For miniaturization, so-called L
It is also possible to add a step of forming a DD structure.

[0042]

According to the method of manufacturing a semiconductor device of the present invention, a semiconductor having two types of MOS transistors having different gate oxide film thicknesses, that is, a high breakdown voltage MOS transistor and a normal breakdown voltage MOS transistor, on the same semiconductor substrate. In the device, it is possible to prevent leakage failure of the normal withstand voltage MOS transistor and the high withstand voltage MOS transistor, and improve reliability and yield.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the method of manufacturing a semiconductor device according to the embodiment of the present invention.

FIG. 3 is a cross-sectional view showing the method of manufacturing the semiconductor device according to the embodiment of the invention.

FIG. 4 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

FIG. 5 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

FIG. 6 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

FIG. 7 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

FIG. 8 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

FIG. 9 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

FIG. 10 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

FIG. 11 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

FIG. 12 is a cross-sectional view showing a method of manufacturing a semiconductor device according to a conventional example.

Claims (4)

[Claims] 1. A method of manufacturing a semiconductor device comprising a first MOS transistor and a second MOS transistor having different gate oxide film thicknesses on the same semiconductor substrate, wherein the first MOS transistor formation region is provided with a first MOS transistor. Forming an oxide film, forming a second oxide film thinner than the first oxide film in the second MOS transistor formation region, and forming a silicon layer on the first and second oxide films. A step of forming a photoresist layer on the gate electrode formation regions of the first and second MOS transistors, and etching the silicon layer using the photoresist layer as a mask, Forming a first gate electrode of a first MOS transistor and a second gate electrode of the second MOS transistor; and the photoresist. A dry etching of the first and second oxide films with the mask layer as a mask; and a step of removing the etching damage layer generated at least in the source / drain formation region of the second MOS transistor by the dry etching. And a step of forming the source / drain layers of the first and second MOS transistors by an ion implantation method. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the etching damage layer is a wet etching step. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the etching damage layer is a dry etching step. 4. The method of manufacturing a semiconductor device according to claim 1, wherein the step of removing the etching damage layer includes a dry etching step and a wet etching step.