JP2003015956A - Cache system having fault recovery function and cache control method for the system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a cache system and a cache control method therefor that, when a fault is detected during the execution of a microcode, achieve the improvement of instruction rewrite success rate by writing data contents executed with a microcode preceding the microcode in execution back into a cache memory, in a processor that unwinds an instruction code into the microcodes to execute it. SOLUTION: In the cache system in which a central processing unit 10 having a processor 13 of a system that unwinds the instruction code into the microcodes to execute it is connected to a main memory 20 through a system bus 30, a cache data save part 12 is provided, for constituting the cache system, that, when a fault is detected during the execution of the microcode with the processor 13, restores the microcode into the state immediately preceding the execution of the microcode by writing the write data that have been saved previously and is updated with the microcode preceding the microcode in execution back into the cache memory.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache system having a failure recovery function, and more particularly to a processor for expanding instruction code into microcode and executing the instruction code.
The present invention relates to a cache system that enables instruction retry when a failure is detected during microcode execution.

[0002]

2. Description of the Related Art Conventionally, as one of means for improving the availability of a processor, when a failure is detected during the operation of the processor, the execution of the instruction code is temporarily interrupted and the instruction code in which the failure is detected is re-executed. By doing so, a method of avoiding system down due to intermittent failure has been adopted.

On the other hand, recent high performance CISC (Comple
x Instruction Set Computer) type microprocessor, the instruction code fetched from memory or cache is decomposed into one or more simple microcodes inside the processor, and the pipeline is operated at high speed to improve performance. The method of seeking is becoming popular.

In such a microcode type processor, if a failure is detected during execution of a microcode sequence formed by expanding one instruction code, the microcode sequence is traced back for instruction retry. The sequence must be re-executed from the beginning, but this requires that the software visible registers and memory contents have not been updated (not destroyed) by the execution of the microcode sequence up to the point of failure. Is an essential condition.

[0005]

However, in the conventional microcode type processor described above, with respect to the instruction code which is usually used often, the contents of the memory and the register are updated while the expanded microcode is being executed. However, there is a problem that the retry success rate is low when a failure is detected during the execution of these instructions.

In order to solve the above-mentioned conventional problems, an object of the present invention is to develop a microcode which precedes the microcode when a failure is detected during microcode execution in a processor which expands and executes the instruction code into the microcode. (EN) A cache system and a cache control method therefor that improve the instruction retry success rate by writing back the data contents executed by a code to a cache memory.

[0007]

In order to achieve the above-mentioned object, the present invention connects a central processing unit having a processor for expanding an instruction code into a microcode and executing the instruction code through a main memory and a system bus. In the cache system, when a failure is detected during the execution of the microcode in the processor, the write data updated by the microcode preceding the previously saved microcode is written back to the cache memory, It is characterized in that a cache data saving unit for restoring the state immediately before the execution of the microcode is provided.

According to another aspect of the cache system of the present invention, the cache data saving unit stores the write data, and a cache data saving control circuit for controlling the saving operation of the write data and the write back to the cache memory. It is characterized in that it is provided with a save data storage means.

According to another aspect of the cache system of the present invention, it is determined whether a write address, which is a part of the write data, is stored in the cache data saving unit, and the result is sent to the cache data saving control circuit as a signal. It is characterized by including an address comparator for transmitting.

According to another aspect of the cache system of the present invention, it is determined whether a write address that is a part of the write data is stored in the cache data saving unit, and the result is sent to the cache data saving control circuit as a signal. When an address comparator for transmitting, an address register for storing a write address that is part of the write data, and the address comparator determines that the write address is not stored in the cache data saving unit, It is characterized in that a write address storage means for storing the write address is provided.

According to a fifth aspect of the cache system of the present invention, the save data storage means is composed of a save data array, and the write address storage means is composed of a write address array.

According to a sixth aspect of the cache system of the present invention, each of the save data storage means and the write address storage means comprises a single register.

According to a seventh aspect of the cache control method of the present invention, there is provided a cache system in which a central processing unit having a processor for expanding an instruction code into a microcode and executing the code is connected via a main memory and a system bus. In the cache control method, when a failure is detected during the execution of the microcode in the processor, the write data updated by the microcode preceding the previously saved microcode is written back to the cache memory, It is characterized in that the state immediately before the execution of the microcode is restored.

The cache control method of the present invention according to claim 8 comprises the steps of controlling the save operation of the write data and the write back to the cache memory, and the step of storing the write data in the save data storage means. It is characterized by

According to a ninth aspect of the cache control method of the present invention, it is determined whether a write address, which is a part of the write data, is stored in the cache data saving unit, and the result is used as a signal for the cache data saving control circuit. It is characterized by comprising a step of transmitting to.

According to a tenth aspect of the cache control method of the present invention, a step of storing a write address which is a part of the write data in an address register, and the write address in the cache data saving section in the address comparator. When it is determined that the write address is not stored, a step of storing the write address in the write address storage means is provided.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a cache system according to the first embodiment of the present invention.

The cache system according to the first embodiment of the present invention comprises a central processing unit 10, a main memory 20, and a system bus 30 connecting them. In FIG. 1, four sets of central processing units 10 are connected to the system bus 30 (10-1 to 10-4), but the system bus 3
The number of central processing units 10 connected to 0 is arbitrary (1
0-m: m is a natural number). Similarly, although one set of the main memory 20 is connected to the system bus 30 in FIG. 1, (20-1),
The number of main memories 20 connected to the system bus 30 is arbitrary (20-n: n is a natural number).

The central processing unit 10 comprises a cache memory 11 of a store-in system, a cache data saving unit 12, and a processor 13 of a system which develops an instruction code into microcode and executes it. Both the processor 13 and the cache data saving unit 12 are the cache memory 1
1 and the cache memory 11 is further connected to the system bus 30.

FIG. 2 is a diagram showing the configurations of the cache memory 11 and the cache data saving unit 12 according to the first embodiment of the present invention.

The cache memory 11 comprises an address array 111, a data array 112, and a cache control circuit 113.

The address array 111 is a memory composed of a plurality of entries, and each entry has a part of the address (address key) that is referred to during cache indexing.
And a valid bit indicating that the data is valid as auxiliary information of the corresponding entry, and a status bit indicating the status of the data in the store-in cache.

The data array 112 is the address array 11
This is a memory composed of a plurality of entries similar to 1, and stores data in each entry.

The cache control circuit 113 is a logic circuit for controlling the operation of the cache memory 11, and has a control function for indexing and data registration in the address array 111 and the data array 112, as well as the system bus 30, the processor 13, and the cache data save. It has an interface function with the unit 12.

The cache data saving unit 12 includes an address register 121, a write address array 122, an address comparator 123, and a cache data saving control circuit 12.
4 and the save data array 125.

The address register 121 is a register for storing the write address sent from the cache control circuit 113 and the information of the status bit of the cache during the write operation to the cache. Address register 121
The write address and the status bit stored in are written to the write address array 122 and the address comparator 123.

The write address array 122 is a memory composed of a plurality of entries, and stores the write address and status bit information output from the address register 121 under the control of the cache data save control circuit 124.

The address comparator 123 is a comparison circuit for comparing the write address stored in the address register 121 with the address stored in each entry of the write address array 122. The result of comparing them is notified to the cache data save control circuit 124 as a signal indicating a match / mismatch.

The cache data save control circuit 124 is
It is a control circuit that controls the operation of the cache data saving unit 12. In particular, the retry-disabled flag 1241 shown in FIG.
This is a flag indicating that it is impossible to execute an instruction retry when a failure occurs in the processor 13, based on the cache data saved by the cache data saving unit 12.

The save data array 125 is a memory composed of a plurality of entries like the write address array 122, stores the data fetched from the data array 112, and sends the fetched data to the cache control circuit 113. .

Next, the operation of the cache system according to the first embodiment of the present invention will be described with reference to FIG.

First, the operation of the cache data save control circuit 124 when the checkpoint signal 200 is received from the processor 13 will be described.

The checkpoint signal 200 is a signal sent when the processor 13 completes the execution of the final instruction of the microcode expanded from one instruction code. In the processor 13, one instruction code is expanded into a sequence of one or more microcodes and executed. As an example thereof, FIG. 3 is a diagram for explaining that the instruction code (MOV) taken in by the processor 13 is expanded into 10 microcodes.

Here, the instruction code MOV is an instruction to copy a character string of length L1 word from the address X on the memory to an area starting from the address Y. Referring to the expanded microcode, microinstruction lod is a register-to-register or memory-to-register load instruction, sto is a register-to-memory write instruction, add is an register-to-register addition instruction, and sub is a register-to-register division instruction. bra represents a branch instruction, and endf represents an instruction indicating the end of a series of microcodes and instructing fetching of a subsequent instruction code.

First, X, Y, L1 are work registers w0,
copied to w1 and w2 respectively (steps 301, 3
02, 303), then 1 via work register w4
It can be seen that the word copy is performed (steps 304 and 305), the address and the counter stored in the work register are updated (steps 306, 307 and 308), and the loop is executed until the copy is completed (step 309). In the actual implementation, the endf added at the end (step 310) may not be defined as an instruction that particularly indicates the end by adding it as bit information to the final instruction of the microcode sequence for the sake of speedup.
Here, it is provided specifically for ease of explanation.

FIG. 4 is a flow chart for explaining the operation of the cache data save control circuit 124 when the checkpoint signal 200 is received from the processor 13 in the first embodiment of the present invention. The cache data save control circuit 124 uses the checkpoint signal 2
When 00 is received (step 401), all the entries registered in the write address array 122 are reset and the retry impossible flag 1241 is reset (step 402).

Next, the cache read operation from the processor 13 will be described in detail with reference to FIG.
FIG. 5 is a flowchart for explaining the cache read operation from the processor 13 in the first embodiment of the present invention.

When the cache read request is sent from the processor 13, the request signal 201 is input to the cache control circuit 113 together with the read address (step 501). Then, the cache control circuit 113 supplies an index address consisting of a part of the read address to the address array 111 and the data array 112, thereby fetching the address key from the address array 111 and the data from the data array 112 to cause a cache hit. (Step 50)
2).

If there is a cache hit here, the data fetched from the data array 112 is processed by the processor 13
(Step 503) and the read operation is completed.

On the other hand, if there is a cache miss, the cache control circuit 113 determines the entry to be replaced (step 504), refers to the value of the status bit of the entry, and flushes to the memory if it is dirty. . After that, the cache control circuit 113 reads the data of the address from the main memory 20 via the system bus 30 (step 505), and outputs the address key, the valid bit and the status bit to the address array 111 and the data to the data array 112. Is registered (step 506). At this time, the status bit is registered in the clean state. Then, by sending the data to the processor 13 (step 503), the read operation is completed.

In the case of the read operation, the operation of the cache data saving unit 12 is not performed.

Next, the cache write operation from the processor 13 will be described in detail with reference to FIGS. 6 and 7. FIG. 6 is a flowchart for explaining the operation of the cache memory 11 at the time of the cache write operation from the processor 13 in the first embodiment of the present invention, and FIG. 7 is the flowchart of the first embodiment of the present invention. 7 is a flowchart illustrating an operation of the cache data saving unit 12 during a cache write operation from the processor 13.

When a cache write request is sent from the processor 13, the request signal 202 indicates the write address and write data together with the cache control circuit 113.
Is input (step 601). Subsequently, the cache control circuit 113 retrieves data from the data array 112, indexes the address array 111, and determines whether the data at the address hits the cache (step 602).

In the case of a cache hit, the cache control circuit 113 completes the write operation by overwriting the write data on the data fetched at the time of indexing and registering it in the cache (step 603). Also, if the status bit of the entry is in the clean state in the read before the writing, it is updated to the dirty state.

In the case of a cache miss, the cache control circuit 113 determines the entry to be replaced (step 604), refers to the value of the status bit of the entry, and flushes to the memory if it is the dirty state. After that, the data of the address is read from the main memory 20 via the system bus 30 (step 605),
The write operation is completed by overwriting the read data with the write data from the processor 13 and registering it in the cache (step 606). At this time, the status bit of the corresponding entry in the cache is registered in the dirty status.

When writing from the processor 13,
The cache data saving unit 12 performs the following operations.

First, when the write data is overwritten in the address array 111 and the data array 112 (steps 603 and 606 in FIG. 6), the cache control circuit 113 sets the write address and the value of the status bit extracted in the read before the write. The cache control circuit 1 stores the data from the main memory 20 via the system bus 30 when the data is stored in the address register 121 from
13 and stores it in the save data array 125 (step 701). Then, in the address comparator 123, the same entry as the write address stored in the address register 121 is written in the write address array 12
It is determined whether or not it is registered in No. 2 (step 702).

When the entry having the same address as the write address stored in the address register 121 is registered in the write address array 122, the operation of the cache data saving unit 12 ends here.

When the entry having the same address as the write address stored in the address register 121 is not registered in the write address array 122, the write address stored in the address register 121 is controlled by the cache data save control circuit 124. And the status bits are stored in the write address array 122 (step 703).

Next, the operation of the cache system when a cache invalidation request is received from another cache memory via the system bus 30 will be described in detail with reference to FIG. FIG. 8 is a flowchart illustrating an operation of the cache system when a cache invalidation request is received from another cache memory via the system bus 30 according to the first embodiment of this invention.

First, the cache control circuit 113 indexes the address array 111 with the address requested to be invalidated (step 801) and determines whether or not there is a cache hit. If there is a hit, address array 1
11. The valid bit of the entry of 11 is reset to invalidate the data of the entry (step 802).

Further, regardless of the cache hit or miss, the address for which invalidation is requested is sent from the cache control circuit 113 to the address register 121, and the save data invalidation signal 203 is sent to the cache data save control circuit 124. Sent out (step 80)
3).

Upon receiving the save data invalidation signal 203, the cache data save control circuit 124 determines whether the entry of the address requested to be invalidated by the output of the address comparator 123 is registered in the write address array 122. (Step 804), if the entry of the address is registered, retry impossible flag 1
241 is set (step 805), and the processor 13
Indicates that the instruction retry cannot be executed when a failure is detected in the microcode sequence currently being executed.

Next, the operation of the cache system when the processor 13 detects a failure during microcode execution will be described in detail with reference to FIG. FIG. 9 is a flowchart illustrating the operation of the cache system when the processor 13 detects a failure during microcode execution in the first embodiment of the present invention.

When the processor 13 detects a failure during microcode execution, the processor 13 sends a failure detection signal 2
The cache control circuit 113 detects that a failure is detected in 04.
And the cache data save control circuit 124 is notified (step 901).

The cache data saving control circuit 124
When the failure detection signal 204 is received, the retry impossible flag 1241 is first referenced to confirm that the flag is reset (step 902).

When the flag is set, the sequence of the microcode operating in the processor 13 cannot be retried, so the cache data saving unit 12 stops the operation at that time, and the cache memory 11 and the processor are stopped. The operation of 13 is also stopped (step 906).

If the flag has been reset, the cache data save control circuit 124 sequentially refers to each entry of the write address array 122, extracts the registered address and status bit, and fetches them from the cache control circuit 113.
At the same time, the registered data is fetched from the save data array 125 and sent to the cache control circuit 113 (step 903).

The cache control circuit 113 determines an address key, a status bit, and an entry in which data should be registered in the address array 111 and the data array 112 based on the sent address (step 904) and overwrites them. The state immediately before the processor 13 starts executing the microcode sequence in which the failure is detected is restored (step 905).

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. Since the configuration of the entire cache system is the same as that of the first embodiment shown in FIG. 1, its explanation is omitted.

FIG. 10 shows a cache memory 11 and a cache data saving unit 12 according to the second embodiment of the present invention.
It is a figure which shows the structure of.

The second embodiment of the present invention is configured by replacing the write address array 122 and the save data array 125 of the first embodiment with a write address register 126 and a save data register 127, respectively. The operation of the cache memory 11 and the cache data saving unit 12 as a whole is the same as that of the first embodiment, and therefore its explanation is omitted.

As shown in FIG. 10, by replacing the write address array 122 and the save data array 125, which are memories composed of a plurality of entries, with a single register, the cache data save unit 1
Although the amount of hardware to be added to 2 can be reduced as much as possible, if two or more write operations occur in the microcode sequence in which one instruction code is expanded,
In this embodiment, there is also a problem that the repair by the instruction retry cannot be performed.

However, with respect to an instruction that uses only one write instruction in the microcode sequence, it can be relieved by instruction retry as in the first embodiment, and an investment is made with a relief rate at the time of failure detection. It can be said that the present embodiment is sufficiently practical from the viewpoint of the trade-off of the amount of hardware.

Although the present invention has been described with reference to the preferred embodiments and examples, the present invention is not necessarily limited to the above-described embodiments and examples, and various modifications are possible within the scope of the technical idea. It can be implemented by modifying the above.

[0067]

As described above, according to the cache system of the present invention, in the processor of the type in which the instruction code is expanded into the microcode and executed, when a failure is detected during the execution of the microcode, the instruction code unit is used. Retry is possible.

The reason is that even after the state of the cache has been changed by writing in the microcode sequence, the data saved in the save data array is written back to the cache memory to the state before the execution of the microcode sequence. This is because it is possible to return the cache status.

Further, by replacing the write address array and the save data array with the write address register and the save data register, which are respectively a single register, the amount of hardware added to the cache data save unit can be minimized. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a cache system according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a cache memory and a cache data saving unit according to the first embodiment of the present invention.

FIG. 3 is a diagram illustrating an example in which the processor according to the first embodiment of the present invention expands an instruction code into microcode.

FIG. 4 is a flowchart illustrating an operation of the cache data save control circuit when a checkpoint signal is received from the processor according to the first embodiment of the present invention.

FIG. 5 is a flowchart illustrating an operation of the cache memory during an operation of reading a cache from a processor according to the first embodiment of the present invention.

FIG. 6 is a flowchart illustrating an operation of the cache memory at the time of the cache write operation from the processor in the first embodiment of the present invention.

FIG. 7 is a flowchart illustrating an operation of a cache data saving unit during a cache write operation from a processor in the first embodiment of the present invention.

FIG. 8 is a flowchart illustrating an operation of the cache system when a cache invalidation request is received from another cache memory via the system bus according to the first embodiment of this invention.

FIG. 9 is a flowchart illustrating an operation of the cache system when a processor detects a failure during execution of microcode in the first embodiment of the present invention.

FIG. 10 is a diagram showing configurations of a cache memory and a cache data saving unit according to a second embodiment of the present invention.

[Explanation of symbols]

10 Central processing unit 11 cache memory 12 Cash data saving unit 13 processors 20 main memory 30 system bus 111 address array 112 data array 113 cache control circuit 121 Address register 122 write address array 123 Address comparator 124 Cache data save control circuit 125 save data array 126 Write Address Register 127 Save data register 200 checkpoint signals 201 Cache read request signal 202 cache write request signal 203 Saved data invalidation signal 204 Fault detection signal 1241 Retry impossible flag

Claims (10)

[Claims] 1. A cache system in which a central processing unit having a processor for expanding an instruction code into microcode and executing the code is connected to a main memory via a system bus, wherein the microprocessor is executing the microcode. When a failure is detected, the write data updated by the microcode preceding the previously saved microcode is written back to the cache memory,
A cache system comprising a cache data saving unit for restoring the state immediately before the execution of the microcode. 2. The cache data saving unit includes a cache data saving control circuit for controlling a saving operation of the write data and a write back to the cache memory, and a save data storage unit for storing the write data. The cache system according to claim 1, wherein: 3. An address comparator for determining whether a write address, which is a part of the write data, is stored in the cache data saving unit, and transmitting the result as a signal to the cache data saving control circuit. The cache system according to claim 2, wherein: 4. The address comparator, which determines whether a write address, which is a part of the write data, is stored in the cache data save unit, and sends the result as a signal to the cache data save control circuit. An address register that stores a write address that is part of the write data, and a write address that stores the write address when the address comparator determines that the write address is not stored in the cache data saving unit. The cache system according to claim 2, further comprising storage means. 5. The backup data storage means is composed of a backup data array, and the write address storage means is composed of a write address array.
The cache system described in. 6. The cache system according to claim 4, wherein each of the save data storage means and the write address storage means comprises a single register. 7. A cache control method for a cache system in which a central processing unit having a processor for expanding an instruction code into microcode and executing the code is connected via a main memory and a system bus. When a failure is detected during execution of, the write data updated by the microcode preceding the previously saved microcode is written back to the cache memory,
A cache control method for a cache system, wherein the microcode is restored to a state immediately before execution. 8. The method according to claim 7, further comprising: a step of controlling a save operation of the write data and a write back to the cache memory; and a step of storing the write data in a save data storage means. Cache control method for a cache system of a computer. 9. The method comprises: determining whether a write address, which is a part of the write data, is stored in the cache data save unit, and transmitting the result as a signal to the cache data save control circuit. The cache control method for a cache system according to claim 8. 10. A step of storing a write address, which is a part of the write data, in an address register; and when the address comparator determines that the write address is not stored in the cache data saving section. 10. The cache system according to claim 9, further comprising the step of storing the write address in a write address storage means.