JP2003008669A - Signal transmission circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To approach a signal level transmitted with interference control resistance inserted into a signal transmission circuit to a voltage in between a power- supply voltage and a ground potential to decrease the reliability of transmission. SOLUTION: A pulldown transistor 5 is connected between a transmission line 8 and the ground potential for transmission signals that belongs to a L level. A first signal production circuit 41 is provided to produce a first signal 5a that is used to turn on a pulldown transistor 5 by catching the transmission signals. The pulldown transistor 5 is turned on with the timing of sending the transmission signals from the first signal 5a. Thereby, the voltage of the transmission line 8 becomes 0 V even it is in the middle level of the transmission signals.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a bidirectional signal transmission circuit for exchanging signals between a plurality of devices or circuits, and more particularly, to an unstable operation under the influence of transmitted signals. Not related to a stable signal transmission circuit.

[0002]

2. Description of the Related Art FIG. 13 shows a typical conventional bidirectional signal transmission circuit (hereinafter referred to as a signal transmission circuit) used for a bus line or the like. An example will be described in which signals are exchanged between circuits. In the figure, 1 is a sending side IC (signal transmission device) having a signal sending / receiving circuit, 2 is a receiving circuit inside the sending side IC 1, 3 is a transmitting transistor inside the sending side IC 1, and 4 is a sending / receiving port (hereinafter referred to as port 4). ).
Reference numeral 11 is a receiving side IC (signal transmission device) having a signal transmitting / receiving circuit, 12 is a receiving circuit inside the receiving side IC 11, 13 is a transmitting transistor inside the receiving side IC 11, and 10 is a transmitting / receiving port (hereinafter referred to as port 10). . Reference numeral 15 is a third IC (signal transmission device) dedicated to reception, and has a reception circuit (not denoted by reference numeral) and a reception port 14 (hereinafter port 14). Reference numeral 6 is a power supply line having a voltage level of Vcc. 8
Is a transmission line connecting the ports 4, 14 and 10, and 7 is a pull-up resistor for applying a bias voltage to the transmission line 8, which is connected between the power supply line 6 and the transmission line 8. Reference numeral 9 is an interference suppression resistor, which is inserted between the transmission line 8 and the port 10 of the receiving side IC 11. The number of signal transmission devices is not limited to three as shown in FIG. 13, and more may be connected.

Next, the operation of the circuit of FIG. 13 will be described with reference to FIG. 14 showing the signal waveform of the transmission line 8. First, on the premise of understanding the circuit operation, such a signal transmission circuit transmits / receives a signal in synchronization with a clock pulse signal as indicated by 30 in FIG. Here, the clock 30 is L
It is assumed that a signal is transmitted and received at a timing (described in the figure). When the transmission signal is not transmitted from either the sending side IC1 or the receiving side IC11, both the sending transistor 3 of the sending side IC1 and the sending transistor 13 of the receiving side IC11 are OFF, so that the port 4 and the port 1
0 is an open state. The voltage Vcc is supplied to the transmission line 8 through the pull-up resistor 7.

Here, the transmitting transistor 3 of the sending side IC1
Is turned on at a certain timing of the clock 30, and the signal 21
Is transmitted, the voltage of the transmission line 8 becomes almost 0 V (level L) as indicated by 21 in FIG. Then, the above-mentioned signal 21 is transmitted to the port 10 of the receiving side IC 11 and the port 14 of the third IC 15, and is surely transmitted as an L bell.

Next, when receiving the above-mentioned signal 21, the receiving side I is set after a predetermined time (time of a predetermined number of clocks).
If it is determined that C11 returns the signal 22, the transmitting transistor 3 of the sending side IC1 turns off and the transmitting signal 21 disappears, and then the transmitting transistor 13 of the receiving side IC11 turns on at the timing of the reply. The signal 22 is output. However, since the interference suppression resistor 9 is inserted in the transmission line 8, the voltage level of the transmission line 8 cannot be completely lowered to 0V, and L level = Vcc × (resistor 9) / {(resistor 7) + ( Resistance 9)} (1), which results in an intermediate voltage (Lm in FIG. 14).

The receiving circuits 2, 12 and 14 are designed to have a predetermined dead zone in order to avoid malfunction due to a little noise or the like.
If the signal is not (low), it is not recognized as an H / (L) signal with certainty, and the reliability is low in the dead region. The dead area is shown as a level range 20 in FIG. 20a or more is the H recognition range, and 20b or less is the L recognition range. As is clear from the above equation (1), the L-level reply signal 22 transmitted from the receiving IC 11 becomes even higher than Lm shown in FIG. It does not have to cover the area 20. Therefore,
In order to bring the L-level signal 22 of the reply signal closer to 0 V, the resistance 7 should be as large as possible and the resistance 9 should be calculated from the equation (1).
Needs to be as small as possible. That is, the resistor 9
When is increased, the signal level Lm reaches the dead area 20 described above and is not recognized as an L signal.

As described above, it is desirable that the pull-up resistor 7 is larger and the interference suppressing resistor 9 is smaller, but the resistance value of the interference suppressing resistor 9 is determined to be as large as possible for the purpose of suppressing interference. There is a need. If it malfunctions due to interference, the function of the circuit cannot be achieved. Therefore, the signal level (L) from the receiving IC is in the dead region 20.
However, there is a problem in that the reliability of signal transmission may be lowered when the signal is approached, and on the other hand, interference may not be suppressed.

[0008]

In the conventional signal transmission circuit, from the viewpoint of interference suppression, an interference suppression resistor must be inserted in the transmission line. Therefore, when there is a reply signal from the receiving IC, the transmission line However, there is a problem that the signal level becomes halfway and it is difficult to determine H or L, and a transmission error is likely to occur. Also, I want to make the resistance value of the interference suppression resistor as large as possible for the purpose of suppressing interference,
If it is set too high, the signal level Lm reaches the dead zone,
There is a problem that the signal cannot be increased because it is not recognized as an L signal and the reliability of signal transmission decreases.

The present invention can solve the above problems and increase the interference suppressing resistance, and further, the receiving side I
It is an object of the present invention to obtain a signal transmission circuit which does not malfunction even if the level of the L signal from C is not sufficiently low, thereby improving the transmission error rate.

[0010]

A signal transmission circuit according to the present invention has a transmission / reception port for inputting / outputting a transmission signal and a transmission signal transmission / reception circuit connected to the transmission / reception port, and is synchronized with a predetermined clock pulse. A signal transmission device for transmitting and receiving a transmission signal by a transmission line, a transmission line connecting the transmission / reception ports of the plurality of signal transmission devices via an interference suppression resistor and a transmission line connected to a power supply circuit via a pull-up resistor, the plurality of signals A first signal generation circuit that outputs one of the first signals based on a transmission signal output to the transmission line by one of the transmission devices, and the first signal that is connected between the transmission line and ground. Thus, the first switching element for bringing the voltage level of the transmission line close to the voltage level of the ground is provided.

Further, the first signal generating circuit synchronizes with the transmission signal output to the transmission line by the signal transmission device, or a time corresponding to a predetermined number of clock pulses from the timing of the transmission signal. The first signal is output with a delay.

Further, the first signal generation circuit is a one-shot multi-circuit which is inverted by the transmission signal output from the signal transmission device to the transmission line as a trigger and is restored after a time corresponding to one pulse of the clock pulse. It includes a vibrator.

Further, the first signal generation circuit predicts the timing at which the reply signal is output from the timing of the transmission signal output to the transmission line by any one of the plurality of signal transmission devices, and this estimation is performed. Based on the first
The signal of is output.

Further, a plurality of signal transmission devices each having a transmission / reception port for inputting / outputting a transmission signal and a transmission signal transmission / reception circuit connected to the transmission / reception port, for transmitting / receiving the transmission signal in synchronization with a predetermined clock pulse. A transmission line connected between the transmission / reception ports of the signal transmission device via an interference suppression resistor and connected to a power supply circuit via a pull-up resistor, and one of the plurality of signal transmission devices connected to the transmission line. The second signal is output based on the output transmission signal.
A second signal generating circuit for outputting a signal of the second transmission line, the second signal generation circuit being connected between the transmission line and the power supply circuit, and making the voltage level of the transmission line close to the voltage level of the power supply circuit by the second signal. It is equipped with a switching element.

The second signal generating circuit is synchronized with the timing of the transmission signal output to the transmission line by the signal transmission device, or corresponds to a predetermined number of clock pulses from the timing of the transmission signal. The second signal is output with a time delay.

The second signal generation circuit inverts the timing of the transmission signal output to the transmission line as a trigger and recovers after a time corresponding to a predetermined pulse of the clock pulse. Is included.

Further, the second signal generation circuit predicts the timing at which the reply signal is output from the timing of the transmission signal output to the transmission line by any one of the plurality of signal transmission devices, and this estimation is performed. Based on the second
The signal of is output.

Further, a sending side signal transmission device having a transmission / reception port for inputting / outputting a transmission signal and a transmission signal transmission / reception circuit connected to the transmission / reception port, for transmitting / receiving the transmission signal in synchronization with a predetermined clock pulse, Receiving side signal transmitting device having a transmitting / receiving port for inputting / outputting a transmitting signal and a transmitting signal transmitting / receiving circuit connected to the transmitting / receiving port, transmitting / receiving the transmitting signal in synchronization with a predetermined clock pulse, and the transmitting side signal transmission While turning off in synchronization with either the transmission signal output by the device or the transmission signal output by the receiving-side signal transmission device, both the sending-side signal transmission device and the receiving-side signal transmission device output the transmission signal. A third signal generating circuit which outputs a third signal which is turned on when not outputting,
A series connection body of a third switching element driven by the third signal and an interference suppression resistor is provided between the transmission / reception port of the transmission side signal transmission device and the transmission signal reception port of the reception side signal transmission device. And a transmission line connected to the power supply circuit via a pull-up resistor.

The third signal generation circuit may be synchronized with the transmission signal output to the transmission line by the sending side or receiving side signal transmission device, or may be the clock pulse from the transmission signal output to the transmission line. The third signal is output with a time delay corresponding to the predetermined number of pulses.

Further, the third signal generating circuit is a one-shot multi-circuit which is inverted after the transmission signal output from the signal transmission device to the transmission line as a trigger and is restored after a time corresponding to one pulse of the clock pulse. It includes a vibrator.

Further, the third signal generation circuit predicts the timing at which the reply signal is output from the timing of the transmission signal output to the transmission line by any one of the plurality of signal transmission devices, and the prediction is performed. Based on the third
The signal of is output.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiment 1. The signal transmission circuit according to the first embodiment of the present invention ensures that the L level of the transmission signal from the receiving IC is 0 V regardless of the value of the resistance in the circuit.
The configuration is shown in FIG. In addition,
Regarding the reference numerals in the drawings, the same reference numerals as those in the conventional drawings indicate the same or corresponding portions, and thus detailed description thereof will be omitted. In the figure, 1 is a sending side IC (signal transmission device) having a signal transmitting / receiving circuit, 2 is a receiving circuit inside the sending side IC 1, 3 is a transmitting transistor inside the sending side IC 1, 4
Is a transmission / reception port (hereinafter referred to as port 4). The reception circuit 2 and the transmission transistor 4 together constitute a transmission signal transmission / reception circuit according to the present invention.

Reference numeral 11 denotes a receiving side IC having a signal transmitting / receiving circuit.
(Signal transmission equipment), 12 is a receiving circuit inside the receiving side IC 11, 13 is a transmitting transistor inside the receiving side IC, 10
Is a transmission / reception port (hereinafter referred to as port 10). The reception circuit 11 and the transmission transistor 13 together constitute a transmission signal transmission / reception circuit according to the present invention. Reference numeral 15 is a third IC dedicated to reception, and has a reception circuit (no reference numeral is attached) and a reception port 14 (hereinafter port 14). Reference numeral 6 is a power supply line having a voltage level of Vcc. 8 is port 4 and port 14
A transmission line 7, which connects the port 10 and the port 10, is a pull-up resistor for applying a bias voltage to the transmission line 8 and is connected between the power supply line 6 and the transmission line 8. Reference numeral 9 is an interference suppression resistor, which is inserted between the transmission line 8 and the port 10. R is the equivalent input resistance of all the receiving circuits.

5 is a transmission line 8 and a 0V line (ground)
A transistor (first switching element) inserted between and is referred to as a pull-down transistor for convenience of description below. When the pull-down transistor 5 is turned on, the voltage level of the transmission line 8 can be brought close to 0V regardless of the values of the resistors 7 and 9. Reference numeral 5a is a first signal transmitted to the base of the pull-down transistor 5, the contents of which will be described with reference to the signal waveform diagram of FIG.

Next, the operation will be described. First, when no signal is transmitted from either the sending side IC1 or the receiving side IC, the transmission transistor 3 of the sending side IC1 is turned off.
Therefore, the port 4 is open. Therefore, the voltage Vcc is supplied through the pull-up resistor 7, and the voltage of the transmission line 8 is at a level close to Vcc, as indicated by 26 in FIG. When the transmission transistor 3 of the IC 1 on the sending side is turned on to transmit the signal 21, the voltage of the transmission line 8 becomes almost 0 V (level L) as indicated by 21 in FIG. Since the receiving circuits 2, 12 and 15 are designed to have a predetermined dead area 20, they cannot be reliably recognized as the (L) signal unless they are signals of a certain level or lower. 20a is an H recognition level and 20b is an L recognition level. Then, with the port 10 of the receiving IC 11,
This signal is transmitted to the port 14 of the third IC 15 and is reliably transmitted as an L bell.

Next, after receiving the above-mentioned signal 21, the receiving IC 11 outputs the signal 22 after a predetermined time (shown in FIG. 28).
Suppose that it is decided to reply
After the transmission transistor 3 of No. 1 is turned off and the transmission signal 21 disappears, the transmission transistor 13 of the receiving side IC 11 is turned on and the signal 22 is output at the timing of reply. Since the interference suppression resistor 9 is inserted in the transmission line 8,
The voltage level of the transmission line 8 does not completely drop to 0V, and as shown in the conventional expression (1), L level = Vcc × (resistor 9) / (resistor 7 + resistor 9) ... (1 ) Is an intermediate voltage (22 in FIG. 2).

At this time, that is, when the transmission signal 22 is output from the receiving IC 11 and the voltage of the transmission line 8 reaches a halfway value 22, a signal for driving the pull-down transistor 5 to ON is given. This is the first signal 5a
Call. A specific circuit for extracting the first signal 5a will be described in the fourth embodiment. The pull-down transistor 5 is turned on by the first signal 5a, and the level of the transmission line 8 is lowered to 0V as indicated by 27 in FIG.

By the pull-down transistor 5, regardless of the resistance values of the interference suppression resistor 9 and the pull-up resistor 7,
Since the L signal level of the transmission line 8 is lowered to 0V and the operations of the sending side IC1 and the third IC 15 are stabilized, the resistance value of the jamming suppression resistor 9 reduces the jamming without fearing that the L level becomes unstable. It is possible to prioritize and decide the purpose to do. As a result of increasing the value of the resistor 9, the signal 22
Even if the level Lm of the signal reaches the above-mentioned dead area 20 and is not recognized as the L signal, it is compensated by the signal 27 and is reliably transmitted. Therefore, it is possible to obtain a signal transmission circuit in which the resistance value of the interference suppression resistor 9 can be sufficiently increased, the occurrence of interference can be suppressed, and the reliability of signal transmission is improved.

When the L level transmission signal is present on the transmission line 8, the first signal 5a may be always applied to the pull-down transistor 5 regardless of its source. However, it is only when the reply signal 22 from the receiving IC is output that the true first signal 5a is required, and it may or may not be present when the signal 21 is output. Therefore, when the sending IC 1 knows that the signal 22 will be returned after a predetermined time has passed after the signal 21 is transmitted, after a predetermined time from the signal 21, (the timing at which the signal 22 should return) Then, the first signal 5a (H level) having a predetermined time width (time width of the signal 22) may be transmitted to the pull-down transistor 5. Although FIG. 1 shows three ICs of the sending side, the receiving side, and the third as the signal transmission equipment, more ICs may be connected. The pull-down transistor 5 is the first switching element according to the present invention. It should be noted that the pull-down transistor 5 may be replaced by the transmitting transistor 3 of the IC 1 on the sending side.

Embodiment 2. In the first embodiment, when the reply signal 22 is output at the L level from the receiving IC 11, the level of the transmission line 8 is forcibly lowered to the L level (that is, the reply signal 22 is masked). Met. However, the reply signal 22 may be known to be output at a certain timing due to the peculiarity of the signal, and at this time, the halfway signal level 2
As a masking method for preventing the transmission error due to 2, it is not always necessary to lower the level to the L level, but a method to raise the level to the H level may be used. The signal transmission circuit according to the second embodiment of the present invention ensures that the level of the transmission line 8 when the reply signal 22 is output is set to the Vcc level regardless of the value of each resistor connected to the transmission line 8. They can be brought close to each other, and the configuration is shown in FIG.

In the figure, 25 is a transmission line 8 and a power source V
It is a pull-up transistor (second switching element) connected to cc6. The second signal 25a is input to the pull-up transistor 25 from the sending side IC1 at the L level only at the timing of the signal 22, and otherwise at H level. The circuit for generating the second signal 25a will be described in detail in the fifth embodiment. As a result, the pull-up transistor 25 is turned off at the timing when the signal 22 is absent, but is turned on at the timing when the signal 22 is present and holds the H level 26 of the transmission line 8 at the Vcc level regardless of the value of each resistor.

To facilitate understanding, the waveform of the transmission line 8 will be described with reference to FIG. While the pull-up transistor 25 of the present embodiment is on, the transmission line 8 is directly connected to the power supply and is not related to the value of the resistor 7. As a result, at the timing when the reply signal 22 is output to the port 10, the level of the transmission line 8 is close to the power supply Vcc (122 in the figure).
Since it becomes the level, the resistance value of the pull-up resistor 7 can be set large without fear of lowering the H level. This also has the effect that the resistance value of the interference suppression resistor 9 can be set to a correspondingly large value, and the effect of interference suppression can be enhanced. The pull-up transistor 25 is the second switching element according to the present invention.

Embodiment 3. The signal transmission circuit according to the third embodiment of the present invention sets the level of the transmission line 8 to the receiving IC
The signal is not placed at a halfway level due to a reply signal from, and its configuration is shown in FIG. Further, waveforms for explaining the operation are shown in FIG. In the figure,
Reference numeral 17 is an auxiliary pull-up resistor connected between the power supply Vcc and the port 10 of the receiving side IC 11, 35 is a transmission line 8
Is a bidirectional switching transistor (third switching element) inserted between the control signal and the interference suppression resistor 9, and is turned on when the third signal 35a is applied at the H level and is applied at the L level to the base thereof. Turns off. The switching transistor 35 and the interference suppression resistor 9 are connected in series to form a series connection body. By changing the level of the third signal 35a between H and L, the interference suppression resistor 9 is connected to or disconnected from the signal transmission circuit 8. When separated by the L level signal, the port 10 of the receiving side IC 11 is held at the H level by the auxiliary pull-up resistor 17. When connected by an H level signal, the circuit configuration is the same as that of the conventional FIG.

The third signal 35a is the signal 2 on the transmission line 8.
When one of the conditions that 1 is transmitted or no signal is transmitted, the H level is set and the switching transistor 35 is turned on. However, when the reply signal 22 is being sent, it becomes L level and the switching transistor 35 is turned off to cut off the transmission line 8. However, here, this signal 22 is a reply signal of the receiving side IC 11, and the fact that this reply signal is sent at this timing means that the sending side I
It is assumed that C1 is known in advance. This prevents the level of the transmission line 8 from becoming halfway due to the reply signal 22.

In FIG. 5, the transmission side I is cut by cutting the transmission line.
Since C1 and the receiving side IC are separated and become independent circuits, the sending side IC1 is called a sending side signal transmission device and the receiving side IC is called a receiving side signal transmission device for distinction. The switching transistor 35 is the third switching element according to the present invention.

Fourth Embodiment First signal 5a for driving pull-down transistor 5 shown in FIG. 1 of the first embodiment.
FIG. 7 shows an example of a specific extraction circuit for the above. In the figure, reference numeral 41 is a first signal generation circuit which takes in the voltage of the port 10 of the receiving side IC 11 and produces the first signal 5a. Reference numeral 41a denotes a transistor circuit including a monostable one-shot multivibrator that operates by using the L level signal of the port 10 as a trigger (not shown in the figure, and shown as one transistor). FIG. 8 is a waveform diagram for explaining the operation of the first signal generation circuit 41 of FIG.

Next, the operation of FIG. 7 will be described. The first signal generation circuit 41 includes the transmission line 8 or the port 1
When the L level transmission signal is not output to 0 (of course to the port 4), the transistor circuit 41a outputs the L level first signal to 5a, and the pull-down transistor 5 is off. Then, for example, at port 10 2 of FIG.
As shown in FIG. 3, when the signal 22 below the threshold level 31 provided on the input dead zone region 20 is input,
The transistor circuit 41a outputs an H level signal to 5a. As a result, the pull-down transistor 5 is turned on and the level of the transmission line 8 is lowered to 0V. Since the transistor circuit 41a includes a one-shot multivibrator, its output automatically returns to the L level after a predetermined time (for example, one clock pulse time) set in advance after outputting the H level signal, The pull-down transistor 5 is also turned off. Reference numeral 27 in FIG. 8 indicates the level of the transmission line 8 pulled down by the pull-down transistor 5 driven by the first signal 5a.

The pull-down transistor 5 receives the reply signal 22.
It should be turned on only at the timing of, but it is not bad to turn on at the timing of the signal 21. Therefore,
Although the first signal generation circuit 41 captures the signal of the port 10 in FIG. 7, it may also capture the signal of the port 4. In this case, the first signal generation circuit 41 may generate the first signal as described in the first embodiment. The circuit 41 can also be configured inside the sending IC 1. If a delay circuit (not shown) is inserted, the first embodiment is started from the first moment when the signal 21 is detected.
It is also possible to output the signal 5a after the time delay 28 shown in FIG. First signal generation circuit 4
1 can also be configured by a microcomputer.

Embodiment 5. Second signal 2 for driving pull-up transistor 25 shown in FIG. 3 of the second embodiment
FIG. 9 shows a specific extraction circuit for 5a. In the figure, reference numeral 50 is a second signal generation circuit which takes in the voltage of the port 4 of the IC 1 on the sending side and produces a second signal 25a. 50a is a transistor circuit including a delay element corresponding to 28 in FIG. FIG. 10 is a waveform diagram for explaining the operation of the signal generation circuit 50 of FIG.

Next, the operation of FIG. 9 will be described. The second signal generation circuit 50 uses the signal 21 and the signal 2 on the transmission line 8.
When 2 is not output, the transistor circuit 50a
Is turned off, the H level is output as the signal 25a,
As a result, the pull-up transistor 25 is off. Then, the voltage of the port 4 is taken in, and when a pulsed signal 21 having a predetermined level, for example, a signal exceeding a threshold level 32 provided under the input dead zone region 20 as shown in FIG. 10, is detected, Delay time 2
After 8, the transistor circuit 50a is turned on and outputs the L-level signal 25a. This turns on the pull-up transistor 25. When the signal 21 at the port 4 disappears, the pull-up transistor 25 turns off again. Reference numeral 27 in FIG. 10 shows the H level of the transmission line 8 pulled up by the pull-up transistor 25 driven by the signal 25a.

In FIG. 9, the second signal generating circuit 50 takes in the signal of the port 4, but it may be configured to take in the signal of the port 10 to operate. The second signal generation circuit 50 may be configured by a one-shot multivibrator that inverts the rising or falling of the transmission signal 21 or 22 as a trigger and inverts it automatically after a predetermined time. Also, the same function can be achieved by a microcomputer.

Sixth Embodiment FIG. 11 shows a concrete extraction circuit of the third signal 35a for driving the switching transistor 35 shown in FIG. 5 of the third embodiment. Switching transistor 35 and interference suppression resistor 9
Are connected in series to form a series connection body. In the figure, reference numeral 60 is a third signal generation circuit which takes in the voltage of the port 4 or the port 10 and produces a third signal 35a.
FIG. 12 is a waveform diagram for explaining the operation of the third signal generation circuit 60 of FIG. Reference numeral 60a is a driving transistor circuit including a delay element.

Next, the operation of the circuit shown in FIG. 11 will be described. The third signal generation circuit 60 outputs the H level as the signal 35a when there is no L level signal in either the transmission line 8 or the port 10. As a result, the switching transistor 35 is turned on. Then, after a predetermined time after the voltage of the port 4 becomes L, or when the voltage of the port 10 becomes L level, for example, as shown in FIG. 12, the threshold level 31 provided above the input dead zone region 20 is set. When the falling signal is detected, the L level is output. Then, the switching transistor 35 turns off, and returns to on when there is no L level signal in either the port 4 or the port 10.

The switching transistor 35 disconnects the interference suppression resistor 9 and the circuit of the receiving side IC 11 from the transmission line 8. As a result, the level of the transmission line 8 does not become halfway due to the reply signal 22. As a result, the selection range of the value of the pull-up resistor 7 becomes wider and the design margin increases. Further, the third signal generation circuit 60 may be configured by a one-shot multivibrator that inverts the rising or falling of the transmission signal 21 or 22 as a trigger and inverts automatically after a predetermined time. Also, the same function can be achieved by a microcomputer.

In the above description of the first to sixth embodiments, each signal generating circuit is configured not by hardware but by using a microcomputer, and the timing at which a reply signal is returned is determined by the sending side IC. The pull-down Tr, the pull-up Tr, or the switching Tr may be driven by predicting from the output timing.

[0046]

Since the signal transmission circuit of the present invention is provided with the pull-down transistor (first switching element) for forcibly dropping the voltage level of the transmission line to the ground side by the first signal, transmission from the terminal side is performed. Even if the level of the generated transmission signal rises due to the influence of the interference suppression resistance, the value of the interference suppression resistance can be increased and the error rate of transmission can be improved because it is surely corrected to the 0V level.

Further, since the first signal for driving the pull-down transistor is generated either by the transmission signal or by delaying the transmission signal by a predetermined number of clock pulses, it is possible to reliably react to an extremely weak transmission signal. The level can be set to 0V.

Since the first signal is composed of a one-shot multivibrator which is inverted by the transmission signal, the operation is reliable.

Further, the first signal generating circuit drives the pull-down transistor by predicting its timing without actually receiving the reply signal, so that the resistance value of the interference suppression resistor can be increased.

Further, since the pull-up transistor (second switching element) for forcibly raising the voltage level of the transmission line to the Vcc side by the second signal is provided, the voltage of the transmission line is surely corrected to the Vcc level. Therefore, even if a halfway level signal is output from the receiving IC via the interference suppression resistor, no malfunction occurs and the transmission error rate can be improved.

Further, since the second signal for driving the pull-up transistor is generated with a delay of the predetermined number of clock pulses from the transmission signal, it is possible to reliably react to the transmission signal of an incomplete level. can do.

Since the second signal is composed of a one-shot multivibrator which is inverted when the transmission signal disappears, the operation is reliable.

Further, the second signal generating circuit drives the pull-down transistor by predicting its timing without actually receiving the return signal, so that the resistance value of the interference suppressing resistor can be increased.

Further, since a switching transistor (third switching element) is provided in the middle of the transmission circuit and is turned on / off by the third signal which is turned off when there is no transmission signal, it is returned. When there is a signal, the receiving circuits connected in parallel are disconnected, and the level of the transmission line approaches the stable level more reliably, so that the transmission error rate can be improved.

Further, since the third signal for driving the switching transistor is generated in the transmission signal or delayed by a predetermined number of clock pulses from the transmission signal, even a very weak transmission signal can be surely recognized. be able to.

Since the third signal is composed of a one-shot multivibrator which is inverted by the transmission signal, the operation is reliable.

Further, since the third signal generating circuit drives the pull-down transistor by predicting its timing even if the return signal is not actually received, the resistance value of the interference suppression resistor can be increased.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a signal transmission device according to a first embodiment of the present invention.

FIG. 2 is a waveform diagram for explaining the operation of FIG.

FIG. 3 is a configuration diagram of a signal transmission device according to a second embodiment of the present invention.

FIG. 4 is a waveform diagram illustrating the operation of FIG.

FIG. 5 is a configuration diagram of a signal transmission device according to a third embodiment of the present invention.

6 is a waveform diagram illustrating the operation of FIG.

FIG. 7 is a configuration diagram of a signal transmission device according to a fourth embodiment of the present invention.

FIG. 8 is a waveform diagram illustrating the operation of FIG.

FIG. 9 is a configuration diagram of a signal transmission device according to a fifth embodiment of the present invention.

FIG. 10 is a waveform diagram illustrating the operation of FIG.

FIG. 11 is a configuration diagram of a signal transmission device according to a sixth embodiment of the present invention.

12 is a waveform diagram illustrating the operation of FIG.

FIG. 13 is a configuration diagram of a conventional signal transmission device.

FIG. 14 is a waveform diagram illustrating the operation of FIG.

[Explanation of symbols]

1 sending side IC (signal transmission equipment), 2 receiving circuit,
3 transmitter transistors, 4 ports, 5 pull-down transistors (first switching elements), 5a first signals, 6 power supply circuits, 7 pull-up resistors,
8 transmission lines, 9 interference suppression resistance, 10 ports 11 receiving side IC (signal transmission equipment), 12 receiving circuit, 13 transmitting transistor, 15 3rd IC, 2
0 Input dead area, 22 Reply signal (0V to port 10
Is output), the L level of the transmission line 8 is 25
Pull-up transistor (second switching element),
25a second signal, 26 H level of transmission line,
28 time delay of a predetermined number of clock pulses, 35 switching transistor (third switching element), 3
5a Third signal, 41 First signal generation circuit, 5
0 second signal generation circuit, 60 third signal generation circuit

Claims (12)

[Claims] 1. A transmission / reception port for inputting / outputting a transmission signal,
A transmission signal transmission / reception circuit connected to the transmission / reception port, which transmits / receives the transmission signal in synchronization with a predetermined clock pulse, and an interference suppression resistor between the transmission / reception ports of the plurality of signal transmission devices. A transmission line connected to the power supply circuit via a pull-up resistor and outputting a first signal based on a transmission signal output to the transmission line by any one of the plurality of signal transmission devices; And a first switching element which is connected between the transmission line and the ground and which is turned on by the first signal to bring the voltage level of the transmission line closer to the voltage level of the ground. A signal transmission circuit characterized by the above. 2. The first signal generation circuit synchronizes with a transmission signal output from the signal transmission device to the transmission line, or a time corresponding to a predetermined number of clock pulses from the timing of the transmission signal. The signal transmission circuit according to claim 1, wherein the first signal is output with a delay. 3. The one-shot in which the first signal generation circuit inverts the transmission signal output from the signal transmission device to the transmission line as a trigger and recovers after a time corresponding to one pulse of the clock pulse. The signal transmission circuit according to claim 2, further comprising a multivibrator. 4. The first signal generation circuit predicts the timing at which the reply signal is output from the timing of the transmission signal output to the transmission line by any one of the plurality of signal transmission devices, and the prediction is performed. The signal transmission circuit according to claim 1, wherein the first signal is output based on 5. A transmission / reception port for inputting / outputting a transmission signal,
A transmission signal transmission / reception circuit connected to the transmission / reception port, which transmits / receives the transmission signal in synchronization with a predetermined clock pulse, and an interference suppression resistor between the transmission / reception ports of the plurality of signal transmission devices. A transmission line connected to the power supply circuit via a pull-up resistor, and outputs the second signal based on a transmission signal output to the transmission line by any one of the plurality of signal transmission devices. A second signal generating circuit, comprising a second switching element which is connected between the transmission line and the power supply circuit and which brings the voltage level of the transmission line closer to the voltage level of the power supply circuit by the second signal. A signal transmission circuit characterized by the above. 6. The second signal generation circuit is synchronized with a timing of a transmission signal output from the signal transmission device to the transmission line, or corresponds to a predetermined number of clock pulses from the timing of the transmission signal. 6. The second signal is output after a delay of
The signal transmission circuit according to. 7. The one-shot multivibrator, wherein the second signal generation circuit inverts the timing of the transmission signal output to the transmission line as a trigger and restores after a time corresponding to a predetermined pulse of the clock pulse. The signal transmission circuit according to claim 6, further comprising: 8. The second signal generation circuit predicts a timing at which a reply signal is output from a timing of a transmission signal output to the transmission line by any one of the plurality of signal transmission devices, and the prediction is performed. The signal transmission circuit according to claim 5, wherein the second signal is output based on 9. A transmission / reception port for inputting / outputting a transmission signal,
A transmission signal transmission / reception circuit having a transmission signal transmission / reception circuit connected to the transmission / reception port, transmitting / receiving the transmission signal in synchronization with a predetermined clock pulse, a transmission / reception port for inputting / outputting a transmission signal, and the transmission / reception port A receiving side signal transmission device having a connected transmission signal transmitting / receiving circuit and transmitting / receiving a transmission signal in synchronization with a predetermined clock pulse; a transmission signal output by the sending side signal transmission device and the receiving side signal transmission device; It turns off in synchronization with any of the output transmission signals, and outputs a third signal that turns on when neither the sending side signal transmission device nor the receiving side signal transmission device outputs the transmission signal. A third signal generation circuit, between the transmission / reception port of the transmission side signal transmission device and the transmission signal reception port of the reception side signal transmission device by the third signal Third signal transmission circuit comprising the transmission line connected through a pull-up resistor to the power supply circuit as well as connected via the series connection of the switching element and the disturbance suppression resistor being dynamic. 10. The third signal generating circuit synchronizes with a transmission signal output to the transmission line by the sending side or receiving side signal transmission device or from the timing of the transmission signal output to the transmission line. 10. The signal transmission circuit according to claim 9, wherein the third signal is output with a time delay corresponding to a predetermined number of clock pulses. 11. The one-shot multi circuit, wherein the third signal generating circuit inverts the transmission signal output from the signal transmission device to the transmission line as a trigger and recovers after a time corresponding to one pulse of the clock pulse. The signal transmission circuit according to claim 10, further comprising a vibrator. 12. The third signal generation circuit predicts the timing at which the reply signal is output from the timing of the transmission signal output to the transmission line by any one of the plurality of signal transmission devices, and the prediction is performed. The signal transmission circuit according to claim 9, wherein the third signal is output based on