JP2002366131A - Image data transfer device and image display processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform image processing, transfer data control, etc., and to reduce memory capacity. SOLUTION: The image data transfer device processes image data of a designated transfer source area and image data of a designated transfer destination area stored in an image data storage device according to parameters regarding the transfer source area and transfer destination area, and then transfers the data to the transfer destination area. The image data of the source are monochromatic image data having one pixel composed of one bit and the image data of the destination are image data having one pixel composed of one or more bits. Address counters 15 to 17 read image data out of the source area and destination area of a local memory 4 in block units larger than image data of one pixel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a CRT (Cathode
Raster scan type display devices such as Ray Tube)
The present invention relates to an image display processing system for data constituting an image expressed on a plane, and more particularly to an image data transfer device and an image display processing system for transferring image data of a specific area.

[0002]

2. Description of the Related Art Conventionally, as a two-dimensional image data processing device using a raster scan type display device such as a CRT, a device disclosed in, for example, JP-A-60-214392 is known. As shown in FIG. 41, this image display processing system includes a central processing unit (CPU).
In order to reduce the burden on the display 202, a display controller 201 for image display processing is provided. Image data processing circuit 21 inside display controller 201
0 reads out still image data, moving image data, and the like stored in a video RAM (hereinafter, referred to as VRAM) 204 via the interface 211 corresponding to the scanning speed of the screen of the CRT display device 205, and CRT
Synchronization signal SYNC necessary for image scanning to display device 205
Is output.

[0003] In this case, the still image and moving image data are composed of 2, 4, or 8 bit color codes for specifying the color of the dots on the display screen.
The read color code is output to the color palette 212. The color palette 212 converts the read color codes into RGB (red, green, blue) signals and supplies the signals to a CRT display device.

Further, the image data processing circuit 210
The image data supplied from the U 202 via the interface 213 is displayed in a screen non-display period (vertical retrace period, etc.).
To the VRAM 204. Further, when accessing the VRAM 204 (at the time of writing and reading),
The signal S1 is supplied to the command processing circuit 215 to notify that access is being performed. The command processing circuit 215
Processing corresponding to various commands supplied from the CPU 2 via the interface 213 is performed.

[0005] In the image display processing system having the above configuration, the movement of the rectangular area including the still image can be performed in a short time by the CPU.
Or when performing the above-described color code transfer, perform a logical operation between each bit of the color code of the dot to be transferred and each bit of the color code of the destination dot, and transfer the result. VR corresponding to the previous dot
A logical operation process for writing to the storage area of the AM 204 and a transparent process (transparent process) in which a color code of a transparent color code among the color codes of each dot in the transfer source area is not transferred and only the other color codes are transferred. ) Etc. can be performed. Also,
This system is provided with a dot unit transfer mode for transferring a color code in dot units and a byte unit transfer mode for transferring a color code in byte units.

[0006]

However, the above-described conventional image display processing system cannot execute predetermined logical operation processing and transparent processing while realizing high-speed transfer. In particular, due to the remarkable improvement of image processing technology and the sudden increase of image data transfer volume,
It has become difficult for such an apparatus to meet the demands for high-speed transfer and fine image processing. Furthermore, even when the pattern is a fixed pattern, if the color code changes in various ways, it is necessary to store the source data for each color code, and there is a problem that the amount of data to be stored increases.

[0007] The present invention has been made in view of such problems, and an image data transfer apparatus capable of performing image processing and transfer data control more efficiently and reducing the memory capacity. And an image display processing system.

[0008]

According to the present invention, there is provided an image data transfer apparatus comprising: an image data transfer device for storing image data of a transfer source area stored in an image data storage device based on parameters relating to a designated transfer source area and a transfer destination area; In the image data transfer device for performing an arithmetic process on the image data of the transfer destination area and transferring the image data to the transfer destination area, the image data of the transfer source area may be monochrome image data in which one pixel is composed of 1 bit. The image data in the transfer destination area is
An address counter for reading image data in which one pixel is composed of one or a plurality of bytes, and which reads image data from the transfer source area and the transfer destination area of the image data storage means in block units larger than one pixel of image data;
In addition to storing the image data in block units read from the image data storage unit, one pixel of the transfer source area is set to 1 or 2 representing one of two colors of data set in advance according to the bit value. A data storage unit with a data extension function for extending to image data composed of a plurality of bytes, and performing position alignment in a block with the extended image data of the source area and the image data of the destination area. Operating means for executing the arithmetic processing.

An image display processing system according to the present invention outputs an image data storage device for storing image data, and a parameter relating to a transfer source region and a transfer destination region of the image data stored in the image data storage device. A central processing unit, and the image data of the source area and the image data of the destination area stored in the image data storage device based on the parameters related to the source area and the destination area output from the central processing apparatus. An image data transfer device that transfers the image data stored in the image data storage device to an image data transfer device that transfers the image data to the transfer destination region after the arithmetic processing. The image data is monochrome image data in which one pixel is composed of one bit, and image data of the transfer destination area. Wherein one pixel is image data composed of one or more bytes, the central processing unit outputs the number of bytes constituting one pixel to the image data transfer device, and the image data transfer device Image data is transferred in units of blocks larger than one pixel of image data, and one or more pixels representing one of two colors of data set in advance according to the bit value of one pixel in the transfer source area. After performing the above-described arithmetic processing by aligning the expanded image data of the transfer source area and the image data of the transfer destination area in the block with the expanded image data, the image data storage is performed. It is stored in a device.

According to the present invention, the image data of the transfer area stored in the image data storage device is based on the parameters relating to the designated transfer source and transfer destination areas (hereinafter, this paragraph is referred to as “transfer area”). When the image data is processed and transferred, the image data is assumed to be image data in which one pixel is composed of one or more bytes, and the image data is transferred in a block unit composed of a plurality of bytes larger than the one-pixel image data. Then, by performing position adjustment within the block in the transfer area and executing the arithmetic processing, high-speed transfer of image data can be performed.

According to the present invention, the image data of the transfer source area is monochrome image data in which one pixel is composed of one bit, and one pixel of the transfer source area is converted to its bit value during transfer processing. Accordingly, the image data is expanded to image data composed of one or more bytes representing one of the two colors of data set in advance, so that the image data of the transfer source area to be stored in the image data storage means is stored. Data amount can be reduced. In particular, when displaying a plurality of different types of color patterns in the same pattern, it is sufficient to store only one type of the pattern itself and change the coloring data in various ways, so that the amount of data to be stored is significantly reduced. can do.

In the present invention, the transfer start and transfer end block addresses are calculated for each scanning line, and the image data is transferred continuously from the transfer start block to the transfer end block. Can be transferred. Further, according to the present invention, a mask pattern for masking the area other than the transfer area is generated based on the transfer image start and end byte addresses in each block, and the position in the block is aligned in the transfer area. Even if it is configured, arithmetic processing can be performed by matching the positions of the transfer source and transfer destination data stored at arbitrary positions. Also, image data 1
By setting a color tag for each pixel byte and setting a color tag for each byte based on the transfer image start byte address in the block, the image display processing efficiency is improved. Therefore, by incorporating the image data transfer device into the image display processing system, it is possible to increase the speed and efficiency of the image display processing.

In a more specific aspect of the present invention, the expansion of the image data is performed by copying 1-bit data of each pixel of the transfer source area in accordance with the number of bytes of each pixel. Is set by assigning a byte specified by the color tag to one or a plurality of bytes of color pixel data representing one color of two-color data set in advance. What should I do?

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image display processing system according to the present invention will be described below with reference to the drawings. FIG.
FIG. 1 is a block diagram illustrating a basic configuration of an image display processing system according to an embodiment of the present invention. The image display processing system includes a local memory 4 such as a DRAM (Dynamic Random Access Memory) for storing image data to be displayed, and an arbitrary rectangular area of the image data stored in the local memory 4. A CPU 1 for outputting various parameters, an image data transfer device 2 for transferring image data of a rectangular area on the local memory 4 based on parameters given from the CPU 1, an image data transfer device 2 and a local memory 4 A memory controller 3 for controlling access to image data, and a CRT for displaying image data in a screen area of a local memory 4.
And a display device 5 such as a liquid crystal display.

FIG. 2 shows an outline of the functions of the image data transfer device 2. The image data transfer apparatus 2 includes a rectangular area of transfer source data (hereinafter, referred to as source data) S stored in a non-display area on the local memory 4 and transfer destination data (hereinafter, destination) stored in a display area. The parameters that define the rectangular areas of D and the parameters that define the rectangular areas of any pattern data P stored in the non-display area added to the source data S are received from the CPU 1 and are stored in the local memory 4. , A source, a destination, and a pattern data are taken in, a predetermined raster operation process is performed between these data, and a process of writing the data in a destination area is executed.

Here, the source data S allows not only a case where each pixel is color data consisting of one or a plurality of bytes, but also a case where each pixel is monochrome data defined by two colors. When the source data is monochrome data, one pixel is composed of one bit. FIG. 3 shows an example in which an “x” mark is stored as a monochrome source pattern in 8 pixels × 8 lines. FIG.
In the case of (1), since a pattern of 8 pixels × 8 lines requires only a capacity of 8 bytes, the storage capacity of the memory can be greatly reduced. Here, for example, the value of each pixel is 0
Is defined as a background color, and 1 is defined as a foreground color. The background color and the foreground color are:
Each pixel is composed of 1 to 4 bytes, and is transferred and stored in a register described later in advance. The number of bytes constituting one pixel is referred to herein as a BPP (byte-per-pixel). If the source data is itself color data, one pixel is defined in the BPP. When the source data is defined by monochrome data, the image data transfer device 2 writes 1-bit data corresponding to one pixel of the source data into 0 bytes as a background color and 1 byte as a foreground color defined in the BPP. And transfer it to destination area D.

Hereinafter, the image data transfer device 2 will be described in detail. FIG. 4 is a block diagram showing a detailed configuration of the image data transfer device 2. The parameters specifying the destination area, source area, and pattern area sent from the CPU 1 are supplied to the destination address calculation circuit 12, the source address calculation circuit 13, and the pattern address calculation circuit 14 via the interface 11. In these address calculation circuits 12, 13, and 14, a start address (FBSPn) indicating the start of transfer of the destination area, the source area, and the pattern area on the local memory 4 for each scan line, and an end address (FBSPn) indicating the end of the transfer. FBEPn). The values are passed to the destination address counter 15, the source address counter 16, and the pattern address counter 17, respectively.

As shown in FIG. 5, the source address calculating circuit 13 includes a color address calculating circuit 131, a monochrome address calculating circuit 132, and a multiplexer 133 for selecting an output of the circuit. The multiplexer 133 is connected to the MO provided in the interface 11.
By referring to a NO register (not shown), it is determined whether the source data is color data or monochrome data, and the output is switched. Thus, when the source data is color data, the output of the color source address calculation circuit 131 is output to the source address counter 16, and when the source data is monochrome data, the output of the monochrome source address calculation circuit 132 is output To the source address counter 16.

On the other hand, the image data transfer device 2 has three SRAMs (Static Random Access Memors) for temporarily storing the image data transferred from the local memory 4.
y), that is, a destination SRAM 18, a source SRAM 19, and a pattern SRAM 20 are provided. Each of the address counters 15, 16, 17 hierarchizes the local memory 4 in units of sectors, blocks, and bytes, and outputs the addresses of the sectors to be transferred to the SRAMs 18, 19, 20. As a result, data for one sector is transferred to the SRAMs 18, 19, and 20 in block units.

Further, since the transfer start pixel and the transfer end pixel are not always the head and end of the block, the block at the start and end of the transfer contains data other than the pixel data to be transferred. It may be. Each of the address counters 15, 16, 17 generates mask data for masking these data, and supplies the mask data to the mask arithmetic circuit 23. The mask operation circuit 23 controls each of the SRAMs 18 and 1 based on the input mask data.
The data is read out from the raster operation circuits 9 and 20 and the raster operation circuit 21
Perform calculations to send data to The raster operation circuit 21 reads the sector data from each of the SRAMs 18, 19, 20 in units of one block, reads the operation result from the mask operation circuit 23, performs a raster operation, and stores the operation result in the output FIFO 22. The data stored in the FIFO 22 is stored in the local memory 4 at a predetermined timing.
Is transferred to the destination area. The controller 24 controls each circuit according to a control command from the CPU 1. A monochrome expansion device 96 described later is provided inside the source SRAM 19. When the source data is defined by monochrome data, 1-bit data corresponding to one pixel of the source data is set to 0, and 0 is set to the background. The color 1 is expanded to the number of bytes defined in the BPP as the foreground color and transferred to the destination area.

FIG. 6 is a flowchart showing the flow of processing of the image data transfer apparatus 2. First, Y = YS is loaded as an initial value of the transfer scan line Y set inside each of the address calculation circuits 12, 13, and 14 (S1). Next, the start address (FBSPn) and the end address (FBEPn) of the scan line are calculated by the address calculation circuits 12, 13, and 14 (S2), and the values are respectively stored in the address counter 1
5, 16, 17 are passed. When the source data is monochrome data, the start address (MSPj) and the end address (MEPj) are calculated by the address calculation circuit 13 (S2), and the values are passed to the address counter 16. Each SRAM 1 is transferred from the local memory 4 in accordance with the address generated by each of the address counters 15, 16 and 17.
Destination data D, source data S, and pattern data P for one sector are transferred to 8, 19, and 20, respectively (S3, S4). SRAM 18, 19, 20
After the transfer to each of the SRAMs 18, 1 in units of one block,
Data is read from 9, 20. When the source data is monochrome data, the data is extended from the source SRAM 19 according to the BPP. The read data is subjected to a raster operation by the raster operation circuit 21 in accordance with the operation result by the mask operation circuit 23, and is stored in the output FIFO 22 (S5).

If the processing of the sector data stored in the source SRAM 19 is completed (S7),
The next sector data is transferred (S4). When the processing of the sector data stored in the destination SRAM 18 is completed, the data stored in the output FIFO 22 is transferred to the local memory 4 after the raster operation is completed.
(S8), and transfer the new sector data to the destination SRAM 18 (S2). When the processing of the sector data stored in the pattern SRAM 20 is completed (S7), the next sector data is transferred (S4).

The above processing is repeated, and when the processing of one line of data is completed (S9), Y is updated (S1).
0), and proceed to processing of the next line. When the processing of the last line is completed, the processing of the rectangular area is completed (S1).
1).

Next, a more specific operation of the image data transfer device 2 will be described. FIG. 7A is a diagram illustrating the rectangular (display) area of the image data including the transfer rectangular area in more detail. This rectangular area corresponds to a screen area for destination data D, and an off-screen area for source data S and pattern data P. For the source data, a transfer image of color data is shown. The parameters displayed here are given from the CPU 1 to the image data transfer device 2 as described above, and are as follows.

BASE: Data representing, in bytes, coordinate values on the local memory 4 corresponding to the reference position of the rectangular area including the transfer rectangular area (normally, the position of the upper left pixel of the area). In some cases, it indicates the base point of the screen area, and in other cases it indicates the base point of the off-screen area. PTCH: Data representing the width of one line of the rectangular area including the transfer rectangular area in bytes. XS: Data representing the transfer start X coordinate value of the transfer rectangular area in pixels. YS: Data indicating the transfer start Y coordinate value of the transfer rectangular area by a scan line. XEXT: Data representing the width of the transfer rectangular area in the X direction by the number of pixels. YEXT: Data representing the width of the transfer rectangular area in the Y direction by the number of scan lines.

XDIR: Data indicating whether the transfer is performed in the positive or negative direction of X. When 0, it is positive (rightward) and when it is 1, it is negative (leftward). That is, as shown in FIG. 8, when XDIR is 0, XS is the left end of the transfer rectangular area, and X is updated in a positive direction from XS. Also, XD
When IR is 1, XS is the right end of the transfer rectangular area, and XS
Are updated in a negative direction from XS.

YDIR: Data indicating whether the transfer is performed in the positive or negative direction of Y. 0 indicates positive (downward) and 1 indicates negative (upward). That is, as shown in FIG. 8, when YDIR is 0, YS is the upper end of the transfer rectangular area, and Y is updated from YS in the positive direction. Also, YD
When IR is 1, YS is the lower end of the transfer rectangular area, and Y
Are updated in the negative direction from YS.

Here, the start address (FBSP) in the n-th line when given by the scan line Y = n
n) and the end address (FBEPn) are XDIR =
When it is 0, it is given by the following equation.

[0029]

FBSPn = BASE + n × PTCH + (XS + XEX) FBSPn = BASE + n × PTCH + XS × BPP
T) × BPP-1

When XDIR = 1, it is given by the following equation.

[0031]

FBSPn = BASE + n × PTCH + (XS
+1) × BPP-1 FBEPn = BASE + n × PTCH + (XS-XEX
T + 1) × BPP

FIG. 7B is a diagram showing the start address (FBSPn) and the end address (FBEPn) at Y = n when BASE = 0 as continuous data on the local memory 4.

On the other hand, when the source data is monochrome data, the parameters given from the CPU 1 to the image data transfer device 2 are as shown in FIG.

SBASE: Data representing the coordinate value on the local memory 4 of the coordinate value serving as a reference for storing the source data S in bytes. MOFST: Monochrome offset, SBA
The storage start position of the monochrome data from the SE in bytes. When a plurality of pieces of monochrome data are stored, the storage start position can be designated by changing the value of MOFST. MPTCH: monochrome pixel pitch, which defines the number of pixels in one line of the monochrome pattern. The number of pixels in one line is defined on the basis of a multiple of eight. That is,

8 pixels / line when MPTCH = 1, 16 pixels / line when MPTCH = 2, 24 pixels / line when MPTCH = 3, 32 pixels / line when MPTCH = 4,

Is defined as follows. The pattern in FIG.
This is an example where MPTCH = 1. The size of the destination area of the transfer destination must match the size of the source area. Since the transfer is specified by an address in bytes, if the destination size is not a multiple of 8, the largest integer less than or equal to MPTC
H is adopted. That is, 8 * (MPTCH-1) <
XEXT (X transfer area width of destination) ≦ 8 *
The MPTCH to be the MPTCH is selected. If it is not a multiple of 8, the monochrome data of each line is stored such that valid monochrome data matches the head of the byte, as shown in FIG. The illustrated example is an example in which the number of pixels in one line is 14, and in this case, 2 MPTCHs are used.
Is selected, and monochrome data is allocated to the first to 14th bits of 2-byte data.

When the source data is monochrome data, the transfer to the destination is always performed in the positive direction for both X and Y. The scan line in the monochrome pattern is also incremented in synchronization with the start scan line YS being set to the destination scan line Y. In the monochrome source address calculation circuit 132, the start address (MSPj) and the end address (MEPj) of the source in the j-th line when Y = j are given.
Is calculated by the following equation.

[0038]

MSPj = SBASE + MOFST + j * MPTCH MEPj = SBASE + MOFST + (j + 1) * MP
TCH-1

The bytes specified by the source are developed in bit units in order from the start address MSPj, and are processed in destination line units. Source start address MSPj and source end address MEPj
Can be calculated by sequentially adding MPTCH to the initial value.

As described above, the start address and the end address calculated by the destination address calculation circuit 12, the source address calculation circuit 13, and the pattern address calculation circuit 14, respectively, correspond to the destination address counter 15, the source address counter 16, and the pattern. It is set in the address counter 17 for each scan line.

Each address counter 15, 16, 17
The local memory 4 is hierarchized, and the interface between the image data transfer device 2 and the local memory 4 is performed for each of a series of continuous data units via the memory controller 3, thereby efficiently transferring data. Therefore, the address is decomposed as follows.

That is, when the source data is color data, each of the address counters 15, 16, and 17 stores the received start address (FBSPn) and end address (FBEPn) as shown in FIG. The local memory 4 is hierarchized by decomposing it into a sector address U bit, a block address V bit and a byte address W bit from the side. The total number of bits is U + V + W bits, as shown in FIG. 2B, and the capacity of the local memory 4 is a maximum of 2 ^{U + V + W} bytes. In other words, the local memory 4 is composed of 2 ^U sectors, and one sector is composed of 2 ^V blocks. One block is composed of 2 ^W bytes. The example of FIG. 10A is an example where V = 3 and W = 3.

Number of bytes in one block 2^WBytes are raw
It is equal to the data bus width of the cull memory 4. That is, local
One address access to memory 4 gives 2^WByte (1
Lock) of data can be transferred. local
Access to memory 4 is 2 ^WBytes (one block)
It is performed continuously as a unit. 2^WByte (1 block
H) data transfer at least once and 2 at maximum^VConsecutive times
In the maximum case, one sector of data is continuously transferred.
Will be sent. The data bus width of each SRAM is
2 equal to the bus width of the local memory 4^WBytes.
The dress is a V bit. This is the data of one sector
Equal to size.

As shown in FIG. 10B, the higher order of the address of the local memory 4 is a row address, and the lower order is a column address. Data transfer is realized.

When the source data is defined by monochrome data, 1-bit data corresponding to one pixel of the source data is extended to the number of bytes defined by BPP as 0 for the background color and 1 for the foreground color. Transfer to the destination area. FIG. 11 shows how the data is extended. The example shown here is an example of extension when one sector is composed of eight blocks and one block is composed of eight bytes. As shown in FIG. 11, the 1-byte (8-bit) monochrome source data S is 8 bytes when the BPP is 1, 16 bytes when the BPP is 2,
When BPP is 3, the data is expanded to 24 bytes, and when BPP is 4, the data is expanded to 32 bytes and transferred to the destination area.

FIG. 12 is a diagram showing a basic configuration of the source address counter 16. The destination address counter 15 and the pattern address counter 17
Has basically the same configuration as that of the source address counter 16, except that there is no selection by the signals NXMQD and MONO. The pattern address counter 17 does not include the color tag calculation counter 40.

The start address (FBSP) is loaded into the start address register 30. FBS at the same time
P passes through the address update circuit 31 and stores the upper U bits (FBSP [U + V + W-1: V + W]) in the sector address register 32 and the central V bit (FBSP [V +
W-1: W] is loaded into the block address register 33, and the lower W bits (FBSP [W-1: 0]) are loaded into the byte address register 34, respectively. The end address (FBEP) is loaded into the end address register 35.

First, in order to transfer the data in the local memory 4 to the source SRAM 19 (destination SRAM 18, pattern SRAM 20), the register 3
The sector address (SEC) indicating the address of the sector of the local memory 4 stored in the memory controller 3 is stored in the memory controller 3.
And a block start address (B) indicating the number of blocks to be transferred in the sector (BLKCNT) and the address of the first block to be transferred in the sector (the address at which the block in the sector starts).
LKSTR) is calculated by the intra-sector block operation circuit 45 and the like, and sent to the memory controller 3. Further, the intra-sector block operation circuit 45 calculates the number of blocks (BL
KCNT) and block start address (BLKST)
In addition to R), a block end address (BLKEND) indicating the address at which the block in the sector ends is also calculated.

The calculation by the intra-sector block operation circuit 45 includes a sector start flag (SECSTRF) output from the sector start comparator 37, a sector end flag (SECENDF) output from the sector end comparator 36, and a start address register 30. Start address (FBSP [V +
W-1: W]) and the block end address (FBEP [V + W-1:
W]) and XDIR indicating the direction of X in the transfer are input and used.

The sector start comparator 37 has a sector address (FBSP [U + V + W-1: V + W]) of the start address from the start address register 30 and a sector address (S
EC), and if they are equal, the output data (SE
CSTRF) is set to 1; otherwise, it is set to 0. Further, the sector end comparator 36 outputs the sector address (F) of the end address from the end address register 35.
BEP [U + V + W-1: V + W]) is compared with the sector address (SEC) from the sector address register 32. If they are equal, the output data (SECENDF) is set to 1, and if not, 0.

FIG. 13 is a diagram for explaining the sector data stored in the sector address register 32.

For example, if XDIR = 0 is defined and SEC
When STRF and SECENDF are 0, the sector address stored in the sector address register 32 is as shown in FIG.
As shown in FIG. 3A, it can be seen that the line is not the first sector of the line constituting the rectangular area and is not the last sector. In this case, the number of blocks in the sector (BLKC
NT) is 2 ^V and the start address of the block (BL)
KSTR) is 0, end address (BLKEND) is 2
It becomes ^V-1 .

SECSTRF is 1 and SECENDF is 0
At this time, it can be seen from FIG. 8B that the sector stored in the sector address register 32 is the first sector of the line constituting the rectangular area. In this case, the number of blocks in the sector is 2 ^V −FBSP [V + W−1:
W] blocks, and the start address of the block is FBSP
[V + W-1: W], and the end address is 2 ^V-1 .

If SECSTRF is 0 and SECEND
When F is 1, the sector stored in the sector address register 32 is the last sector of the line constituting the rectangular area, as can be seen from FIG. In this case, the number of blocks in the sector is FBEP [V + W-1:
W] +1, the start address of the block is 0, and the end address is FBEP [V + W−1: W].

Further, when both SECSTRF and SECENDF are 1, the sector stored in the sector address register 32 is the first sector of the line constituting the rectangular area and is also the last sector in FIG. You can see from In this case, the number of blocks is FBEP [V +
W-1: W] -FBSP [V + W-1: W] +1, and the start address of the block is FBSP [V + W-
1: W], and the end address is FBEP [V + W-1:
W]. FIG. 14 is a table summarizing the above results and the respective cases where XDIR = 1.

The block start comparator 39 stores the block address (FB) of the start address register 30.
SP [V + W-1: W]) and the block address (BLK) stored in the block address register 33, and if they are equal, the output data (BLKSTR) is compared.
F) is output as 1; otherwise, it is output as 0. Also,
The block end comparator 38 outputs a block address (FBEP [V + W-
1: W]) and the block address (BLK) stored in the block address register 33, and when they are equal, the output data (BLKENDF) is output as 1;

The output S of each of the comparators 36 to 39 described above.
ECENDF, SECSTRF, BLKENDF, BL
Based on KSTRF, a start mask (STRMSK) is calculated by a start mask calculation circuit 46 and an end mask (ENDMSK) is calculated by an end mask calculation circuit 47. As shown in FIG. 15, each of the start and end masks is a continuous 2 ^W bit pattern made up of data of 0 or 1, and one bit of each mask corresponds to each SRAM 1.
The pattern corresponds to one byte of data read from 8, 19, and 20, and the 2 ^W bit pattern corresponds to one block of data.

The mask AND operation circuit 48 receives the start and end masks, which are output data from the start and end mask operation circuits 46 and 47, and calculates the AND data (AMSK) of these to obtain a start address. The byte existing between (FBSP) and the end address (FBEP) has a role of giving 1 as a flag, and 0 as a flag otherwise.

For example, as shown in FIG. 16A, the calculation of the start mask in the start mask operation circuit 46 is as follows.
When XDIR = 0, the binary pattern (2 ^W -1) in which all of the W bits are 1 is shifted rightward by the number indicated by the byte address (BYT) in the byte address register 34 and becomes 0 from the left. It is done by packing. Similarly, as shown in FIG. 4B, when XDIR = 1, the calculation of the start mask is 2 in which all 1s in the W bit are 2
This is performed by shifting the hexadecimal pattern (2 ^W −1) to the left by the number indicated by 2 ^W −1-BYT (byte address) and padding zeros from the right. In this case, the start address (F
When BSP) is in the block, both SECSTRF and BLKSTRF become 1. The intra-block start address calculation circuit 49 calculates an address (BYTSTR) in the block where the mask at this time starts.

On the other hand, as shown in FIG. 9C, the end mask calculation in the end mask operation circuit 47 is performed by XDIR
= 0, if the byte address of the end address (FBEP) is FBEP [W-1: 0], the binary pattern (2 ^W -1) in which all 1s in the W bit are 2 ^W -1
This is performed by shifting to the left by FBEP [W-1: 0] and padding 0 from the right. Similarly, as shown in FIG. 11D, when XDIR = 1, the calculation of the end mask is performed by converting the binary pattern (2 ^W −1), which is all 1s in W bits, to FBEP [W−1: 0]. ] To the right, and zeroing from the left. In this case as well, when the start address is within the block, SECSTRF and BLKST
RF becomes 1 in both cases. Each mask calculated in this way is sent to the mask operation circuit 23 for each block.

The start flag circuit 50 receives the output SECSTRF of the sector start comparator 37 and the output BLKSTRF of the block start comparator 39 and outputs a start flag XSTRF. The end flag circuit 51 outputs the output S of the sector end comparator 36.
The ECENDF and the output BLKENDF of the block end comparator 38 are input to output an end flag XENDF.

The color tag calculation counter 40 is used at a later stage for calculation of transparent processing (transparency processing), and is initialized when a start address (FBSP) and an end address (FBEP) are input. It is set as follows. The color tag calculation counter 40 updates the output tag block address (TGBLK) in synchronization with the update of the output BLK from the block address register 33.

The update pattern is determined by BPP and XDIR, and the initial value and the update pattern are as shown in FIG. For example, if XDIR is 0,
When 1 byte per pixel (BPP is 1), the initial value is 0 and always 0 is output. When 2 bytes per pixel (BPP is 2), the initial value is 0 and TGBLK is 0, 1, Are updated so as to repeat 0, 1... When 3 bytes per pixel (BPP is 3), the initial value = 0.
, And TGBLK is updated so as to repeat 0, 1, 2, 0, 1, 2,..., And when 4 bytes per pixel (BPP is 4), the initial value is 0 and TGBLK is 0, 1,
Are updated so as to repeat 2,3,0,1,2,3. When XDIR is 1, the initial value is 0 when the byte is 1 byte per pixel (BPP is 1), and 0 is always output. When the byte is 2 bytes per pixel (BPP is 2), the initial value is 1 TGBLK is updated to repeat 1,0,1,0... And 3 bytes per pixel (B
When PP is 3), the initial value is 2, and TGBLK is 2,
Are updated to repeat 1, 0, 2, 1, 0... When 4 bytes per pixel (BPP is 4), the initial value is 3, and TGBLK is 3, 2, 1, 0, 3, 2 , 1,0
… Updated to repeat. The output TGBL of the color tag calculation counter 40 in the destination address counter 15 and the source address counter 16
K is the destination S, as described later.
Sent to the RAM 18 and the source SRAM 19,
It is used to select the output of the tag selection circuit 93 located inside.

The address update circuit 31 takes the output sector address (SEC) from the sector address register 32 and the output block address (BLK) from the block address register 33 as a series of values, and
4 increments the address in BLK units until the value matches the value in the end address register 35, and updates the sector address (SEC) and block address (BLK). In this case, whether or not the value in the end address register 35 coincides with the value in the end flag circuit 51 is determined by setting both SECENDF and BLKENDF to 1
Is detected.

The above description is for the case where the source data is color data. The specific function of the source address counter 16 when the source data is monochrome data will be described. When color data is selected as the source data, the address updating circuit 31 increments the address in units of one block (2 ^W bytes) as described above. However, when monochrome data is selected as the source data, the tag block Signal N from counter 40
The address is incremented by 1 byte by XMQD. The signal NXMQD is output from the tag block counter 4
The tag block indicated by “0” is output at the end of the block, and the output timing differs depending on the BPP. The details are shown in FIG. When BPP = 1,
The signal NXMQD is always ON. When BPP = 2, the tag block is 0 and OFF and 1 and ON. When BPP = 3, the tag block is 0 and 1 and OFF and 2 and ON and BPP.
= 4, tag blocks are OFF at 0,1,2,3
Turns on.

The start mask operation circuit 46 and the end mask operation circuit 47 switch their functions when the MONO signal is turned on in order to correspond to monochrome data, and are always all 1 as a start mask (STRMSK) and an end mask (ENDMSK). Output data. Thus, the initial value of the mask (AMSK) of the source data is always all ones. Similarly, the byte start address (BYTSTR) is always output as BYTSTR = 0 in the case of monochrome data. The tag block counter 40 receives the signal NMEX. The signal NXMEX is output from the controller 24. When the source data is monochrome data and the source mask value becomes 0, the next mask (all 1s) is loaded into the mask arithmetic circuit 23 and the tag block counter 40 is incremented. Output for If the source data is monochrome data, the tag block counter 40
Is updated by the signal NXMEX. When the tag block counter 40 is updated to the last block, the signal N
Outputs XMQD.

Next, the mask operation circuit 23 in the image data transfer device 2 will be described. Mask operation circuit 23
Are the destination, source, and pattern mask data AMSK (hereinafter referred to as DSTMS, respectively) mainly transmitted from the address counters 15, 16, and 17, respectively.
K, SRCMSK, and PATMSK. ) And the start address BYTSTR in each block (hereinafter referred to as DBBYTSTR, SBYTSTR, PBYTST, respectively)
Called R. The calculation for controlling the data transfer of the image display device 5 is performed based on (1) and the like. Each start address represents an address at which the mask at that time starts.

As shown in FIG. 19, each start address (FBS) of the destination, source and pattern
P) indicates an arbitrary address in the local memory 4. The mask arithmetic circuit 23 controls the transfer based on these addresses so that the destination, source, and pattern bytes are transferred one-to-one from the start byte of the transfer at the time of data transfer. .

FIG. 20 is a block diagram showing an internal configuration of the mask operation circuit 23. The mask operation circuit 23
Until there is no more sector data of the destination, source, or pattern transferred from the local memory 4 to the SRAMs 18 to 20, each SRAM 18,
A calculation for reading the data from 19 and 20 and outputting the data to the raster operation circuit 21 is performed.

First, as shown in FIG. 21A, the DSTM from the destination address counter 15
SK and SRCMS from source address counter 16
K and PATMS from the pattern address counter 17
K is input to the mask operation circuit 23, passes through each of the mask selectors 53, 54 and 55, and
6, 57, 58. On the other hand, the start addresses DBYTSTR, SBYTSTR, PBYTST in each block from the address counters 15, 16, 17 are described.
R is input to the subsequent subtractors 63, 64, 65, and 66 through the address selectors 60, 61, and 62.

The subtractor 63 comprises DSTMSK and SRCMS.
The address difference (SRCSFT) within one block where the K mask starts is calculated and output to the register 67. Similarly, the subtractor 65 calculates the address difference (PAT) in one block where the mask of DSATMSK and PATMSK starts.
SFT) is calculated and output to the register 69. Subtractor 6
The shifters 71 and 72 receive the address differences SRCSFT, PATSFFT and XDIR output from the registers 3 and 65 and stored in the registers 67 and 69, respectively. The start of the mask is D
Shift until it matches STMSK. The shift at this time is possible in both the positive and negative directions with respect to DSTMSK. Then, the result is output from the shifters 71 and 72 to the logical operation circuit 73 as adjusted mask data (SRCADJ, PATADJ), respectively. The logical operation circuit 73, as shown in FIG. 3A, receives the DSTMSK in addition to the mask data and calculates a logical product to determine a byte to be processed in the DSTMSK.

At the same time, the subtracters 64 and 66
1, 72 calculate the number of shifts (SRRCEV, PATREV) corresponding to the shift in the direction opposite to the direction shifted based on the address difference SRCSFT, PATFT, and output them to the registers 68, 70. The shifters 74 and 75 store the shift numbers SRCREV,
PATREV is input, and the output mask data (PRCMSK) from the logical operation circuit 73 is shifted by the above shift number to calculate a mask (SRCRMV, PATRMV). Output. The masks SRCRMV and PATRMV correspond to the source mask SRCM
The portion of SK and the pattern mask PATMSK that has contributed to the calculation of the destination mask DSTMSK is shown.

As shown in FIGS. 21 (c) and 21 (d), the source mask logical operation circuit 77 and the pattern mask logical operation circuit 79 use the parts corresponding to the masks SRCRMV and PATRMV from the source mask SRCMSK and the pattern mask PATMSK, respectively. To remove the mask of As a result, the mask (SR
CUDT, PATUDT) SRCMS to calculate next
These are updated as K and PATMSK, and they are stored in registers 57 and 58 through a source mask selector 54 and a pattern mask selector 55, respectively.
Further, both logical operation circuits 77 and 79 output signals (SRCZR, PATZR) indicating that the mask has become zero to the controller 24 when it is determined that the mask does not exist. This signal SRCZR and P
The controller 24 that has received the ATZR performs control so that mask data for one new block is stored in the registers 57 and 58 through the source and pattern mask selectors 54 and 55.

At this time, the controller 24 instructs the source and pattern address counters 16 and 17 to update the block,
The mask data for one new block output from the registers 6 and 17 is stored in the registers 57 and 58. At the same time that the mask data is stored in the registers 57 and 58, new start addresses SBYTSTR and PBYTSTR
Are input from the address counters 16 and 17 to the source and pattern address selectors 61 and 62, and then output to the subtracters 63 to 66 as described above as mask start addresses (SSTAD, PSTAD).

The source and pattern masks (SRCMSK, PATMSK) updated in this way are stored in the source priority encoder (SPRIENC) 8 respectively.
1, Pattern priority encoder (PPRIEN
C) The address S which is input to 80 and at which the mask starts
XUDT and PXUDT are calculated. If the updated mask is not zero, the source and pattern address selectors 61 and 62 use the previously calculated address SXU
DT and PXUDT are set to the mask start address SSTA
As D and PSTAD, SSTAD is subtractors 63 and 64
, And PSTAD outputs to subtracters 65 and 66, respectively.

On the other hand, as shown in FIG. 21B, the destination mask logical operation circuit 76 removes a portion of the input destination mask data DSTMSK that matches the PRCMSK from the logical operation circuit 73. The output is the stripped mask DSTU
DT is updated as DSTMSK to be calculated next,
The data is stored in the register 56 through the destination mask selector 53. This logical operation circuit 76
Also, when it is determined that the mask does not exist, a signal DSTZR indicating that the mask has become zero is output to the controller 24. Upon receiving the signal DSTZR, the controller 24 sets the destination address counter 15
To update the block, and output a new block of mask data. This mask data is input to the destination mask selector 53 and stored in the register 56.

The updated destination mask DSTMSK is input to a destination priority encoder (DPRIENC) 82, where an address DXUDT at which the mask starts is calculated.
If the updated mask is not zero, the destination address selector 60 determines whether the previously calculated address D
XUDT as a mask start address DSTAD,
Output to the subtractors 63 to 66, respectively.

In the mask operation process as described above, for example, the source mask becomes zero and the source S
When all the blocks in one sector transferred from the local memory 4 to the RAM 19 have been updated, the controller 2
4 controls so as to transfer the next sector data to the source SRAM 19. Also, the destination mask becomes zero and the destination SRAM 18
When the update of all the blocks in one sector transferred from the local memory 4 is completed, the controller 24 waits for the end of the raster operation by the raster operation circuit 21 and outputs the output F.
Control is performed to write the updated destination data stored in the IFO 22 to the local memory 4 and transfer the next sector data to the destination SRAM 18. Further, when the mask of the pattern becomes zero and the update of all the blocks in one sector transferred from the local memory 4 to the pattern SRAM 20 is completed, the controller 24 controls to transfer the next sector data to the pattern SRAM 20. I do.

At this time, the logical operation circuit 78 calculates a mask (SRCPRC) indicating a portion contributing to PRCMSK in the byte pattern of the source data.
This mask SRCPRC can be obtained by the following calculation. That is, if the byte with SRCPRC of zero does not contribute to PRCMSK, but the byte with SRCPRC of 1 assumes that it contributes to PRCMSK, then SRCPRC = SRCMSK & SR
It can be obtained as CRMV. This is used in the calculation of the enable flag in the subsequent raster operation circuit 21.

Next, each S in the image data transfer device 2
The color tag calculation processing performed in the RAMs 18 to 20 will be described. FIG. 22 is a block diagram showing a configuration of the source SRAM 19. Note that the destination SRA
M18 and pattern SRAM 20 are also basically the source S
Although the configuration is the same as that of the RAM 19, the destination SRAM 18 and the pattern SRAM 20 are not provided with the monochrome expansion device 96 and the associated selection circuits (MUX) 97, 98 for selecting color / monochrome data. In the pattern SRAM 20, a start byte register 90, a tag block register 91,
There is no tag calculation circuit 92, tag selection circuit 93, and transparent flag calculation circuit (TRP) 95.

A line address counter (CNTR) 85 in the source SRAM 19 (destination SRAM 18 and pattern SRAM 20) receives a block start signal (BL) from the corresponding destination, source and pattern address counters 15, 16 and 17, respectively.
KSTR) and block counter signal (BLKCNT)
Receive. These signals are also output to the memory controller 3 at the same time.

The memory controller 3 reads from the local memory 4 only the data designated by BLKCNT from the sector address SEC and the address designated by BLKSTR, and stores the data in a memory such as an SRAM (not shown) in the image display device 5. ) To transfer this data. This B
LKSTR starts the write address of the SRAM 88, data is transferred from the local memory 4 by the address given by BLKCNT from that address, and the transferred data is written to the SRAM 88. After the data is transferred to the SRAM 88, the data is read out this time. The reading of this data
This is performed based on the corresponding block address (BLK) sent from each of the address counters 15, 16, and 17.

At this time, the address of the SRAM 88 is determined by the BLK output from each of the address counters 15 to 17 by the selector 86 in accordance with an instruction from the controller 24.
The data for one block read from the SRAM 88 by the BLK is temporarily stored in the register 89, and if the data is color data, the data is sent to the subsequent stage via the selection circuit 97 and the register 94. Is transferred to the raster operation circuit 21 of FIG. In the case of monochrome data, one block of data read from the SRAM 88 is expanded into color data by the monochrome expansion device 96, and then the selection circuit 97 and the register 9 are read.
4 and is transferred to the raster operation circuit 21 at the subsequent stage.

At this time, each of the S
Calculations for transparent processing (transparency processing) are simultaneously performed in the RAMs 18 to 20. This will be described below.

The start byte register 90 keeps holding the byte address of the first FBSP of one line constituting the rectangular area while the processing of one line is continued. The tag block register 91 is a register that holds a tag block for each block, and is updated each time a block is processed. The output data BYTSTR of the start byte register 90 is supplied to the following tag calculation circuit (TAG).
TBL) 92 and the tag block register 91
Output data TGBLK of the tag selection circuit (MUX) 9
Access 3 The tag selection circuit 93 has a role of selecting one of the plurality of output data TAGTBL from the tag calculation circuit 92.

Here, as shown in FIG. 23, one pixel is composed of data of a maximum of 4 bytes, and a color tag (CT) of 0 to 3 is added to each byte of the pixel data of a maximum of 4 bytes. By definition, it can be seen that the color tag is 0 when one pixel is one byte. According to the figure, when one pixel is 2 bytes, the upper byte is 1 byte.
When the lower byte is 0 or 3 bytes, the upper byte is 2, 1,
It can be seen that in the case of 0 or 4 bytes, 3, 2, 1, 0 from the upper side.

This color tag, as shown in FIG.
It is allocated in order from the first byte specified by the start address FBSP, and is repeated in units of BPP up to the end address FBEP. Here, the maximum BPP is 4
Since the byte is a byte, the tag calculation circuit 92
It can be seen that the output of the color tag of ^W × 4 bytes.
Since 2 ^W bytes of data are processed at the same time, assuming that a color tag for every 2 ^W bytes is a tag block TGBLK, the configuration is defined as shown in FIG.

The relationship between the color tag, the tag block, and the BPP defined in this manner is determined by the output T of the tag calculation circuit 92.
Considering AGTBL, it will be as shown in FIGS. Note that the lower bits W in this case are W = 3.

As shown in FIG. 26A, the value of the color tag when the BPP is 1 byte is always zero. BPP
Is 2 bytes, the value of the color tag is the LSB (Les
ast Significant Bit / Byte). XDIR =
0 and BYTSTR [0] = 0 or XDIR = 1
(B) when BYTSTR [0] = 1 and BYTSTR [0] = 1 when XDIR = 0, or when BYTSTR [0] = 0 when XDIR = 1. The result is as shown in FIG.

When the BPP is 3 bytes, the value of the color tag is determined by the XDIR and the 3 bits on the LSB side of the byte portion BYTSTR of the start address as shown in FIG. When XDIR = 0, BYTSTR [2: 0] =
BYTSTR when 0, 3, 6 or XDIR = 1
When [2: 0] = 1, 4, 7 as shown in FIG. 7A, when XDIR = 0 and BYTSTR [2: 0] = 2,5, or when XDIR = 1, BYTSTR [2: 0] =
In the case of 0, 3, and 6, as shown in FIG.
= 0 and BYTSTR [2: 0] = 1,4,7, or XDIR = 1 and BYTSTR [2: 0] = 2,5 are defined as shown in FIG.

Further, when the BPP is 4 bytes, the value of the color tag is XDIR and BYTST as shown in FIG.
It is determined by the two LSB bits of R. XDIR = 0 and B
When YTSTR [1: 0] = 0, or when XDIR = 1 and BYTSTR [1: 0] = 3, as shown in FIG. 7A, when XDIR = 0 and BYTSTR [1: 0] = 3. Or BYTSTR [1: 0] = 2 with XDIR = 1
In this case, the result is as shown in FIG. Similarly, XDI
When R = 0 and BYTSTR [1: 0] = 2, or XD
When IR = 1 and BYTSTR [1: 0] = 1, as shown in FIG.
BYTST when [1: 0] = 1 or XDIR = 1
When R [1: 0] = 0, they are defined as shown in FIG.

TAGTB which is the output of the tag calculation circuit 92
L is input to the tag selection circuit 93, where the portion designated by TGBLK calculated by the color tag calculation counter 40 in the destination and source address counters 15 and 16 is selected and becomes a color tag (CT). . The color tag is 2 ^W data composed of 2 bits, and indicates a color tag of each byte data in one block. This color tag is output to a transparent calculation circuit (TRP) 95 for transparent calculation.

Next, the monochrome extension device 96 will be described. The monochrome expansion device 96 expands the number of bits of each pixel when the source data is monochrome data, and a byte address register (BYTR)
EG) 101 and a byte data selection circuit (PXLMU)
X) 102 and a data extension circuit (BYTEXT) 103
, A block selection circuit (BLKMUX) 104, and a color output circuit (COLEXP) 105.

The byte address register 101 is a register for storing the byte address BYT from the source address counter 16. When the source is monochrome data, the source address counter 16 at the preceding stage is incremented in byte units.
Stores an address indicating which byte of 2 ^W bytes (8 bytes in the illustrated example) of data output from the local memory 4. The byte data selection circuit 102 outputs 2 ^W bytes of color output data to the byte address BYT stored in the byte register 101.
This is a circuit for selecting by. FIG. 29 shows further details of the monochrome extension device 96. The byte data selection circuit 102 outputs the 2
^{Of the W-} byte read data RDT [63: 0], only one byte specified by the byte address BYT is selected and output to the subsequent stage. By incrementing the source address counter 16 by one byte, the byte data selection circuit 102 sequentially selects the read data RDT one byte at a time and outputs it to the subsequent stage.

The data extension circuit 103 extends monochrome 1-bit data from 1 bit to 4 bits based on BPP designation. FIG. 30 shows this expansion. The data extension circuit 103 inputs one-byte data selected by the byte address BYT in the read data RDT. This 1-byte (8-bit) data is expanded to a maximum of 32 bits by BPP and output as an expanded byte BYTEX. Since the 8-bit data is monochrome data, 0 indicates a background color and 1 indicates a foreground color. When BPP = 1, 8-bit data is output as BYTEX as it is. In the case of BPP = 2,
As shown in FIG. 30, the data of each bit of the 8-bit data is copied two bits at a time, and is expanded as a whole into 16-bit data BYTEXT. In the figure, [0]
[0] indicates that the data (0 or 1) of the input bit [0] has been copied into 2 bits. The two copied bits indicate the same pixel. Similarly, when BPP = 3, one bit of the input is copied to three bits and the B bit of 24 bits is copied.
When YTEXT is output and BPP = 4, one bit of the input is copied to 4 bits, and 36 bits of BYTEX are output.
Is output.

The block selection circuit 104 selects a portion (8 bits) specified by the tag block TGBLK from the monochrome data BYTEX extended by the data extension circuit 103, and outputs the monochrome output block MONF.
The signal is output to the next-stage color output circuit 105 as LG. FIG. 31 shows the relationship between the extended bit data, the tag block TGBLK, and the color tag CT. If BPP = 1,
Assuming that TGBLK = 0, the entire 8-bit BYTEX is selected and output. If BPP = 2, TGBLK =
When 0, the lower 8 bits of the 16-bit BYTEX are selected, and when TGBLK = 1, the upper 8 bits are selected.
The same applies hereinafter.

As shown in FIG. 32, when the bus width 2 ^W is 8 bytes, the color output circuit 105
Color expansion units (COL_EXP_UNIT)
It is composed of 110-117. One bit of the expanded 1-bit monochrome data MONFLG is input to one color expansion unit 11n, and converted into 1-byte color component data MONEX for output. Each color expansion unit 11n refers to whether the expanded monochrome data MONFLG is 0 or 1 and the color tag CTnC corresponding to the expanded monochrome data MONFLG, and determines an appropriate one of the foreground color or the background color stored in the register in advance. Choose the ingredients. The color expansion unit 11n includes a background selection circuit (BGMUX) 118a for selecting a background color component,
It comprises a foreground selection circuit (FGMUX) 118b for selecting a foreground color component and a BG / FG selection circuit (BFMUX) 119 for selecting output data. The background selection circuit 118a and the foreground selection circuit 118b respectively generate an 8-bit component of the 32-bit color data constituting the background color and the foreground color according to the values of the corresponding color tags CT0C to CT7C. select. The BG / FG selection circuit 119 selects a background color component when the monochrome data MONFLG is 0, and sets the monochrome data MONFLG to 1
In the case of, the foreground color component is selected. BG
The output MONEX of the / FG selection circuit 119 is input to a selection circuit (MUX) 97 for selecting color / monochrome data, which switches between color data and monochrome data and outputs the same.
Transferred to 1. The output MONEX of the BG / FG selection circuit 119 is also input to a transparent calculation circuit (TRP) 95 via a similar selection circuit 98.

Next, the transparent calculation circuit 95 will be described. Transparent processing is processing that does not update a pixel when the pixel value matches a predefined transparent color.
Specifically, when the source pixel value matches the source parent color, the pixel is not updated or the destination pixel value is overwritten. If the pixel value of the destination matches the destination color, the pixel is not updated or the pixel value of the destination is overwritten.

FIG. 33 is a diagram showing the internal configuration of the transparent calculation circuit 95. The transparent calculation circuit 95 mainly includes the FG / BG selectors 120 and 2W
Selectors 121-126, 2W comparators 127-
132,2 ^W number of registers 133～138,2 ^W number of arithmetic units 139 to 144, and a register 145 and R / L selector 146. The 2 ^W selectors, comparators, registers, and arithmetic units are provided corresponding to the respective byte data in one block.

The FG / BG selector 120 also sends the background color (FG: foreground color) of the transfer destination area and the background color (BG: background color) of the transfer source area sent from an interface (not shown). Transparent color data (FGT
R) to make a selection and determine which is the transparent color. As a result, the output TRCOL of the FG / BG selector 120 becomes a new transparent color. The transparent calculation circuit 95 compares the pixel data stored in the destination area or the source area with the transparent color on a pixel-by-pixel basis. If the result is the same, the pixel data is determined to be transparent, as shown in FIG. (TRPF) to prevent the data from being rewritten with new data.

The TRCOL output from the FG / BG selector 120 has a maximum of 4 bytes according to the definition of BPP. Each of the selectors 121 to 126 has a color tag (CT0).
ＣＴCT2 ^W -1), the byte component constituting TRCOL is selected by the value of the color tag, and each of the comparators 127 to 13 is selected.
Output to 2. In response, each of the comparators 127 to 132
Compares the output data (RDT) from a memory (not shown) with the selected transparent color component on a byte-by-byte basis, defines 1 if they are equal, and 0 if they are not equal, and outputs a comparison result NEQ. Each register 13
3 to 138 temporarily store the NEQ and color tag (CT) corresponding to the result compared by the comparators 127 to 132, and output the stored NEQ and CT as CEQ and CCT of the current data. I do. Register 145
Holds the current comparison result CEQ and outputs them to the R / L selector 146 as PEQ.

Here, as shown in FIG. 34, the direction approaching the zero byte of the byte address in one block
Assuming that the direction approaching ^W- 1 byte is right, since the maximum of the BPP is 4 bytes, refer to the comparison results of each of the comparators 127 to 132 for a maximum of 3 bytes left and right including the current color tag. Then, it can be determined whether the pixel is equal to the color given as transparent.

At this time, the byte data in one pixel may extend between blocks.
As shown in FIG. 5, the comparison results of the block data immediately before or after the block currently being processed by the comparators 127 to 132 are referred to.

Further, the PEQ is a comparison result of each of the comparators 127 to 132 of the block processed immediately before the current processing, and the NEQ is processed one after the current processing. The comparison result is obtained by each of the comparators 127 to 132 of the block. The left and right adjacent three bytes for each byte from the zero byte to the 2 ^W -1 byte of the comparison result CEQ in each of the comparators 127 to 132 in the current process can be represented as shown in FIG.

As is clear from Tables (a) and (b) of FIG. 36, left3, left2,
left1 and left3, left for CEQ1
2, left3 for CEQ2, and CEQ2 ^W −3
And ri for CEQ2 ^W -2
ght3, right2, and r for CEQ2 ^W −1
right3, right2, right1 are XDI
It depends on R.

The R / L selector 146 is connected to the NEQ,
Input and select PEQ and XDIR, select the appropriate one
^{EQ2 W -1, CEQ2 W -2,} CEQ2 W -3, CEQ
2, CEQ1 and CEQ0 are output to the computing units 139 to 144. Each of the computing units 139 to 144 can know from the input CCT and BPP which of the left and right comparators 127 to 132 should refer to the comparison result. For example, when the BPP is 1, it can be said that the comparison result of each of the comparators 127 to 132 from the zero byte to 2 ^W -1 byte indicates whether or not it is transparent as it is. At this time, if it is 0, it is not transparent, and if it is 1, it can be said that it is transparent.

For example, as shown in FIG.
When P is 2, referring to the comparison result of each of the comparators 127 to 132 for each byte left and right with respect to the current processing, it is determined whether the left or right comparison result should be referred to during the current processing. Determined by the value of the color tag. If the color tag of the current process is zero, the right byte is the same pixel, and if the color tag of the current process is 1, the left byte is the same pixel. If each comparator 1
If the comparison results at 27-132 are both 1, then this pixel can be said to be transparent. FIG. 37 shows that the portion other than the white background is the same pixel.

When the BBP is 3, each of the comparators 127 to 13 has a maximum of 2 bytes left and right with respect to the current processing.
Reference is made to the comparison result in 2. If all the comparison results of the same pixel portion in each of the comparators 127 to 132 are 1, this pixel can be said to be transparent.

Further, when the BPP is 4, the comparators 127 to 13 each have a maximum of 3 bytes left and right for the current processing.
Reference is made to the comparison result in 2. In this case as well, if all the comparison results of the comparators 127 to 132 of the same pixel portion are 1, it can be said that this pixel is transparent. As described above, each comparator 12
The results calculated in 7 to 132 are output to the raster operation circuit 21 as TRPF.

Finally, the raster operation circuit 21 in the image data transfer device 2 will be briefly described. FIG.
FIG. 3 is a diagram showing an internal configuration of a raster operation circuit 21. The raster operation circuit 21 performs a raster operation on data read from the destination, source, and pattern SRAMs 18, 19, and 20.

The raster operation circuit 21 mainly includes the source SRA
SB shifter 150 for shifting one block of data from M19 in units of byte data, pattern SR
The data of one block from AM20, likewise byte data shift to PB shifter 151,8 executes raster operation of the bit 2 ^W pieces of 8-bit raster operation circuit 1521~152n units is calculated according to the data of the write enable Enable data calculation circuit 153, shifter (not shown) for shifting the source transparent flag, and 2 ^W registers 1541 to 154 for storing the result of the raster operation in enable data calculation circuit 153
54n and the like.

First, 2 ^W- byte destination data read from the destination SRAM 18 is stored in the corresponding 8-bit raster operation circuit 1521.
To 152n. The 2 ^W byte source data read from the source SRAM 19 is equivalent to the address difference SRCSFT in one block, which is the shift data calculated by the mask operation circuit 23, and is equivalent to the SB shifter 15.
The data is shifted in units of bytes at 0, and is made to correspond to the destination data. Similarly, the pattern SRAM 20
The 2 ^W- byte pattern data read from the PB shifter 151 is also shifted in bytes by the PB shifter 151 by an amount equal to the PASSFT calculated by the mask operation circuit 23, and is made to correspond to the destination data. The 8-bit raster operation circuits 1521 to 152n perform a raster operation on these destination, source, and pattern data in accordance with a designated code, and store the result in a register 154.
1 to 154n. At this time, the mask operation circuit 2
3 is stored in each register 1541 to 1
54n is input and stores only data for which PRCMSK becomes 1.

The enable data calculation circuit 153 includes a transparent flag (DTRPF) from the destination SRAM 18, a transparent flag (STRPF) from the source SRAM 19, and SRCPRC, SRCSFT, and PRCMSK from the mask operation circuit 23.
And so on. Based on these pieces of input information, the enable data calculation circuit 153 calculates an enable flag EN that determines whether or not writing to the local memory 4 is performed for each byte data. In the case of the transparent state, the enable flag EN is changed so that writing to the local memory 4 is not performed and the previous value is maintained in the local memory 4 as it is.

The output FIFO 22 at the subsequent stage of the raster operation circuit 21 has the registers 1541 to 1541 when the raster operation of all the byte data in one block is completed.
The result stored in 154n is written to its own memory (not shown). When all the data for one sector of the destination has been written to the memory in the output FIFO 22, the data for one sector is continuously output to the memory controller 3 and the data is written to the local memory 4. Of the transfer.

Finally, a specific processing example when the source data is given as monochrome data will be described. Assuming that one sector is composed of 8 blocks and one block is composed of 8 bytes, and BPP = 3, transfer of monochrome data of 16 pixels × 16 lines indicated by “x” shown in FIG.

The interface 11 receives the parameters of the destination data of the transfer destination and the parameters of the monochrome source data, and stores the data in the registers corresponding to the monochrome source address calculation circuit 132 in the destination address calculation circuit 12 and the source address calculation circuit 13. Is set. The calculated destination address (start address and end address) and source monochrome address (start address and end address) are transferred to the destination address counter 15 and the source address counter 16. Thereafter, under the control of the controller 24, the local memory 4 is accessed using the address from the destination address counter 15, and the sector including the data of the first line is stored in the destination SRAM.
Transfer to 18. If all data cannot be transferred to the destination SRAM 18, the transfer is repeated in sector units. Similarly, the first one line of monochrome data is also transferred to the source SRAM 19.

After both the destination data and the source data have been transferred from the local memory 4, the SRAM 1
8 and 19 are read. The data marked with a cross are shown in FIG.
(B). For example, it is assumed that monochrome source data indicated by x is stored from address A000004 outside the display area of the local memory 4 as shown in the figure. The source address counter 16 resolves the address A000004, and
Is set to BYT = 4, 0 is set to the block address register 33, and 280000 is set to the sector address register 32. The start address (BYTSTR) in the block where the mask starts is BYTST
R = 0. The color tag calculation counter 40 has a TG
BLK = 0 is reset. The source data mask (AMSK) is 11111111, which is output to the mask operation circuit 23 as a source mask pattern.

From the SRAM 88 in the source SRAM 19, data for one block is read at a time. The read data is input to a byte data selection circuit (PXLMUX) 102 of the monochrome extension device 96, and 1-byte data of a corresponding portion is selected by the byte address BYT output from the source address counter 16. In the case of the figure, 80 data having an address of 4 in the block is output. Byte data selection circuit (PXLM
The output from the UX 102 is a data extension circuit (BYTE).
XP) 103. Here, the 1-byte data 80 is extended to BPP = 3 data. Therefore, one byte of data 80 (10000000) becomes 1
11 000 000 000 000 000 000 000 000
It is expanded to 00 and 3-byte data. The block selection circuit (BLKMUX) 104 selects a portion (1 byte) indicated by the color tag calculation counter 40 from the expanded 3-byte data, and outputs this as a monochrome output block MONFLG. In this case, when TGBLK = 0, 1110000 is selected and input to the color output circuit (COLEXP) 105.

The color output circuit 105 has a color tag C operating in synchronization with the color tag calculation counter 40.
T0C to CT7C are input. Color tag CT0C ~
The CT7C has a corresponding color expansion unit 110-11.
7 is input to the foreground selection circuit 118b and the background selection circuit 118a, and outputs 1-byte components constituting the foreground color and the background color stored in advance. Color tag C
The data of T0C to CT7C are in order of 01201201.
Becomes It is assumed that 0 of the output block MONFLG corresponds to the background color and 1 corresponds to the foreground color. FG [23: 0] foreground color
= 123456h, background color is BG [2
3: 0] = 789ABCh, the color expansion unit (# 0) 110 outputs 0 for the color tag CT0C and 1 for the output block MONFLG, and outputs 56 of the foreground color component. These are shown in the table in FIG.
It becomes as follows.

As shown in the table of FIG. 40, correctly assigned foreground color components and background color components are output from the monochrome extension device 96 via the selection circuit 97.

The output data is supplied to the mask operation circuit 23.
Is controlled by Source mask data is 000000
When it becomes 00, the color tag calculation counter 40 in the source address calculation circuit 13 is incremented, and at the same time, the mask of 11111111 is newly loaded into the mask calculation circuit 23 as a source mask. At the same time, the block selection circuit 1 in the monochrome extension device 96
The value of the tag block TGBLK input to 04 becomes 1, and the color tags CT0C to CT7C are also updated. Output block MON output from block selection circuit 104
The FLG becomes 1-byte data (00000000) in the middle of the extended 24 bits [FIG. 40.
(B)].

Similarly, if the source mask data is 00000
000, the source address calculation circuit 13
Is incremented, and at the same time, the mask 11111111 is newly loaded into the mask operation circuit 23 as a source mask. At the same time, the block selection circuit 1 in the monochrome extension device 96
The value of the tag block TGBLK input to 04 becomes 2, and the color tags CT0C to CT7C are also updated. The output block MONFLG becomes the last one-byte data (0000000000) of the expanded 24 bits [FIG. 40 (c)].

In this state, when the source mask becomes 0,
The signal NXMQD is sent from the color tag calculation counter 40 in the source address calculation circuit 13 to the address update circuit 31. As a result, the address update circuit 31 is incremented by one byte. Address update circuit 31
Is incremented, the byte address register 101 of the monochrome expansion device 96 stores BYT =
5 is set. BYT = 5 newly set in the byte address register 101 is input to the byte data selection circuit 102, and 1-byte data corresponding to the data output from the SRAM 88 is selected. In this case, data of 01 in the block whose address is 5 is output.

Hereinafter, the same processing is performed. When the processing of one line is completed, the address of the next line is calculated by the destination address calculation circuit 12 and the source address calculation circuit 13. As in the first line, the destination SRAM 18 from the local memory 4
Data is transferred to the source SRAM 19. As a result, the source address counter is updated to the address A000006. BYT is stored in the byte address register 101.
= 6 is set. The byte data selection circuit 102 in the source SRAM 19 selects 1-byte data of a corresponding portion based on the BYT of the data read from the SRAM 88. Data “40” of address 6 in the block
Is output. By repeating the above, the monochrome source data is expanded to the designated destination.

[0125]

As described above, according to the present invention,
When calculating and transferring the image data of the transfer area stored in the image data storage device based on the parameters related to the designated transfer source and transfer destination area,
Assuming that a pixel is image data composed of one or a plurality of bytes, image data is transferred in units of a block composed of a plurality of bytes larger than the image data of one pixel, and the position within the block is aligned in the transfer area and calculated. By executing the processing, high-speed transfer of image data is possible, and the image data in the transfer source area is monochrome image data in which one pixel is composed of 1 bit. One pixel of the area is set to one of two colors of data set in advance according to the bit value.
Since the image data is expanded to one or a plurality of bytes representing a color, the data amount of the image data in the transfer source area stored in the image data storage unit can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a basic configuration of an image display processing system according to an embodiment of the present invention.

FIG. 2 is a diagram schematically showing functions of an image data transfer device in the system.

FIG. 3 is a diagram showing an outline of monochrome transfer of the image data transfer device in the same system.

FIG. 4 is a block diagram showing a detailed configuration of the device.

FIG. 5 is a block diagram showing a main part of a source address calculation circuit in the same device.

FIG. 6 is a flowchart showing an operation of the apparatus.

FIG. 7 is a diagram showing in more detail a rectangular (display) area of image data including a transfer rectangular area in the same device.

FIG. 8 shows XDIR, Y of a transfer rectangular area in the same device.
It is a figure which shows DIR schematically.

FIG. 9 is a diagram illustrating a configuration of monochrome image data in the device.

FIG. 10 is a diagram showing a configuration of image data constructed in a local memory in the device.

FIG. 11 is a diagram for explaining expansion of monochrome image data.

FIG. 12 is a diagram showing a basic configuration inside an address counter in the same device.

FIG. 13 is a diagram for explaining sector data stored in a sector address register inside the counter.

FIG. 14 is a diagram showing sector data stored in a sector address register inside the counter.

FIG. 15 is a diagram for explaining the configuration of each data at the time of mask calculation processing inside the counter.

FIG. 16 is a diagram for explaining a result of a mask calculation process inside the counter.

FIG. 17 is a diagram showing an initial value and an update pattern of a color tag calculation counter inside the counter.

FIG. 18 is a diagram illustrating a relationship between a tag block and an address update signal during monochrome image data processing.

FIG. 19 is a diagram showing a configuration in a local memory of each start address of a destination, source, and pattern in the same device.

FIG. 20 is a block diagram showing an internal configuration of a mask operation circuit in the same device.

FIG. 21 is a diagram for explaining processing of each data in a mask operation circuit in the same device.

FIG. 22 is a diagram showing an internal configuration of each SRAM in the same device.

FIG. 23 is a diagram illustrating a data configuration of a color tag calculation process in each SRAM in the same device.

FIG. 24 is a diagram for explaining a data configuration of the same processing.

FIG. 25 is a diagram illustrating a data configuration of the same processing.

FIG. 26 is a diagram showing a relationship among a color tag, a tag block, and a BPP in the same processing.

FIG. 27 is a diagram showing a relationship among a color tag, a tag block, and a BPP in the same processing.

FIG. 28 is a diagram showing the relationship between a color tag, a tag block, and a BPP in the same color tag calculation process.

FIG. 29 is a detailed functional block diagram of a monochrome extension device in the device.

FIG. 30 is a diagram for explaining a bit extension operation of the monochrome extension device.

FIG. 31 is a diagram illustrating a data extension operation of the monochrome extension device.

FIG. 32 is a detailed block diagram of a color extension unit of the monochrome extension device.

FIG. 33 is a diagram showing an internal configuration of a transparent calculation circuit in each SRAM.

FIG. 34 is a diagram illustrating a data configuration of a transparent calculation process in the same circuit.

FIG. 35 is a diagram for explaining a data comparison method in the same process.

FIG. 36 is a diagram illustrating a configuration of a comparison result of data in the same process.

FIG. 37 is a diagram showing a comparison result of data in the same process.

FIG. 38 is a diagram showing an internal configuration of a raster operation circuit in the same device.

FIG. 39 is a diagram illustrating monochrome image data and a storage state of the monochrome image data in a memory, showing an example of processing of monochrome data by the same device.

FIG. 40 is a table showing extended data of the monochrome data.

FIG. 41 is a block diagram illustrating a configuration of a conventional image display processing system.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... Image data transfer device, 3 ... Memory controller, 4 ... Local memory, 5 ... Display device, 11 ...
Interface, 12: destination address calculation circuit, 13: source address calculation circuit, 14: pattern address calculation circuit, 15: destination address counter, 16: source address counter, 17 ...
Pattern address counter, 18: destination SRAM, 19: source SRAM, 20: pattern SR
AM, 21: raster operation circuit, 22: output FIFO, 2
3. Mask operation circuit, 24 Controller.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 5/02 G09G 5/00 555J

Claims (10)

[Claims] An arithmetic processing unit configured to calculate image data of the transfer source area and image data of the transfer destination area stored in an image data storage device based on parameters regarding a designated transfer source area and a transfer destination area; In the image data transfer apparatus for transferring data to a transfer destination area, the image data of the transfer source area is monochrome image data in which one pixel is composed of one bit, and the image data of the transfer destination area is one or more pixels. An address counter for reading image data in blocks larger than one pixel of image data from the transfer source area and the transfer destination area of the image data storage means; and The read image data of the block unit is stored and one pixel of the transfer source area is set to the A data storage unit with a data extension function for extending image data composed of one or more bytes representing one of two colors of data set in advance according to the following: An image data transfer device comprising: an arithmetic unit for performing the arithmetic processing by performing position adjustment in a block between the image data and the image data of the transfer destination area. 2. A transfer start block address and transfer for each scanning line including the transfer source area and the transfer destination area, based on the parameters related to the specified transfer source area and transfer destination area and the number of bytes per pixel. An address calculating means for calculating an end block address and setting the same in the address counter, wherein the address counter continuously transfers the image from a transfer start block including a transfer start block address to a transfer end block including the transfer end block address. 2. The image data transfer device according to claim 1, wherein the image data is transferred. 3. The address counter generates a mask pattern for masking an area other than the source area and the destination area based on a transfer image start byte address and a transfer image end byte address in each block. 3. The image data transfer device according to claim 1, further comprising a mask calculation unit that performs position alignment within the block between the transfer source area and the transfer destination area using a mask pattern. 4. The image data of one pixel has a color tag set for each byte, and the address counter determines a color tag of each byte based on a transfer image start byte address in the block. 4. The image data transfer apparatus according to claim 1, wherein the image data is set. 5. The data storage means copies 1-bit data of each pixel of the transfer source area according to the number of bytes of each pixel, sets a color tag for each bit after the copy, and sets the color tag in advance. And monochrome image expansion means for expanding image data by allocating a byte specified by the color tag among color pixel data of one or more bytes representing one color of the two-color data thus obtained. 5. The image data transfer device according to claim 4, wherein: 6. An image data storage device for storing image data, a central processing unit for outputting parameters relating to a source area and a destination area of the image data stored in the image data storage device, and a central processing unit. After performing arithmetic processing on the image data of the transfer source area and the image data of the transfer destination area stored in the image data storage device based on the parameters related to the transfer source area and the transfer destination area outputted from the transfer destination area, An image display processing system comprising: an image data transfer device for transferring; and an image display device for displaying image data stored in the image data storage device. In the configured monochrome image data and the image data of the transfer destination area, one pixel includes one or more bytes. The central processing unit outputs the number of bytes constituting the one pixel to the image data transfer device, and the image data transfer device outputs a block unit larger than the one-pixel image data. Transferring the image data, and extending one pixel of the transfer source area to image data composed of one or more bytes representing one of two colors of data set in advance according to the bit value; The image data of the extended transfer source area and the image data of the transfer destination area are aligned in a block, the arithmetic processing is performed, and the image data is stored in the image data storage device. Image display processing system. 7. The image data transfer apparatus according to claim 1, wherein each of the scan lines including the transfer source area and the transfer destination area is performed based on the designated parameters regarding the transfer source area and the transfer destination area and the number of bytes per pixel. Calculating a transfer start block address and a transfer end block address, and continuously transferring the image data from a transfer start block including the transfer start block address to a transfer end block including the transfer end block address. 7. The image display processing system according to claim 6, wherein: 8. The image data transfer device generates a mask pattern for masking an area other than the source area and the destination area based on a transfer image start byte address and a transfer image end byte address in each block. 8. The image display processing system according to claim 6, wherein said mask pattern is used to perform positioning within said block between said source area and destination area. 9. The image data for one pixel has a color tag set for each byte, and the image data transfer device performs a color image processing for each byte based on a transfer image start byte address in the block. The image display processing system according to claim 6, wherein a tag is set. 10. The image data transfer apparatus copies 1-bit data of each pixel in a transfer source area according to the number of bytes of each pixel, sets a color tag for each bit after the copy, and sets a color tag in advance. The image data is extended by allocating a byte specified by the color tag among color pixel data of one or more bytes representing one color of the set two-color data. The image display processing system according to claim 9.