JP2002358503A - Signal processing circuit and pattern recognizing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a large scale of hierarchical parallel processing by a small scale of circuit configuration. SOLUTION: In a parallel processing circuit configuration which comprises a plurality of analog processing elements, analog signal processing elements AB and switch elements SW are arrayed on a prescribed grid, the turning on/off of the switch elements SW or the signal modulation amount of the analog signal processing elements AB is controlled and, then, different signal processing functions are realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog / digital hybrid type signal processing circuit technology capable of changing a circuit configuration according to processing contents.

[0002]

2. Description of the Related Art Conventionally, an FPGA has been provided as a logic IC that allows a user to configure an arbitrary logic.

An FPGA is configured by regularly arranging a plurality of relatively large circuit blocks and wiring blocks on a chip. A large number of "programmable devices" for electrically connecting or disconnecting circuits are arranged inside the circuit block and the wiring block. The user can program (define) these devices to establish connections between blocks and between blocks. The circuit can be designed in the field (use site). Cell library blocks having various logic circuits are arranged in a matrix in a chip, and horizontal, horizontal and vertical lines are placed between these cell library blocks.
Signal wiring is provided in the vertical direction. A switch element is provided between the intersections of these wirings and between the wirings.

[0004] The following three systems are employed as switch elements. (1) A method in which an amorphous Si is sandwiched between metal wirings to be insulated as initials, a current flows between desired metal wirings, and this insulating film is broken to short-circuit (anti-fuse method). (Fuse method), which is short-circuited by laser or the like and cut by laser or the like. (2) A normal MOS transistor is used as a switching element,
A method in which the potential state of the gate is stored in a memory. As the memory, there are a memory using a volatile DRAM, an SRAM, or the like, a memory using a nonvolatile EEPROM, and a memory using a ferroelectric memory (FRAM) has been proposed. Volatile ones have the disadvantage that the logical connection and wiring connection information must be imported into the FPGA every time they are used, but Reconfigurab allows information to be changed any number of times.
le Logic. In contrast, the non-volatile ones
There is an advantage that the logical connection and wiring connection information can be maintained even when the power is turned off / on. (3) The switch element itself is composed of an EEPROM or the like,
A method of storing ON / OFF information of a transistor.

When designing a logic system using an FPGA, a desired logic function is converted to an HDL (Hardware Description Lan) using a support tool or the like provided by an EDA vendor.
guage) and logic circuit data using logic synthesis tool (type of logic gate used and information on connection between terminals, etc.)
Get. The logic operation control data of the basic logic cell CLB and the connection data between the CLBs are obtained so as to realize the logic circuit obtained here, and the wiring to be used and the ON / OFF control of the cross point switch CSW are determined from the connection data. The data is determined to construct an overall logic circuit system. Such a logical design can be easily executed by a user, and its convenience has been widely recognized.

On the other hand, as a method of applying an FPGA and reconfigurablely connecting analog processing elements, Japanese Patent Application Laid-Open No. H11-168
A configuration disclosed in Japanese Patent Application Laid-Open No. 185-185 and Japanese Patent Application Laid-Open No. 2000-331113 is known. In the former, an FPGA is formed on one side of a laminated substrate, an analog processing circuit is formed on the other side, and an input / output terminal and an interface circuit for connecting the two are provided. In the latter, after converting the first and second analog signals into pulse width modulation (PWM) signals, both signals are input to the FPGA circuit, and the two PWM signals are input to the FPGA circuit.
By performing a logical operation on the signal, the signal can be reconfigured.

[0007] The hierarchical neural network disclosed in Japanese Patent No. 2679730 discloses a hierarchical neural network architecture that enables a single-layer hardware to be multi-layered using time division multiplexing. The purpose of the present invention is to enable time-division multiplexing of the hardware of a neural network. It is possible to generate the product of the signal and the digital weight data from the outside, integrate the product by adding it in a time-division manner via a capacitor, and output the voltage through the nonlinear output function in a time-division manner. A single-layer unit collecting means for forming a single-layer unit set by installing a plurality of units of the neuron model Feedback means for returning the output of the unit aggregation means to the input unit of the same single-layer unit aggregation, time-division multiplexing of analog signals from each unit output from the single-layer unit aggregation means, and further via the feedback means Control means for executing control for time-division multiplexing of the single-layer unit assembling means, and a time-division multiplexing of the single-layer unit assembling means to equivalently form a hierarchical neural network It is constituted so that.

An FPAA (Field Programma) according to US Pat.
In a ble Analog Array) circuit, programmable analog processing cells including a multiplexer, a demultiplexer, a control circuit, and analog processing elements are arranged in parallel via signal lines to perform a programmable analog processing operation.

[0009]

In the above conventional example,
All so-called FPGAs have a configuration based on a logic circuit. That is, only the connection state between logical blocks is variable. Therefore, it was not possible to implement a neural network or other analog parallel arithmetic processing using only an FPGA.

When the configuration according to Japanese Patent Application Laid-Open No. 11-168185 is applied to a neural network, the number of input / output terminals increases exponentially as the number of neural elements increases, which makes handling difficult. Therefore, there are problems that it is difficult in principle to set an arbitrary wiring structure, and a special process for mounting on a laminated substrate is required. Further, in the configuration disclosed in Japanese Patent Application Laid-Open No. 2000-331113, even if a pseudo addition circuit or a pseudo integration circuit of two analog signals can be basically formed,
There is a problem that it is difficult to realize a large-scale parallel hierarchical processing circuit similarly.

On the other hand, the hierarchical neural network disclosed in Japanese Patent No. 2679730 does not have means for arbitrarily variably controlling the interlayer coupling, so that the types of processing that can be substantially realized are extremely limited. There was a problem of becoming.

In the configuration according to US Pat. No. 5,598,971, each analog processing unit (cell) has a control circuit, an analog processing circuit element, a signal branch circuit, and the like.
The circuit scale of circuit components (analog processing cells) has become very large, and the overall circuit area has to be very large. Also, with a structure in which analog processing units incorporating a multiplexer and a demultiplexer are arranged in a two-dimensional plane, it has been difficult to realize an arbitrary connection structure, particularly a hierarchical connection.

[0013]

According to an aspect of the present invention, an arithmetic processing circuit, a circuit configuration information storage means for storing circuit configuration information, and a signal read from the circuit configuration information storage means are provided in a signal processing circuit. Circuit configuration control means for outputting a predetermined control signal to the arithmetic processing circuit based on circuit configuration information, wherein the arithmetic processing circuit includes a plurality of switch block means each including a plurality of switch elements and a plurality of signal lines. Analog processing block means for performing predetermined signal modulation on an input signal, and a signal line connecting between the switch block means or the analog processing block, wherein the circuit configuration control means turns on the plurality of switch element operations;
By controlling an off pattern or a signal modulation amount in the analog processing block means, the arithmetic processing circuit is caused to execute a plurality of different signal processing functions.

According to another aspect of the present invention, the signal processing circuit includes an arithmetic processing circuit, circuit configuration information storage means for storing circuit configuration information, and circuit configuration information read from the circuit configuration information storage means. A circuit configuration control unit that outputs a predetermined control signal to the arithmetic processing circuit, wherein the arithmetic processing circuit includes a plurality of switch block units, and a plurality of first and second types of analog processing block units, respectively. Are connected in a predetermined pattern by a predetermined signal line, and the first type of analog processing block means includes:
Applying a predetermined modulation to a signal from the second type of analog processing block means, wherein the second type of analog processing block means integrates signals from the first type of multiple analog processing block means; The switch block means has a plurality of switch elements and a plurality of signal lines, and the circuit configuration control means controls the on / off pattern of the plurality of switch element operations or the analog processing block. By controlling the signal modulation parameters described above, the arithmetic processing circuit performs a plurality of different signal processing functions.

According to another aspect of the present invention, a signal processing circuit includes an arithmetic processing circuit, circuit configuration information storage means for storing circuit configuration information, and circuit configuration information read from the circuit configuration information storage means. Circuit configuration control means for outputting a predetermined control signal to the arithmetic processing circuit, the arithmetic processing circuit comprising: a plurality of switch block means each including a plurality of switch elements and a plurality of signal lines; a logic processing block Means, and an analog processing block means for performing a predetermined modulation on an input signal are connected by a predetermined signal line, and the circuit configuration control means performs an on / off pattern of the plurality of switch element operations or the analog processing block. Controlling the signal modulation amount causes the arithmetic processing circuit to execute a plurality of different signal processing functions.

According to another aspect of the present invention, an input unit for inputting pattern data, an arithmetic processing circuit, a circuit configuration information storage unit for storing circuit configuration information, and the circuit configuration information storage in the pattern recognition apparatus. Circuit configuration control means for outputting a predetermined control signal to the arithmetic processing circuit based on circuit configuration information read from the means, wherein the arithmetic processing circuit includes a plurality of switch means, an analog processing block means, At least a signal line connecting between the switching means or the analog processing blocks, wherein the circuit configuration information storage means stores at least the plurality of switching means on / off pattern information and the signal modulation data of the plurality of analog processing blocks. One type is stored, and the circuit configuration control unit stores the circuit configuration read out from the circuit configuration information storage unit. By providing on / off pattern control signals for the plurality of switch means and predetermined signal modulation data to the plurality of analog processing blocks based on the information, a predetermined plurality of positions for a part or all of the input pattern are provided. And output means for detecting a plurality of predetermined feature categories and outputting a predetermined recognition result.

According to another aspect of the present invention, the signal processing circuit has an arithmetic processing circuit, circuit configuration information storage means for storing circuit configuration information, and storage means for holding intermediate output data from the arithmetic processing circuit. And a circuit configuration control unit that outputs a predetermined control signal to the arithmetic processing circuit based on the circuit configuration information read from the circuit configuration information storage unit and the intermediate output data held by the storage unit, The arithmetic processing circuit includes a plurality of switch block units each including a plurality of switch elements and a plurality of signal lines, an analog processing block unit that performs predetermined signal modulation on an input signal, and the switch block unit or the analog processing block. At least a signal line connecting them, wherein the circuit configuration control means turns on the plurality of switch elements,
By controlling an off pattern or a signal modulation amount in the analog processing block, the arithmetic processing circuit is caused to execute a plurality of different signal processing functions.

According to another aspect of the present invention, the signal processing circuit has an arithmetic processing circuit, circuit configuration information storage means for storing circuit configuration information, and storage means for holding intermediate output data from the arithmetic processing circuit. And a circuit configuration control unit that outputs a predetermined control signal to the arithmetic processing circuit based on the circuit configuration information read from the circuit configuration information storage unit and the intermediate output data held by the storage unit, The arithmetic processing circuit includes a plurality of switch block units including a plurality of switch elements and a plurality of signal lines, and a plurality of first and second types of analog processing block units in a predetermined pattern by predetermined signal lines. Connected, the first type of analog processing block means applies a predetermined modulation to a signal from the second type of analog processing block means, Second type of analog processing block means outputs a predetermined signal by integrating the signal from the first type of multiple analog processing blocks,
The circuit configuration control unit controls the operation processing circuit to execute a plurality of different signal processing functions by controlling on / off patterns of the plurality of switch element operations or signal modulation parameters of the analog processing block. I do.

According to another aspect of the present invention, the signal processing circuit has an arithmetic processing circuit, circuit configuration information storage means for storing circuit configuration information, and storage means for holding intermediate output data from the arithmetic processing circuit. And a circuit configuration control unit that outputs a predetermined control signal to the arithmetic processing circuit based on the circuit configuration information read from the circuit configuration information storage unit and the intermediate output data held by the storage unit, The arithmetic processing circuit includes a plurality of switch block units each including a plurality of switch elements and a plurality of signal lines, a logic processing block unit, and an analog processing block unit that performs predetermined modulation on an input signal. And the circuit configuration control means controls the on / off pattern of the plurality of switch elements or the signal modulation amount of the analog processing block. By controlling, characterized in that to perform different signal processing function to the arithmetic processing circuit.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> Overview of Overall Configuration and Each Part Hereinafter, a first embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of a main part of a reconfigurable processing circuit according to the present embodiment. As shown in FIGS. 5 to 7, this circuit constitutes a signal processing circuit as a reconfiguration processing circuit 3 together with the circuit configuration information storage means 1 and the circuit configuration control means 2 as a whole.

The reconstruction processing circuit 3 includes three types of processing element blocks, ie, a switch block SW capable of multiple inputs and multiple outputs, two types of analog processing blocks (AB ^I and AB ^S ), and transmission of signals between the blocks. , Switch block control line for controlling ON / OFF pattern of switch block SW (Fig. 2
1, and an analog processing block control line (see FIG. 2, not shown in FIG. 1) for controlling signal modulation parameters of the analog processing block.

Each control line includes a clock signal line (not shown), and digitally transmits a control signal to a predetermined block at a predetermined clock timing. Here, the analog processing block AB ^I represents the neuron elements of the hierarchical level I, the analog processing block AB ^S represents the synapse elements described below. The switch block is a circuit block that receives a predetermined clock signal and is digitally controlled.
The analog processing blocks (AB ^I and AB ^S ) are for performing analog processing, and are not necessarily composed of only analog circuit elements such as capacitors and resistors, but include digital circuit elements internally. May be included.

In FIG. 1, the neuron element AB of the I + 1 layer^{I + 1}
₃The signal transmission path that receives the input is AB^I ₄→ SW → AB_S4
→ SW → AB^{I + 1} ₃, AB^I _Three→ SW → AB_S3→ SW → AB^{I + 1} ₃,as well as,
AB^I _Two→ SW → AB_S2→ SW → AB^{I + 1} ₃These are the three routes. On the other hand, I
+1 layer neuron element AB^{I + 1} ₂Signal transmission
The route is AB^I _Three→ SW → AB_S3→ SW → AB^{I + 1} ₂, AB^I _Two→ SW → A
B_S2→ SW → AB^{I + 1} ₂And AB^I ₁→ SW → AB_S1→ SW → AB^{I + 1}
₂These are three routes. These two paths partially overlap
But the analog applied by the synapse element in the overlapping part
The amount of modulation generally depends on the signal path,
In the child, different modulation is given depending on the path (input signal)
As shown in FIG. 3 (details will be described later).
Description).

The circuit configuration control means 2 shown in FIG. 4 outputs control signals to the switch block control line and the analog processing block control line shown in FIG. The control signal corresponding to the former is
Switch elements inside each switch block SW (Figs. 5-7)
Control signal corresponding to the latter,
A signal modulation characteristic (for example, a pulse phase modulation amount or the like) at a synapse element or a time window width of an integration with a time window weight and a weight function at a neuron element are controlled.

Each analog processing block AB described below
(AB ^I, none of the AB _S), the switch block SW around
They are arranged so that they are surrounded by. Since each block shape has six input / output directions, it is displayed as forming a regular hexagon, but other shapes having a predetermined number of input / outputs may be used. FIG. 2 shows an example of a connection state between the blocks. The numbers attached around SW ₂ indicate the general signal transmission direction (vertical direction and oblique direction) from the switch block SW. In the transmission direction, the solid line is between the blocks via the switch block SW (between the switch blocks or between the switch block and the analog processing block)
Indicate the state in which signals can be transmitted, and the broken line indicates the state of the wiring in which signals cannot be transmitted.

The ON / OFF operation of each switch block SW is set for each signal input / output direction (six directions in the figure) via a switch block control line running in the horizontal direction in FIG. A plurality of types of ON / OFF pattern data for each switch block SW are stored in a predetermined memory (SRAM, DRAM, MRAM, or the like) in advance, and can be updated (switched) according to the processing content.

FIG. 5A shows the configuration of the switch block SW. Here, a total of six switch elements, which are digital circuit elements, are arranged for each direction, and according to their ON / OFF patterns (ON state is indicated by black circles, OFF state is indicated by white circles),
It is possible to realize a function of controlling a signal output direction as shown in FIG. 5B and a function of integrating a plurality of input signals and outputting the signal in a predetermined direction as shown in FIG. 6A.

As shown in FIG. 6B or FIG. 7, a plurality of signal lines may be independently set in each direction. FIG.
In (2), one switch element is assigned to a plurality of signal lines running in the same direction. In FIG. 7, a switch element is provided for each of a plurality of signal lines running in the same direction. In this way, the flow of a plurality of pulse signals can be controlled separately and independently by the same switch block SW. As the switch element, an element as described in the description of the related art may be used. The state control of the switch elements in the switch block is performed at a predetermined clock timing via a switch block control line.

In FIG. 1 and FIG.
It is shown the signal line 2 is a line for transmitting an analog signal modulated by the synapse element AB _S neuron element AB ^I. This corresponds to a case where the configuration shown in FIG. 6B is used in the switch block SW. In FIG. 1, the signal line 1 is connected to the neuron element AB ^{I + 1} ₃ and the signal line 2
Transmits a signal to the neuron element AB ^{I + 1} _4. These signal lines are used as local common bus lines to be described later, and a pulse train signal having a predetermined interval pattern propagates.

Although only two signal lines as described above are shown in FIG. 2 for convenience, more signal lines may be actually arranged. However, if the number of signal lines increases, the ratio of the area of the wiring portion to the entire circuit becomes too large, causing a problem that the degree of integration does not increase.
There is a certain limit on the number.

However, the number of signal lines exceeding the limit may be required. For example, n I + 1-layer neuron elements synapse different analog modulations on output signals from s neurons in the I layer that partially overlap each other using m (n> m) signal lines. This is a case where the input is performed after the operation is performed by the element.

[0032] In such a case, time division switch block SW to be connected to a neuron element AB ^I blocked with ON / OF
Process by switching the F pattern. At that time, the control signal from the modulation amount circuit configuration controller 2 analog modulation circuit of the analog processing block AB _S as synaptic elements (described later) is updated via the analog block control line (Fig. 2) .

Next, the function of each block in the signal processing circuit of this embodiment will be described. Switch block
SW is connected to the analog processing block (AB ^I , A
By controlling the flow of signals from B _S ), the range of neuron elements in the lower hierarchy (hereinafter referred to as “receptive field”) to which neuron elements in the higher hierarchy level receive input is determined. The coupling structure provided by this receptive field can be arbitrarily set by the ON / OFF pattern of the plurality of arranged switch blocks SW.

Further, the distribution structure of the synaptic connection load in the receptive field can be arbitrarily given by setting individual parameters of a plurality of modulation circuits in the analog processing block described later.

As a result, it is not necessary to store synapse load information or wiring information in the digital memory element and to adopt a configuration in which memory access is frequently performed, so that the characteristics of high-speed parallel processing can be ensured. At the same time, flexibility and expandability such as a change in the circuit configuration according to the processing content (the type of feature to be extracted) are provided.

The analog processing block AB _S is a multi-input multi-output device can be set individually in accordance with the modulation of the signal into a plurality of synapse load value, typically the signal obtained by integrating the synapse load value to an input signal (In the embodiment described later, a phase modulation signal of the input pulse signal is output). As shown in FIG. 3, a plurality of analog modulation means corresponding to a plurality of synapse load values are provided inside.

[0037] One of the analog processing block AB _S is capable of setting a range of each neuron of the output-side I and the input side J within a certain range, synapses determined by the input neuron device address and the output neuron element address therein It has a plurality of analog modulation means for giving a modulation corresponding to the load value. FIG. 3 shows the structure.

FIG. 3A shows the structure of a synapse element used in the present invention, and internally has the same number of analog modulation means as the number of output lines (input lines). In FIG. 3, the analog block control line is not shown to simplify the display,
The modulation amount (in this embodiment, the modulation of the pulse phase (delay amount) or the pulse width) is set or updated in each analog modulation unit via the control line.

FIG. 3B shows the configuration of a multi-input, one-output synapse element. This element is used when multiple neurons in the upper layer receive signal outputs from the overlapping lower layer neurons in a time-sharing manner, and when different analog modulation is performed by the synapse element for each signal according to the upper layer neurons. Used.

[0040] For example, in FIG. 1, the neuron elements of I + 1 layer from the neuron element AB ^I ₃ I-layer AB ^{I + 1} ₃ to reach the signal transmission path (dashed arrows) and the neuron element AB ^I ₃ neuron element from AB signal transduction pathway leading to ^{I + 1} ₂ (solid arrows) are both passing through the synapse element AB _S3.

In the synapse element _ABS3 , the modulation amount (pulse phase modulation, pulse width modulation, etc.) that differs depending on each transmission path (or the address of the upper layer neuron)
Are set for each of the plurality of modulation means provided therein so as to obtain the following.

[0042] With this arrangement, it is possible to set a plurality of different signal transmission path via the same analog processing block AB ^S even when there is a receptive field structure that overlap each other between the neuron elements close Becomes As a result, the problem of wiring between circuit elements constituting the neural network is reduced, and the number of circuit elements is reduced.

The analog modulation amount in the pulse phase modulation, described below, can be provided by such as a charge amount to be given to the capacitor is an element constituting the synapse circuit, in each modulation means of the analog processing block AB _S floating A predetermined amount of charge is given to the gate element or the capacitor via an analog processing block control line (shown in FIG. 2A).

Here, the circuit configuration control means 2 shown in FIG.
Reads out synapse load value data (e.g., an applied voltage that gives a predetermined accumulated charge amount) stored in the circuit configuration information storage means 1 and accumulates charges corresponding to the synapse load value in the floating gate element (or capacitor) ( Voltage is generated)
Inject current until After that, each synaptic circuit element AB _Sk (k = 1, 2,.
) Are accessed in a time series, and a voltage is applied to inject charges (hot electrons) to set a distribution structure (receptive field structure) of a synaptic load. A memory element (MRAM, FeRAM) capable of rewriting data corresponding to a load value at high speed and retaining the data for a predetermined time.
Etc.) can be used if such a memory element is available.

Next, a case where a neural network for performing image recognition by parallel hierarchical processing using the configuration shown in FIG. 1 will be described. First, the processing content of the neural network will be described in detail with reference to FIG. This neural network hierarchically handles information related to recognition (detection) of an object or a geometric feature in a local region in input data, and its basic structure is a so-called Convolutional network structure (LeCun, Y. andBengio, Y., 1995, “Convolutio
nal Networks for Images Speech, and Time Series ”
in Handbook of Brain Theory and Neural Networks
(M. Arbib, Ed.), MIT Press, pp. 255-258). The output from the last layer (top layer) is the category of the recognized target as a recognition result and the position information on the input data.

The data input layer 101 includes a CMOS sensor,
Alternatively, it is a layer for inputting local area data from a photoelectric conversion element such as a CCD element under the instruction of the scanning means 1. The first feature detection layer (1, 0) is a local low-order feature of the image pattern input from the data input layer 101 (geometric features such as specific direction components and specific spatial frequency components, as well as color component features). May be included) in a local area centered on each position of the entire screen (or a local area centered on each predetermined sampling point over the entire screen) at a plurality of scale levels or resolutions at the same location. Detect only the number of categories. For this purpose, a receptive field structure corresponding to the type of the feature (for example, in the case of extracting a line segment in a predetermined direction as a geometric feature) has a receptive field structure corresponding to the degree, It is composed of neuron elements that generate a corresponding pulse train.

The feature integration layer 103 (2,0) has a predetermined receptive field structure (hereinafter, “receptive field” indicates a coupling range with the output element of the immediately preceding layer, and “receptive field structure” indicates a distribution of the coupling load. ) And integrates a plurality of neuron element outputs in the same receptive field from the feature detection layer 102 (1, 0) (local sampling, sub-sampling by maximum output detection, etc.). Operation). Further, each receptive field of the neuron in the feature integration layer has a common structure among neurons in the same layer.

Each feature detection layer 102 as a subsequent layer
((1, 1), (1, 2),..., (1, M)) and each feature integration layer 103 ((2, 1), (2, 2),. )) Has a predetermined receptive field structure, and the former ((1, 1),...) Detects a plurality of different features in each feature detection module and performs the latter ((( 2,1), ...)
Performs integration of detection results for a plurality of features from the preceding feature detection layer. However, the former feature detection layer is connected (wired) so as to receive the cell element output of the preceding feature integration layer belonging to the same channel. The sub-sampling, which is a process performed in the feature integration layer, is for averaging the output from a local region (local receptive field of the feature integration layer neuron) from the feature detection cell population of the same feature category. .

The case of realizing the configuration shown a parallel hierarchical structure described above in FIG. 1, synapse constitutes the analog processing block AB _S, neuron element of the I layer, which constitutes the analog processing block AB ^I is there.

In FIG. 8, the coupling means relating to the output from the neuron group (n _i ) of the feature-integrated (detected) cells forming the receptive field for a certain detected (integrated) cell (input when viewed from the cell) is shown. 1 shows the configuration. Portions indicated by thick lines as signal transmission means constitute a local common bus line, and pulse signals from a plurality of neurons are transmitted in time series on this signal transmission line.

The so-called excitatory connection amplifies the pulse signal in the synaptic connection means S, and the inhibitory connection gives a reverse attenuation. When transmitting information using a pulse signal, amplification and attenuation are performed by amplitude modulation of the pulse signal,
It can be realized by any of pulse width modulation, phase modulation, and frequency modulation. In the present embodiment, the synapse coupling means S is mainly used as a phase modulation element of the pulse, and the amplification of the signal is substantially advancing the pulse arrival time as a characteristic-specific amount, and the attenuation is substantially a delay. Is converted. That is, the synaptic connection gives the arrival position (phase) on the time axis unique to each feature in the output neuron, and qualitatively the excitatory connection leads the phase of the arrival pulse to a certain reference phase, Inhibitory coupling also gives a delay.

In FIG. 8A, each neuron element n
_j outputs a pulse signal (spike train) and performs so-called integral-and-fire type input / output processing. It will be described next neuron circuits constituting the analog processing block AB ^I. Each neuron element is a so-called integrat
This is an extended model based on e-and-fire neurons. It fires when the result of linear addition of input signals (pulse trains corresponding to action potentials) in time and space exceeds a threshold, and outputs a pulse-like signal. So what is called in
Same as the tegrate-and-fire neuron.

FIG. 8B shows an example of a basic configuration showing the operation principle of a pulse generation circuit (CMOS circuit) as a neuron element, and a known circuit (IEEE Trans.
etworks Vol. 10, pp. 540) to enable weighted integration of input pulse signals within a predetermined time window. See Japanese Patent Application No. 2000-181487. Here, it is configured to receive excitatory and inhibitory inputs as input signals.

The operation control mechanism for the pulse firing timing of each neuron element and the like are not the main subject of the present application, and therefore the description is omitted.

Transmission of signals between neurons by pulse signals is a so-called AER (Address Event Representation) method (Lazzaro, et al. 1993, Silicon Auditory Procedure).
ssorsas Computer Peripherals, In Tourestzky, D. (e
d), Advances in Neural Information Processing Syst
ems 5. San Mateo, CA: Morgan Kaufmann Publishers)
And Japanese Patent Application No. 2000-18 filed by the present applicant.
No. 1487 may be used.
These are suitable methods for transmitting pulse signals from a plurality of neurons via a local common bus as shown in FIG.

The above-described pattern recognition apparatus can be mounted on a camera or other image input means, or a printer and a display or other image output means. as a result,
With a low-power consumption and small-scale circuit configuration, a specific operation is performed by recognizing or detecting a specific object, for example, for image input means, focusing around the specific object,
Processing such as exposure correction, zooming, or color correction can be performed. The image output means can also automatically perform processing such as optimal color correction for a specific subject.

Next, FIG. 10 shows a case where a pattern detection (recognition) device according to the configuration of the present embodiment is mounted on an imaging device to perform focusing on a specific subject, color correction of the specific subject, and exposure control. It will be described with reference to FIG. FIG. 10 is a diagram illustrating a configuration of an example in which the pattern detection (recognition) device according to the embodiment is used for an imaging device.

An image pickup apparatus 1101 shown in FIG. 10 includes an image forming optical system 1102 including a photographing lens and a drive control mechanism for zoom photographing.
D or CMOS image sensor 1103, imaging parameter measurement unit 1104, video signal processing circuit 1105, storage unit 1106, control signal generation unit 1107 that generates control signals such as control of imaging operation, control of imaging conditions, and viewfinders such as EVF And a pattern recognition device that performs the above-described time-division multiplexing process as a subject detection (recognition) device 1111.

The image pickup apparatus 1101 performs detection (detection of the position and size) of a face image of a person registered in advance from, for example, a captured image by using a subject detection (recognition) apparatus 1111. When the position and size information of the person is input from the subject detection (recognition) device 1111 to the control signal generation unit 1107, the control signal generation unit 1107
Focus control for that person based on the output from 04,
A control signal for optimally controlling exposure condition control, white balance control, and the like is generated.

As a result of using the above-described pattern detection (recognition) apparatus in an image pickup apparatus, a small-sized and low-power-consumption circuit can perform high-speed (real-time) person detection and optimal control of photographing based on the detection. become able to.

<Second Embodiment> FIG. 11 shows another configuration example of a neural network realized as a reconfigurable analog / digital mixed circuit. The reconfigurable signal processing circuit according to the present embodiment is another embodiment for realizing a hierarchical neural network for pattern recognition as shown in FIG. 8, and converts a pulse signal into a synapse circuit according to a detection category. (Analog processing block) is the same as the first embodiment in that hierarchical modulation is performed from low-order features to high-order features by performing phase modulation.

[0062] This signal processing circuit includes an analog processing block AB _S as synaptic elements, digital processing block DB provide a phase delay of a pulse signal, the switch for the variable (local connection structure between neurons) receptor field structure configured block SW, and because the logic processing block LB performing predetermined signal output based on the output from the analog processing block AB _TI (part of neuron element). The overall configuration including the circuit configuration information storage unit 1 and the circuit configuration control unit 2 is as shown in FIG. 6, as in the first embodiment.

As described above, the configuration in which the logic processing elements and other digital circuit elements are distributed and mixed in the same manner as the analog circuit elements makes it hard to be affected by the variation in the operating characteristics of the analog processing elements even in the case of large-scale integration. Stable operation is enabled. This is because digital circuit elements can absorb fluctuation factors of analog processing elements.

In FIG. 11, the neuron element LB ^J ₃ in the J layer is shown.
However, the transmission path of the signal received from the neuron element of the I layer (J> I, generally J = I-1) is LB ^I ₄ → AB _S4 → SW → DB ₃ → LB ^J ₃ , LB ^I ₃ → AB _S3 → DB ₃ → LB ^J ₃ , LB ^I ₂ → AB _S2 → SW → DB ₃ → LB ^J ₃

On the other hand, the signal transmission path of the neuron element LB ^J ₂ in the J layer receiving the input from the neuron element in the I layer is as follows: LB ^I ₃ → AB _{S 3} → SW → DB ₂ → LB ^J ₂ , LB ^I ₂ → AB _S2 → a third path of _{^{DB 2 → LB J 2, LB}} I 1 → AB S1 → SW → DB 2 → LB J 2.

[0066] While the two types of route from the three paths are partially overlapping at the synapse element AB _S, as in the first embodiment, the analog modulation amount synaptic elements in the overlapping parts are subjected by the signal path Generally different. Further, synapse element AB _S, in addition to the modulation function for the input signals from a plurality of paths (signal lines), also has a branch output function to the appropriate path (direction). For this, the analog processing block AB _S for synapse element used in the present embodiment has a configuration as shown in FIG. 12. Here, the analog processing block AB _S receives three input signals separately and independently, has three analog modulation means and the one switch element therein. Each output from the analog modulation means can be arbitrarily output in five directions from the switch element.

FIG. 13 shows a configuration example of the digital processing block DB used in the present embodiment. Here, the digital processing block DB has three delay elements and one switch block inside. The switch block is different from the switch block SW shown in FIG. 3 in that the switch block particularly includes a switch element that temporally branches the output direction. The outputs from the three delay elements are integrated and output to one signal line.

[0068] In the synapse analog processing block AB _S, enter the first pulse signal similar to the embodiment of the outputs giving a predetermined pulse phase modulation (or time delay). The modulation amount (or delay) is controlled via the AB _S control line in FIG. 14. In addition, the delay characteristics of the digital processing block DB that gives a time delay are controlled via a DB control line shown in FIG.

In the present embodiment, the function of integrating the detection signals of a plurality of lower categories by the neuron element is constituted by using the logic processing block LB, and a part of the neuron element circuit constitutes the logic processing block LB. The logic processing block refers to combination list structure data described in advance in a list or dictionary format, and determines whether there is an input signal of a combination corresponding to a recognition category, and a predetermined recognition (detection). It comprises a signal output circuit (Flip-Flop circuit and logic circuit) and the like.

As the simplest form of a logic circuit, as shown in the first embodiment, a logic processing block receives a plurality of pulse signal trains each receiving a phase modulation by a synapse circuit and representing a different feature category. , And a circuit that ANDs them. In this embodiment, a predetermined delay is given to each input pulse by a delay element (digital circuit element) in the digital processing block DB before the AND operation is performed by the logical processing block LB, so that the pulse arrival times are substantially the same on the time axis. To be.

For example, _assuming that a pulse arrival time of a pulse signal representing the detection of a certain feature category with respect to a reference time is t _n , the delay element has a delay of Tt _n (T>
t _n ) is given to the pulse signal. Since the delay amount is digitally given, output pulses from the delay elements may not exactly coincide with each other on the time axis, but the magnitude of the mismatch is at most about half of the pulse width. It is assumed that the accuracy of the delay amount is given so that

As shown in the first embodiment, when a pulse signal modulated by a synapse circuit element is input to a logic processing block via a common bus, the above-described delay element changes the delay amount according to the input pulse. Switch (modulate).
Multi-input, one-output AN via multiplexer circuit
Input to D element.

As described above, the detection of the high-order feature data given by the low-order feature list structure is simple.
It can be realized by AND processing. However, a simple A
In the ND processing, higher-order features are not detected unless all lower-order feature data as constituent elements are detected.
Therefore, the logic circuit may be configured such that if the ratio of the detected components is equal to or more than a certain value, the corresponding higher-order feature is detected. For example, assuming that the detection of higher-order features composed of M lower-order feature elements is performed by detecting N lower-order feature elements in a predetermined spatial arrangement, _M C _N (= M! / (MN)! N!) (However, m! = M
(M-1)... 2-1) N-input 1-output AND elements for inputting different combinations of pulse signals may be set, and the outputs may be ORed.

Next, the list structure data will be described. As shown in FIG. 7, it is provided as a linked list structure of middle-order (low-order) patterns constituting a high-order pattern.

FIG. 9 shows an example of this data structure. Here, the category of the higher-order pattern is “face”, and the category of the middle-order pattern to be detected corresponding to this is “eye”,
Given like "nose", "mouth". Similarly, each intermediate pattern is given as low-order pattern list structure (tree structure) data constituting the same.

Although this data structure does not describe the spatial arrangement information of each of the middle-order patterns as constituent elements, this is because in the configuration using the hierarchical neural network shown in FIG. This is because it is presumed that synapse connection is performed so that it is possible to detect the presence of a plurality of local feature elements satisfying the spatial arrangement previously learned with respect to the feature integration layer of the previous layer (Japanese Patent Application 2000-
181487). That is, if there is a local feature element that satisfies the predetermined spatial arrangement relationship, each detection signal (pulse signal) is input to the feature detection layer neuron at a preset time interval. This is because it is not necessary to refer to data describing the spatial arrangement relationship between the feature elements in the neuron element.

In FIG. 9, the middle features are indicated by black circles, indicating the state of detection of the middle ear feature necessary for detection as “face”, and the white circles indicate undetected states. Is shown. FIG. 9 clearly shows that detection of at least three intermediate features is required.

<Third Embodiment> FIG. 16 shows the configuration of the main part. In the present embodiment, the initial data and the intermediate output data holding means 4 are used to control (reconfigure) the circuit configuration while feeding back the intermediate output data, so that the parallel configuration shown in FIG. Implement a hierarchical processing circuit. Here, the type (category or size) of the feature detected in each feature detection layer at a certain time is one, and the type is updated by the circuit configuration control means 2 in time series. Therefore, the number s of feature types arranged in parallel in the reconstruction processing circuit 3 can be significantly reduced as compared with the number N of feature types in the first embodiment (s = 1 is also possible).

In this case, the reconstruction processing circuit 3 for performing pattern recognition performs the following operations at each sampling point on the input data.
The processing is performed hierarchically while holding the intermediate processing results relating to the detection of patterns of different categories in time series in the intermediate output storage means 4. The circuit configuration control means 2 outputs the detection result (neuron element AB ^D ) of each feature detection layer 102 read from the intermediate output storage means 4 to each neuron element (AB ^I ) of the feature integration layer 103, and the circuit configuration Information storage means 1
ON / OFF pattern of switch block SW and analog processing block based on circuit configuration information read from
Set the parameters of AB.

In the reconstruction processing circuit 3, similarly to the first embodiment, the feature detection layers 102 and the feature integration layers 103 which are arranged alternately in a cascade form hierarchically from low-order to high-order pattern detection. (FIG. 8), but in this embodiment,
In order to virtually realize the hierarchical structure of the processing, the processing is performed in time series. By doing so, the overall circuit scale can be significantly reduced.

The output from each feature detection layer 102 is temporarily stored in the intermediate output information holding means 4 after the same sub-sampling processing as in the previous embodiment is performed in the subsequent feature integration layer 103. Furthermore, the feature detection layer 102 receives the update of the synapse load distribution (local receptive field structure) as described below and, at the same time, inputs the detection results for each feature type from the intermediate output data holding unit 4 in time series.

For example, the local receptive field structure of the feature detection layer 102 for detecting a pattern corresponding to the eye (intermediate pattern) is composed of low-order patterns P ₁ , P ₂ ,.
Update (or set) each time a feature detection layer output for each pattern Pk (k = 1,..., N) is input from the intermediate output data holding means 4 as a local receptive field structure unique to each of P _n Is done. Note that the receptive field structure of each neuron in the feature detection layer is updated according to the feature type, but the receptive field structure of each neuron in the feature integration layer is not updated if the receptive field size is the same among the feature types.

The local receptive field structure is stored as digital data in the circuit configuration information storage means 1 for each type of feature to be input, read out from the storage means 1, and read from the control signal from the circuit configuration control means 2. Will be updated by

For example, the receptive field structure of the neuron of the feature detection layer 102 (the layer for performing the secondary feature detection) that has detected the pattern corresponding to the eye at a certain time is different from that at another time.
It is updated in a predetermined order according to a control signal from the circuit configuration control means 2 so as to detect a pattern corresponding to a nose or a mouth.

As described above, by performing the multiplexing process for detecting different features (recognition) at different timings in one reconstruction processing circuit 3 on the input data, a plurality of features at the sampling position on the input data are obtained. Compared with a circuit configuration in which detection is performed independently and simultaneously in parallel, the circuit scale is greatly reduced.

The structure of the temporally controlled receptive field is an SRAM (or MRA) (not shown) that stores circuit configuration information data including dynamically reconfigurable analog / digital circuit elements.
M, FRAM, etc.) and a circuit configuration information storage unit 1 and a circuit configuration control unit 2.

When realizing a hierarchical neural network composed of neurons having a local receptive field structure as shown in FIG. 9, a storage means for updating circuit configuration information for each layer and a circuit configuration control means are generally used. Although it is necessary in this embodiment, as shown below, a single set of the circuit configuration information storage unit 1 and the circuit configuration control unit 2 suffices regardless of the number of layers in the hierarchical structure.

For example, assuming that the type of feature (for example, feature category and size) to be detected by the feature detection layer 102 at each sampling point on the input data at a certain time is one, each localization of the neuron of the feature detection layer 102 The structure of the target receptive field is the same. As a result, the circuit configuration information storage means 1 and the circuit configuration control means 2 for providing the receptive field structure are shared, and each switch block SB and the analog processing block AB _S
Can be given circuit configuration information.

The updating and setting of the weight coefficient for each connection reflecting the receptive field structure is performed in accordance with the analog processing block AB _S according to the weight coefficient data supplied from the circuit configuration information storage means 1.
Is realized by updating the load data of the synapse circuit.

[0090] For example, when the synapse load value is given by injection amount of charges stored in the floating gate devices in the analog processing block AB _S, etc. set of synaptic weights, weight coefficients stored in the circuit configuration information storage means 1 injection of charges corresponding to the load value for each synapse corresponding to the data is performed by being made via the AB _S control line shown in FIG.

[0091]

As described above, according to the present invention,
In a parallel processing circuit configuration including a plurality of analog processing elements, an analog signal processing element and switch elements, which are digital circuit elements, are arranged on a predetermined lattice, and control of each element is performed, so that a wiring structure between the processing elements and processing are performed. Since the weight of the signal transmitted between the elements is arbitrarily controllable,
A plurality of circuit configurations can be variously configured with a small number of basic circuit configurations, and a large-scale parallel processing analog processing circuit can be realized with a small-scale circuit configuration without increasing or decreasing the number of circuit elements.

Also, by arranging analog processing elements, logic processing elements, which are digital circuit elements, and switch elements on a predetermined grid, and controlling each element, the wiring structure between the elements and the analog processing element can be controlled. By making it possible to arbitrarily set and control the weighting of the signal transmission between the elements, the circuit scale can be significantly reduced as compared with the case where the circuit is composed of only analog circuit elements or only digital circuit elements.

In particular, by distributing and mixing logic processing elements and other digital circuit elements in the same manner as analog circuit elements, even when integrated on a large scale, it is less susceptible to variations in the operating characteristics of analog processing elements and stable operation. Can be possible.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a main part of an arithmetic processing circuit.

FIG. 2 is a connection diagram between basic element blocks of a reconfigurable signal processing circuit.

FIG. 3 is a configuration diagram of a synapse analog processing block.

FIG. 4 is a diagram showing a configuration of a synapse unit and a neuron element.

FIG. 5 is a configuration diagram of switch block means.

FIG. 6 is a configuration diagram of switch block means.

FIG. 7 is a configuration diagram of switch block means.

FIG. 8 is a configuration diagram of a hierarchical neural network.

FIG. 9 is an overall configuration diagram of a reconfigurable signal processing circuit.

FIG. 10 is a main part configuration diagram of an application example in which a pattern recognition device is mounted on a photographing device.

FIG. 11 is a configuration diagram of a main part of an arithmetic processing circuit.

FIG. 12 is a configuration diagram of a synapse analog processing block.

FIG. 13 is a configuration diagram of a digital processing block according to a second embodiment of the present invention.

FIG. 14 is a connection diagram between basic element blocks of a reconfigurable signal processing circuit.

FIG. 15 is a diagram showing an example of list structure data representing the arrangement relationship of secondary features.

FIG. 16 is a configuration diagram of a main part of an arithmetic processing circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Osamu Nomura 3-30-2 Shimomaruko, Ota-ku, Tokyo F-term in Canon Inc. (reference) 5L096 HA11 LA11 LA14 LA17

Claims (17)

[Claims] An arithmetic processing circuit; circuit configuration information storage means for storing circuit configuration information; and a circuit for outputting a predetermined control signal to the arithmetic processing circuit based on circuit configuration information read from the circuit configuration information storage means. A plurality of switch blocks each including a plurality of switch elements and a plurality of signal lines; and an analog processing block for performing a predetermined signal modulation on an input signal. A signal line connecting the switch block means or the analog processing block, wherein the circuit configuration control means controls an on / off pattern of the plurality of switch element operations or a signal modulation amount in the analog processing block means. A signal processing circuit for causing the arithmetic processing circuit to execute a plurality of different signal processing functions. 2. An arithmetic processing circuit, circuit configuration information storage means for storing circuit configuration information, and a circuit for outputting a predetermined control signal to the arithmetic processing circuit based on circuit configuration information read from the circuit configuration information storage means A configuration control unit, wherein the arithmetic processing circuit includes a plurality of switch block units;
Each of the plurality of first and second types of analog processing block means is connected in a predetermined pattern by a predetermined signal line, and the first type of analog processing block means is the second type of analog processing block. Applying a predetermined modulation to the signal from the means, the second type of analog processing block means outputs a predetermined signal by integrating signals from the plurality of analog processing block means of the first type, The switch block means has a plurality of switch elements and a plurality of signal lines, and the circuit configuration control means controls on / off patterns of the plurality of switch element operations or signal modulation parameters of the analog processing block. A signal processing circuit for causing the arithmetic processing circuit to execute a plurality of different signal processing functions. 3. An arithmetic processing circuit; circuit configuration information storage means for storing circuit configuration information; and a circuit for outputting a predetermined control signal to the arithmetic processing circuit based on circuit configuration information read from the circuit configuration information storage means. The arithmetic processing circuit includes a plurality of switch block units each including a plurality of switch elements and a plurality of signal lines, a logic processing block unit, and performs a predetermined modulation on an input signal. The arithmetic processing circuit is connected to an analog processing block means by a predetermined signal line, and the circuit configuration control means controls an on / off pattern of the operation of the plurality of switch elements or a signal modulation amount of the analog processing block. A plurality of different signal processing functions. 4. The signal processing circuit according to claim 1, wherein the switch block unit inputs signals from the plurality of analog processing block units via a predetermined signal line. 5. The signal processing circuit according to claim 1, wherein said analog processing block means includes an input signal modulation means and an output signal branch circuit. 6. The analog processing block means according to claim 1, wherein a predetermined time-dependent addition processing or weighted integration processing is performed on the input signal.
4. The signal processing circuit according to any one of claims 1 to 3. 7. The signal processing circuit according to claim 1, wherein said analog processing block means has a plurality of input signal modulation circuits capable of setting different degrees of modulation. 8. The signal processing circuit according to claim 7, wherein said input signal modulation circuit is a circuit for modulating a delay or a phase of a pulse signal. 9. The switch block means includes a plurality of input / output signal lines and a plurality of switch elements, and outputs a signal input from a predetermined signal line to another signal line. The signal processing circuit according to claim 1, wherein: 10. The signal processing circuit according to claim 3, wherein said logic processing block means has at least one AND circuit for a plurality of input signals. 11. The first type of analog processing block includes input signal modulating means, and the second type of analog processing block performs weighted time integration of the input signal. The signal processing circuit according to claim 2, wherein 12. The signal processing circuit according to claim 9, wherein said switch block means sets on / off operations of said plurality of switch elements by a control signal from a predetermined control line. 13. The signal processing circuit according to claim 9, wherein said switch block means comprises a plurality of signal lines arranged in the same direction. 14. An input means for inputting pattern data, an arithmetic processing circuit, a circuit configuration information storage means for storing circuit configuration information, and the arithmetic processing circuit based on circuit configuration information read from the circuit configuration information storage means. And a circuit configuration control means for outputting a predetermined control signal, wherein the arithmetic processing circuit comprises a plurality of switch means,
An analog processing block means, and at least a signal line connecting between the switching means or the analog processing blocks, wherein the circuit configuration information storage means includes a plurality of switching means on / off pattern information and signals of the plurality of analog processing blocks And at least one type of modulation data, respectively, the circuit configuration control means, based on the circuit configuration information read from the circuit configuration information storage means, on and off pattern control signal of the plurality of switch means, By applying predetermined signal modulation data to the plurality of analog processing blocks, a predetermined plurality of feature categories are detected at predetermined positions and a predetermined recognition result is output for a part or all of the input pattern. A pattern recognition device comprising: 15. An arithmetic processing circuit, circuit configuration information storage means for storing circuit configuration information, storage means for holding intermediate output data from the arithmetic processing circuit, and a circuit configuration read from the circuit configuration information storage means Circuit configuration control means for outputting a predetermined control signal to the arithmetic processing circuit based on information and the intermediate output data held by the storage means, wherein the arithmetic processing circuit has a plurality of switch elements and a plurality of A plurality of switch block units including a signal line, an analog processing block unit for performing predetermined signal modulation on an input signal, and a signal line connecting between the switch block unit or the analog processing block; The control means controls an on / off pattern of the operation of the plurality of switch elements or a signal change in the analog processing block. By controlling the amount, the signal processing circuit, characterized in that to execute a plurality of signal processing functions different to the arithmetic processing circuit. 16. An arithmetic processing circuit, circuit configuration information storage means for storing circuit configuration information, storage means for holding intermediate output data from the arithmetic processing circuit, and a circuit configuration read from the circuit configuration information storage means Circuit configuration control means for outputting a predetermined control signal to the arithmetic processing circuit based on information and the intermediate output data held by the storage means, wherein the arithmetic processing circuit includes a plurality of switch elements and a plurality of signals. A plurality of switch block means including a plurality of lines, and a plurality of first and second types of analog processing block means are respectively connected in a predetermined pattern by predetermined signal lines; Provides a predetermined modulation to the signal from the second type analog processing block means, The stage outputs a predetermined signal by integrating signals from the plurality of analog processing blocks of the first type, and the circuit configuration control means controls the on / off pattern of the operation of the plurality of switch elements or the analog processing block. A signal processing circuit that controls the arithmetic processing circuit to execute a plurality of different signal processing functions. 17. An arithmetic processing circuit, circuit configuration information storage means for storing circuit configuration information, storage means for holding intermediate output data from the arithmetic processing circuit, and a circuit configuration read from the circuit configuration information storage means Circuit configuration control means for outputting a predetermined control signal to the arithmetic processing circuit based on information and the intermediate output data held by the storage means, wherein the arithmetic processing circuit has a plurality of switch elements and a plurality of A plurality of switch block units including a signal line, a logic processing block unit, and an analog processing block unit for performing predetermined modulation on an input signal are connected by a predetermined signal line; By controlling the on / off pattern of the switch element operation or the signal modulation amount of the analog processing block, the arithmetic processing Signal processing circuit, characterized in that to execute a plurality of signal processing functions differ.