JP2002298374A - Light receiving signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a light receiving signal processor that can eliminate the need for changing a circuit even when the configuration of a part to output a light receiving signal is changed, can be made low in cost by relaxing required specifications of a part having a plurality of light sources and light receiving parts especially to compatibly cope with a plurality of kinds of light receiving signals, can reduce signal degradation due to noise in signal supply by an FPC board and can reduce the number of signal lines transferring the signal. SOLUTION: An output to a plurality of kinds of processes is changed over by inputting the light receiving signals of analog signals by an input selecting part 1, the light receiving signals are successively converted from the analog signals to digital signals in time series and outputted by an A/D converter 3, the light receiving signals are transmitted by a first I/F part 32 and a second I/F part 33 and arithmetic processings of the plurality of kinds of processes are executed based on the light receiving signals by a servo signal arithmetic processing part 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CD-ROM drive, a CD-R drive, and a CD-RW drive for performing required signal processing on a received light signal obtained by receiving reflected light from an information recording medium. , DVD-ROM drive device, DVD-R drive device, DVD-RW drive device, DVD-RAM drive device, MD drive device, MO drive device, etc. It relates to a processing device.

[0002]

2. Description of the Related Art For example, in an optical disk device, a reflected light of a laser beam applied to an optical disk as an information recording medium in an optical pickup is reflected by a PD (Photo D).
The light is detected by receiving light by a light receiving element such as a detector, and a light receiving current obtained by the PD is supplied to a signal processing unit. Since the light receiving current is generally a weak current, the light receiving signal is generated by converting the current into a voltage, and the light receiving signal is supplied to the signal processing unit. The received light signal has a high S / N ratio for reproducing quality and stable servo operation.
A ratio is required. In addition, since the amount of received light and the gain of the servo error signal vary due to factors such as the amount of irradiation light, the reflectance of the information recording medium, and characteristic variations among the individual optical pickups, gain adjustment is performed in each signal processing unit to absorb the variations. ing. Further, since the optical pickup is moved in a radial direction of the information recording medium (referred to as a seek operation), the optical pickup and a circuit board on which the signal processing unit and the like are mounted are flexible print circuits (Flexible Print Circuit).
t: FPC) is generally connected by a bendable board called a board, and the transmission path of the received light signal is the FPC.
Wired on the board.

In recent years, various types of optical discs have been proposed, and information recording / reproducing apparatuses which are compatible with a plurality of different types of information recording media formats have been provided. In addition, various types of optical pickups mounted on these information recording / reproducing apparatuses are in practical use, and further, optical pickups having various configurations for the purpose of miniaturization, cost reduction, and performance improvement. Has been proposed. However, in a conventional information recording / reproducing apparatus, the configuration and circuit characteristics of a signal processing unit (in particular, an arithmetic processing unit for generating a servo error signal) required for each optical pickup having a different configuration are different. A signal processing integrated circuit (that is, a servo error signal generation unit) suitable for the pickup is required, and there is a problem that it is difficult to shorten the development period and reduce the cost. Further, in an information recording / reproducing apparatus compatible with different information recording medium formats, if the signal processing units have different configurations and circuit characteristics, the signal processing units must be separately provided, so that miniaturization becomes difficult. There was also a problem. On the other hand, if the signal processing unit is to be shared as much as possible, the required specifications for the optical pickup become strict, which leads to difficulties in construction of the optical pickup and an increase in cost, resulting in a problem that the feasibility is poor. .

Conventionally, as a solution to such a problem, a photodetection signal obtained by converting a received light current into a voltage on the optical pickup side is first subjected to A / D conversion, thereby performing a subsequent reproduction RF signal extraction process. Matrix processing for servo control and various servo controls is performed by digital signal processing. Also, according to the medium format of the information recording medium, for example, calculation processing for generating a tracking error signal, various servo gains and wobbles. There has been proposed a light-receiving signal processing device (for example, see Japanese Patent Application Laid-Open No. H11-238245) configured to switch a pass band of a band-pass filter when extracting an address from a groove. Therefore, by performing all the various processes by digital signal processing, it is possible to realize a simple process and configuration.

[0005]

However, the above-mentioned conventional light receiving signal processing apparatus has a problem that the following problems are posed. That is, the light receiving signal is usually a minute analog signal in many cases, and the FPC board serving as the supply wiring (transmission wiring) cannot be avoided to have a certain length. However, there is a problem that the S / N ratio cannot be realized in some cases. In addition, the light receiving section usually has a large number of signal lines, each of which uses a plurality of divided light receiving elements to supply a light receiving signal, which limits the miniaturization of the FPC board. There was a problem that it became difficult. On the other hand, if the FPC board is miniaturized by narrowing the signal line width, there is a problem in that signal deterioration due to noise is further increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and it is not necessary to change the circuit even if the configuration of a portion for outputting a light receiving signal is changed. In order to achieve compatibility, the required specifications of the part equipped with a plurality of light sources and light receiving parts are relaxed to reduce costs, and signal deterioration due to noise in signal supply by the FPC board is reduced, and the number of signal lines to be transferred is reduced. The purpose is to be able to.

[0007]

In order to achieve the above object, the present invention provides a light receiving signal output switching means for inputting a light receiving signal of an analog signal and switching an output to a plurality of types of processing steps, and a light receiving signal output thereof. Digital signal conversion means for sequentially converting a received light signal output by the switching means from an analog signal to a digital signal in a time series and outputting the converted signal; transmission means for transmitting the received light signal output from the digital signal conversion means; The present invention also provides a light receiving signal processing device provided with light receiving signal arithmetic processing means for executing arithmetic processing of the plurality of types of processing steps based on the light receiving signal transmitted by the means.

Further, a light receiving signal output switching means for inputting a light receiving signal of an analog signal and switching the output to a plurality of types of processing steps, and sequentially receiving the light receiving signals output by the light receiving signal output switching means in time series Digital signal converting means for converting the digital signal into a digital signal and outputting the digital signal;
A plurality of first holding means for temporarily storing and holding light receiving signals converted into digital signals by the digital signal converting means, respectively, based on the light receiving signals held by the first holding means; Light reception signal calculation processing means for performing a plurality of types of processing processing, and a plurality of second holding means for temporarily storing and holding the output signal obtained by the calculation processing by the light reception signal calculation processing means, The output signal held by each of the second holding means or the light receiving signal held by each of the first holding means and a part of the output signal held by each of the second holding means are transmitted. Provided is a light receiving signal processing device provided with a transmitting means for performing the above.

Further, analog signal processing means for inputting an analog light receiving signal, performing analog signal processing in an RF signal band, and outputting the signal, light receiving signal of the analog signal, and light receiving signal output from the analog signal processing means. Signal output switching means for switching the output to a plurality of types of processing processes by inputting the received light, and a digital signal for converting the received light signal output from the received light signal output switching means from an analog signal to a digital signal in time series and outputting the signal. Signal conversion means, transmission means for transmitting a light reception signal output from the digital signal conversion means, and light reception signal calculation for executing the arithmetic processing of the plurality of types of processing steps based on the light reception signal transmitted by the transmission means Provided is a light receiving signal processing device provided with a processing unit.

In the above-described light-receiving signal processing apparatus, the transmission means may be a means for transmitting a signal in a time-division multiplex manner, and the transmission of the light-receiving signal and the control command signal converted by the digital signal converting means may be performed together. It is better to do it. Further, in the above-described light-receiving signal processing device, it is preferable that the transmission means only transmits a control command signal when the light-receiving signal is not input or when processing is unnecessary even if the light-receiving signal is input.

In the above-described light-receiving signal processing device, at least one of offset adjustment and gain adjustment is performed on the light-receiving signal output from the light-receiving signal output switching means and supplied to the digital signal converting means. Adjusting means for calculating a gain adjustment value based on a light receiving signal output from the digital signal converting means or an output signal obtained by arithmetic processing by the light receiving signal arithmetic processing means, and adjusting the gain adjusting value to the adjusting means It is preferable to provide a gain calculating means for resetting the gain.

Further, in the above-described light-receiving signal processing device, at least one of offset adjustment and gain adjustment is performed on the light-receiving signal output from the light-receiving signal output switching means and supplied to the digital signal converting means. Adjusting means for performing the above operation, adding means for sequentially adding and outputting a predetermined number of light receiving signals among the light receiving signals output in time series from the digital signal converting means, and an output signal output from the adding means being preset. It is preferable to provide a gain calculation unit that calculates a gain adjustment value so as to substantially match the predetermined target value and resets the gain adjustment value to the adjustment unit.

In the above-mentioned light receiving signal processing apparatus, a predetermined gain storage means for storing a predetermined gain adjustment value calculated in advance for the adjustment means, It is preferable to provide a gain adjustment value selecting means for switching and selecting the gain adjustment value to be reset. Further, in the above-described light receiving signal processing device, a gain adjustment value reading unit that reads a current value of the gain adjustment value calculated by the gain calculation unit may be provided.

In the above-described light receiving signal processing device, the light receiving signal output from the digital signal converting means is subjected to data conversion for increasing the number of bits in accordance with the offset adjustment value and the gain adjustment value of the adjusting means. It is preferable to provide data conversion means for supplying the light reception signal calculation processing means. Further, in the above-mentioned light receiving signal processing device, the transmission means may be a means for performing serial transmission.

The light-receiving signal processing apparatus according to the present invention is, for example, a light-receiving signal output from one or more light-receiving means for detecting the reflected light of light applied to an information recording medium, the amount of light emitted from a light source, and other states of an optical pickup. The present invention can be applied to a signal processing device for performing required signal processing related to a recording or reproducing operation on an information recording medium with respect to a signal and an information recording / reproducing device using the same. It is not necessary, especially in an optical pickup having a plurality of light sources and light receiving sections for compatibility with a plurality of different types of information recording media in particular, to reduce the required specifications for the optical pickup to reduce the cost, and A signal that reduces signal degradation due to noise in signal supply by the FPC board and further reduces the number of signal lines to be transferred The management circuit and the information recording and reproducing apparatus using the same can be easily realized.

[0016]

Embodiments of the present invention will be specifically described below with reference to the drawings. First, an overall configuration and operation of an information recording / reproducing apparatus to which the light receiving signal processing apparatus of the present invention is applied will be described. FIG. 1 is a block diagram showing a schematic configuration of an information recording / reproducing device to which a light receiving signal processing device of the present invention is applied.

This information recording / reproducing apparatus includes an information recording medium 1
This is a device that records and reproduces information (data) for 00. The information recording medium 100 is, for example, a CD-R
OM, DVD-ROM, CD-R, CD-RW, DVD
-R, DVD-RAM, MD, MO, etc. This is a recording medium on which information to be reproduced is recorded or information is recorded.

The optical pickup 101 irradiates laser light (emission light, irradiation light) emitted from a light source 102 of, for example, a semiconductor laser (LD) onto the recording surface of the information recording medium 100 to record information or to record information. The light source 102 receives the reflected light from the information recording medium 100 with respect to the irradiation light at the time of reproduction or information reproduction, converts the light into a light reception signal, and outputs the signal.
And a light source driving unit for driving the light source 102 (illustration and detailed description are omitted because it is a known technology), a light receiving unit 103 for receiving reflected light and converting it into a light receiving signal, and the like. The optical pickup 101 is also provided with a monitor light receiving unit (also shown in the drawing and detailed description is omitted because it is a well-known technology) for monitoring a part of the light emitted from the light source 102, and a monitor signal output from the monitor light receiving unit is provided. Light source 102 based
Of the emitted light (emitted light) is controlled.

Further, a tilt detecting light receiving unit (illustrated and detailed description is omitted because it is a well-known technology) for detecting a tilt (referred to as "tilt") of the information recording medium 100 with respect to irradiation light may be provided. Furthermore, when the information recording / reproducing apparatus is an information recording / reproducing apparatus capable of recording and reproducing information on a plurality of types of information recording media having different medium formats (for example, DVD and C)
D), a light source having a wavelength suitable for each information recording medium, and a light receiving unit and a monitor light receiving unit for receiving reflected light from the information recording medium when each light source emits light are provided separately. Good.

The signal processing unit 104 includes the optical pickup 10
Light-receiving signals from various light-receiving units arranged in 1 are input, and various signal processing is performed based on the light-receiving signals. For example,
Focus servo control and track servo control to reproduce information from the received light signal and to always irradiate light within a predetermined error with respect to fluctuations such as surface deflection and track radial deflection due to rotation of the information recording medium 100. For control, a servo error signal is generated from the light receiving signal, and the optical pickup 101 is controlled according to the servo error signal. Further, the information to be recorded is modulated according to a predetermined rule, and is output as a recording signal to the light source 102 (or the light source driving unit), or the output light amount is controlled when the light source 102 emits laser light.

The rotation drive unit 105 is connected to the information recording medium 100.
And a signal processing unit 10
The rotation speed is controlled by 4 (spindle servo control). When performing the CLV rotation control, a rotation control signal embedded in the information recording medium 100 is detected via the optical pickup 101 for more accurate rotation control, and the rotation control is performed based on the rotation control signal. . The rotation control signal includes, for example, a synchronization signal arranged at predetermined intervals in recorded information in a read-only information recording medium or the like, and a wobble in which a recording track meanders at a predetermined frequency in a recordable information recording medium. Is used. Controller 106
Performs transfer of recording / reproducing information and command communication with a host computer (not shown), and controls the entire information recording / reproducing apparatus.

The optical pickup 101 is moved in the radial direction of the information recording medium 100 (the direction of arrow 107 in the figure) (this operation is called a "seek operation"). A flexible printed circuit (Fle)
In general, components connected to the optical pickup 101 such as a light source 102 and a light receiving unit 103 are connected to the FPC board by means of a board (or cable) called an xixable print circuit (FPC) board (or cable). Often implemented.

Next, a description will be given of a normal signal processing section in the information recording / reproducing apparatus, which is a premise of the present invention.
FIG. 2 is a block diagram showing an internal configuration of a normal signal processing unit which is a premise of the present invention. This signal processing unit 104
Is provided with two light sources LD1 and LD2 to support information recording media of different formats,
And PD5 monitor part of the irradiation light of the respective light sources LD1 and LD2.

The light receiving section PD1 receives the reflected light from the information recording medium when the laser light is emitted from the light source LD1, and the light receiving section PD4 receives the reflected light from the information recording medium when the laser light is emitted from the light source LD2. The light receiving unit PD3 is a light receiving unit for detecting a tilt amount. The light receiving unit PD1
, PD3 and PD4 are composed of a plurality of divided light receiving elements, and each of the light receiving elements receives reflected light. It should be noted that some optical pickups are configured so that light emitted from the light sources LD1 and LD2 is monitored by the same light receiving unit. Similarly, there is also a configuration in which the same light receiving unit receives the reflected light from the information recording medium.

The input selection section 1 receives the respective light receiving signals output from the light receiving sections PD1 to PD5, and inputs one of the signals to the control section 11
Sequentially output according to the selection signal from. The adjustment unit 2 performs offset adjustment and gain adjustment of the received light signal output from the input selection unit 1. The A / D converter 3 digitally converts (A / D converts) the light receiving signal output from the adjusting unit 2 from an analog signal to a digital signal. The light receiving signal processed in the path by each unit is a signal of a relatively low band as described later, and a plurality of signals are processed in time series. The input selector 1, the adjuster 2 and the A / D converter 3 constitute a light receiving signal converter 21 '.

The servo signal arithmetic processing unit 13 performs digital arithmetic processing for generating a servo error signal based on each light receiving signal converted into a digital signal by the A / D converter 3. At the same time, offset adjustment and gain adjustment are also performed, and the generated servo error signal is supplied to the servo processor 14. The RF selecting unit 4 receives the light receiving signals output from the light receiving units PD1 and PD4, selects a signal necessary for a subsequent circuit, performs an operation such as partial addition and subtraction, and performs a high-speed analog signal processing unit 5 and a subsequent high-speed analog signal processing. The signals are supplied to the circuits of the wobble signal generator 6 and the RF signal preprocessor 8.

The high-speed analog signal processing section 5 performs high-speed analog signal processing such as DPD signal generation and RF envelope signal generation. The details of each generation process will be described later,
Since the generated signal does not require a wide band, it is input to the input selection unit 1 and subjected to time-series processing like other signals.
The wobble signal generator 6 detects a wobble preformatted on a recordable information recording medium.
The A / D converter 7 performs digital conversion (A / D conversion) of the wobble signal generated by the wobble signal generation unit 6 from an analog signal to a digital signal.

The wobble signal processing section 15 extracts a binary wobble signal from the wobble signal digitally converted by the A / D converter 7 and supplies it to the WCK generation section 17 and the rotation control section 18. Also, demodulates address information modulated according to a predetermined rule for each information recording medium from the wobble signal,
Supply to controller 19. The RF signal preprocessing unit 8
RF signal post-processing unit / phase-locked loop (PL
L) The reproduction R input from the RF selection unit 4 together with the circuit 16
A binary RF signal is generated based on the F signal, and demodulation is performed in accordance with the modulation scheme rules of the information recording medium being reproduced. Further, the reproduction clock is extracted from the binary RF signal by the PLL circuit. The demodulated data is sent to the controller 19
Supply to Further, a rotation control signal is extracted by a synchronization signal inserted at a predetermined interval into the binarized RF signal and supplied to the rotation control unit 18.

The rotation control unit 18 includes a wobble signal processing unit 1
5 generates a spindle error signal for performing rotation control from the binarized wobble signal or the rotation control signal input from the RF signal post-processing unit / PLL circuit 16 and supplies the spindle error signal to the servo processor 14. When the information recording medium is rotated at a constant angular velocity (CAV), a spindle error signal is generated by a signal (not shown) indicating the disk rotation output from a rotation control drive unit (not shown). The servo processor 14 generates a servo control signal from various input servo error signals based on a command from the controller 19 and outputs the servo control signal to the servo driver 20.

The servo driver 20 generates a servo drive signal based on the servo control signal input from the servo processor 14 and supplies it to each drive unit. Each drive unit performs a servo control operation according to the supplied servo drive signal. Here, the servo control operations are focus control, track control, seek control, spindle control, and tilt control. The WCK generation unit 17 generates a recording clock signal WCK based on the binarized wobble signal supplied from the wobble signal processing unit 15, and supplies the recording clock signal WCK to each unit of the LD modulation signal generation unit 10 and the controller 19. At the time of recording, recording data is generated based on the recording clock signal WCK. At the time of recording, the controller 1
9 and supplies the recording data signal Wdata to the LD modulation signal generation unit 10 in synchronization with the recording clock signal WCK.
In the recording data signal Wdata, information to be recorded is modulated according to a predetermined rule.

The LD modulation signal generator 10 is an LD for modulating the light source LD1 or LD2 from the recording clock signal WCK input from the WCK generator 17 and the recording data signal Wdata input from the controller 19.
A modulated signal is generated and supplied to the LD driver 12. LD
The control unit 9 receives a monitor light receiving signal from the light receiving unit PD2 or the light receiving unit PD5 via the input selecting unit 1 and the adjusting unit 2, and based on the monitor light receiving signal, the light sources LD1 and LD
2 so that the output light amount of the LD driver 2 becomes a desired value.
Is supplied with an LD control signal. So-called APC (Auto
The power control is performed. The LD driver 12 drives the light source LD1 or LD2 to emit laser light based on the LD control signal input from the LD control unit 9 and the LD modulation signal input from the LD modulation signal generation unit 10.

The light sources LD1 and LD2 and the light receiving sections PD1 to PD1
A portion including the PD 5, the light receiving signal conversion unit 21 ', the servo signal calculation processing unit 13, and the like corresponds to a main part according to the present invention, and the configuration example shown in FIG. 2 is a premise of the present invention in this embodiment. The configuration and processing of the main part according to the present invention will be described later. 1 is an integrated circuit 22, and the integrated circuit 22 is mounted on the optical pickup 101 in FIG. 1. The control unit 11 sends a control signal to each unit in the integrated circuit 22. Supply and control. At that time, the controller 1
A control command for each section is issued by the control command sent from 9.

Next, the main circuit blocks according to the present invention will be described in detail. The configuration and operation of the light receiving signal conversion unit 21 according to the present invention, which is provided in place of the light receiving signal conversion unit 21 'which is assumed above, will be described. FIG. 3 is a block diagram showing a detailed configuration of a main part according to the present invention. FIG. 4 is a signal waveform diagram for explaining the operation of the main part according to the present invention shown in FIG. FIG.
FIG. 3 is a block diagram showing a configuration of each light receiving unit shown in FIG.

As shown in FIG. 3, in this main part, first to n-th light receiving units PD1 to PDn each output one to a plurality of light receiving signals. The input selector 1 includes N switches SW
1 to SWN, and one end of each switch is connected to light receiving signals Sin1 to SinN from the corresponding light receiving unit. One of these switches SW1 to SWN is turned on in response to the selection signals Ssel1 to SselN, and the light receiving signal corresponding to the turned on switch is selected and output. The output light receiving signal is Sselo. The adjustment unit 2 includes an offset adjustment unit 30 and a gain adjustment unit 31, and performs offset adjustment and gain adjustment of the light receiving signal Sselo in accordance with the offset signal Sofs and the gain signal Sgain, respectively. The light reception signal output after the adjustment is referred to as ADin.

The A / D converter 3 converts the offset-adjusted and gain-adjusted light receiving signal ADin from an analog value (analog signal) to an n-bit digital value (digital signal).
Convert to The A / D converted data is supplied to a first interface (I / F) unit 32 and a second interface (I / F).
The data is transferred to the data holding unit 34 via the
The data is sequentially stored in the registers Reg1 to RegM of the data holding unit 34 according to the write signals Wr1 to WrM from No. 1. The servo signal calculation processing unit 13 performs a calculation process of generating a servo error signal from the data of the light receiving signal stored in the registers Reg1 to RegM of the data holding unit 34.
In addition, gain adjustment and offset adjustment for adjusting a gain variation due to an individual variation of the information recording medium and the optical pickup are also performed.

It should be noted that the number, type, and number of light receiving signal lines provided in this embodiment are merely examples. It can also be realized with the number of light receiving signal lines. In the following description, these light receiving units are provided with the light receiving units PD1 as in FIG.
A description will be given of an information recording / reproducing apparatus including five light receiving units of PD5.

For more specific description, the first light receiving portion P
D1 receives the reflected light from the information recording medium by the four-divided light receiving element 35 as shown in FIG.
Then, each divided light receiving element (a, b,
c, d) output the received light current according to the amount of received light by the current-to-voltage converters 37a to 37d, respectively.
VB, VC, and VD are converted and output. Here, since the amount of received light greatly varies depending on the amount of light emitted from the light source and the reflectance of the information recording medium, the current-voltage converters 37a to 37d
, Ie, the current-voltage conversion rate, can be switched in accordance with the gain switching signal. In this case, switching can usually be performed by switching the resistance value of the feedback resistor. This may be such that it can be switched between recording and reproduction.

The light receiving signal VA is output to the terminal of the switch SW1, the light receiving signal VB is output to the terminal of the switch SW2, the light receiving signal VC is output to the terminal of the switch SW4, and the light receiving signal VD is output to the terminal of the switch SW3. At this time, the focus servo method is an astigmatism method, the track servo method is a push-pull method, and the focus error signal FE and the track error signal TE are obtained by arithmetic processing based on the following equation 1, respectively. Since both the astigmatism method and the push-pull method are well-known methods, detailed description thereof will be omitted.

[0039]

FE = (VA + VD)-(VB + VC)

[0040]

## EQU2 ## TE = (VA + VC)-(VB + VD)

The control unit 11 in FIG. 3 sequentially changes the signals for turning on the selection signals Ssel1 to SselN depending on time based on a predetermined rule, and repeats this at a cycle Tsmp. The cycle Tsmp is divided into M periods, and the switch turned on by the input selection unit 1 changes for each of the divided periods, and the light receiving signal flowing through the terminal of the turned on switch is adjusted by the next stage adjustment unit. 2 is selectively output.

As shown in FIG. 4, when the selection signal Ssel1 is turned on in the period T1, the selection signal Ssel2 is turned on in the period T2, and the selection signals Ssel4, Ssel3,. VA, VB, VC, V
D,... Are output as Sselo. The A / D converter 3 A / D-converts the signal ADin obtained by adjusting the gain / offset of the light receiving signal Sselo once during a period Ti (i = 1 to M). If the A / D converted value is a value converted during the period Ti, the register Reg of the data holding unit 34
Stored in i. That is, the value of the light receiving signal VA is
The value of VB is stored in the register Reg2, respectively.

That is, each light receiving signal can be A / D converted at a sampling rate fsmp (= 1 / Tsmp), and a servo error signal can be generated by digitally operating the signal. Here, the servo control can be performed by sampling at a sampling rate fsmp that is sufficiently higher than the required bandwidth without requiring a wide band (for example, several kHz) for the servo error signal and each light receiving signal for generating the servo error signal. I use. Similarly, since it is not usually necessary to control the output light amount of the light source and the tilt control at a high speed, the monitor light receiving signal of the light source (the light receiving signal output from the light receiving units PD2 and PD4) and the tilt light receiving signal (the output of the light receiving unit PD3) Light receiving signal).

Incidentally, the selection signal S
The switching sequence of sel is programmable.
For example, when the light receiving signals VA, VB, VC, and VD are connected to switches different from those described above, the light receiving signals VA, V
If the switching order of the selection signal Ssel is programmed so that the switches to which B, VC, and VD are respectively turned on sequentially, the value of the light receiving signal VA is set to the register Reg1 and the value of the light receiving signal VB is set to the same as described above. Register Reg
2 and the subsequent processing unit does not need to be changed. For example, when the light receiving signal VA is connected to the terminal of the switch SW5, the light receiving signal VB is connected to the terminal of the switch SW6, the light receiving signal VC is connected to the terminal of the switch SW3, and the light receiving signal VD is connected to the terminal of the switch SW2.
The selection signal Ssel5 is sent to the control unit 11 during the period T1.
Programming is performed so that the selection signal Ssel6 is turned on in the period T2, the selection signal Ssel3 is turned on in the period T3, and the selection signal Ssel2 is turned on in the period T4.

When a plurality of light sources are used, a switch connected as an output destination of a light receiving signal output from a light receiving unit corresponding to an unused light source is not selected. When the reflected light from the information recording medium is received by another light receiving section (PD4), if the input selection section 1 is programmed so that the light receiving signals output from the PD4 are sequentially selected, the subsequent signals can be obtained. The processing can be performed by the same circuit system, and the circuit can be downsized.

With this configuration, even if there are a plurality of light receiving sections and the light receiving signal is input to any input terminal, it is possible to cope with the programming by the control section 11. The degree of freedom in arranging the parts that make up the optical pickup, including the light source and the LD driver, is improved. Further, even if the light receiving elements are light receiving elements having different division shapes and the servo error signal generation methods are different, after the light receiving signals output from the light receiving parts are sequentially selected by programming in the control unit 11, the A / A Since D-conversion can be performed to generate and generate a servo error signal, a variety of processes can be performed without changing existing circuits.

FIG. 6 is a block diagram showing a configuration of a programmable selection signal generation unit provided in control unit 11 shown in FIG. The selection signal generation unit generates the synchronization signal Ss
and a period information signal Sti output from the M-ary counter 38 which starts counting by y.
Rewritable conversion table (LU) for selecting and specifying an address of a data storage destination of the data holding unit 34 based on the selection signal Ssel1 to SselN.
T) 39.

The LUT 39 stores the switching order of the selection signals Ssel1 to SselN programmed in advance, and determines any one of the selection signals Ssel1 to SselN in that order based on the period information signal Sti. For example, the period information signal Sti = 3, that is, the period T
3, the selection signal Ssel4 = 1, and other selection signals S
sel1 to Ssel3 and Ssel5 to SselN output 0. Programming of the selection signal switching order is performed by rewriting the contents of the LUT 39. Further, even if the switching order of the selection signals Ssel1 to SselN is fixed, each register R of the data holding unit 34
If the order of writing to eg1 to RegM can be programmed, the same effect as described above can be obtained.

That is, the selection signals are Ssel1, Sse
.., Ssel3, Ssel4,..., the respective light receiving signals are output from the input selecting section 1 in the order of VA, VB, VD, VC,. A / D converted values may be written in the register Reg1 in T1, in the register Reg2 in the period T2, in the register Reg4 in the period T3, and in the register Reg3 in the period T4. This can be realized by controlling the write signals Wr1 to WrM to the registers Reg1 to RegM. FIG.
The programmable write signal generation unit provided in the control unit 11 shown in FIG. 6 may have the same configuration as the selection signal generation unit shown in FIG.

Further, the selection signals Ssel1 to SselN
May be combined with the order of writing to the registers Reg1 to RegM. In addition, only inputs necessary for programming the selection signal are sequentially selected (for example, a switch whose input terminal is not connected is not selected), and the registers Reg1 to R
The data may be exchanged in the order of writing to the egM. Further, it is preferable that the number of time divisions M can be programmed according to the number of data series (the number of registers) required in the processing unit at the subsequent stage, and the period Ti is sufficient for A / D even if the delay time of each circuit is taken into consideration. The sampling period Tsmp may be changed as long as the conversion time can be secured.

When the selection signal is generated by the selection signal generation section or the write signal generation section shown in FIG. Further, the offset adjustment unit 30 and the gain adjustment unit 31 are provided for effectively utilizing the input range of the A / D converter 3, and are provided at the subsequent stage of the input selection unit 1 as shown in FIG. Circuits can be shared.

Further, if the offset signal Sofs and the gain signal Sgain are changed in conjunction with the switching of the selection signals Ssel1 to SselN, the gain / offset adjustment can be performed individually for each light receiving signal in the same circuit. Even if there is a difference between the levels of the light receiving signals output from the respective light receiving units, the respective signals can be accurately A / D converted. For example, since the amount of received light usually changes for each light receiving unit, the gain may be changed for each light receiving unit.

The offset adjustment value and the gain adjustment value are stored in the control unit 11 in advance. The calculation of the gain adjustment value may be performed as follows, for example. The amount of received light varies depending on the amount of light applied to the information recording medium, the reflectivity of the information recording medium, variations in characteristics among the individual optical pickups, and the like. Therefore, by detecting the monitor light receiving signal of the light source and calculating the gain adjustment value based on the detected monitor light receiving signal, it is possible to absorb the change in the irradiation light amount. Also, when the reflected light from the information recording medium is received by the divided light receiving elements, the amount of received light can be detected by calculating the sum of the respective light receiving signals output from the divided light receiving elements.
The gain may be calculated based on the resultant sum signal.

Similarly, the peak envelope signal of the RF signal (the bottom envelope signal when the polarity of the RF signal is negative) also depends on the amount of received light, and may be used. According to this embodiment, those detected values can be detected by the A / D converter 3. Further, the data which is A / D converted by a data converter not shown is converted so as to increase the number of bits according to the offset adjustment value and the gain adjustment value of the offset adjustment unit 30 and the gain adjustment unit 31, If the data conversion value is arithmetically processed by the servo signal arithmetic processing unit 13, it is possible to perform an arithmetic operation with higher accuracy without increasing the number of bits of the A / D converter 3.

FIG. 7 is a block diagram showing a configuration of a gain control section for automatically controlling the gain of the gain adjustment section 31 according to the amount of received light in the information recording / reproducing apparatus of this embodiment. The gain control unit 80 is provided in the control unit 11,
An adder 81 for adding predetermined data among the A / D converted light receiving signals, an averaging unit 82 for averaging the output from the adding unit 81, and a predetermined target value and an output from the averaging unit 82 And a gain calculator 83 for calculating a gain from the above. The adder 81 multiplies the output from the A / D converter 3 by a coefficient of “1” or “0”, and adds the output from the multiplier 87 and the output from the delay register 89. Unit 88 and the output from the adder 88
An output from the adder 88 is an output from the adder 81.

According to the above-described example, each light receiving signal is A / D converted and output from the A / D converter 3 in the order of Dva, Dvb, Dvc, Dvd, and other light receiving unit outputs. Dva ~
Assuming that the coefficient up to Dvd is a coefficient 1 and the other coefficients are 0, an addition output of Dva to Dvd, that is, a sum signal of the first light receiving unit PD1 is obtained in one cycle (Tsmp). The DC signal of the sum signal is detected by averaging the sum signal in the averaging unit 82. The gain calculating unit 83 compares the predetermined target value with the output from the averaging unit 82 by using the comparing unit 90, and increases or decreases the current value of the gain based on the comparison result to reset the gain. That is, if the sum signal is smaller than the target value, the gain is increased, and if it is larger, the gain is decreased. If the sum signal is within the predetermined value, the current value is held. Adder 91
Is the gain increase / decrease signal output from the comparing section 90 and the holding section 92
The current value of the gain, which is the output of, is added to update the gain.

In this manner, the sum signal (that is, each light receiving signal) can be automatically controlled so as to be substantially a predetermined value, and the amount of light emitted from the light source and the reflectance of the information recording medium change. Even if the amount of received light fluctuates, A /
D conversion can be performed, and thereby a stable servo operation can be performed. The signal to be controlled need not be the above-described sum signal as long as the signal fluctuates in proportion to the amount of received light. For example, there is a peak hold signal (or bottom hold signal) of an RF signal described later. If the signal is used, it is not necessary to perform the calculation in the adding section in the gain control section, so that the circuit can be simplified.

The same effect can be obtained even if the connection order of the averaging unit 82 and the comparison unit 90 is changed. If a gain control unit 86 having the same configuration as that of the gain control unit 80 is provided in parallel with the gain control unit 80, the gain can be automatically controlled for each light receiving unit. The gain selector 84 switches the gain calculated by the gain controllers 80 and 86 or the gain adjustment value stored in the gain register 85 in conjunction with the selection signal Ssel. For example, the adjustment value stored in the gain register 85 may be used in a signal or situation that does not require automatic gain control, such as when the reflectance of an information recording medium is detected by a monitor light receiving signal or a sum signal. . If the gain calculated by the gain control unit 80 is read, the above-described conversion of increasing the number of bits of the A / D conversion data can be performed.

The light receiving signal converter 21 shown in FIG. 3 includes an input selector 1, an offset adjuster 30, and a gain adjuster
1, A / D converter 3 and first interface (I / F)
The optical pickup 1 is separated from the signal processing unit 104 at the subsequent stage together with the control unit 11 for controlling them.
01.

In this case, the signal line transferred by the FPC board becomes a digital signal between the first I / F 32 and the second I / F 33, and these circuits can be arranged in the immediate vicinity of each light receiving section. Therefore, there is no need to transfer a light receiving signal, which is often a minute analog signal, over a long distance, and the signal is hardly affected by noise. Further, by performing serial data transfer between the interfaces, the number of signal lines to be transferred can be significantly reduced.

Further, in this embodiment, in order to connect a light receiving signal from each light receiving section to a specific input terminal on the FPC board (or on the optical pickup board), the signal line becomes long or the signal line crosses. If it increases, there arises a disadvantage that the wiring itself becomes impossible. Therefore, in this embodiment, the above-described liberalization of the connection input terminal by programming works particularly effectively. Furthermore, since each light receiving signal before the servo calculation by the servo signal calculation processing unit 13 is converted into a digital signal and transferred, a servo signal calculation processing unit that can be programmed in a calculation method described later can be realized with a simple process and configuration.

Next, the operation of the interface unit and the data communication method will be described. FIG. 8 is a block diagram showing a configuration of a main part relating to data communication in the main part shown in FIG. FIG. 9 is a signal waveform diagram for explaining a data communication method by a main part related to the data communication shown in FIG. As shown in FIG. 8, the main parts related to data communication are:
The signal AD whose offset / gain is adjusted by the A / D converter 3
in is converted from analog to digital (A / D) according to the conversion start signal CNV. The latch unit 40 converts the A / D-converted n-bit data into a latch signal L from the control unit 11.
Hold according to EN.

The parallel / serial converter (P / S converter) 41 outputs a data communication clock Sck (having a cycle of Tsc
k), the n-bit latch output is subjected to parallel / serial conversion to output serial data Dout. Shift register (SR) 42 that performs serial / parallel conversion of data output from P / S converter 41
In accordance with the register write signals Wr1 to WrM, and sequentially store them in the registers Reg1 to Reg of the data holding unit 34. The control unit 43 that performs communication control on the control unit 11 and the second I / F unit 33 outputs a control signal to each unit based on a synchronization signal Ssy output from a controller (not shown). The control unit 11 starts outputting the selection signals Ssel1 to SselN in synchronization with the synchronization signal Ssy.

The selection signals Ssel1 to SselN are output in the order programmed as described above. At this time, the time Tc for turning on one channel
h is Tch = n · Tsck (n is the number of A / D conversion bits). If necessary, the offset signal Sofs and the gain signal Sgain are simultaneously changed in synchronization with this. Further, the conversion start signal CNV is sent to the A / D converter 3.
Is output for each time Tch.

In FIG. 9, the output timing of the conversion start signal CNV is a case where the switching time of the input selector and the delay time of each circuit are negligibly short. It may be made to be.
Further, a latch signal LEN is output every time Tch in order to hold the converted data. These operations are performed for M channels (hereinafter, this is referred to as one frame). Naturally, the period Tsmp of the synchronization signal Ssy is Tsmp ≧ M ·
It is assumed that the relationship of Tch is established.

On the other hand, the control section 43 outputs a register write signal Wr based on the synchronization signal Ssy. In the case of the example of the signal waveform shown in FIG. 9, 2 · Tch of the synchronization signal Ssy
After (= 2n · Tsck), the first write signal Wr1 is output, and the write signal Wr is sequentially output for each time Tch during which one channel is turned on. As described above, the write signal Wr
The output order of 1-WrM may be programmable. Further, the synchronization signal Ssy may be synchronized once every k frames (k: natural number) or not every one or several channels, instead of being synchronized every frame.

Next, time division multiplexing of command communication to the control unit 11 and data transfer will be described. According to the following embodiment, a signal line from the controller 19 to the control unit 11 can be shared for command communication and data transfer. That is, the signal line is connected from the controller 19 to the control unit 11.
A command communication phase for performing command communication to the PC and a data transfer phase for transferring data are used. By doing so, the number of signal lines can be reduced. Usually, it is not necessary to frequently perform the command communication, and the data transfer is not prevented.

An embodiment of the communication method will be described below. A signal line C / D (Hi: command communication phase, Low: data transfer phase) for identifying a command communication phase and a data transfer phase is provided, and the control unit 11 identifies the phase according to the signals. Also, the signal line C /
If the data transfer is synchronized with the falling edge of D, it can also serve as the synchronization signal Ssy.

In the signal waveform shown in FIG. 9, the time corresponding to one channel is allocated as the command communication phase after the period TM. When the command communication is time-division multiplexed, the above-described definition of the frame is extended to an interval from the period T1 to the next period T1. That is, it is assumed that a period for the command communication phase to be inserted is added to a period for the M channels.

Command communication to the control unit 11 is performed by accessing a command register (not shown) in the control unit 11, and one command is composed of a command register address (7 bits) and a read / write command. It consists of a bit indicating write access distinction and write / read data (8 bits). The period of the command communication phase inserted in one frame may be a time during which one or several commands can be transferred, or a time during which one command can be transferred in a plurality of frames (that is, for example, the command communication in the first frame). An address and a read / write access bit may be transferred to a phase, and data may be transferred to a command communication phase in the next frame.) In this way, if the method of inserting the command communication phase is determined in advance, the signal line C for identifying the phase can be used.
/ D becomes unnecessary, and the number of signal lines can be reduced.

Note that the synchronization signal Ssy may be provided by command communication to the control unit 11 without providing a dedicated signal line. That is, when an access is made to a predetermined command register, a synchronization signal may be generated at the same timing in each control unit after the access is completed.
In this way, the number of signal lines can be further reduced.
Further, when information is not reproduced / recorded, such as during startup or standby, that is, when the optical pickup 101 does not operate, there is no need to transfer A / D conversion data, and this period is always referred to as the command communication phase. For example, it is possible to quickly initialize a command register that requires a large amount of command communication. When the pickup operation is performed, the mode is shifted to the multiplexing mode.

FIG. 10 is a block diagram showing the configuration of another embodiment of the light receiving signal input section comprising the light receiving section and the light receiving signal converting section. The N light receiving units PD1 to PDn and the input selection unit 1 are the same as those in FIG.
The output signal Ssel is obtained by programming SselN.
In o, each light receiving signal is sequentially output. The offset / gain adjustment of the output signal Sselo is performed by the offset adjustment unit 30 and the gain adjustment unit 31 in the same manner as described above, and the sample / hold (S / H) circuit 44 includes the first sample / hold (S / H) circuits SH1 to SH1. M sample hold (SH
M) M circuits SHM, each S / H circuit SH
1 to SHM, each light receiving signal is sampled and held. The signal operation unit 45 generates a servo error signal from the output (or a part thereof) of each of the S / H circuits SH1 to SHM.

Next, this light receiving section is the light receiving section shown in FIG.
A description will be given of a case in which (the generation of E is described) is calculated based on Equations 1 and 2. The input selector 1 has the same configuration and operation as described above, and sequentially outputs the light receiving signals VA, VB, VC, VD as the output signal Sselo (corresponding to the periods T1, T2,..., Respectively). S / H circuit S
H1 performs the sampling operation in the period T1 according to the sampling signal Ssmp1, and performs the hold operation in the other periods. That is, the light receiving signal VA selected in the period T1 is sampled in the cycle Tsmp. Similarly, S / H
The circuit SH2 is in the period T2, and the S / H circuit SH3 is in the period T3.
In addition, the S / H circuit SH4 performs a sampling operation in the period T4.

In this manner, the first S / H is selected by programming the selection order no matter where the respective light receiving signals are input.
The output of the circuit SH1 receives the light receiving signal VA, the output of the second S / H circuit SH2 receives the light receiving signal VB, and the third S / H circuit SH.
3, the light receiving signal VC is output to the output of the fourth S / H circuit SH4, and the light receiving signal VD is output to the output of the fourth S / H circuit SH4. The track error signal can be generated by the arithmetic circuit 47 that performs the arithmetic processing based on the above equation 2, and the track error signal can be generated by the arithmetic circuit 46 that performs the arithmetic processing based on the equation 1. Further, even if the switching order of the selection signal Ssel is fixed, the first S / H circuits SH1 to MS
/ H circuit SHM sample timing Ssm
If p1 to M can be programmed, they can be implemented in the same manner as described above.

Next, another embodiment of the input selector 1 will be described. FIG. 11 shows the input selection unit 1 shown in FIG.
FIG. 13 is a block diagram showing another example of the configuration. In the input selection unit 1, a low-pass filter (LPF) 48 and a sample hold (S / H) are provided for each of the switches SW1 to SWN.
A circuit 49 is provided (switches SW1 and SW2 in the figure).
And low-pass filters LPF1 to LPF1 for the input light receiving signal Sin.
Unnecessary high frequency components are cut by the LPFN and input to the respective switches SW1 to SWN. In addition, by sampling and holding each input signal at the same timing SMPin by each of the sample and hold circuits SH1 to SHN, it is possible to obtain an A / D conversion value at the same time, which may cause a delay difference of the maximum Tsmp. As a result, when the servo error signal is generated in the subsequent stage, the common-mode noise components that cannot be completely removed by the LPF can be canceled out.
More accurate signal generation becomes possible.

Conventionally, as a method of stabilizing the servo operation during recording, a light receiving signal of reflected light from an optical disk is held for a period synchronized with a writing period in which the light amount is large, and is sampled during the other periods to obtain a signal for the writing period. Is not used for generating a servo signal, so that a change in servo gain due to a change in light amount during recording is eliminated, and the servo operation is stabilized. Therefore, at the time of recording, the sampling operation of the sample and hold circuit is performed at the sample timing S.
If MPin is performed at Hi level and during a period other than the writing period, in addition to the above-described effects, a change in servo gain due to a change in light amount during recording can be eliminated, and the servo operation can be stabilized.

As the light receiving section, a light receiving element alone (PD: Photo Detect) without a built-in current / voltage converter.
tor, etc.), and the light receiving signal in that case is output as a current. In such a case, it is desirable to integrate the current-voltage converter in the signal processing unit from the viewpoint of installation space and cost. Therefore, an embodiment in that case will be described next.

Next, still another embodiment of the input selector 1 will be described. FIG. 12 is a block diagram showing still another configuration example of the input selection unit 1 shown in FIG.
In the input selection unit 1, the input terminals of (or part of) the switches SW1 to SWN are respectively provided with a current / voltage converter 50 and a voltage buffer 51 (which can be omitted) and a selector for selecting and outputting their outputs. 52 (only the switch SWN is shown in the figure, and other illustrations are omitted), and the selector 52 can set which output is to be selected.

In this way, regardless of whether the light receiving signal output from the light receiving unit is a current signal or a voltage signal,
Also, no matter which input terminal is connected, it is possible to make it correspond by programming. The light-receiving signal converted by the current-voltage converter is a signal on the positive side with respect to a predetermined reference voltage (the voltage increases as the amount of received light increases) and a signal on the negative side. is there. In order to make effective use of the A / D converter in the latter stage, it is desirable to unify them into one. Therefore, an embodiment in that case will be described next.

Next, still another embodiment of the input selector 1 will be described. FIG. 13 is a block diagram showing still another configuration example of the input selection unit 1 shown in FIG. In this input selection unit 1, each of the switches SW1 to S
A polarity selection unit 53 is connected to the input terminal of WN (or a part thereof) (only the switch SWN is shown in the figure, and other illustrations are omitted), and the polarity of the input signal is determined by the polarity selection signal. Invert can be set. The polarity selection unit 53 includes an inverting amplifier 55, a non-inverting amplifier 54, and a selector 56 that selects and outputs the output of these.

Further, a predetermined offset may be applied to the offset adjusting unit 30 without using the polarity selecting unit 53. For example, the input light receiving signal is a signal on the negative side with respect to the reference voltage Vref, and the input dynamic range is 0 to Vref.
f (see FIG. 14A), if only the voltage of the reference voltage Vref is applied to the offset, A
Since the input of the / D converter becomes a signal on the positive side with respect to the reference voltage (see FIG. 14B), it is not necessary to uselessly widen the input range of the A / D converter. A / D
After the conversion (for example, in the servo signal calculation processing unit 13), the correction for the applied offset voltage may be performed.

FIG. 15 shows the input selection unit 1 and the adjustment unit 2
It is a block diagram showing the composition of other embodiments. The input light receiving signals Sin1 to SinN are provided by N switches SW1 to SW1.
Each of the switches SW1 of the switch 140 made of SWN
To SWN. The other terminals of the switches SW1 to SWN are connected in series to the negative input terminal of the operational amplifier 142 via a resistor. Switch 1
41 also includes N switches SW (N + 1) to SW (2
N), and each of the switches SW (N + 1) to SW (2
The input terminal N) is connected to the input light receiving signals Sin1 to N, and the other terminal is connected to the positive input terminal of the operational amplifier 142 via a series resistor.

The resistance values connected to the switches are all the same. Each switch is connected to a selection signal Ssel1 to Ssel1.
On / off control is performed according to Ssel (2N). The variable resistor 145 is a feedback resistor of the operational amplifier 142, and the variable resistor 146 is connected between the positive input terminal of the operational amplifier 142 and the reference voltage, and a resistance value is set by a gain control signal. Further, a D / A converter (DAC) 143 performs D / A conversion of the offset adjustment value Sofs, and is connected to a negative input terminal of the operational amplifier 142 via a variable resistor 144. By changing the variable resistor 144, the offset adjustment range can be changed.

Here, assuming that the selection signal Ssel is given so that the switches SW1, SW3, SW (N + 2) and SW (N + 4) are turned on during the input selection period Ti, the output from the operational amplifier 142 is It becomes a value obtained from the calculation based on the following Expression 3, and the addition / subtraction calculation of the input light receiving signal can be performed. Here, G: gain, Ofs: offset.

[0085]

## EQU3 ## G · (−Sin1 + Sin2-Sin3 + Si
n4-Ofs)

Therefore, if configured as shown in FIG.
The operational amplifier 142 can add or subtract any signal of the received light signals Sin1 to SinN and adjust the gain / offset by setting the selection signal Ssel. If the output is inputted to the A / D converter 3, the operational signal becomes a digital value. Can be converted to If only one switch is selected, the light receiving signal can be selected by the same circuit, and the polarity can be selected by selecting the switches 140 and 141. Although not shown, if a switch for short-circuiting the resistor connected to the switch 140 is provided in parallel with the resistor connected to the switch 140, the operational amplifier 142 is used as a current-to-voltage converter when the input signal is a light receiving current. It is also possible.

In this way, if the signal subjected to the addition / subtraction operation is converted into a digital value and transferred, the first I / F 32 and the second I / F 33 are compared with the case where each light receiving signal data before the operation is transferred and digitally operated. In some cases, the number of data to be transferred during the period may decrease, and the transfer rate can be reduced, so that unnecessary radiation can be reduced. In addition, a computing unit such as the adding unit 81 shown in FIG. 7 can be omitted.

Next, A / D conversion of a wideband signal processing output will be described. Incidentally, a tracking method called a phase difference detection method is used in a DVD-ROM or the like.
This phase difference detection method (hereinafter referred to as the DPD method) compares the phases of two signals obtained from the diagonal sum of the four-divided light receiving elements, and detects the phase difference between the two signals generated when the beam spot passes through the center of the pit. The tracking operation is performed by detecting the phase shift between the beam spot and the track from the amount of phase advance or the amount of delay.

Since each received light signal and its signal processing unit require an RF band, when performing A / D conversion and digital signal processing, a high-speed A / D converter must be used, and the circuit scale is reduced. When the A / D converter speed is insufficient, a signal may not be generated with high accuracy. Further, since it is not necessary to perform wideband signal processing for generating other servo error signals as described above, it is wasteful to use a common circuit. On the other hand, the DPD signal generated after the signal processing is a signal in the same band as the other servo error signals.

FIGS. 16 and 17 are block diagrams showing the configuration of a preferred embodiment in such a case. The first light receiving unit PD1 is a light receiving unit that receives reflected light from the information recording medium when tracking is performed by the DPD method, and is, for example, a light receiving unit having a configuration illustrated in FIG. The DPD signal generation unit 71 may use a well-known signal processing circuit, and a detailed illustration and description will be omitted. DPD signal generator 71
The DPD signal Sdpd generated in (1) is connected to one end of the input selection unit 1 (the switch SW5 in FIG. 16).
The signal processing band required for the generated DPD signal Sdpd may be the same as other servo error signals and the light reception signal before generation, so that the subsequent processing is performed in the same manner as described above.
The D-converted value is stored in a predetermined register.

In this manner, since a high-speed analog signal processing circuit is used for a portion requiring signal processing in the RF band, a signal can be generated with high accuracy. Since transfer is performed, signal deterioration due to noise during transfer can be prevented without using a high-speed A / D converter. Furthermore, the same signal as the other signal before servo error generation can be processed by the same circuit, and the transfer signal line can be shared, so that the circuit scale can be reduced and the transfer signal line can be reduced.

Further, before each input to the DPD signal generating section 71, an RF selecting section 4 (having the same configuration as the input selecting section 1 shown in FIG. 3) is provided, and the light receiving signals Sin1 to SinN are provided.
(The selection of the switch is determined by the pickup and does not change during operation), the effect of improving the degree of freedom in the arrangement of parts constituting the optical pickup can be obtained in the same manner.

Also, the envelope signal of the RF signal (generated by the peak hold (P / H) circuit 74 or the bottom hold (B / H) circuit 75) and the change in the amount of reflected light caused by the recording mark formed during recording. OPC (Optimum) that controls recording power by
Recording RF used in Power Control)
The output from the sample and hold (S / H) circuit 76 for sampling a predetermined level of the signal also requires a high-bandwidth processing by the signal generation processing unit as in the case of the DPD signal, but the generated signal itself requires a wideband. No, so it can be done in the same way.

The addition amplifier 72 adds the light receiving signals of the main spot and generates an RF signal. Some light-receiving units may output the RF signal by incorporating the addition amplifier 72. In this case, the addition amplifier 72
May be omitted, and illustration and its detailed description are omitted.
You may make it possible to select these signals. Further, the variable gain amplifier 73 amplifies the RF signal in accordance with the RF gain signal instructed by the control unit, and can improve the detection accuracy by increasing the input level to the subsequent circuit.

Next, generation of a servo error signal by digital signal processing will be described. FIG. 18 is a block diagram showing the internal configuration of the servo signal calculation processing unit 13. FIG. 19 shows the servo signal processing unit 1 shown in FIG.
FIG. 6 is a waveform chart for explaining the operation of No. 3; According to the servo signal arithmetic processing unit 13 having the configuration shown in FIG. 18, various types of arithmetic methods for generating a servo error signal can be handled by changing coefficients described later. As an example, the focus error signal FE is generated by the astigmatism method, and the track error signal TE is generated by the differential push-pull method.
A case in which it is generated by an arithmetic process based on. Since the astigmatism method and the differential push-pull method are well-known methods, detailed description is omitted.

[0096]

FE = (VA + VD)-(VB + VC)

[0097]

## EQU5 ## TE = (VA + VC)-(VB + VD) -K1
・ ((VE + VG)-(VF + VH))

Here, K1 in Equation 5 is a constant determined from the light amount ratio between the main beam and the sub beam, and the like.
By properly setting this, it is possible to correct the offset component generated due to the optical axis shift. Data holding unit 34
Registers Reg1-RegM are light-receiving signals VA-V
A register in which A / D conversion values Dva to Dvh of H are stored, and are stored in registers Reg1 to Reg8, respectively, and are updated at intervals of a cycle Tsmp. Each register outputs the value of the register selected by the output enable signals OE1 to OEM. The output enable signal OE is sequentially switched from OE1 to OEM according to the clock MCK. That is, the output Dx is Dva, Dvb,.
, Dvh,... Are output in this order. The subsequent circuits also operate according to the clock MCK.

The adder 60 adds the signal Dv and the pre-operation offset Dofs, and the multiplier 62 multiplies the output from the adder 60 by a factor of Kv. According to the output enable signals OE1 to OEM, the offset value Dofs and the coefficient Kv are calculated by one of the pre-operation offset registers OFS1 to OFSM of the pre-operation offset register group 61 and the operation coefficient registers Kv1 to KvM of the operation coefficient register group 63.
Are selectively output. While the output enable signal OE1 is on, the output from the multiplier 62 is Kv1 · (Dva + OFS1).

The pre-computation offset registers OFS1 to OFSM of the pre-computation offset register group 61 store offset adjustment values of the respective light receiving signals VA to VH. The operation coefficient register group 63 includes a plurality of banks. Each bank is a group of M registers of operation coefficient registers Kv1 to KvM, and the banks are switched by the operation phase signal Sph.
The calculation phase signal Sph is a signal indicating the phase of each servo error signal calculation generation such as the FE calculation phase and the TE calculation phase. When FE and TE are generated by the arithmetic processing based on the above equations (4) and (5), the operation coefficient register group 6
3 stores coefficients shown in Table 1 below.

[0101]

[Table 1]

The adder 64 adds the output from the multiplier 62 and the output from the register RegTmp65. The register RegTmp65 holds the output from the adder 64 one clock before, and the output enable signal OE
It is reset during the period when 1 is turned on. The adder 66
Output from adder 64 and servo signal offset SVOf
and the multiplier 68 multiplies the output from the adder 66 by a factor of Kg. Servo signal offset SVOf
s and coefficient Kg are an offset adjustment value and a gain of each servo error signal, and the output is switched by the operation phase signal Sph. Servo error signal register Reg
SV70 is holding means for storing the calculated servo error signals. Here, assuming that it is the FE calculation phase, the output of the register RegTmp becomes the period t1, t2,.
.., The values shown in the following equations (6) to (9) are obtained. During the period tm, the output of the adder 64 is FE-calculated.

[0103]

## EQU6 ## t1: 0

[0104]

T2: Dva + OFS1

[0105]

T3: (Dva + OFS1) + (− 1 · (Dv
b + OFS2))

[0106]

T4: (Dva + OFS1) + (− 1 · (Dv
b + OFS2)) + (− 1 · (Dvc + OFS3))

That is, the value shown in the following expression 10 (the offset adjustment value is omitted).

[0108]

Dva-Dvb-Dvc + Dvd + 0. (D
ve + ...)

At this time, the output from the adder 64 is multiplied by the addition of the FE offset value FEOfs and the FE gain to generate an FE signal, which is stored in the register RegFE. Similarly, when the operation proceeds to the TE operation phase, the period t
The output from the adder 64 becomes the value shown in the following equation 11 (the offset adjustment value is omitted), and the output of the adder 64 is multiplied by the addition of the TE offset value TEOfs and the TE gain to m. A signal is generated and the register Reg
Stored in TE.

[0110]

Dva−Dvb + Dvc−Dvd−K1 · D
ve + K1 · Dvf−K1 · Dvg + K1 · Dvh

Further, other servo error signals (for example, a lens position signal, a track cross signal, a sum signal, a tilt servo error signal, etc.) necessary for control are generated in a subsequent calculation phase.

In this way, a plurality of servo error signals can be generated by the same circuit, and the circuit scale can be reduced. Further, by changing the operation coefficient Kv, it is possible to generate servo error signals by various operation methods, and it is possible to correspond to various optical pickups. further,
A medium format discriminating unit (not shown) for discriminating the type of the medium format of the information recording medium is provided, and the servo signal calculation processing unit 13 changes the content of the above-described calculation processing based on the discrimination result of the type of the medium format. For example, even if the servo error signal generation method is different in a device corresponding to a plurality of information recording media of different formats,
Since the type of the information recording medium can be identified and changed by changing the operation coefficient Kv according to the identification result, it is not necessary to separately provide each servo error signal generation unit, and the circuit scale can be reduced. . Furthermore, when high-speed arithmetic processing is required, a similar arithmetic unit may be provided to perform parallel processing.

During this operation phase, each A / D conversion data needs to be determined (not updated).
By assigning the above-described command communication phase to this calculation phase, data and command communication can be performed without waste. Further, the output of the servo error signal register RegSV70 for storing the operation result is output to a D / A converter (D / A converter).
If the signal is converted into an analog signal by the A conversion means), an existing servo processor which assumes a servo error signal input as an analog signal can be used.
Further, by providing a plurality of sample and hold circuits for sampling and holding the output from the D / A converter and holding the servo error signal generated in each operation phase, the D / A converter can be shared. Can be.

Next, the wobble signal generator 6 will be described in detail. FIG. 20 is a block diagram showing the internal configuration of the wobble signal generator 6 shown in FIG. 2 together with other related components. This wobble signal generation unit 110
And a so-called push-pull signal PP is generated by an arithmetic process based on the following equation 12, and a recording track (referred to as a groove) meanders at a predetermined frequency from the push-pull signal PP. The wobble signal component is extracted to generate a wobble signal WBL.

[0115]

## EQU12 ## PP = (VA + VC)-(VB + VD)

The summing amplifiers 111 and 112 are connected to V
A + VC and VB + VD are added to each other to output VAC and VBD. The DC component removing units 113 and 114
It removes the DC components of the respective light receiving signals VAC and VBD, and extracts the DC component extracting unit 11 from each signal.
9 is subtracted from the DC removal signal, and the signal VA is subtracted.
C 'and VBD' are output.

[0117] The DC component extracting section 119 is provided with the A / D converter 3
The digital values of the light receiving signals VA to VD converted by the above are added by an adder 120, and the signals VA + VC and VB are respectively added.
+ VD is obtained, and the averaging unit 121 calculates a DC removal signal. At this time, since the digitally added value is increased or decreased by the gain adjusted by the gain adjusting unit 31, the value is corrected so as to match the gain of the addition amplifiers 111 and 112.
The DC component removing units 113 and 114 are high-pass filters (H
Although a low cut-off frequency HPF that usually removes a DC component requires a large-capacity capacitor, a terminal for increasing the chip size of an integrated circuit and externally connecting a capacitor may be used. The problem that it becomes necessary arises.

However, according to this embodiment, the above problem does not occur. Further, the band of the DC removal signal generated by changing the averaging unit 121 can be changed. AGC (Automatic Gain Cont)
orol) circuits 115 and 116 provide signals VAC 'and VB
This is a circuit for automatically adjusting the gain so that the amplitude of D 'becomes a predetermined value. The subtraction amplifier 117 subtracts the outputs of the AGC circuits 115 and 116 to generate a wobble signal WBL. The generated wobble signal WBL is A / D converted by the A / D converter 118 and transferred through the first I / F unit 32 and the second I / F unit 33. The data communication method and the interface unit are the same as those shown in FIG.
The operation may be performed in the same manner as the operation based on the signal waveform shown in FIG.

The wobble signal processing section 122 performs digital signal processing for generating a binary wobble signal and demodulating address information according to a predetermined information recording medium format.
When tracking the already recorded area, the recorded RF signal is detected by being superimposed on the signals VAC and VBD in the same phase. The amplitude of the RF signal component to be superimposed depends on the amount of received light, and if the amount of light is the same, it can be removed by subtraction. However, if the center of the light receiving spot deviates from the dividing line due to the optical axis deviation or the initial adjustment deviation of the light receiving element, the amount of received light is uneven between the light receiving elements, and the RF signal component cannot be sufficiently removed. Similarly, the removal of the modulated component of the light source during recording becomes insufficient. If signal processing is performed by A / D conversion in a state where such noise is superimposed, accurate detection cannot be performed. In order to remove this noise component in digital signal processing at the subsequent stage, an extremely high-speed A / D converter and a digital processing circuit capable of sampling at several times the noise component band are required, which is not practical. .

However, according to this embodiment, the RF signal component and the light source modulation component can be removed even if there is a deviation in the amount of received light by making the amplitude of each signal constant by the AGC circuits 115 and 116. , S / N ratio can be improved. This enables accurate detection. If a wobble signal from which an RF signal component and a light source modulation component are removed is generated by an analog circuit as in this embodiment, and this is A / D converted and the wobble signal processing is performed by digital signal processing, high-speed A / D conversion is achieved. It can be detected with high accuracy even without a vessel. Further, since digital values are transferred, signal deterioration due to the transfer does not occur.

FIG. 21 is a signal waveform diagram for describing a communication method when the transfer of the converted data of the wobble signal is used in common with the above-described transfer line of the signal before servo operation. The wobble frequency requires a higher frequency than the servo error signal band. Therefore, in this embodiment, one wobble signal conversion data ADw is inserted and transferred for each channel of the pre-servo operation signal ADch which is the output data of the A / D converter 3.

Assuming that the number of conversion bits of the A / D converter 3 is m, the sampling period Tws of the wobble signal is T
ws = (n + m) · Tck (Tck is a transfer clock cycle). Further, the sampling period (frame period) Tsmp of each signal before servo calculation is Tsmp = (M +
α) · Tws. Where M is the number of channels to be transferred,
α is the number corresponding to the channel transfer time Tch when the command communication phase is inserted. In FIG. 21, α = 2. In this way, the number of signal lines to be transferred can be reduced.

Next, the above LD control and LD modulation will be described. FIG. 22 is a block diagram showing the internal configuration of the LD driver 12 shown in FIG. 2 together with the LD control unit 9, the LD modulation signal generation unit 10, and other related units. FIG. 23 is a signal waveform diagram for explaining the operation of the LD control unit 9, the LD modulation signal generation unit 10, and the LD driver 12 shown in FIG. An information recording medium assumed in this embodiment is a phase change recording medium (for example, CD-RW), and an LD is emitted with an optical modulation waveform as shown in FIG. f)) is formed. That is, L
D power level is write power Pw, erase power P
e, the bottom power Pb, and a recording mark is formed by a multi-pulse as shown in the figure. At this time, accurate recording is performed by precisely controlling the recording power level and the pulse width and pulse interval of each pulse.

During reproduction, light is emitted with a constant reproduction power Pr. Although not shown, a high-frequency signal may be superimposed to suppress noise due to return light from the information recording medium. As shown in FIG. 22, the LD modulation signal generator 10 converts the recording data signal Wdata from the recording clock signal WCK into the LD modulation signal MOD and the state signal ST as shown in FIGS. 23D and 23C, respectively. Generate In FIGS. 23D and 23C, for simplicity, the delay of the signals MOD and ST with respect to the recording data Wdata is ignored (usually a predetermined clock delay is performed for convenience of the generation circuit). At this time, it is assumed that the pulse width control of the LD modulation signal MOD is optimally performed for a required information recording medium.

The current source 137 outputs a drive current to the light source LD, and the current values Iw and Ie of the respective current sources
(= Ie0 = Ie1) and Ib are set by the current setting unit 131. The switch 132 selects the selection signals St0 and St
1 and one of the current sources is selected according to the LD modulation signal MOD, and a modulation current value Imod is output. The switch 133 selects a modulation current value Imod or a reproduction current value Ir according to a signal R / W indicating recording / reproduction. And
The output current value of the switch 133 and the LD control current value Iapc output from the LD control unit 9 are added to obtain an LD drive current value I.
Generate an LD and drive the LD. This drive current value ILD
The amount of light emitted from the LD is determined by this.

That is, the drive current value ILD = Iapc +
In the case of Iw, the output power P = Pw and the drive current value ILD =
When Iapc + Ie, the output power P = Pe, and when drive current value ILD = Iapc + Ib, the output power P = Pb. The state machine 130 selects the selection signal St according to the LD modulation signal MOD and the state signal ST.
0 and St1 are output.

FIG. 24 is a state transition diagram of the state machine 130 shown in FIG. 22, and the selection signals St0 and St1 are determined according to each of the states S0 to S3. The state transition conditions are as shown in FIG. 24, and FIG. 23 (b) shows the transition state. Table 2 below shows the modulation current values Imod selected by the selection signals St0 and St1 and the modulation signal MOD.
Shows the current value of.

[0128]

[Table 2]

The light receiving section PD2 receives a part of the light emitted from the light source LD and outputs a monitor light receiving current. The monitor light receiving current is supplied to the LD control unit 9 via the current / voltage converter 134, the S / H circuit 135, the input selection unit 1, the adjustment unit 2, and the S / H circuit 136. The S / H circuit 135 samples the monitor light receiving level while the light source LD is irradiating with the predetermined power (for example, if the light waveform signal is an optical waveform signal as shown in FIG. 23E, the sampling may be performed with the erase power Pe. ).

The S / H circuit 136 samples during the period when the input selection unit 1 is selecting the monitor light receiving signal. Other operations are the same as those described above. The LD control unit 9
The LD control current value Iapc is controlled so that the input monitor light receiving signal becomes a predetermined target value. Further, the LD control unit 9 may receive the monitor light receiving signal A / D converted by the A / D converter 3 and perform digital signal control. The timing signal generator 138 generates a timing signal of a circuit that performs sample and hold in synchronization with an optical waveform of the S / H circuit 135 and the like, and receives an optical waveform from the LD modulation signal generator 10 that generates an LD modulation signal. A synchronization signal is provided.

As can be seen from the above, the pulse width of the light modulation waveform of the light source LD is determined only by the modulation signal MOD.
Even if there is a skew between the two signals output from the LD modulation signal generation unit 10, the optical waveform is not affected, and an accurate recording mark can be formed. Therefore, the LD modulation signal generation unit 10 may be formed of an integrated circuit different from the LD driver 12, and a semiconductor process suitable for each desired circuit characteristic can be selected, and an apparatus suitable for cost and performance can be selected. Can be configured. That is, the LD modulation signal generation unit 10 requires high-speed operation and high integration, so a fine CMOS process is suitable.

On the other hand, since a light source LD having an operating voltage of about 1 to several V is connected to the LD driver 12, a high withstand voltage process (for example, 5 V or 3.3 V) is required.
Normally, it is difficult to increase the breakdown voltage in a fine CMOS process (for example, in a 0.18 μm CMOS process, there is only a breakdown voltage of about 1.8 V), but according to this embodiment, each can be configured by a suitable process. become. Further, by providing the LD modulation signal generation unit 10 in an integrated circuit mounted on the optical pickup, the wiring length of the modulation signal to the LD driver 12 can be reduced,
It is possible to prevent the deterioration of the modulation signal, that is, the deterioration of the optical modulation waveform. Furthermore, since it can be provided in the same integrated circuit as a circuit that requires synchronization with an optical waveform, the delay of each timing signal and the number of integrated circuit terminals can be reduced.

Next, a case where the information recording / reproducing apparatus of the above embodiment is applied to different optical modulation waveforms will be described.
Usually, the optimum optical modulation waveform differs depending on the type of information recording medium. However, according to the configuration of each unit shown in FIG.
By changing the set current value of the current source 137 and the means for generating the D modulation signal MOD and the state signal ST, it is possible to drive an optimal optical waveform for each recording medium. For example, in the case of an information recording medium requiring an optical modulation waveform as shown in FIG. 25 (e), the LD modulation signal generation unit 10 generates the waveforms as shown in FIGS. 25 (d) and (c), respectively. A signal may be generated, and each current value of the current source 137 may be set according to Table 3. The current values Ib, Iw, It are L
This is added to the D control current value Iapc, and the light source LD emits light at each of the output powers Pb, Pw, and Pt. Also in this case, the above-described effects can be obtained similarly. In the above description, the case where the irradiation level is three-valued has been described. First, each state managed by the state machine 130 is a combination state of two of the irradiation levels. The selection signals St0 and St1 select the current source 137 according to the current values of these states. And the modulation signal MOD
Performs the modulation between the two values. Further, only one of the state transitions which is not selected by the modulation signal MOD changes. In this way, various light modulation waveforms can be driven by the method of assembling the state machine. Further, if the state transition condition can be changed, optimal light modulation can be performed according to the information recording medium. Further, it can be easily applied to binary level modulation.

[0134]

[Table 3]

Next, an example of the configuration of an integrated circuit in the information recording / reproducing apparatus of the above embodiment will be described. In the above-described embodiment, the integrated circuit 22 is described as a case where the block enclosed by the dashed line shown in FIG. 2 is integrated unless otherwise specified. However, the configuration of the integrated circuit 22 may be modified as follows. May be performed. The A / D converter 3 may be arranged at the subsequent stage, that is, the integrated circuit 22 may include the input selection unit 1 and the adjustment unit 2, and transfer the signal ADin on the FPC board. By doing so, the circuit scale of the integrated circuit 22 mounted on the optical pickup for which miniaturization is desired can be reduced.

Although the transferred signal line is an analog signal, if the gain is adjusted for each light receiving signal as described above, a sufficient signal level of the S / N ratio can be obtained. Is hard to receive. In addition, effects such as reduction of transfer signal lines and improvement of the degree of freedom in arranging optical pickup parts by programming connection input terminals can be obtained.
Further, the servo signal operation processing unit 13 may be provided in the integrated circuit 22. By doing so, the data to be transferred is only the servo error signal after the calculation, and the number of data to be transferred may be smaller than the transfer of each light-receiving signal data before the calculation, and the transfer rate can be reduced. Radiation can be reduced.

Further, the A / D converter 7 is arranged at the subsequent stage,
The (analog) wobble signal WBL may be transferred. Depending on the format of the information recording medium, the wobble frequency may be relatively high (for example, about a fraction of the RF signal band). In such a case, if the digitally converted data is serially transferred, the transfer rate must be high. In order to reduce noise due to unnecessary radiation generated in this case, the wobble signal WBL may be transferred. Also, by adjusting the gain of the wobble signal to a sufficient amplitude level, signal degradation due to noise can be reduced,
The above-described effects can be obtained without increasing the number of signal lines. The functions and effects of using the LD driver 12 as another integrated circuit have been described above.

According to the information recording / reproducing apparatus of this embodiment, as a function according to claim 1 of the present invention, a light receiving signal output switching means for inputting a light receiving signal of an analog signal and switching output to a plurality of types of processing steps. (The above input selector 1
And a digital signal converting means (corresponding to the A / D converter 3) for sequentially converting the light receiving signal output by the light receiving signal output switching means from an analog signal to a digital signal in time series and outputting the signal. And transmission means for transmitting the received light signal output from the digital signal conversion means (corresponding to the first I / F 32 and the second I / F 33).
And a light-receiving signal arithmetic processing means (corresponding to the servo signal arithmetic processing unit 13) for executing arithmetic processing of the above-mentioned plural types of processing steps based on the light-receiving signals transmitted by the transmitting means. Since the signal line transmitted by the board becomes a digital signal and can be placed in the immediate vicinity of each light receiving unit, it is not necessary to transfer the light receiving signal, which is often a minute analog signal, over a long distance, and noise Be less affected. Further, the processing in the servo signal arithmetic processing unit can be performed by digital signal processing, and can be realized with a simple processing and configuration.

As a function according to a second aspect of the present invention, there is provided a light receiving signal output switching means (corresponding to the input selecting section 1) for inputting a light receiving signal of an analog signal and switching the output to a plurality of types of processing steps. Digital signal converting means (corresponding to the A / D converter 3) for sequentially converting the light receiving signal output by the light receiving signal output switching means from an analog signal to a digital signal in time series and outputting the digital signal;
A plurality of first holding means (corresponding to the data holding unit 34) for temporarily storing and holding the light receiving signals converted into digital signals by the digital signal converting means, respectively; A light receiving signal arithmetic processing unit (the servo signal arithmetic processing unit 1) that executes arithmetic processing of the plurality of types of processing steps based on the held light receiving signals.
3) and a plurality of second holding means (servo error signal register R) for temporarily storing and holding the output signal obtained by the arithmetic processing by the light receiving signal arithmetic processing means.
egTmp) and a part of the output signal held by each of the second holding means or the light receiving signal held by each of the first holding means and the output signal held by each of the second holding means. Transmission means (the first I / F 32)
And the second I / F 33), the number of data to be transferred may be reduced by transferring (transmitting) each light-receiving signal data before the calculation. In that case, the transfer rate can be reduced. . As a result, unnecessary radiation can be reduced.

Further, as a function according to a third aspect of the present invention, an analog signal processing means (an input to the high-speed analog signal processing unit 5) for inputting a light receiving signal of an analog signal, performing analog signal processing in an RF signal band, and outputting the processed signal. Equivalent to)
Light-receiving signal output switching means (corresponding to the input selection unit 1) for inputting a light-receiving signal of the analog signal and a light-receiving signal output from the analog signal processing means and switching output to a plurality of types of processing steps; Digital signal converting means (corresponding to the A / D converter 3) for sequentially converting a light receiving signal output from the light receiving signal output switching means from an analog signal to a digital signal in time series and outputting the signal;
Transmission means for transmitting the light receiving signal output from the digital signal conversion means (the first I / F 32 and the second I / F 3
3) and light-receiving signal calculation processing means (corresponding to the servo signal calculation processing unit 13) for executing calculation processing of the plurality of types of processing steps based on the light-receiving signals transmitted by the transmission means. Therefore, a high-speed analog signal processing circuit is used for a portion requiring signal processing in the RF band, so that a signal can be generated with high accuracy. When the required band becomes narrow, A / D conversion is performed and digital transfer is performed. Therefore, signal deterioration due to noise at the time of transfer can be prevented without using a high-speed A / D converter. Also,
The signals can be processed by the same circuit as other signals before servo error generation, and the transfer signal lines can be shared, so that the circuit scale and the transfer signal lines can be reduced.

As a function according to a fourth aspect of the present invention, the transmission means is means for transmitting a signal by time division multiplexing, and transmits the light receiving signal and the control command signal converted by the digital signal conversion means. Since both are performed, the number of signal lines to be transmitted can be reduced.

Further, as a function according to a fifth aspect of the present invention, the transmission means only transmits a control command signal when the light receiving signal is not input or when processing is unnecessary even if it is input. Therefore, during the time when information is not reproduced / recorded, such as during startup or standby,
Since only the communication of the control command signal is performed without transferring the light receiving signal output from the digital signal conversion means, the initialization of the command register which requires a large amount of command communication can be quickly performed.

According to a sixth aspect of the present invention, at least one of offset adjustment and gain adjustment is performed on the light receiving signal output from the light receiving signal output switching means, and the light receiving signal is output to the digital signal converting means. An adjusting means for supplying (corresponding to the adjusting unit 2), and a gain adjustment value calculated based on a light receiving signal output from the digital signal converting means or an output signal obtained by an arithmetic processing by the light receiving signal arithmetic processing means. Since the gain calculating means (function provided inside the control unit 11) for resetting the gain adjustment value to the adjusting means is provided, the gain / offset adjustment can be performed individually for each light receiving signal by the same circuit. Thus, even if there is a difference between the levels of the light receiving signals output from the respective light receiving units, the respective signals can be accurately A / D converted.

Further, as a function according to a seventh aspect of the present invention, at least one of an offset adjustment and a gain adjustment is performed on the light reception signal output from the light reception signal output switching means, and the light reception signal is transmitted to the digital signal conversion means. Adjusting means for supplying (corresponding to the adjusting unit 2) and adding means for sequentially adding and outputting a predetermined number of light receiving signals among the light receiving signals output in time series from the digital signal converting means (the adding unit) 81), a gain adjustment value is calculated so that the output signal output from the addition means substantially matches a predetermined target value set in advance, and the gain adjustment value is reset to the adjustment means. Since the calculating means (corresponding to the gain calculating section 83) is provided, it is possible to automatically control the sum signal (that is, each light receiving signal) to be substantially a predetermined value. , Even if the received light amount is varied reflectance of the emitted light amount and information recording medium of the light source is changed in a stable A / D conversion performed accurately, so that can be performed as a result stable servo operation.

Further, as a function according to an eighth aspect of the present invention, a predetermined gain storage means (corresponding to the gain register 85) for storing a predetermined gain adjustment value calculated in advance for the adjustment means; Means and a gain adjustment value selection means (corresponding to the gain selection unit 84) for switching and selecting a gain adjustment value to be reset to the adjustment means from the gain calculation means. Similar effects can be obtained as needed.

Further, as a function according to claim 9 of the present invention, the gain calculating means (the gain calculating section 83)
A gain adjustment value reading means (an internal function of the control unit 11) for reading the current value of the gain adjustment value calculated by the above is provided, so that the light receiving signal level before the gain adjustment can be calculated.

As a function according to a tenth aspect of the present invention, data conversion for increasing the number of bits in accordance with an offset adjustment value and a gain adjustment value of the adjusting means is applied to the light receiving signal output from the digital signal converting means. If data conversion means (corresponding to a data conversion unit not shown) is provided to supply the data to the light reception signal arithmetic processing means, a higher precision can be achieved without increasing the number of bits when converting to a digital signal. Calculations can be performed.

Further, as a function according to claim 11 of the present invention, if the transmission means is a means for performing serial transmission (see the configuration shown in FIG. 8 and the description of the processing), the received light signal is transmitted serially. And the number of signal lines to be transferred can be greatly reduced.

[0149]

As described above, according to the light receiving signal processing apparatus of the present invention, it is not necessary to change the circuit even if the configuration of the portion for outputting the light receiving signal is changed. In order to make compatible with the received light signal, the required specifications of the portion including the plurality of light sources and the light receiving section are relaxed to reduce the cost, and the signal deterioration due to the noise in the signal supply by the FPC board is reduced, and the signal line to be transferred is provided. The number can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration of an information recording / reproducing device to which a light receiving signal processing device of the present invention is applied.

FIG. 2 is a block diagram showing an internal configuration of a normal signal processing unit as a premise of the present invention.

FIG. 3 is a block diagram showing a detailed configuration of a main part according to the present invention.

FIG. 4 is a signal waveform diagram for explaining the operation of the main part according to the present invention shown in FIG. 3;

FIG. 5 is a block diagram showing a configuration of each light receiving unit shown in FIG.

FIG. 6 is a block diagram showing a configuration of a programmable selection signal generator provided in the controller shown in FIG. 3;

FIG. 7 is a block diagram illustrating a configuration of a gain control unit that automatically performs gain control of a gain adjustment unit according to the amount of received light in the information recording / reproducing apparatus of the embodiment.

8 is a block diagram showing a configuration of a main part relating to data communication in the main part shown in FIG. 3;

9 is a signal waveform diagram for describing a data communication method by a main part related to the data communication shown in FIG. 8;

FIG. 10 is a block diagram showing a configuration of another embodiment of a light receiving signal input unit including the light receiving unit and the light receiving signal converting unit.

FIG. 11 is a block diagram illustrating another example of the configuration of the input selection unit illustrated in FIG. 10;

FIG. 12 is a block diagram illustrating still another example of the configuration of the input selection unit illustrated in FIG. 10;

FIG. 13 is a block diagram showing still another configuration example of the input selection unit shown in FIG. 10;

FIG. 14 is a waveform chart for explaining application of a predetermined offset to the offset adjustment unit according to the embodiment.

FIG. 15 is a block diagram illustrating a configuration of another embodiment of the input selection unit and the adjustment unit.

FIG. 16 is a block diagram showing a configuration example of another embodiment of a main part according to the present invention.

FIG. 17 is a block diagram showing a configuration example of another embodiment of a main part according to the present invention.

FIG. 18 is a block diagram showing an internal configuration of the servo signal calculation processing unit.

FIG. 19 is a waveform chart used for describing the operation of the servo signal calculation processing unit shown in FIG.

20 is a block diagram showing an internal configuration of the wobble signal generation unit shown in FIG. 2 together with other related units.

FIG. 21 is a signal waveform diagram for explaining a communication method in a case where transfer of converted data of a wobble signal is used in common with a transfer line of a signal before servo calculation in this embodiment.

FIG. 22 shows an internal configuration of the LD driver shown in FIG.
It is a block diagram shown with a control part, an LD modulation signal generation part, and other related parts.

FIG. 23 is a signal waveform diagram for explaining operations by the LD control unit, the LD modulation signal generation unit, and the LD driver shown in FIG. 22;

FIG. 24 is a state transition diagram of the state machine shown in FIG. 22.

FIG. 25 is a signal waveform diagram for describing a case where this embodiment is applied to different optical modulation waveforms.

[Explanation of symbols]

1: Input selector 2: Adjuster 3, 7, 118: A / D converter 4: RF selector 5: High-speed analog signal processor 6: Wobble signal generator 8: RF signal preprocessor 9: LD controller 10: LD modulation signal generation unit 11, 43: control unit 12: LD driver 13: servo signal calculation processing unit 14: servo processor 15, 122: wobble signal processing unit 16: RF signal post-processing unit / PLL circuit 17: WCK generation Unit 18: Rotation control unit 19, 106: Controller 20: Servo driver 21, 21 ': Light receiving signal conversion unit 22: Integrated circuit 30: Offset adjustment unit 31: Gain adjustment unit 32: First I / F 33: Second I / F 34: Data holding unit 35: Quadrant light receiving element 36: Light receiving spot 37a-37d: Current-voltage converter 38: M-ary counter 39: Conversion table 40: Switch 41: parallel / serial converter (P / S converter) 42: shift register (SR) 45: signal operation unit 46, 47: operation circuit 48: low-pass filter (LPF) 49, 76, 136: sample hold (S / H) circuit 50: current-voltage converter 51: voltage buffer 52, 56: selector 53: polarity selector 54: non-inverting amplifier 55: inverting amplifier 60, 64, 66, 88, 91: adder 61: operation Previous offset register group 62, 68, 87: multiplier 63: operation coefficient register group 65: register RegTmp 70: servo error signal register RegSV 71: DPD signal generator 72, 111, 112: addition amplifier 73: variable gain amplifier 74: Peak hold (P / H) circuit 75: Bottom hold (B / H) circuit 80: Gain control unit 81, 120: adder 82, 121: averaging unit 83: gain calculator 84: gain selector 85: gain register 86: gain controller 89: delay register 90: comparator 92: holding unit 100: information recording medium 101 : Optical pickup 102, LD1, LD2: light source 103, PD1 to PDn: light receiving unit 104: signal processing unit 105: rotation driving unit 107: driving direction of the optical pickup 110: wobble signal generation unit 113, 114: DC component removal unit 115 , 116: AGC circuit 117: subtraction amplifier 119: DC component extraction unit 130: state machine 131: current setting unit 132, 133, 140, 141, SW1 to SW (2
N): Switch 134: Current-voltage converter 137: Current source 138: Timing signal generator 142: Operational amplifier 143: D / A converter 144-146: Variable resistor

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5D090 AA01 BB02 BB03 BB04 CC04 CC16 DD03 EE12 EE18 FF02 FF05 LL05 5D118 AA14 AA26 AA29 BA01 BB01 BB02 BC08 CA02 CA08 CB01 CC06 CD01 CD07 CD08 CD11

Claims (11)

[Claims] 1. A light receiving signal output switching means for inputting a light receiving signal of an analog signal and switching the output to a plurality of types of processing steps, and sequentially receiving a light receiving signal output by the light receiving signal output switching means in an analog signal in a time series. Digital signal converting means for converting the digital signal into a digital signal and outputting the digital signal; transmitting means for transmitting the received light signal output from the digital signal converting means; and the plurality of types of processing based on the received light signal transmitted by the transmitting means. A light receiving signal processing device for performing a calculating process in the process. 2. A light-receiving signal output switching means for inputting a light-receiving signal of an analog signal and switching the output to a plurality of types of processing steps, and sequentially converting the light-receiving signal output by the light-receiving signal output switching means into an analog signal in time series. Digital signal converting means for converting the digital signal into a digital signal and outputting the digital signal; a plurality of first holding means for temporarily storing and holding light receiving signals converted into digital signals by the digital signal converting means; Light receiving signal arithmetic processing means for executing arithmetic processing of the plurality of types of processing steps based on each light receiving signal held in one holding means; and temporarily outputting an output signal obtained by the arithmetic processing by the light receiving signal arithmetic processing means. A plurality of second holding means for temporarily storing and holding, and an output signal held by each of the second holding means or a light receiving signal held by each of the first holding means And a light-receiving signal processing apparatus characterized by comprising a transmitting means for transmitting said portion of the signal out of the second output signals held in the holding means. 3. An analog light receiving signal is input and RF
Analog signal processing means for performing and outputting analog signal processing of a signal band; light receiving for inputting a light receiving signal of the analog signal and a light receiving signal output from the analog signal processing means to switch output to a plurality of types of processing steps Signal output switching means, digital signal conversion means for sequentially converting a light reception signal output from the light reception signal output switching means from an analog signal to a digital signal in a time series and outputting the same, and light reception output from the digital signal conversion means A light receiving signal processing device comprising: a transmitting means for transmitting a signal; and a light receiving signal arithmetic processing means for executing arithmetic processing of the plurality of types of processing steps based on the light receiving signal transmitted by the transmitting means. . 4. The light receiving signal processing device according to claim 1, wherein said transmission means is means for transmitting a signal by time division multiplexing, and wherein said light receiving signal and said control command signal are converted by said digital signal converting means. A light-receiving signal processing device, wherein transmission is performed together. 5. The light-receiving signal processing device according to claim 4, wherein the control unit transmits only a control command signal when the light-receiving signal is not input or when processing is unnecessary even if the light-receiving signal is input. A light reception signal processing device characterized by the above-mentioned. 6. The digital signal conversion apparatus according to claim 1, wherein at least one of an offset adjustment and a gain adjustment is performed on the light receiving signal output from the light receiving signal output switching means. Adjusting means for supplying to the means, a gain adjustment value based on a light reception signal output from the digital signal conversion means or an output signal obtained by arithmetic processing by the light reception signal arithmetic processing means, and calculating the gain adjustment value A light receiving signal processing device, wherein the adjusting means is provided with a gain calculating means for resetting. 7. The digital signal conversion device according to claim 1, wherein at least one of an offset adjustment and a gain adjustment is performed on a light receiving signal output from the light receiving signal output switching means. Adjusting means for supplying to the means, adding means for sequentially adding and outputting a predetermined number of light receiving signals among the light receiving signals output in time series from the digital signal converting means, and an output signal output from the adding means Calculate the gain adjustment value so that almost matches the predetermined target value set in advance,
A light-receiving signal processing device comprising: a gain calculating means for resetting the gain adjustment value to the adjusting means. 8. The light receiving signal processing device according to claim 7, wherein a predetermined gain storage unit stores a predetermined gain adjustment value calculated in advance for the adjustment unit, and the predetermined gain storage unit and the gain calculation unit perform the adjustment. And a gain adjustment value selecting means for switching and selecting a gain adjustment value to be reset. 9. The light reception signal processing device according to claim 7, further comprising gain adjustment value reading means for reading a current value of the gain adjustment value calculated by said gain calculation means. apparatus. 10. The light receiving signal processing device according to claim 6, wherein the light receiving signal output from the digital signal converting means is subjected to data conversion for increasing the number of bits according to an offset adjustment value and a gain adjustment value of the adjusting means. A light-receiving signal processing device provided with data conversion means for supplying the data to the light-receiving signal arithmetic processing means. 11. The light-receiving signal processing device according to claim 1, wherein the transmission unit is a unit that performs serial transmission.