JP2002190549A - Multilayer wiring board and manufacturing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multilayer wiring board having outer connection terminals of high connection reliability. SOLUTION: The multilayer wiring board 113b has the outer connection terminals 120a and 220c in the outermost layer. The outer connection terminals are constituted of a columnar metallic core 118c obtained by etching a metallic layer having uniform thickness. The connecting part of the metallic core and a wiring pattern on the outermost layer is formed by connection through electrolytic plating or electroless plating.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multilayer wiring board and a method for manufacturing a multilayer wiring board. More particularly, the present invention relates to a multilayer wiring board on which a semiconductor chip is mounted, and more particularly to a method for manufacturing a multilayer wiring board having external connection terminals with high connection reliability and a multilayer wiring board manufactured by the manufacturing method.

[0002]

2. Description of the Related Art In recent years, with the demand for higher functionality and lighter, thinner and smaller electronic devices, high-density integration and high-density mounting of electronic components have been progressing. Semiconductor packages have been increasingly miniaturized and have more pins than ever before.

[0003] A conventional circuit board is called a printed wiring board, and after patterning copper foil adhered to a glass epoxy board made of a laminated board made of glass fiber woven fabric impregnated with epoxy resin, a plurality of sheets are stacked. The mainstream was to use a wiring board in which a through-hole was formed by bonding and drilling, a via was formed by performing copper plating on the wall surface of the hole, and a via was formed to perform electrical connection between layers. However, the mounting components have been reduced in size and density, and the wiring density of the above-described wiring boards has become insufficient, and problems have arisen in mounting components.

[0004] Against this background, recently, build-up multilayer wiring boards have been adopted. The build-up multilayer wiring board is formed while stacking an insulating layer made of only a resin and a conductor. As a via forming method, a high density is achieved by freely arranging small diameter via holes in various ways such as a laser method, a plasma method and a photo method instead of the conventional drilling. Examples of the interlayer connection portion include a blind via (Blind Via) and a buried via (Buried Via: a structure in which a via is filled with a conductor). A buried via hole capable of forming a stacked via on the via is particularly attracting attention. ing. The buried via hole is classified into a method of filling the via hole with plating and a method of filling the via hole with a conductive paste or the like. On the other hand, as a method of forming a wiring pattern, there are a method of etching a copper foil (subtractive method), a method of electrolytic copper plating (additive method), and the like. Is starting to be.

When a semiconductor package using such a multilayer wiring board is mounted on a printed circuit board (motherboard), it has become very common to use solder bumps. The connection by the solder bump is performed by QFP (Quad F
However, there are still many problems from the viewpoint of bonding reliability because the bonding area is smaller than that of the method of connecting the metal leads by soldering as in the case of the “lat package” and there is no stress relaxation by the metal leads.

On the other hand, as a method of mounting a semiconductor chip on a substrate, a wire bonding method, a TAB method, a flip chip method, and the like are known. Recently, flip chip connection, which is advantageous for miniaturization of a semiconductor package, is known. The method is receiving attention. In this flip chip connection method, it is necessary to form solder bumps on electrodes of a semiconductor chip in advance. As a method of forming solder bumps, a vacuum evaporation method, a printing method, a solder ball alignment method, a stud bump method, an electrolytic plating method, and the like are known.
There are problems such as manufacturing time, manufacturing cost, and variations in the height of solder bumps.

[0007] Solder bumps include lead-free materials such as Sn-37Pb (eutectic solder) generally used and Sn-36Pb-2Ag and Sn-3.5Ag obtained by adding a small amount of silver to eutectic. Solder and various types are used. On the other hand, a type in which a copper core is coated with solder, such as a copper core solder bump, is also being studied.

The Journal of Japan Institute of Electronics Packaging, vol.
2, No. 4 (1999), P298-302,
"The joint strength decreases with or without the presence of a Cu core when left at high temperatures, but the Cu-core solder balls are better than Sn-37P.
It was found that the solder balls were less susceptible to high temperature deterioration than the b solder ball and the Sn-36Pb-2Ag solder ball. ”,“ C
In the case of a u-core solder ball, the Au—Cu—Sn layer formed on the Ni plating layer during reflow is N
To act as a barrier layer that suppresses the reaction of i-Sn,
Even when left at a high temperature, a Pb segregation layer that causes high-temperature deterioration is not formed at the joint. It is described. The use of copper core solder balls can improve the bonding reliability, but the copper core solder balls are not used as much as the Sn-37Pb solder balls, which can lead to a significant cost increase. You can easily imagine.

As described above, the copper core solder bump can be expected to have high connection reliability, but it is expensive and Sn-37P.
Solder bumps without a copper core, such as solder bumps, are low in cost but have a problem in connection reliability.

[0010]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of solder bumps in a multilayer wiring board on which a semiconductor chip is mounted. It is intended to provide a manufacturing method.

[0011]

That is, the present invention provides the following multilayer wiring board and its manufacturing method. (1) A multilayer wiring board having an external connection terminal in an outermost layer, wherein the external connection terminal has a substantially uniform height obtained by etching a metal layer having a substantially uniform thickness. A connection portion between the metal core and the outermost wiring pattern is a connection by electrolytic plating or electroless plating. (2) The multilayer wiring board according to the above (1), wherein at least a part of the surface of the metal core is covered with a solder coating. (3) A method for manufacturing a multilayer wiring board including a step of forming a wiring pattern by electrolytic plating using a metal layer as a lead for electrolytic plating and a step of removing the metal layer by etching, wherein the outermost layer of the multilayer wiring board is provided. By partially etching and removing the metal layer used in forming the
A method for manufacturing a multilayer wiring board, comprising a step of forming an external connection terminal having a metal core on an outermost layer of the multilayer wiring board. (4) A step of forming a wiring pattern by electrolytic plating using the metal layer as a lead for electrolytic plating, a step of forming an insulating layer on the wiring pattern, and forming a via in the insulating layer so that a part of the wiring pattern is exposed. Forming a conductive post by electrolytic plating using the metal layer as a lead for electrolytic plating, and forming a metallic material layer for bonding on at least one of the surface of the conductive post or the surface of the portion to be bonded of the connected layer. A step of forming an adhesive layer on at least one of the surface of the insulating layer and the surface of the layer to be connected, and bonding the conductor post and the part to be bonded with the bonding metal material layer via the adhesive layer, A method of manufacturing a multilayer wiring board including a step of bonding a layer and a layer to be connected with an adhesive layer, and a step of removing a metal layer by etching, when forming an outermost layer of the multilayer wiring board. Forming a terminal for external connection having a metal core on the outermost layer of the multilayer wiring board by partially etching and removing a metal layer to be used. Method. (5) The method for manufacturing a multilayer wiring board according to the above (3) or (4), wherein a solder coating is formed on a surface of the metal core. (6) A multilayer wiring board obtained by the method for manufacturing a multilayer wiring board according to any one of the above items (3) to (5).

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings, but the present invention is not limited thereto.

FIGS. 1A to 4R are views for explaining an example of a method for manufacturing a multilayer wiring board according to a first embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view showing an example of the structure of a multilayer wiring board obtained by the method described above.

In the method for manufacturing a multilayer wiring board of the present invention, first, a patterned plating resist 102 is formed on a metal layer 101a (FIG. 1A). The plating resist 102 can be formed by, for example, laminating an ultraviolet-sensitive dry film resist on the metal layer 101a, selectively exposing the resist using a negative film or the like, and then developing. The material of the metal layer 101a may be any material as long as it is suitable for the manufacturing method of the present invention. In particular, the material has resistance to a used chemical solution and can be finally removed by etching. It is necessary to be. Examples of the material of the metal layer 101a include copper, a copper alloy, a 42 alloy, and nickel.

Next, a resist metal layer 103 is formed by electrolytic plating using the metal layer 101a as a lead for electrolytic plating (FIG. 1B). By this electrolytic plating, a resist metal layer 103 is formed on a portion of the metal layer 101a where the plating resist 102 is not formed. The material of the resist metal layer 103 may be any material as long as it is suitable for this manufacturing method. In particular, the resist metal layer 103 must have resistance to a chemical used when the metal layer 101a is finally removed by etching. is necessary. As a material of the resist metal layer 103, for example, nickel, gold, tin,
Silver, solder, palladium and the like can be mentioned. A preferred configuration of the resist metal layer is one or more layers composed of respective materials of gold, silver, palladium and nickel, a two-layer configuration of gold and nickel, or a layer configuration including solder.
The purpose of forming the resist metal layer 103 is to prevent the wiring pattern 104 shown in FIG. 1C from being eroded and corroded by a chemical used when etching the metal layer 101a. Therefore, when the wiring pattern 104 shown in FIG. 1C has resistance to the chemical used for etching the metal layer 101a, the resist metal layer 103 is unnecessary. The resist metal layer 103 does not need to be the same pattern as the wiring pattern 104, and the plating resist 1 is formed on the metal layer 101a.
Before the formation of the resist layer 02, the resist metal layer 103 may be formed on the entire surface of the metal layer 101a.

Next, a wiring pattern 104 is formed by electrolytic plating using the metal layer 101a as a lead for electrolytic plating (FIG. 1C). By this electrolytic plating, the metal layer 1
A wiring pattern 104 is formed on the portion of the substrate 01a where the plating resist 102 is not formed. The material of the wiring pattern 104 may be any material as long as it is suitable for this manufacturing method. In particular, the material has resistance to a chemical used when the resist metal layer 103 is finally removed by etching. It is necessary. Actually, it is advisable to select a material for the resist metal layer 103 that can be etched with a chemical solution that does not corrode or corrode the wiring pattern 104. Examples of the material of the wiring pattern 104 include copper, nickel, gold, tin, silver, and palladium. Further, by using copper, a stable wiring pattern 104 with low electric resistance can be obtained.

Next, the plating resist 102 is removed (FIG. 1D), and the insulating layer 1 is formed on the formed wiring pattern 104.
05 is formed (FIG. 1E). As the resin constituting the insulating layer 105, any resin suitable for the manufacturing method of the present invention can be used. The method for forming the insulating layer 105 may be a method suitable for the resin to be used. The resin varnish may be directly applied by printing, curtain coating, bar coating, or the like, or a dry film type resin may be vacuum laminated or vacuum pressed. And the like.
In particular, commercially available copper foil with resin is easy to obtain,
If the wiring pattern 104 is formed by embedding the unevenness of the wiring pattern 104 by vacuum lamination, and the copper foil is finally etched, the surface of the insulating layer 105 becomes very flat without being affected by the unevenness of the wiring pattern 104. Further, the insulating layer 105
Since the finely roughened shape of the copper foil surface is transferred to the surface of, the adhesion to the adhesive layer 109 shown in FIG. 2 (i) can be ensured.

Next, a via 106 is formed in the formed insulating layer 105.
Is formed (FIG. 1F). The method for forming the via 106 is as follows.
Any method may be used as long as it is suitable for the manufacturing method of the present invention, and examples thereof include dry etching by laser and plasma, and chemical etching. When the insulating layer 105 is made of a photosensitive resin, the via 106 can be formed by selectively exposing and developing the insulating layer 105.

Next, the conductor post 107 is formed by electrolytic plating using the metal layer 101a as a lead for electrolytic plating (FIG. 2 (g)). By this electrolytic plating, the insulating layer 10
5 is formed in the portion where the via 106 is formed.
07 is formed. Conductive post 107 by electrolytic plating
Is formed, the shape of the tip of the conductor post 107 can be freely controlled. The material of the conductor post 107 may be any material as long as it is suitable for the manufacturing method of the present invention, and examples thereof include copper, nickel, gold, tin, silver, and palladium. Furthermore, by using copper, the conductor post 107 which is stable with low electric resistance can be obtained.

Next, the surface (tip) of the conductor post 107
Next, a bonding metal material layer 108 is formed (FIG. 2).
(H)). As a method of forming the bonding metal material layer 108, a method of forming by electroless plating, the metal layer 101a
As a lead for electrolytic plating, and a method of printing a paste containing a bonding metal material. In the printing method, the printing mask needs to be accurately positioned with respect to the conductor post 107. However, in the method of electroless plating or electrolytic plating, the bonding metal material layer 108 is formed on the surface other than the surface of the conductor post 107. Therefore, it is easy to cope with miniaturization and high density of the conductor posts 107. In particular, the method using electroplating is very suitable because the metal that can be plated is more diverse and the management of the chemical solution is easier than the method using electroless plating. The material of the joining metal material layer 108 may be any metal as long as it can be metal-joined to the portion 112 to be joined shown in FIG. 2 (j), for example, solder. Among the solders, Sn and In, or Sn, Ag, Cu, Zn, Bi, Sb, Pb, I
It is preferable to use solder composed of at least two kinds of n and Au. More preferably, it is an environment-friendly Pb-free solder. In addition, in FIG.
Although the example in which the joining metal material layer 108 is formed on the surface of the substrate is shown, the purpose of forming the joining metal material layer 108 is to join the conductor post 107 and the portion 112 to be joined. A bonding metal material layer 108 may be formed on 112. Of course, it may be formed on both surfaces of the conductor post 107 and the joint 112.

Next, an adhesive layer 1 is formed on the surface of the insulating layer 105.
09 (FIG. 2 (i)). The adhesive layer 109 may be formed by a method suitable for the adhesive resin to be used. A resin varnish may be directly applied by printing, curtain coating, bar coating, or the like, or a dry film type resin may be vacuum-laminated, A method of laminating by a method such as a vacuum press may be used. Although FIG. 2I shows an example in which the adhesive layer 109 is formed on the surface of the insulating layer 105, the connection layer 11
The adhesive layer 109 may be formed on the surface of the first substrate. Of course, it may be formed on both surfaces of the insulating layer 105 and the connected layer 111.

Next, the connection layer 1 obtained by the above-described steps
10 and the connected layer 111 (see FIG. 2).
(J)). For the alignment, a method of aligning the positioning marks formed on the connection layer 110 and the connected layer 111 in advance by reading with an image recognition device, a method of aligning with a positioning pin, or the like can be used. FIG. 2 (j) shows an example in which a core substrate 116 such as FR-4 used for imparting rigidity to the multilayer wiring board 113a shown in FIG. 4 (r) is used as the connected layer 111. Is a metal layer 10 as shown in FIG.
One in which the wiring pattern 104 is simply formed on 1a can also be used.

Next, the connecting layer 110 and the connected layer 111
Are laminated (FIG. 2 (k)). As a lamination method, for example, using a vacuum press, the conductor post 107 is pressed through the adhesive layer 109 until it is metal-bonded to the portion 112 to be bonded by the bonding metal material layer 108, and further heated to be bonded. The agent layer 109 is cured so that the connection layer 110 and the
11 can be bonded.

Next, the metal layer 101a is removed by etching (FIG. 3 (l)). A resist metal layer 103 is formed between the metal layer 101a and the wiring pattern 104, and the resist metal layer 103 has resistance to a chemical used when the metal layer 101a is removed by etching. Therefore, even if the metal layer 101a is etched, the resist metal layer 103 is not eroded or corroded,
As a result, the wiring pattern 104 is not eroded or corroded. The material of the metal layer 101a is copper, the resist metal layer 10
When the material of No. 3 is nickel, tin or solder, a commercially available ammonia-based etchant can be used. When the material of the metal layer 101a is copper and the material of the resist metal layer 103 is gold or silver, a ferric chloride solution and a cupric chloride solution are included.
Most etchants can be used.

Next, the resist metal layer 103 is removed by etching (FIG. 3 (m)). Wiring pattern 104
Is resistant to the chemical used when the resist metal layer 103 is removed by etching, so that the wiring pattern 104 is not eroded or corroded. for that reason,
By removing the resist metal layer 103, the wiring pattern 104 is exposed. When the material of the wiring pattern 104 is copper and the material of the resist metal layer 103 is nickel, tin, or solder, a commercially available solder / nickel release agent (for example, Petax, manufactured by Mitsubishi Gas Chemical Co., Ltd.) can be used. The material of the wiring pattern 104 is copper, the resist metal layer 1
When the material of 03 is gold, it is difficult to etch the resist metal layer 103 without eroding or corroding the wiring pattern 104. In this case, the step of etching the resist metal layer 103 may be omitted, and the resist metal layer 103 may be left.

Subsequently, the above-described process, that is, FIG.
3 (m) are repeated. That is, FIG.
As shown in FIG. 2 (j), a multilayer wiring board 113 (113a, 113b) being manufactured is used as a layer to be connected, and a connection step is formed on both sides of a core substrate 116 by performing a lamination step shown in FIG. The connection layer is formed on both surfaces of the core substrate 116 by repeatedly performing the lamination steps shown in FIGS. 2J to 3M using the obtained material as a connection target layer. (FIG. 3 (n)).

FIGS. 3 (o) to 4 (p) show the multilayer wiring board 1.
FIG. 13 is a diagram for explaining a step of forming an external connection terminal 120a on the outermost layer 117b on the side opposite to the semiconductor chip 202a mounting surface 13a. That is, the multilayer wiring board 113
a of the metal layer 10 used to form the outermost layer 117b of FIG.
The metal core 118a of the external connection terminal 120a is formed by partially etching 1c.
(O)). Subsequently, a solder coating 119a is formed so as to cover the formed metal core 118a (FIG. 4 (p)). The method for forming the solder coating 119a includes a method for forming by electroless plating, a method for forming by electrolytic plating, and a method for printing a solder paste. In the case of electrolytic plating, the metal layer 101 used to form the outermost layer 117a on the mounting surface of the semiconductor chip 202a of the multilayer wiring board 113a is used.
b is used as a lead for electrolytic plating and solder plating is performed.
The solder coating 119a can be formed.

When the material of the metal layer 101c is copper or a copper alloy containing copper as a main component, the external connection terminal 120a has a structure in which a solder coating 119a is formed on a copper core (metal core 118a). Therefore, the external connection terminal 120
An improvement in connection reliability can be expected as compared with the case where a is formed only with solder. Further, since the metal layer 101c used for manufacturing the multilayer wiring board 113a is etched to form the metal core 118a and the solder film 119a is applied, the same effect can be obtained without using an expensive copper core solder ball or the like. Can be obtained, and significant cost reduction can be expected. When a solder paste or the like is formed on a wiring board (mother board: not shown) on which the semiconductor device 201a shown in FIG. 7 is mounted, the solder coating 119a is not necessarily required.

Next, the metal layer 101b is removed by etching (FIG. 4 (q)).
Is formed to obtain the multilayer wiring board 113a of the present invention (FIG. 4 (r)). FIG. 4 (r) shows the core substrate 116.
Multi-layer wiring board 113 in which two connection layers are laminated on both sides of
1A shows an example, and a solder resist 115 is formed on a surface of the multilayer wiring board 113a on which the semiconductor chip 202a is mounted. The solder resist 115 is applied to the pad 11
4 is open.

By the above steps, the external connection terminals 120
a is a metal core 118a and a solder coating 119 covering the metal core 118a
a can be manufactured.

Next, a method for manufacturing a multilayer wiring board according to a second embodiment of the present invention will be described in detail with reference to FIG. FIGS. 5 (o ′) to (q ′) show the second embodiment of the present invention.
FIG. 4 is a cross-sectional view for explaining the method for manufacturing the multilayer wiring board of FIG. 3, and is for explaining a step performed instead of FIGS. 3 (o) to 4 (q). Therefore, here, portions different from those of the first method for manufacturing a multilayer wiring board will be particularly described in detail, and description of the same portions will be basically omitted.

In FIG. 5 (o '), a solder coating 119b is formed on the surface of the metal layer 101c. Solder coating 119b
May be formed by electroless plating, electrolytic plating, or printing a solder paste. In the case of electrolytic plating, the metal layer 101
The solder plating 119b can be formed by performing solder plating using b or 101c as a lead for electrolytic plating. When the solder coating 119b is formed by electrolytic plating or electroless plating, a plating resist (not shown) is formed so that the solder coating 119b is formed only on a necessary portion, and the plating resist is removed after plating. Of course, it needs to be removed.

Next, referring to FIG.
The metal core 101b is formed by etching the metal layer 101c using 19b as an etching mask. When the material of the metal layer 101c is copper, a commercially available ammonia-based etchant can be used. Further, the metal layer 101b is also etched.

Next, referring to FIG.
19b is reflowed to form an external connection terminal 119b composed of a metal core 118b and a solder coating 119b.
At this time, a flux may be applied to the solder coating 119b and then reflowed to clean the flux. Note that reflow at this point is not essential, and the semiconductor device 201a shown in FIG. 7 is connected to a wiring board (mother board: not shown).
Since there is a reflow process when mounting on a device, it is also possible to use that.

Next, a method for manufacturing a multilayer wiring board according to a third embodiment of the present invention will be described in detail with reference to FIG. FIG. 6 is a sectional view showing a third multilayer wiring board of the present invention. Here, portions different from those of the first method for manufacturing a multilayer wiring board will be particularly described in detail, and description of the same portions will be basically omitted.

In FIG. 6, the metal layer (for example, metal layer 101b in FIG. 4 (p)) used for forming the outermost layer on the side on which the semiconductor chip 202b is mounted is etched to form the metal core 118c. And solder coating 11
9c is formed. As a result, a multilayer wiring board 113b having external connection terminals 120c necessary for mounting the semiconductor chip can be obtained. Note that the method of forming the external connection terminal 120c is basically the same as the method of forming the external connection terminal 120a in the first embodiment, and a description thereof will not be repeated. Further, the method for forming the external connection terminal 120b in the second embodiment can be applied.

The multilayer wiring board 11 obtained by the above steps
The semiconductor chips 202a and 202 are attached to 3a and 113b.
By mounting 2b, semiconductor devices 201a and 201b can be obtained (FIGS. 7A and 7B).

The external connection terminals 120a, 120
It is apparent from the above description and drawings that the positions and arrangements forming b and 120c are mainly as follows. (1) The external connection terminals 120a and 120b are mainly located and arranged in substantially the same position and arrangement as connection lands formed on a wiring board (mother board: not shown) on which the semiconductor devices 201a and 201b are mounted. (2) The external connection terminals 120c are mainly located in the same position and arrangement as the electrodes of the semiconductor chips 202a and 202b. In addition, since the semiconductor chips 202a and 202b are often mounted at the central portions of the multilayer wiring boards 113a and 113b, the external connection terminals 120c are formed so as to have a position and an arrangement corresponding thereto.

The greatest features of the multilayer wiring board according to the present invention are the following two points. (1) A metal layer is etched to form a metal core, and a solder coating is applied to form a columnar external connection terminal having a substantially uniform height. (2) Without using expensive copper core solder balls, etc.
It is possible to form an equivalent external connection terminal,
As a result, significant cost reduction can be expected, and further improvement in connection reliability can be expected.

[0040]

EXAMPLES The present invention will be described in more detail with reference to the following Examples, but it should not be construed that the invention is limited thereto.

Example of Formulation of Adhesive m, p-cresol novolak resin (Nippon Kayaku Co., Ltd.
AS-1, 100 g of OH group equivalent) and 100 g of bisphenol F type epoxy resin (RE-404 manufactured by Nippon Kayaku Co., Ltd.)
140 g of S, epoxy equivalent group 165) was dissolved in 60 g of cyclohexanone, and 0.2 g of triphenylphosphine (manufactured by Hokuko Chemical Industry Co., Ltd.) was added as a curing catalyst.
An adhesive varnish was prepared.

Example 1 (Production Example 1 of Multilayer Wiring Board) A 150 μm-thick rolled copper sheet (metal layer 1) having a roughened surface
Roll lamination of a dry film resist (AQ-2058 manufactured by Asahi Kasei Corporation) on EFTEC-64T manufactured by Furukawa Electric Co., Ltd., and exposure and development using a predetermined negative film. A resist 102) was formed. Next, using a rolled copper plate as a lead for electrolytic plating, a resist metal layer (resist metal layer 103) made of gold was formed by electrolytic plating, and a wiring pattern (wiring pattern 104) was formed by electrolytic copper plating. The wiring pattern is
Line width / line interval / thickness = 20 μm / 20 μm / 10 μm. Next, a resin-coated copper foil (APL manufactured by Sumitomo Bakelite) was formed by vacuum lamination while embedding the unevenness of the wiring pattern, and the copper foil was entirely etched to form an insulating layer (insulating layer 105) having a thickness of 25 μm. Next, a via (via 106) having a diameter of 50 μm was formed by a UV-YAG laser. Next, using the rolled copper plate as a lead for electrolytic plating,
The via was filled with copper by electrolytic copper plating to form a copper post (conductor post 107). Next, using a rolled copper plate as a lead for electrolytic plating, a Sn-Pb eutectic solder layer (metallic material layer for joining 108) is formed on a copper post by electrolytic plating.
Was formed. Next, the above-mentioned adhesive varnish was applied to the surface of the insulating layer, that is, the surface on which the Sn-Pb eutectic solder layer was formed, by a bar coat, and then dried at 80 ° C for 20 minutes.
An adhesive layer (adhesive layer 109) having a thickness of μm was formed. By the steps described above, a build-up layer (connection layer 110) could be obtained. On the other hand, a core substrate (core substrate 116)
As an example, a glass epoxy resin copper-clad laminate equivalent to FR-5 on which a 12-μm thick copper foil is formed (E made by Sumitomo Bakelite Co., Ltd.)
Using LC-4781, the copper foil was etched to form a wiring pattern and a land (joined portion 112), thereby obtaining a core layer (connected layer 111). Next, the positioning marks formed in advance on the build-up layer and the core layer obtained in the above-described steps were read by an image recognition device, the two were aligned, and they were temporarily compressed at a temperature of 100 ° C. Further, the above-described positioning and temporary compression were performed again, and a product in which the build-up layers were temporarily compressed on both surfaces of the core layer could be obtained. This was heated and pressurized at a temperature of 220 ° C. by a press, so that the copper post penetrated the adhesive layer and joined to the land by soldering, and the build-up layers were bonded to both surfaces of the core layer by the adhesive layer. Next, the rolled copper plate was removed by etching using a cupric chloride solution. Further, the above steps were repeated, and two build-up layers were laminated on both sides of the core layer.

Subsequently, a semiconductor chip (semiconductor chip 20)
2a) An external connection terminal (external connection terminal 120a) is obtained by partially etching a rolled copper plate (metal layer 101c) used to form an outermost layer (outermost layer 117b) opposite to the mounting surface. Copper core (metal core 118a)
Was formed. The copper core had a top diameter: 200 μm, a bottom diameter: 300 μm, and a height: 150 μm. further,
Using a rolled copper plate (metal layer 101b) used for forming the outermost layer (outermost layer 117a) of the semiconductor chip mounting surface as a lead for electrolytic plating, electrolytic plating is performed to a thickness of 10 μm.
A Sn—Pb eutectic solder film (solder film 119a) was formed. Finally, solder resist (solder resist 1
15) was formed, and a multilayer wiring board (multilayer wiring board 113a) in which external connection terminals were made of a copper core and a Sn-Pb eutectic solder coating covering the copper core was obtained.

Example 2 (Example 2 of manufacturing multilayer wiring board) In Example 1, a semiconductor chip (semiconductor chip 202
b) 150μ used to form the outermost layer of the mounting surface
Only the rolled copper sheet having a thickness of m was changed to an electrolytic copper foil having a thickness of 70 μm (3EC-VLP manufactured by Mitsui Kinzoku Mining Co., Ltd.).
Similarly to the above, a rolled copper plate was used.

First, in the same manner as in the first embodiment, a copper core (metal core 118a) and a Sn—Pb eutectic solder coating are formed on the outermost layer (outermost layer 117b) opposite to the surface on which the semiconductor chip (semiconductor chip 202b) is mounted. An external connection terminal (external connection terminal 120a) made of (solder coating 119a) was formed.

Subsequently, a semiconductor chip (semiconductor chip 202)
b) The copper core (metal core 118c) of the external connection terminal (external connection terminal 120c) by partially etching the electrolytic copper foil (metal layer 101c) used to form the outermost layer of the mounting surface. Was formed. Copper core: top diameter: 60 μm, bottom diameter: 100 μm, height: 70 μm
It became. Further, by electroless plating, a thickness of 10 μm
Was formed, and an external connection terminal (external connection terminal 120c) was obtained.
Thus, a multilayer wiring board (multilayer wiring board 113b) was obtained.

[0047]

According to the multilayer wiring board obtained by the present invention, the metal layer used for manufacturing the multilayer wiring board is etched to form a metal core, and a solder coating is applied. A connection terminal can be formed. In addition, since an external connection terminal equivalent to that can be formed without using an expensive copper core solder bump or the like, significant cost reduction can be expected, and further improvement in connection reliability can be expected.

[Brief description of the drawings]

FIG. 1 is a sectional view illustrating an example of a method for manufacturing a multilayer wiring board according to an embodiment of the present invention.

FIG. 2 is a sectional view showing an example of a method for manufacturing a multilayer wiring board according to the embodiment of the present invention (continuation of FIG. 1).

FIG. 3 is a sectional view showing an example of the method for manufacturing a multilayer wiring board according to the embodiment of the present invention (continuation of FIG. 2).

FIG. 4 is a sectional view showing an example of the method for manufacturing a multilayer wiring board according to the embodiment of the present invention (continuation of FIG. 3).

FIG. 5 is a sectional view showing another example of the method for manufacturing a multilayer wiring board according to the embodiment of the present invention;

FIG. 6 is a sectional view showing another example of the method for manufacturing a multilayer wiring board according to the embodiment of the present invention;

FIG. 7 is a cross-sectional view illustrating an example of a semiconductor device manufactured using the multilayer wiring board according to the embodiment of the present invention.

[Explanation of symbols]

 101a, 101b, 101c Metal layer 102 Plating resist 103 Resist metal layer 104 Wiring pattern 105 Insulating layer 106 Via 107 Conductor post 108 Bonding metal material layer 109 Adhesive layer 110 Connection layer 111 Connected layer 112 Bonded portion 113a, 113b Multilayer Wiring board 114 Pad 115 Solder resist 116 Core substrate 117a, 117b Outermost layer 118a, 118b, 118c Metal core 119a, 119b, 119c Solder coating 120a, 120b, 120c External connection terminal 201a, 201b Semiconductor device 202a, 202b Semiconductor chip 203 Solder Bump 204a, 202b underfill

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masaaki Kato 2-5-8 Higashishinagawa, Shinagawa-ku, Tokyo Sumitomo Bakelite Co., Ltd. (72) Inventor Hideki Hara 2-5-2-8 Higashishinagawa, Shinagawa-ku, Tokyo F-term (reference) within Sumitomo Bakelite Co., Ltd. GG25 GG28 HH07

Claims (6)

[Claims] 1. A multilayer wiring board having an external connection terminal in an outermost layer, wherein the external connection terminal has a columnar shape having a substantially uniform height obtained by etching a metal layer having a substantially uniform thickness. A multilayer wiring board comprising a metal core, wherein a connection portion between the metal core and an outermost wiring pattern is connected by electrolytic plating or electroless plating. 2. The multilayer wiring board according to claim 1, wherein at least a part of the surface of the metal core is covered with a solder coating. 3. A method for manufacturing a multilayer wiring board, comprising: a step of forming a wiring pattern by electrolytic plating using a metal layer as a lead for electrolytic plating; and a step of removing the metal layer by etching. Forming a terminal for external connection having a metal core on the outermost layer of the multilayer wiring board by partially etching and removing a metal layer used in forming the outermost layer. Manufacturing method of a multilayer wiring board. 4. A step of forming a wiring pattern by electrolytic plating using the metal layer as a lead for electrolytic plating, a step of forming an insulating layer on the wiring pattern, and a step of forming a via in the insulating layer so that a part of the wiring pattern is exposed. Forming a conductive post by electrolytic plating using the metal layer as a lead for electrolytic plating, and forming a bonding metal material layer on at least one of the surface of the conductive post or the surface of the portion to be bonded of the connected layer. Forming, forming an adhesive layer on at least one of the surface of the insulating layer and the surface of the layer to be connected, and bonding the conductor post and the portion to be bonded by the bonding metal material layer via the adhesive layer. A method of manufacturing a multilayer wiring board, comprising: a step of bonding an insulating layer and a connected layer with an adhesive layer; and a step of removing a metal layer by etching, wherein the outermost layer of the multilayer wiring board is formed. Forming a terminal for external connection having a metal core on the outermost layer of the multilayer wiring board by partially etching and removing a metal layer used in the multi-layer wiring board. Plate manufacturing method. 5. The method for manufacturing a multilayer wiring board according to claim 3, wherein a solder coating is formed on a surface of the metal core. 6. A multilayer wiring board obtained by the method for manufacturing a multilayer wiring board according to any one of claims 3 to 5.