JP2002153079A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control an oscillation phenomenon appearing in a potential of a control electrode of a switching element. SOLUTION: The emitter electrodes of a plurality of IGBT 3 which are connected in parallel are connected with each other through a wiring pattern 26 (or 27) not relaying a wiring pattern 22 (or 23) and conductor wires W1, W2, W3 and W4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device suitable for controlling a large current, and more particularly to an improvement for suppressing an oscillation phenomenon that appears in a potential of a control electrode of a switching element.

[0002]

2. Description of the Related Art FIG. 28 is a plan sectional view of a base portion of a conventional semiconductor device as a background of the present invention. The semiconductor device 150 is formed as a power module including a plurality of power semiconductor elements. As shown in FIG. 28, the semiconductor device 150 includes a substrate 62 at the bottom. On the main surface of the substrate 62, a plurality of isolated wiring patterns 81 to 85 are arranged in an island shape. On the wiring pattern 81, two I
The GBT 63 and the two diodes 64 are arranged. On the wiring pattern 82, the two IGBTs 63 and the two diodes 64 belonging to the lower arm 71 are arranged.

[0003] Each of the four IGBTs 63 and the four diodes 64 is formed as a bare chip.
Thereby, the two IGBTs 63 belonging to the upper arm 70
And the cathode electrodes of the two diodes 64 are electrically connected to each other through a wiring pattern 81. Similarly, two IGs belonging to the lower arm 71
The collector electrode of the BT 63 and the cathode electrodes of the two diodes 64 are electrically connected to each other through a wiring pattern 82.

[0004] Two IGBTs 63 belonging to the upper arm 70
Are connected to each other by a large number of conductor wires 75. Further, the anode electrodes of the two diodes 64 belonging to the upper arm 70 and the wiring pattern 82 are connected to each other by a number of conductor wires 76. Similarly, the emitter electrodes of the two IGBTs 63 belonging to the lower arm 71 and the wiring patterns 83
Are connected to each other by a large number of conductor wires 75. Also, two diodes 6 belonging to the lower arm 71
The four anode electrodes and the wiring pattern 83 are connected to each other by a large number of conductor wires 76.

In FIG. 28, the conductor wire 75 is not shown for the upper arm 70 and the conductor wire 76 is not shown for the lower arm 71 to avoid complication.

The wiring pattern 84 and the gate electrodes of the two IGBTs 63 belonging to the upper arm 70 are connected to the conductor wires 77.
Connected by Similarly, the wiring pattern 85 and the gate electrodes of the two IGBTs 63 belonging to the lower arm 71 are connected by a conductor wire 77.

The wiring patterns 81 to 85 include an external terminal CC supplied with a high power supply potential, an external terminal EE supplied with a low power supply potential, an external terminal OUT connected to a load, and an external terminal connected to a drive circuit. Terminals G1, G2, S1, S2
Is connected. In FIG. 28, connection portions between the respective wiring patterns and the external terminals are indicated by hatching.

As described above, in the semiconductor device 150, the upper arm 70 and the lower arm 71 connected in series are interposed between the high power supply potential and the low power supply potential, and the external terminal G1
(And G2), the two IGBs belonging to the upper arm 70 (and the lower arm 71)
T63 turns on and off.

[0009]

As shown in the example of the semiconductor device 150, in a power module having a large rated current (for example, 100 A or more), a plurality of power switching elements are connected in parallel so as to share a large current. Is done. However, in the power module, when an unexpected short circuit occurs in the load, a short circuit current having a magnitude of about 5 to about 10 times the rated current flows. In a power module including a plurality of power switching elements, when a short-circuit current flows, the potential of a control electrode (a gate electrode in an IGBT) of each switching element may oscillate. It is recognized that the larger the rated current of the power module, the more the oscillation is likely to occur.

[0010] Even when only one switching element is provided in each of the upper arm and the lower arm, the main electrodes of the switching element are connected to a plurality of bonding pads (see FIG. 28). In I
In the case of having a plurality of strips drawn in the GBT 63, similar oscillation may occur when a short-circuit current flows.

[0011] Oscillation may affect normal operation of applied equipment using the power module, and may cause noise. Furthermore, if the switching element is an IGBT, the influence on the gate insulating film is also assumed.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventional device, and has as its object to provide a semiconductor device capable of suppressing an oscillation phenomenon appearing in the potential of a control electrode of a switching element. I do.

[0013]

An apparatus according to a first aspect of the present invention is a semiconductor device, comprising a substrate having a main surface, a first wiring pattern provided on the main surface, and a first wiring. A plurality of switching elements having one main electrode electrically connected to each other, a second wiring pattern provided on the main surface, and a plurality of switching elements arranged on the main surface. A plurality of first conductor wires each having one end connected to the other main electrode and the other end connected to the second wiring pattern; and a plurality of first conductor wires connected to the second wiring pattern and connected to the other main electrode of the plurality of switching elements. An external terminal electrically connected through the second wiring pattern, and a conductor electrically connected to the other main electrodes of the plurality of switching elements without relaying the second wiring pattern. Equipped with a.

In the device according to a second aspect of the present invention, in the semiconductor device according to the first aspect of the present invention, the conductor is provided on the main surface in isolation from the second wiring pattern; A plurality of second conductor wires having one ends connected to the other main electrodes of the plurality of switching elements and the other ends connected to the third wiring pattern.

In the device according to a third aspect of the present invention, in the semiconductor device according to the second aspect of the present invention, the second wiring pattern extends along an arrangement direction of the plurality of switching elements, and the third wiring pattern is And extending along the direction in which the plurality of switching elements are arranged on the opposite side of the plurality of switching elements from the second wiring pattern.

According to a fourth aspect of the present invention, in the semiconductor device of the third aspect, the third wiring pattern is adjacent to the plurality of switching elements without interposing another wiring pattern.

According to a fifth aspect of the present invention, in the semiconductor device of any of the second to fourth aspects, the third wiring pattern has a repeated bent portion.

According to a sixth aspect of the present invention, in the semiconductor device of the first aspect, the conductor includes a third conductor wire for directly connecting the other main electrodes of the plurality of switching elements.

In a device according to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, the second wiring pattern extends along an arrangement direction of the plurality of switching elements, and the plurality of first conductors are arranged. The wires are arranged in a direction substantially orthogonal to the arrangement direction, and the third conductor wires are arranged along the arrangement direction.

In a device according to an eighth aspect of the present invention, in the semiconductor device according to the seventh aspect, the third conductive wire is located at a portion farther from the second wiring pattern than the one end of the plurality of first conductive wires. The plurality of switching elements are connected to the other main electrodes.

A device according to a ninth aspect is the semiconductor device according to any one of the second to fifth aspects, wherein a fourth wiring pattern provided on the main surface and a control electrode of the plurality of switching elements are provided. And a plurality of fourth conductor wires, one ends of which are connected to the fourth wiring pattern, and a voltage clamp having one end connected to the third wiring pattern and the other end connected to the fourth wiring pattern. And an element.

A tenth aspect of the present invention is a semiconductor device, comprising a substrate having a main surface, a first wiring pattern provided on the main surface, and a first wiring pattern provided on the first wiring pattern. Thereby, one main electrode has a plurality of switching elements electrically connected to each other, a second wiring pattern disposed on the main surface, and one end of the other main electrode of the plurality of switching elements. A plurality of first conductor wires connected to each other, the other end of which is connected to the second wiring pattern; and the other main electrodes of the plurality of switching elements connected to the second wiring pattern and the outside are connected to the second wiring pattern. An external terminal electrically connected through a wiring pattern; and a voltage clamp element electrically connected between the control electrodes of the plurality of switching elements and the other main electrode.

An eleventh aspect of the present invention is a semiconductor device, comprising: a substrate having a main surface; a first wiring pattern provided on the main surface; and a first wiring pattern provided on the first wiring pattern. Accordingly, a plurality of switching elements in which one main electrode is electrically connected to each other, and a second switching element disposed on the main surface so as to extend along an arrangement direction of the plurality of switching elements. One end is connected to the wiring pattern and the other main electrode of the plurality of switching elements;
A plurality of first conductor wires, the other ends of which are connected to the wiring pattern, and the other main electrodes of the plurality of switching elements and the outside, which are connected to the second wiring pattern, are electrically connected through the second wiring pattern. An external terminal to be connected and the same number as the plurality of switching elements are arranged on the first wiring pattern, whereby one of the electrodes is electrically connected to each other, and the plurality of switching elements are in one-to-one correspondence with each other. A plurality of diodes disposed between the plurality of switching elements and the second wiring pattern so as to be adjacent to each other, and one ends connected to the other electrodes of the plurality of diodes, and the other ends connected to the second wiring pattern. Are connected to one another and the other main electrodes of the plurality of switching elements are connected at one end, and a small number of the plurality of diodes are connected. An intermediate portion is connected to some of the other electrodes, and the other end is connected to the second wiring pattern, whereby all the other main electrodes of the plurality of switching elements are connected to the second wiring pattern. A plurality of third conductor wires that are electrically connected without relaying the pattern.

In the apparatus according to the twelfth aspect, the first to the first
In the semiconductor device according to any one of the first to third aspects, the second wiring pattern extends along an arrangement direction of the plurality of switching elements, and the second wiring pattern has one end side in the arrangement direction. A slit extending along the arrangement direction is formed so as to leave the connecting portion and not to leave the connecting portion on the other end side, and the other end of the plurality of first conductor wires is more than the slit. The first terminal near the switching element is connected to the second wiring pattern, the external terminal is connected to the second wiring pattern at the connection portion on the one end side, and the semiconductor device is The other end of the second portion farther from the plurality of switching elements than the slit is connected to the second wiring pattern, and the other main power supply of the plurality of switching elements is connected to the second wiring pattern. Another external terminal for electrically connecting the outside through the second wiring pattern and further comprises.

A thirteenth invention is a semiconductor device, which is a semiconductor device, comprising a substrate having a main surface, a first wiring pattern provided on the main surface, and a first wiring pattern provided on the first wiring pattern. The one main electrode is disposed on the main surface so as to extend in a direction in which the plurality of switching elements are electrically connected to each other and the plurality of switching elements. A second wiring pattern in which a slit extending along the arrangement direction is formed so as to leave a connecting part at one end in the direction and not to leave a connecting part at the other end, and the other main electrode of the plurality of switching elements A plurality of first conductor wires, the other ends of which are connected to the second wiring pattern in a first portion closer to the plurality of switching elements than the slit, and the connecting portion on the one end side. Is connected to the serial second wiring pattern,
An external terminal for electrically connecting the other main electrode of the plurality of switching elements to the outside through the second wiring pattern; and the other end in a second portion farther from the plurality of switching elements than the slit. And another external terminal that is connected to the second wiring pattern on the side and electrically connects the other main electrodes of the plurality of switching elements to the outside through the second wiring pattern.

The device according to a fourteenth aspect is the semiconductor device according to the twelfth aspect, further comprising a fifth conductor wire having one end connected to the first portion and the other end connected to the second portion.

According to the fifteenth aspect of the present invention, the first to the first
4. The semiconductor device according to claim 4, wherein each of the plurality of switching elements is an insulated gate switching element.

A device according to a sixteenth aspect of the present invention is a semiconductor device, comprising a substrate having a main surface, a first wiring pattern provided on the main surface, and a first wiring pattern provided on the first wiring pattern. Thus, one main electrode is electrically connected to the first wiring pattern, and the other main electrode is disposed on the main surface with the switching element having a plurality of bonding pads separated by control electrode wiring. A second wiring pattern, a plurality of first conductor wires each having one end connected to the plurality of bonding pads and the other end connected to the second wiring pattern, and a plurality of first conductor wires connected to the second wiring pattern; An external terminal for electrically connecting the other main electrode to the outside through the second wiring pattern;
One end is connected to a third wiring pattern provided on the main surface in isolation from the wiring pattern, and to two or more bonding pads of the plurality of bonding pads;
Two or more second conductor wires having the other end connected to the third wiring pattern.

According to a seventeenth aspect of the present invention, in the semiconductor device of the sixteenth aspect, the switching element is divided into a plurality of unit switching elements having the same configuration, and each of the plurality of unit switching elements is But,
It has at least two of the plurality of bonding pads, and the one end of the two or more second conductor wires is, for each of the plurality of unit switching elements,
It is connected to two or more bonding pads of the at least two bonding pads.

According to an eighteenth aspect of the present invention, in the semiconductor device of the sixteenth or seventeenth aspect, the two or more second
The one end of the conductor wire is connected to all of the plurality of bonding pads.

According to a nineteenth aspect of the present invention, in the semiconductor device of the sixteenth aspect, the plurality of bonding pads are arranged along one direction, and the switching elements are formed of a plurality of unit units which are identical to each other. The plurality of unit switching elements are divided into switching elements and are arranged along the one direction, each of the plurality of unit switching elements has at least two of the plurality of bonding pads, and the two or more The one end of the two-conductor wire is connected to at least one bonding pad occupying a position closest to a unit switching element located next to the unit switching element for each of the plurality of unit switching elements.

A device according to a twentieth aspect is a semiconductor device, comprising: a substrate having a main surface; a first wiring pattern provided on the main surface; and a first wiring pattern provided on the first wiring pattern. Thus, one main electrode is electrically connected to the first wiring pattern, and the other main electrode is disposed on the main surface with the switching element having a plurality of bonding pads separated by control electrode wiring. A second wiring pattern, a plurality of first conductor wires each having one end connected to the plurality of bonding pads and the other end connected to the second wiring pattern, and a plurality of first conductor wires connected to the second wiring pattern; An external terminal for electrically connecting the other main electrode to the outside through the second wiring pattern and two or more bonding pads of the plurality of bonding pads are mutually connected. And a second conductor wire that connects to.

In a device according to a twenty-first aspect, in the semiconductor device according to the twentieth aspect, the switching element is divided into a plurality of unit switching elements having the same configuration, and each of the plurality of unit switching elements is But,
The second conductor wire includes at least two of the plurality of bonding pads, and the second conductor wire is configured to bond two or more of the at least two bonding pads for each of the plurality of unit switching elements. The pads are connected to each other, and the bonding pads belonging to each of the unit switching elements are connected to each other.

In a device according to a twenty-second aspect, in the semiconductor device according to the twentieth or twenty-first aspect, the second conductor wire connects all of the plurality of bonding pads to one another.

An apparatus according to a twenty-third aspect is a semiconductor device, comprising: a substrate having a main surface; a first wiring pattern provided on the main surface; and a first wiring pattern provided on the first wiring pattern. Thus, one main electrode is electrically connected to the first wiring pattern, and the other main electrode is disposed on the main surface with the switching element having a plurality of bonding pads separated by control electrode wiring. A second wiring pattern, a plurality of first conductor wires corresponding one-to-one with the plurality of bonding pads, one end of which is connected to the plurality of bonding pads, and the other end of which is connected to the second wiring pattern; An external terminal connected to a second wiring pattern and electrically connecting the other main electrode of the switching element to the outside through the second wiring pattern; The said pad second wiring patterns are connected only by the plurality of first conductor wire.

According to a twenty-fourth aspect of the present invention, in the semiconductor device according to the twenty-third aspect, the one electrode is electrically connected to the one main electrode of the switching element. And a diode disposed between the switching element and the second wiring pattern, wherein an intermediate portion of the plurality of first conductor wires is connected to the other electrode of the diode.

According to a twenty-fifth aspect of the present invention, in the semiconductor device of the sixteenth to eighteenth aspects, the plurality of bonding pads are arranged along one direction.
The second wiring pattern extends along the one direction, and the third wiring pattern extends along the one direction on a side opposite to the second wiring pattern across the switching element. Are there.

[0038] In a device according to a twenty-sixth aspect, in the semiconductor device according to the twenty-fifth aspect, the third wiring pattern is adjacent to the switching element without interposing another wiring pattern.

According to a twenty-seventh aspect of the present invention, in the semiconductor device of the twentieth to twenty-second aspects, the plurality of bonding pads are arranged along one direction.
The second wiring pattern extends along the one direction, the plurality of first conductor wires are provided in a direction substantially orthogonal to the one direction, and the second conductor wire is It is arranged along the direction.

According to a twenty-eighth aspect of the present invention, in the semiconductor device according to the twenty-seventh aspect, the second conductor wire is located at a portion farther from the second wiring pattern than the one ends of the plurality of first conductor wires. The switching element is connected to the other main electrode.

According to a twenty-ninth aspect of the present invention, in the semiconductor device of the twenty-third or twenty-fourth aspect, the plurality of bonding pads are arranged along one direction, and the second wiring pattern is arranged in the one direction. Extending along.

According to a thirtieth aspect, in the semiconductor device according to any one of the sixteenth to twenty-ninth aspects, the switching element is an insulated gate switching element.

[0043]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Outline of the embodiment. As a technique for preventing a phenomenon in which a power module including a plurality of switching elements, for example, the semiconductor device 150 in FIG. The following three approaches were assumed. (1) The reference potential of the potential of the control electrode (the gate electrode in the example of the IGBT) between the switching elements connected in parallel, that is, one main electrode (the example of the IGBT,
The potential of the emitter electrode). (2) When oscillation occurs, an element for absorbing the oscillation is provided. (3) Short circuit current is reduced.

When a short-circuit current flows, the main current (IGB
In the example of T, the rate of increase of the emitter current I (= dI / dt)
However, the rate of increase of the main current I under a normal switching operation becomes higher. Due to the change of the main current, the internal inductance L which is parasitic inside the power module is reduced.
Generates an induced electromotive force V (= −L × dI / dt),
This induced electromotive force V is superimposed on the potential of the control electrode. This induced electromotive force V is applied in a direction to increase the potential of the control electrode, that is, in a direction to increase the main current. When the rate of rise of the potential of the control electrode exceeds a certain limit, oscillation occurs in the potential of the control electrode.

The induced electromotive force V is applied to each of a plurality of switching elements connected in parallel, and each switching element operates independently in a transient state. For this reason,
Due to slight differences in characteristics between the switching elements, a vibration exchange is caused between the switching elements, which acts in the direction of expanding the oscillation. Therefore, in order to suppress the expansion of oscillation, it is effective to make the reference potential uniform among a plurality of switching elements.

In order to equalize the reference potential among the plurality of switching elements, one main electrode formed on the semiconductor chip of the plurality of switching elements is placed at a position as close as possible to the main current. An effective means is to connect with a conductor that is not affected. In the power module provided with such a means, the inductive starting force V acting between the switching elements is automatically balanced by the increase rate (= dI / dt) of the main current when the short-circuit current flows, As a result, the oscillation phenomenon can be suppressed or prevented. This is the first approach.

In the second approach, a voltage clamp element is interposed between the control electrodes of a plurality of switching elements connected in parallel and one main electrode. Thereby,
Even if oscillation occurs, the potential of the control electrode can be kept below a certain limit. That is, the intensity of the oscillation phenomenon can be reduced. When the switching element is an insulated gate type switching element such as an IGBT, the intensity of the oscillation phenomenon is reduced, so that it is possible to prevent the influence on the gate insulating film.

To suppress the oscillation phenomenon, it is effective to reduce the induction starting force V applied to the control electrode. However, in the current technology including the semiconductor device 150 of FIG. 28, the internal inductance L parasitically existing in the power module has already been reduced to the limit level. Therefore, to reduce the induction starting force V,
It is necessary to suppress the current increase rate (= dI / dt). The current increase rate (= dI / dt) can be reduced by keeping the potentials of the control electrodes of the plurality of switching elements low.

When the load is short-circuited, a large short-circuit current flows through the wiring pattern through which the main current flows. At this time, an inductive starting force is generated in the wiring pattern due to an inductance unique to that portion. The induced electromotive force raises the potential of the one main electrode, and as a result, lowers the potential of the control electrode with respect to the one main electrode, thereby suppressing an increase in the main current of each switching element. This is the third approach.

As described above, even when only one switching element is provided in each of the upper arm and the lower arm, the main electrodes of the switching elements are divided into a plurality of parts separated from each other. In some cases, when a short circuit current flows, oscillation may occur. Even in suppressing this oscillation, the first to third approaches described above can be assumed by regarding the plurality of bonding pads as the main electrodes of the plurality of switching elements.

In the following, preferred embodiments based on these three approaches will be described in detail. Embodiments 1-4 and 8-15 are based on the first approach, Embodiment 5 is based on the first and second approaches, and Embodiments 6 and 7 are based on the first and third approaches. It is based on an approach. Embodiment 1
6, 17 are based on the third approach.

Embodiment 1 FIG. 1 is a circuit diagram of the semiconductor device according to the first embodiment. FIG. 2 is an external perspective view of the semiconductor device 101 of FIG. 1, and FIG. 3 is a cross-sectional view of the semiconductor device 101 taken along section line XX of FIG.

As shown in FIG. 1, the semiconductor device 101 comprises:
An upper arm 10 having two IGBTs 3 and two diodes 4 and a lower arm 11 also having two IGBTs 3 and two diodes 4 are provided. IG
A power IGBT is used as the BT 3, and a power diode is used as the diode 4. That is, the semiconductor device 101 is formed as a power module including a plurality of power semiconductor elements.

In both the upper arm 10 and the lower arm, between the two IGBTs 3, the emitter electrodes, the collector electrodes, and the gate electrodes are connected. That is, the two IGBTs 3 are connected in parallel with each other as if they function as one IGBT. The two diodes 4 are connected in parallel with the two IGBTs 3 in a direction in which a forward current flows so as to function as a freewheel diode. That is, the anode electrode of the diode 4 is connected to the emitter electrode of the IGBT 3, and the cathode electrode is connected to the collector electrode of the IGBT 3.

The upper arm 10 and the lower arm 11 are connected in series with each other. Two IGBTs on the upper arm 10
3, the collector electrode is connected to the external terminal CC, the gate electrode is connected to the external terminal G1, and the emitter electrode is connected to the external terminal OUT and the external terminal S1. The collector electrodes of the two IGBTs 3 of the lower arm 11 are external terminals OU
T, the gate electrode is connected to the external terminal G2,
The emitter electrode is connected to the external terminal EE and the external terminal S2.

As shown in FIG. 2, these external terminals are
It protrudes from the upper surface of the case 1 to the outside, thereby enabling connection to an external device (not shown). FIG.
Returning to, a high power supply potential (positive power supply potential in the example of FIG. 1) is supplied to the external terminal CC, and a low power supply potential (ground potential in the example of FIG. 1) is supplied to the external terminal EE. . The load 93 is connected to the external terminal OUT.

A drive circuit 90 is connected to the external terminals G1 and S1. The driving circuit 90 has an external terminal S
A drive signal based on the potential of 1 is supplied to the external terminal G1. The IGBT 3 of the upper arm 10 turns on / off in response to a drive signal input through the external terminal G1. Similarly, the driving circuit 9 is connected to the external terminal G2 and the external terminal S2.
1 is connected. The drive circuit 91 supplies a drive signal based on the potential of the external terminal S2 to the external terminal G2. The IGBT 3 of the lower arm 11 turns on / off in response to a drive signal input through the external terminal G2.

As shown in FIG. 3, the semiconductor device 101 comprises:
The substrate 2 is provided at the bottom. On the main surface of the substrate 2, a plurality of isolated wiring patterns 21 to 27 are arranged in an island shape. The plurality of wiring patterns 21 to 27 are electrically insulated from each other. For that purpose, for example, the main surface of the substrate 2 may be an insulator. Alternatively, an insulator may be interposed between the wiring patterns 21 to 27 and the substrate 2. On the wiring pattern 21, the upper arm 10
Are arranged, and two IGBTs 3 and two diodes 4 belonging to the lower arm 11 are arranged on the wiring pattern 22.

Each of the four IGBTs 3 and the four diodes 4 is formed as a bare chip. Thereby, the collector electrodes of the two IGBTs 3 and the cathode electrodes of the two diodes 4 belonging to the upper arm 10 are
They are electrically connected to each other through a wiring pattern 21. Similarly, the collector electrodes of the two IGBTs 3 belonging to the lower arm 11 and the cathode electrodes of the two diodes 4 are electrically connected to each other through a wiring pattern 22.

Two diodes 4 connected in parallel with each other
And the two IGBTs 3 are arranged adjacent to each other in a one-to-one relationship. That is, one IG
The arrangement is such that one diode 4 is adjacent to BT3. Thereby, the diode 4 and the IGBT 3
The resistance and inductance between the IGBT 3 and the IGBT 3 of the diode 4 as a freewheel diode are reduced.
The protection function against is enhanced.

The external terminal CC is connected to the wiring pattern 21. That is, the external terminal CC is connected to the wiring pattern 2
1 are electrically connected to the collector electrodes of two IGBTs 3 and the cathode electrodes of two diodes 4 belonging to the upper arm 10. Similarly, the wiring pattern 22
Is connected to an external terminal OUT. That is, the external terminal OUT is connected to the lower arm 10 through the wiring pattern 22.
Are electrically connected to the collector electrodes of the two IGBTs 3 and the cathode electrodes of the two diodes 4. In FIG. 3 (and each of the following figures), a connection portion between each wiring pattern and an external terminal is indicated by hatching.

The emitter electrodes of the two IGBTs 3 belonging to the upper arm 10 and the wiring pattern 22 are connected to each other by a large number of conductor wires 15. Further, the anode electrodes of the two diodes 4 belonging to the upper arm 10 and the wiring pattern 22 are connected to each other by a large number of conductor wires 16. Similarly, the emitter electrodes of the two IGBTs 3 belonging to the lower arm 11 and the wiring pattern 23 are
They are connected to each other by a number of conductor wires 15.
Further, the anode electrodes of the two diodes 4 belonging to the lower arm 11 and the wiring pattern 23 are formed by a large number of conductor wires 1.
6 are connected to each other. Conductor wire 15,1
For example, an aluminum wire is used as the conductor wire 6 and the conductor wires described below.

In FIG. 3 (and each of the following figures), the conductor wire 15 is omitted for the upper arm 10 and the conductor wire 16 is omitted for the lower arm 11 to avoid complication. .

Further, the wiring pattern 22 is
The wiring pattern 23 extends along the arrangement direction of the two IGBTs 3 belonging to the lower arm 11 and extends along the arrangement direction of the two IGBTs 3 belonging to the lower arm 11. And
In each of the upper arm 10 and the lower arm 11, a conductor wire 15 for connecting the emitter electrode of the two IGBTs 3 connected in parallel and the wiring pattern 22 (or 23)
Are arranged in a direction substantially orthogonal to the arrangement direction of the two IGBTs 3 so as to be shortest.

Similarly, the conductor wire 16 connecting the anode electrodes of the two diodes 4 connected in parallel and the wiring pattern 22 (or 23) is substantially orthogonal to the arrangement direction of the two IGBTs 3 so as to be shortest. It is arranged in the direction to do. As a result, the emitter electrodes of the two IGBTs 3 connected in parallel and the anode electrodes of the two diodes 4 are connected to the wiring pattern 22 (or 23) through low resistance and low inductance.

The wiring pattern 22 is connected to the external terminal S1 in addition to the external terminal OUT, and the wiring pattern 23 is connected to the external terminal EE and the external terminal S2. Thereby, two IGs belonging to the upper arm 10
The emitter electrode of the BT 3 and the anode electrodes of the two diodes 4 are electrically connected to both the external terminal OUT and the external terminal S1 through the conductor wires 15, 16 and the wiring pattern 22. Similarly, the emitter electrodes of the two IGBTs 3 and the anode electrodes of the two diodes 4 belonging to the lower arm 11 are electrically connected to both the external terminal EE and the external terminal S2 through the conductor wires 15, 16 and the wiring pattern 23. It is connected to the.

The external terminal G 1 is connected to the wiring pattern 24, and the wiring pattern 24 and the gate electrodes of the two IGBTs 3 belonging to the upper arm 10 are connected by the conductor wires 17. That is, the external terminal G1 and the gate electrodes of these IGBTs 3 are electrically connected to each other through the conductor wires 17 and the wiring patterns 24. Similarly, the external terminal G2 is connected to the wiring pattern 25, and the wiring pattern 25 and the gate electrodes of the two IGBTs 3 belonging to the lower arm 11 are connected to the conductor wires 17
Connected by That is, the external terminal G2 and the gate electrodes of these IGBTs 3 are electrically connected to each other through the conductor wires 17 and the wiring patterns 25.

The wiring pattern 26 and the emitter electrodes of the two IGBTs 3 belonging to the upper arm 10 are
1 and W2. As a result, the emitter electrodes of the two IGBTs 3 belonging to the upper arm 10 are paths that do not relay the wiring pattern 22 and that are paths through which the emitter current flowing through the external terminal OUT does not flow. 26
Are electrically connected to each other. As a result, the emitter potentials of the two IGBTs 3 belonging to the upper arm 10 are made uniform, so that even when the load 93 is short-circuited,
The oscillation phenomenon at the potential of the gate electrodes of the two IGBTs 3 is suppressed.

Similarly, the wiring pattern 27 and the lower arm 11
Are connected to the emitter electrodes of the two IGBTs 3 by conductor wires W3 and W4. As a result, the emitter wires of the two IGBTs 3 belonging to the lower arm 11 are paths that do not relay the wiring pattern 23 and that do not allow the emitter current flowing through the external terminal EE to flow. 27, they are electrically connected to each other. As a result, the emitter potentials of the two IGBTs 3 belonging to the lower arm 11 are equalized, so that even when the load 93 is short-circuited, the oscillation phenomenon at the potentials of the gate electrodes of the two IGBTs 3 is suppressed.

The connection between the emitter electrodes of the two IGBTs 3 for equalizing the emitter potentials is made by connecting each emitter electrode and the wiring pattern 26 (or 27) with the conductor wires W1, W2 (or W3, W4). It is easily realized by connecting. That is, there is an advantage that the manufacturing process is easy. Moreover, the conductor wire W
1, W2 (or W3, W4) is connected to the wiring pattern 26 (or 27), so that the conductor wire W
In the process of arranging 1, W2 (or W3, W4), it is not necessary to perform wire cutting on the IGBT3.
For this reason, the conductor wires W1 and W2 can be easily formed without requiring any special means for preventing the IGBT 3 from being damaged.
(Or W3, W4) can be provided.

Further, the wiring pattern 22 is
The wiring pattern 26 extends along the arrangement direction of the two IGBTs 3 belonging to the IGBT 3 and the wiring pattern 26 extends on the opposite side to the wiring pattern 22 across these IGBTs 3 and also along the arrangement direction of the IGBTs 3. . Therefore, the conductor wire 1
5, the conductor wires W1 and W2 can be easily arranged. Further, the conductor wire 15
And inductive coupling between the conductor wires W1 and W2 can be reduced, so that the effect of suppressing oscillation can be enhanced.

Similarly, the wiring pattern 23 is
The wiring pattern 27 extends along the direction of arrangement of the two IGBTs 3 belonging to 1, and the wiring pattern 27 also extends along the direction of arrangement of the IGBTs 3 on the opposite side to the wiring pattern 23 across these IGBTs 3. . Therefore, the lower arm 1
In the case of No. 1, the same effect as that described above for the upper arm can be obtained.

Further, the upper arm 10 and the lower arm 11
In each of the two IGBTs 2
3 and the wiring pattern 22 (or 23), the conductor wire 1 connecting the anode electrodes of the two diodes 4 and the wiring pattern 22 (or 23).
6, the conductor wires W1 and W2 (or W3 and W4) can be easily arranged.

Further, the wiring pattern 26 is formed by two IGs belonging to the upper arm 10 without interposing other wiring patterns.
Adjacent to BT3. Therefore, the conductor wires W1, W
2 can be set short. Thereby, the inductance of the path for electrically connecting the emitter electrodes of the two IGBTs 3 belonging to the upper arm 10 is reduced, so that the effect of making the potentials of the emitter electrodes uniform can be further enhanced. Similarly, the wiring pattern 27 is adjacent to the two IGBTs 3 belonging to the lower arm 11 without sandwiching another wiring pattern. Therefore, the same effect as described above for the upper arm can be obtained for the lower arm 11 as well.

It should be noted that FIGS. 1 to 3 show I connected in parallel.
Although the example in which the number of the GBTs 3 and the diodes 4 is two has been described, three or more IGBTs 3 and the diodes 4 may be connected in parallel.

Embodiment 2 FIG. 4 is a plan sectional view of the semiconductor device according to the second embodiment. This semiconductor device 10
2 is the same as FIGS. 1 and 2 of the first embodiment, and FIG. 4 is a semiconductor device 101 of FIG.
Corresponds to a cross-sectional view taken along the line XX when the semiconductor device 102 is In the following figures, FIGS.
The same or corresponding portions (portions having the same functions) as those of the semiconductor device 101 shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The semiconductor device 102 includes a wiring pattern 26,
27 is characteristically different from the semiconductor device 101 in FIG. 3 in that each of the semiconductor devices 27 has a repeated bent portion. Experiments show that the inductance of a path connecting two emitter electrodes of two IGBTs 3 connected in parallel without relaying the wiring pattern 22 (or 23) has an optimum value for suppressing oscillation. Has been confirmed by In the semiconductor device 102, the wiring patterns 26 and 27
Have a repeating bend, the conductor wire W
By changing the connection positions of 1 to W4, the inductance of the path for electrically connecting the emitter electrodes of the two IGBTs 3 connected in parallel can be freely adjusted. Thus, in the final stage of the manufacturing process of the semiconductor device 102, it is possible to finely adjust the inductance of each of the wiring patterns 26 and 27 to an optimum value.

FIG. 4 shows IGBTs connected in parallel.
Although the example in which the number of the IGBTs 3 and the number of the diodes 4 are two has been described, three or more IGBTs 3 and the number of the diodes 4 may be connected in parallel.

Embodiment 3 FIG. 5 is a plan sectional view of the semiconductor device according to the third embodiment. This semiconductor device 10
3 is the same as FIGS. 1 and 2 of the first embodiment, and FIG. 5 is a semiconductor device 101 of FIG.
Corresponds to a cross-sectional view taken along the line XX when the semiconductor device 103 is used as the semiconductor device 103.

The semiconductor device 103 includes the wiring pattern 26,
3 in that the emitter electrodes 27 and the conductor wires W1 to W4 are not provided, and instead, the emitter electrodes of two IGBTs 3 connected in parallel are directly connected by the conductor wire W5 (or W6). It is characteristically different from 101. Since the wiring patterns 26 and 27 are not required, the manufacturing process is simplified and the substrate 2
And the semiconductor device 103 can be reduced in size.

As shown in FIG. 5, in each of the upper arm 10 and the lower arm 11, the conductor wire W5 (or W6) is arranged along the direction in which the two IGBTs 3 connected in parallel are arranged. I have. As a result, the conductor wire W
5 (or W6) are two IGBTs 3 connected in parallel.
And the conductor wire 15 connecting the wiring pattern 22 (or 23) is approximately orthogonal. Thereby, the inductive coupling between the conductor wire 15 and the conductor wire W5 (or W6) is suppressed low, and the effect of suppressing oscillation is further enhanced.

Further, the upper arm 10 and the lower arm 11
In each of the above, the conductor wire W5 (or W6) is connected to the wiring pattern 22 (or 2
In a portion far from 3), it is connected to the emitter electrodes of two IGBTs 3. For this reason, the inductive coupling between the conductor wire 15 and the conductor wire W5 (or W6) is further suppressed, and the effect of suppressing oscillation is further enhanced. Also, the conductor wire 15 and the conductor wire W5
(Or W6) can be easily arranged without interfering with each other.

FIG. 5 shows IGBTs connected in parallel.
Although the example in which the number of the IGBTs 3 and the number of the diodes 4 are two has been described, three or more IGBTs 3 and the number of the diodes 4 may be connected in parallel. At this time, a plurality of IGs connected in parallel
Of the BT3s, the emitter electrodes may be individually connected between two adjacent BTBTs by a conductor wire, and three or more IGBT3s may be connected by connecting three or more locations including the middle part of the conductor wire to the emitter electrode. May be connected by a single conductor wire.

Embodiment 4 FIG. 6 is a plan sectional view of the semiconductor device according to the fourth embodiment. This semiconductor device 10
4 is the same as FIG. 1 and FIG. 2 of the first embodiment, and FIG. 6 is a semiconductor device 101 of FIG.
Corresponds to a cross-sectional view taken along the line XX when the semiconductor device 104 is taken as a semiconductor device.

The semiconductor device 104 includes the wiring pattern 26,
27 and the conductor wires W1 to W4 are not provided. Instead, the emitter electrodes of the two IGBTs 3 connected in parallel are connected to one anode of the two diodes 4 by the conductor wires W7 and W8 (or W9 and W10). It is characteristically different from the semiconductor device 101 in FIG. 3 in that it is connected to the electrode and the wiring pattern 22 (or 23). That is, the conductor wires W7, W8 (or W9, W
One end of 10) is connected to the emitter electrodes of two IGBTs 3 connected in parallel, the middle part is connected to one anode electrode of the two diodes 4, and the other end is connected to the wiring pattern 22 (or 23). It is connected.

Therefore, two IGBs connected in parallel
The emitter electrodes of T3 are electrically connected to each other through the conductor wire W7 (or W9), the anode electrode of the diode 4, and the conductor wire W8 (or W10) without passing through the wiring pattern 22 (or 23) through which the emitter current flows. Connected. As a result, similarly to the semiconductor device 101 (FIG. 3), two IGBs connected in parallel
Since the potential of the emitter electrode of T3 is made uniform, an effect of suppressing the oscillation phenomenon can be obtained.

Further, the conductor wires W7, W8 (or W
9, W10) is connected to the second wiring pattern. Therefore, in the step of arranging the conductor wires W7, W8 (or W9, W10), it is necessary to perform wire cutting on either the IGBT 3 or the diode 4. Nor. Therefore, no means for preventing damage to the IGBT 3 and the diode 4 is required in the manufacturing process. That is, there is an advantage that the manufacturing process can be simplified.

FIG. 6 shows IGBTs connected in parallel.
Although the example in which the number of the IGBTs 3 and the number of the diodes 4 are two has been described, three or more IGBTs 3 and the number of the diodes 4 may be connected in parallel. At this time, the emitter electrodes of all the IGBTs 3 are electrically connected to each other through the anode electrodes of the single or plural diodes 4 and the plural conductor wires without passing through the wiring pattern 22 (or 23). A plurality of conductor wires are provided. Also in this case, one end of each conductor wire is connected to the emitter electrode of the IGBT 3, the intermediate portion is connected to the anode electrode of the diode 4, and the other end is connected to the wiring pattern 22 (or 2).
Connected to 3). One end of at least one conductor wire is connected to all of the plurality of IGBTs 3, but the plurality of diodes 4 may be connected to the middle part of the conductor wire only to a part thereof. is there.

Embodiment 5 FIG. 7 is a plan sectional view of the semiconductor device according to the fifth embodiment. FIG. 8 is a circuit diagram showing a part of the semiconductor device 105. Semiconductor device 10
5 is the same as FIG. 2 of the first embodiment,
FIG. 7 is a cross-sectional view taken along the line XX when the semiconductor device 101 of FIG.

The semiconductor device 105 includes the wiring pattern 24
The point that two Zener diodes 9 connected in series with each other so that the direction of the forward current is reversed is interposed between (or 25) and the wiring pattern 26 (or 27) in FIG. Is characteristically different from the semiconductor device 101 of FIG. The two Zener diodes 9 are connected to each other via a wiring pattern 31 provided on the substrate 2. The two Zener diodes 9 connected in series are:
The voltage clamp element 30 is formed.

Voltage clamp element 30 prevents the potential difference between the gate electrode and the emitter electrode of two IGBTs 3 connected in parallel from increasing beyond a certain limit. Therefore, even if oscillation occurs, the amplitude is suppressed so as not to exceed a certain limit.

FIG. 7 shows IGBTs connected in parallel.
Although the example in which the number of the IGBTs 3 and the number of the diodes 4 are two has been described, three or more IGBTs 3 and the diodes 4 may be connected in parallel. In FIG. 7, the semiconductor device 1 of FIG.
Although the example in which the clamp element 30 is provided in FIG. 1 is shown, it is also possible to provide the clamp element 30 in the semiconductor device 102 in FIG.

In FIG. 7, the wiring pattern 26
(Or 27) and the conductor wires W1, W2 (or W
3, W4) without providing a plurality of I
The clamp element 30 may be electrically connected between the emitter electrode and the gate electrode of the GBT 3. For example, the clamp element 30 may be connected between the wiring pattern 22 (or 23) and the wiring pattern 24 (or 25). In this embodiment, the occurrence of the oscillation phenomenon cannot be suppressed, but the amplitude of the generated oscillation can be suppressed to a certain limit or less.

Embodiment 6 FIG. FIG. 9 is a plan sectional view of the semiconductor device according to the sixth embodiment. This semiconductor device 10
6 is the same as FIG. 2 of the first embodiment,
FIG. 9 is a cross-sectional view taken along the line XX when the semiconductor device 101 of FIG.

The semiconductor device 106 differs from the semiconductor device 106 shown in FIG. 7 in that a slit 40 (or 41) is formed in a wiring pattern 22 (or 23) extending along the arrangement direction of two IGBTs 3 connected in parallel. Is characteristically different from the semiconductor device 105 of FIG. Slit 40 (or 41)
Extends along the arrangement direction such that a connection part is left at one end side in the arrangement direction and a connection part is not left at the other end side.
That is, the slit 40 (or 41) extends from the other end side toward the one end side so as to leave a connecting portion at one end side.

As schematically shown in FIG. 10, an example of the wiring pattern 23, the conductor wire 15 (and 16) in the wiring pattern 22 (or 23) is two more than the slit 40 (or 41). First portion 23a close to IGBT3
It is connected to the. The external terminal OUT (or EE)
It is connected to the connecting portion on the one end side in the wiring pattern 22 (or 23). Further, the external terminal S1 (or S2) is connected to the other end of the second portion 23b farther from the two IGBTs 3 than the slit 40 (or 41) in the wiring pattern 22 (or 23). . Therefore, two IGBTs 3 connected in parallel, the external terminal OUT (or EE), and the external terminal S1 (or S1)
The relationship between 2) is represented by the circuit diagram of FIG.

Since the emitter current flows to the external terminal OUT (or EE) through the first portion 23a, the load 93
When the emitter current sharply increases due to short circuit of
Due to the inductance L1 of the portion 23a, the IGBT
Back electromotive force is generated between the emitter electrode 3 and the external terminal OUT (or EE). That is, the external terminal OUT
The potential of the emitter electrode of the IGBT 3 with reference to the potential of (or EE) rises. However, the external terminal S1
(Or S2) is connected to the external terminal OUT (or E
Since the same height as the potential of E) is maintained, the gate voltage applied between the gate electrode and the emitter electrode of the IGBT 3 is reduced by the rise in the potential of the emitter electrode. As a result, an increase in the emitter current is suppressed, and the effect of suppressing the oscillation phenomenon is further enhanced.

FIG. 9 shows IGBTs connected in parallel.
Although the example in which the number of the IGBTs 3 and the number of the diodes 4 are two has been described, three or more IGBTs 3 and the number of the diodes 4 may be connected in parallel. FIG. 9 shows the semiconductor device 1 of FIG.
05 shows an example in which the slits 40 and 41 are formed,
For the semiconductor devices 101 to 104, the slits 40,
41 can be provided, and the effect of suppressing the oscillation phenomenon can be similarly increased.

The wiring pattern 26 (or 27) and the conductor wires W1 and W2 (or W3 and W4) are not provided, and the conductor wires W5 and W6 are not provided. Slit 4
0 (or 41) may be provided. Also in this embodiment, the effect of suppressing the occurrence of the oscillation phenomenon can be obtained accordingly.

Embodiment 7 FIG. FIG. 12 is a plan sectional view of the semiconductor device according to the seventh embodiment. This semiconductor device 1
07 is the same as FIG. 2 of the first embodiment, and FIG. 12 shows the semiconductor device 101 of FIG.
7 corresponds to a cross-sectional view along the XX cutting line.

The semiconductor device 107 includes the wiring pattern 22
(Or 23) formed in the slit 40 (or 4)
1) a first portion 23a and a second portion 2 that face each other
3b is characteristically different from the semiconductor device 106 in FIG. 9 in that it is connected with the conductor wire 50 (or 51). As schematically shown in FIG. 13, the arrangement of the conductor wire 51 at a distance a from the opening end of the slit 41 is caused by the potential of the external terminal EE and the potential of the external terminal S2. In this relation, the depth b of the slit 41 is substantially the same as the depth a, which is the same as the distance a, as shown in FIG. The same applies to the conductor wires 50 installed on the wiring pattern 22. Therefore, when the conductor wire 50 (or 51) is provided, the two I
The relationship between GBT3, external terminal OUT (or EE), and external terminal S1 (or S2) is represented by the circuit diagram of FIG.

That is, the conductor wire 50 (or 51)
By changing the position of the external terminal S1.
(Or S2) between the potential of the emitter electrode of the IGBT 3 and the potential of the external terminal OUT (or EE).
The advantage is that it can be adjusted freely. Thus, fine adjustment can be performed at the final stage of the manufacturing process so that characteristics are uniform among the individual mass-produced semiconductor devices 107.

Structure of IGBT in each embodiment. FIG. 16 shows a semiconductor device 1 according to the first to seventh embodiments.
01 to 107, and Embodiments 8 to 17 described below
IGB provided in each of semiconductor devices 108-117
It is a top view of T3. The IGBT 3 has a gate wiring 32, a gate pad 33, and a plurality of emitter pads 34 on its upper surface. Gate wiring 32 is connected to gate pad 33. For example, the conductor wire 17 shown in FIG. 3 is connected to the gate pad 33. That is, the gate pad 33 is a bonding pad for the gate electrode. The plurality of emitter pads 34 are portions of the emitter electrode covering most of the upper surface of the IGBT 3 to which a conductor wire can be connected. That is, the emitter pad 34
This is a bonding pad for the emitter electrode.

[0104] Inside the IGBT 3 (not shown),
A basic unit called a large number (for example, about 100,000) of unit cells (the minimum unit which itself functions as an IGBT)
Are connected in parallel with each other. The gate electrode of each unit cell is connected to the gate pad 33 through the gate wiring 32, and the emitter electrode covering most of the upper surface of the IGBT 3 is commonly connected to all unit cells. In the IGBT 3, a gate wiring 32 is provided in a form branched from a gate pad 33 that receives a gate voltage through the conductor wire 17 (FIG. 3) in order to operate these many unit cells as evenly as possible.
The gate wiring 32 is also called a gate finger due to its shape. For this reason, the emitter electrode covering most of the upper surface of the IGBT 3 has a plurality of
That is, the plurality of emitter pads 34 are partitioned.

The plurality of emitter pads 34 are formed at the bridge portions 3 corresponding to the gaps between the gate wires 32 of the emitter electrodes.
5 are integrally connected to each other. The bridge portion 35 is distinguished from the emitter pad 34 to which a conductor wire can be connected in that the bridge portion 35 is a portion that is too narrow to connect a conductor wire. In the normal operation of the IGBT 3, the emitter current of the IGBT 3 is
The conductor wires are connected equally to each of the emitter pads 34 so that the conductor wires hardly flow through the bridge portion 35. As a result, even though the bridging portion 35 is sufficiently narrow, the plurality of emitter pads 34 are
During this period, the potential is kept uniform.

However, when a short-circuit current flows, the magnitude of the current flowing through the bridge portion 35 cannot be ignored.
In some cases, non-uniform potential may occur between the plurality of emitter pads 34. As a result, even in a semiconductor device in which only one IGBT 3 is provided in each of the upper arm 10 and the lower arm 11 (FIG. 1), an oscillation phenomenon may appear in the IGBT 3. In the following embodiments 8 to 17, a semiconductor device capable of suppressing an oscillation phenomenon caused by non-uniform potential between a plurality of emitter pads 34 will be described.

Embodiment 8 FIG. FIG. 17 is a plan sectional view of the semiconductor device according to the eighth embodiment. This semiconductor device 1
08 is a circuit diagram and an external perspective view of FIG.
FIG. 17 is the same as FIG.
FIG. 11 corresponds to a cross-sectional view taken along the line XX when 01 is the semiconductor device 108.

The wiring patterns 26 and 27 are
Each of the plurality of emitter pads 34 of each IGBT 3 and the corresponding wiring pattern 2
6 or 27 each being a plurality of conductor wires W1
-W4,
The semiconductor device 108 is the semiconductor device 1 according to the first embodiment.
01 is characteristically different. For example, the upper arm 10
One end of each of the six conductor wires W1 is individually connected to all of the six emitter pads 34 provided on one of the two IGBTs 3 (the IGBT 3 located at the left end in FIG. 17). The other end of the conductor wire W1 is connected to the wiring pattern 26.

A plurality of conductor wires 15 for connecting the emitter electrode of each IGBT 3 to the wiring pattern 22 or 23
Are connected to all of the plurality of emitter pads 34 of each IGBT 3. Therefore, as described above, in the normal operation of the semiconductor device 108, almost no current flows through the bridge portion 35 in FIG. In the example of FIG. 17, one end of two conductor wires 15 is connected to each of the plurality of emitter pads 34 of each IGBT 3, and the other ends are connected to the wiring patterns 22 or 23.
Each of the plurality of emitter pads 34 of each IGBT 3
Wiring pattern 22 or 2
3 is the same in each of the drawings illustrating the semiconductor devices 101 to 107 according to the first to seventh embodiments, and according to the following embodiments 9 to 15 excluding the sixteenth and seventeenth embodiments. The same applies to each of the drawings illustrating the semiconductor devices 109 to 115.

In the semiconductor device 108, as described above, each I
All of the plurality of emitter pads 34 of the GBT 3 are conductors that do not relay the wiring patterns 22 and 23, that is, conductor wires through which emitter current does not flow.
4 and one of the wiring patterns 26 and 27 are electrically connected to each other. Therefore, the potential is made uniform among the plurality of emitter pads 34. As a result, even when the load of the semiconductor device 108 is short-circuited, that is, when an excessive short-circuit current flows through each IGBT 3, the oscillation phenomenon at the potential of the gate electrode of each IGBT 3 is suppressed.

In the example of FIG. 17, any one of the conductor wires W1 to W4 is connected to each emitter pad 34 of each IGBT 3 one by one. Good. However, in the embodiment of FIG. 17 in which the conductor wires W1 to W4 are connected one by one, the number of the conductor wires W1 to W4 can be minimized, the connection of the conductor wires W1 to W4 can be easily performed, and the oscillation of each IGBT 3 can be effectively suppressed. Benefits are obtained.

In the semiconductor device 108, each IGBT
3 are arranged along one direction, and the corresponding wiring pattern 22 or 23 and the wiring pattern 26 or 27 are arranged on each other with the corresponding IGBT 3 interposed therebetween. Extending along the direction. Therefore, the conductor wire 15 and the conductor wires W1 to W4 can be easily arranged without interfering with each other. Further, the inductive coupling between the conductor wire 15 and the conductor wires W1 to W4 can be reduced, thereby increasing the effect of suppressing oscillation.

In the semiconductor device 108, each of the wiring patterns 26 and 27 is adjacent to the corresponding IGBT 3 without interposing other wiring patterns. Therefore, the conductor wires W1 to W4 can be set short. Thereby, the inductance of the conductor electrically connecting the emitter pads 34 is reduced,
The potential can be more effectively equalized between the emitter pads 34. Also, the wiring patterns 26 and 2
7 is divided for each corresponding IGBT 3, so that there is an advantage that there are few restrictions on the layout of the IGBT 3.

Although the semiconductor device 108 has an example in which each of the upper arm 10 and the lower arm 11 includes two IGBTs 3 connected in parallel with each other, three or more IGBTs 3 connected in parallel with each other are shown. An IGBT 3 may be provided, or only a single IGBT 3 may be provided. In any case, all of the plurality of emitter pads 34 of each IGBT 3 are electrically connected to each other through a conductor that does not relay the wiring patterns 22 and 23.
The oscillation of the GBT 3 can be suppressed.

Embodiment 9 FIG. FIG. 18 is a plan sectional view of the semiconductor device according to the ninth embodiment. This semiconductor device 1
09 is a circuit diagram and an external perspective view of FIG.
FIG. 18 is the same as FIG.
FIG. 11 corresponds to a cross-sectional view taken along the line XX when 01 is the semiconductor device 109.

Each of the plurality of emitter pads 34 included in each IGBT 3 is two or more (4 in the example of FIG. 18).
) Of the conductor pads W1 to W
4 is connected, the semiconductor device 109 is
It is characteristically different from the semiconductor device 108 according to the eighth embodiment. For example, two IGBs belonging to the upper arm 10
One of the T3s (the IGBT located at the left end of FIG. 17)
Of the six emitter pads 34 provided in 3), 4
Four conductor wires W1 only on the emitter pads 34
Are individually connected, and the other ends of the conductor wires W1 are connected to the wiring pattern 26.

In the semiconductor device 109, a part (two or more) of the plurality of emitter pads 34 of each IGBT 3 are connected to each other by the wiring pattern 2.
Conductors that do not relay 2, 23 (ie, conductor wire W
1 to W4 and any of the wiring patterns 26 and 27).
The effect of suppressing oscillation when the GBT 3 is short-circuited is obtained accordingly. Further, since a large interval between the conductor wires W1 to W4 can be ensured, these conductor wires W1 to W4 can be secured.
The advantage that connection of W4 is easy is obtained.

The ratio occupied by one or more of the emitter pads 34 connected to any of the conductor wires W1 to W4 among the plurality of emitter pads 34 included in each IGBT 3 is 以上 or more (in the example of the IGBT 3 in FIG. Above). This is because if the above ratio is 以上 or more,
This is because the effect of suppressing oscillation appears significantly.

Embodiment 10 FIG. FIG. 19 shows Embodiment 1
0 is a plan sectional view of the semiconductor device according to FIG. A circuit diagram and an external perspective view of this semiconductor device 110 are the same as those of FIGS. 1 and 2 of the first embodiment, and FIG. 19 is a sectional view taken along line XX when semiconductor device 101 of FIG. Corresponds to a cross-sectional view taken along the line.

In each of the upper arm 10 and the lower arm 11, two or more (two in the example of FIG.
Wiring patterns 26 or 2 corresponding to IGBT3)
Semiconductor device 110 is characteristically different from semiconductor device 108 according to the eighth embodiment in that semiconductor device 110 is not divided for each corresponding IGBT 3 and is integrally connected. For this reason, in each IGBT 3, the emitter pad 3
4 are connected not only through one of the conductor wires W1 to W4 and any of the wiring patterns 26 and 27, but also between the IGBTs 3 connected in parallel, the emitter pads 34 are connected through their conductors. Connected to each other. As a result, the effect of suppressing the oscillation of each IGBT 3 is smaller than that of the semiconductor device 108 of the eighth embodiment.
Further enhanced.

In the semiconductor device 110, the IGBTs 3 are arranged so that the emitter pads 34 of the IGBTs 3 connected in parallel to each other are arranged along one direction, and the wiring patterns 26 and 27 correspond to the corresponding emitter pads. 34 extend in the arrangement direction. For this reason, the conductor wires W1 to W4 can be easily arranged.

Embodiment 11 FIG. FIG. 20 shows Embodiment 1
1 is a plan sectional view of a semiconductor device according to No. 1; The circuit diagram and the external perspective view of the semiconductor device 111 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 20 is a sectional view taken along the line XX when the semiconductor device 101 in FIG. Corresponds to a cross-sectional view taken along the line.

In each of the upper arm 10 and the lower arm 11, two or more (two in the example of FIG. 19)
Wiring patterns 26 or 2 corresponding to IGBT3)
The semiconductor device 111 is characteristically different from the semiconductor device 109 according to the ninth embodiment in that the semiconductor device 111 is not divided for each corresponding IGBT 3 but is integrally connected. For this reason, in each IGBT3, some of the emitter pads 34 are connected to one of the conductor wires W1 to W4,
Some of the emitter pads 34 are connected to each other through their conductors not only between the IGBTs 3 and the wiring patterns 26 and 27 but also between the IGBTs 3 connected in parallel. Therefore, each IGBT3
The semiconductor device 1 of the ninth embodiment has the effect of suppressing oscillation of
09 compared to 09. In addition, each IGBT3
Among the plurality of emitter pads 34 included in the semiconductor device, the emitter pad 34 to which one of the conductor wires W1 to W4 is connected.
It is the same as semiconductor device 109 of the ninth embodiment in that the ratio of

In the semiconductor device 111, among the plurality of emitter pads 34 of each IGBT 3, the conductor wire W
Two or more emitter pads 34 to which any one of 1 to W4 is connected are relatively evenly allocated. FIG.
In the example of 0, the four emitter pads 34 to which any of the conductor wires W1 to W4 are connected are assigned to both ends and a center. The same applies to the semiconductor device 109 (FIG. 18). Thereby, the potential is made more uniform among the plurality of emitter pads 34 belonging to each IGBT 3, so that the oscillation is more effectively suppressed.

On the other hand, the semiconductor device 1 shown in FIG.
As in 11a, any of the conductor wires W1 to W4 may be connected to the emitter pad 34 closest to each other between the IGBTs 3 connected in parallel and adjacent to each other. In the example of FIG. 21, one of the conductor wires W1 to W4 is connected to the three emitter pads 34 for each IGBT 3;
May be connected to any of the conductor wires W1 to W4. When three or more IGBTs 3 are connected in parallel to each other, the conductor wires W1 to W4 are connected to at least two emitter pads 34 including the emitter pads 34 located at both ends of the IGBTs 3 except for the IGBTs 3 located at both ends. Is connected.

In the semiconductor device 111a, each IGB
In T3, some of the emitter pads 34 are connected to one of the conductor wires W1 to W4 and the wiring pattern 2
Some of the emitter pads 34 are connected to each other through their conductors between the IGBTs 3 connected in parallel as well as through any one of the IGBTs 3 and 6. Therefore, the effect of suppressing the oscillation of the IGBT 3 is as follows.
Obtained accordingly. In particular, a plurality of I
The wiring pattern 26 or 2 along the arrangement direction of the GBTs 3
7 can be kept small. This contributes to miniaturization of the semiconductor device 111a.

In the semiconductor device 111a, as in the case of the semiconductor devices 109 and 111, the conductor wires W1 to W1 of the plurality of emitter pads 34 of each IGBT 3 are provided.
It is more desirable that the ratio occupied by the emitter pad 34 to which any one of W4 is connected is 以上 or more. FIG.
In the example of 1, the ratio is set to 1/2.

Embodiment 12 FIG. FIG. 22 shows Embodiment 1.
2 is a plan sectional view of the semiconductor device according to FIG. The circuit diagram and the external perspective view of the semiconductor device 112 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 22 is a sectional view taken along the line XX when the semiconductor device 101 in FIG. Corresponds to a cross-sectional view taken along the line.

The wiring patterns 26 and 27 are not provided and are a part of the plurality of emitter pads 34 of each IGBT 3. Two or more (four in the example of FIG. 22) emitter pads 34 are The semiconductor device 112 is directly connected by any of W1 to W4.
Is characteristically different from the semiconductor device 109 according to the ninth embodiment. In the semiconductor device 112, similarly to the semiconductor device 109, a part (two or more) of the plurality of emitter pads 34 included in each IGBT 3 has a conductor that does not relay the wiring patterns 22 and 23 (that is, a conductor). , Or any of the conductor wires W1 to W4), the effect of suppressing oscillation when the IGBT 3 is short-circuited is obtained accordingly. Similarly to the semiconductor device 109 of the ninth embodiment, of the plurality of emitter pads 34 of each IGBT 3, the conductor wire W1
It is more preferable that the ratio occupied by the emitter pad 34 to which any one of W4 to W4 is occupied is 1/2 or more.

In the semiconductor device 112, the wiring pattern 2
Since the semiconductor device 112 and the semiconductor device 112 are not required, the manufacturing process is simplified, and the area of the substrate 2 is reduced.
Can be reduced in size. Further, the conductor wires W1 to W1
Since each of W4 is connected only to a part of the plurality of emitter pads 34 of each IGBT 3, even if the width of each emitter pad 34 is narrow, the conductor wires W1 to W
4 can be easily connected to the emitter pad 34.

Further, as shown in FIG. 22, the conductor wire W
Each of 1 to W4 is arranged along the direction in which the plurality of emitter pads 34 of each IGBT 3 are arranged. as a result,
The conductor wires W1 to W4 are substantially orthogonal to the conductor wire 15. Thereby, the inductive coupling between the conductor wire 15 and the conductor wires W1 to W4 is suppressed low, and the effect of suppressing oscillation is further enhanced.

Further, for each IGBT 3, the conductor wires W1 to W4 are connected to two or more emitter pads 34 at a portion farther from the wiring pattern 22 or 23 than one end of the conductor wire 15. For this reason, the inductive coupling between the conductor wire 15 and the conductor wires W1 to W4 is further reduced, and the effect of suppressing oscillation is further enhanced. Furthermore, the conductor wire 15 and the conductor wires W1 to W4 can be easily arranged without interfering with each other.

Although FIG. 22 shows an example in which two IGBTs 3 are connected in parallel, three or more IGBTs 3 may be connected in parallel. Further, each of upper arm 10 and lower arm 11 may include only a single IGBT 3.
In any case, since a part of the plurality of emitter pads 34 of each IGBT 3 is electrically connected to each other through a conductor that does not relay the wiring patterns 22 and 23, the effect of suppressing the oscillation of the IGBT 3 is correspondingly obtained. can get.

Embodiment 13 FIG. FIG. 23 shows Embodiment 1.
FIG. 3 is a plan sectional view of the semiconductor device according to No. 3; A circuit diagram and an external perspective view of the semiconductor device 113 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 23 is a sectional view taken along the line XX when the semiconductor device 101 in FIG. Corresponds to a cross-sectional view taken along the line.

The semiconductor device 1 is different in that all of the plurality of emitter pads 34 of each IGBT 3 are connected to one another by one of the conductor wires W1 to W4.
13 is characteristically different from the semiconductor device 112 according to the twelfth embodiment. Therefore, in the semiconductor device 113,
Oscillation of each IGBT 3 is more effectively suppressed.

Embodiment 14 FIG. FIG. 24 shows Embodiment 1
4 is a plan sectional view of the semiconductor device according to FIG. The circuit diagram and the external perspective view of the semiconductor device 114 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 24 is a sectional view taken along the line XX when the semiconductor device 101 in FIG. Corresponds to a cross-sectional view taken along the line.

All of the plurality of emitter pads 34 of each IGBT 3 are not only connected to each other by conductor wires W1 or W3, but are also connected in parallel to each other.
Even between two or more IGBTs 3 (two in the example of FIG. 25),
Semiconductor device 114 is characteristically different from semiconductor device 113 according to the thirteenth embodiment in that emitter pads 34 are connected to each other by conductor wires W1 or W3. Therefore, in the semiconductor device 114, each IGB
The effect of suppressing the oscillation of T3 is further enhanced as compared with the semiconductor device 113 of the thirteenth embodiment. In addition, since all the emitter pads 34 are arranged in one direction between two or more IGBTs 3 connected in parallel to each other, the conductor wires W1 and W3 can be easily arranged along the one direction. .

Embodiment 15 FIG. FIG. 25 shows Embodiment 1.
5 is a cross-sectional plan view of the semiconductor device of FIG. The circuit diagram and the external perspective view of this semiconductor device 115 are the same as those of FIGS. 1 and 2 of the first embodiment, and FIG. 25 is a sectional view taken along line XX when semiconductor device 101 of FIG. Corresponds to a cross-sectional view taken along the line.

A part of the plurality of emitter pads 34 of each IGBT 3 are not only connected by the conductor wire W1 or W3, but also two or more (two in the example of FIG. 25) IGBT 3 connected in parallel with each other. Also, the semiconductor device 115 is characteristically different from the semiconductor device 112 according to the twelfth embodiment in that the emitter pads 34 are connected to each other by the conductor wire W1 or W3. Therefore, the effect of suppressing the oscillation of each IGBT 3 is further enhanced as compared with the semiconductor device 112 of the twelfth embodiment.

Embodiment 16 FIG. FIG. 26 shows Embodiment 1
6 is a plan sectional view of the semiconductor device according to No. 6; A circuit diagram and an external perspective view of this semiconductor device 116 are the same as those in FIGS. 1 and 2 of the first embodiment, and FIG. 26 is a sectional view taken along line XX when semiconductor device 101 of FIG. Corresponds to a cross-sectional view taken along the line.

The semiconductor device 116 differs from the conventional semiconductor device 15 in that each of the plurality of emitter pads 34 of each IGBT 3 is connected to the wiring pattern 22 or 23 through only one conductor wire 15.
Characteristically different from 0. Therefore, the semiconductor device 1
Even when an excessive short-circuit current flows through each IGBT 3 due to short-circuiting of the load 16, the magnitude of the emitter current flowing through each IGBT 3 is limited by the resistance of the conductor wire 15. The oscillation phenomenon at the potential of is suppressed. In addition, each IGBT3
Are arranged along one direction, and the corresponding wiring patterns 22 or 23 extend along the one direction.
Can be easily arranged without interfering with each other.

Embodiment 17 FIG. FIG. 27 shows Embodiment 1
7 is a cross-sectional plan view of the semiconductor device of FIG. The circuit diagram and the external perspective view of this semiconductor device 117 are the same as those of FIGS. 1 and 2 of the first embodiment, and FIG. 27 is a sectional view taken along line XX when semiconductor device 101 of FIG. Corresponds to a cross-sectional view taken along the line.

Each conductor wire 1 connected to each IGBT 3
The semiconductor device 117 is characteristically different from the semiconductor device 116 according to the sixteenth embodiment in that an intermediate portion of the semiconductor device 117 is connected to the anode electrode of the corresponding diode 4. Therefore, in the semiconductor device 117, the corresponding I
There is no need to separately provide a conductor wire for connecting between the GBT 3 and the diode 4. That is, the number of conductor wires in the entire semiconductor device 117 is reduced,
The number of manufacturing steps and manufacturing costs can be reduced.

Modified example. (1) In each of the above embodiments, the semiconductor device is an IGBT3
However, the present invention provides a pair of main electrodes through which a main current (eg, an emitter current, a drain current, etc.) flows,
The present invention can be widely applied to a semiconductor device including a switching element having a control electrode for receiving a drive signal and controlling a main current in response thereto. The switching element may be, for example, a MOSFET or a bipolar transistor. In a general switching element, the gate wiring 32 is extended to a control electrode wiring, and a gate pad 33 is formed.
Is extended to the bonding pad of the control electrode, and the emitter pad 34 is extended to the bonding pad of the main electrode.

However, the semiconductor device 1 according to each embodiment
01 to 117 are insulated gate switching elements that can suppress oscillation and are easy to control despite using an IGBT3 that is an insulated gate switching element that originally tends to cause oscillation. By taking advantage of the above, the present invention can be widely used for application to an application device for controlling a large current. In the case of an insulated gate switching element, the necessity of protecting the gate insulating film is high, and the present invention is particularly useful in that sense.

(2) In general, the emitter electrodes (generally, main electrodes) of a plurality of IGBTs 3 (generally, a plurality of switching elements) are connected to each other via a wiring pattern 22 (or 23) through which an emitter current (generally, a main current) flows. If some kind of conductor is provided for electrical connection without the need for electrical connection, the uniformity of the potential of the emitter electrode (generally, the main electrode) can be improved, as in the case of the semiconductor devices 101 to 107, whereby the oscillation phenomenon Can be suppressed. In the semiconductor devices 101 and 102, the wiring pattern 26 (or 27) and the conductor wires W1, W2 (or W3, W
4) corresponds to a conductor, and in the semiconductor device 103, the conductor wire W5 (or W6) corresponds to a conductor.

[0147]

According to the device of the first invention, the other main electrodes of the plurality of switching elements connected in parallel to each other are:
Since they are electrically connected to each other through a conductor that does not relay the second wiring pattern, that is, a conductor through which the main current does not flow, the potential of the other main electrode is equalized among the plurality of switching elements. As a result, even when the loads of the plurality of switching elements are short-circuited, the oscillation phenomenon at the potential of the control electrode of the plurality of switching elements is suppressed.

In the device according to the second aspect of the invention, the electrical connection between the other main electrodes of the plurality of switching elements is easily realized through the third wiring pattern and the second conductor wire. In addition, since it is not necessary to perform wire cutting on the switching element in the step of arranging the second conductor wire, there is no need for a means for preventing damage to the switching element.

In the device according to the third aspect of the invention, the second and third wiring patterns are disposed on opposite sides of the plurality of switching elements, and extend along the arrangement direction of the plurality of switching elements. The first conductor wire and the second conductor wire
The conductor wires can be easily arranged without interfering with each other. Further, it is possible to reduce the inductive coupling between the first conductor wire and the second conductor wire, thereby increasing the effect of suppressing oscillation.

In the device according to the fourth aspect, since the third wiring pattern is adjacent to the plurality of switching elements without interposing other wiring patterns, it is possible to set the second conductor wire short. Thus, the inductance of the conductor electrically connecting the other main electrodes of the plurality of switching elements is reduced, so that the effect of equalizing the potentials of the other main electrodes can be enhanced.

In the device according to the fifth aspect of the present invention, since the third wiring pattern has a repetitive bent portion, the inductance of the conductor electrically connecting the other main electrodes of the plurality of switching elements is reduced to suppress oscillation. Can be adjusted to an optimum value.

In the device according to the sixth aspect of the present invention, the other main electrodes of the plurality of switching elements are directly connected to each other by the third conductor wire, so that the manufacturing process of the device is simplified and the device is downsized. Can be.

In the device according to the seventh aspect of the present invention, the first conductor wire and the third conductor wire are disposed so as to be substantially orthogonal to each other, so that the inductive coupling between them is suppressed low, thereby suppressing the oscillation. The effect is enhanced.

In the device according to the eighth aspect of the present invention, the third conductor wire is connected to the other main electrode of the plurality of switching elements at a portion farther from one end of the plurality of first conductor wires than the second wiring pattern. Inductive coupling between the first conductor wire and the third conductor wire is further reduced, and the effect of suppressing oscillation is further enhanced. Further, the first conductor wire and the third conductor wire can be easily arranged without interfering with each other.

In the device according to the ninth aspect, the voltage clamp element is interposed between the control electrodes of the plurality of switching elements and the third wiring pattern. The amplitude can be kept low.

In the device according to the tenth aspect of the present invention, since the voltage clamp element is interposed between the control electrodes of the plurality of switching elements and the other main electrode, the oscillation amplitude can be kept low.

In the device according to the eleventh aspect, the other main electrodes of the plurality of switching elements are electrically connected to each other through the third conductor wire and the other electrode of the diode without relaying the second wiring pattern. Thereby, the potential of the other main electrode is made uniform among the plurality of switching elements, so that the oscillation phenomenon at the potential of the control electrode is suppressed even when the load is short-circuited. Further, since the other end of the third conductor wire is connected to the second wiring pattern,
In the step of arranging the conductor wires, it is not necessary to perform wire cutting on the switching element and the diode. Therefore, it is not necessary to provide a means for preventing damage to the switching element and the diode during the manufacturing process.

In the device according to the twelfth aspect, the second wiring pattern extends along the arrangement direction of the plurality of switching elements, and has a connection portion at one end in the arrangement direction and a connection portion at the other end. It has a slit extending along the arrangement direction so as not to leave, and the other ends of the plurality of first conductor wires
The external terminal is connected to the connection portion on one end side, and another external terminal is connected to the other end side of the second portion. For this reason, when another external terminal is used as a terminal for applying the reference potential of the potential of the control electrode, the first
Due to the feedback effect caused by the inductance of the portion, a rapid increase in the main current is suppressed. As a result, the oscillation phenomenon of the potential of the control electrode is more effectively suppressed.

In the device according to the thirteenth aspect, the second wiring pattern extends along the arrangement direction of the plurality of switching elements, and has a connection portion at one end in the arrangement direction and a connection portion at the other end. It has a slit extending along the arrangement direction so as not to leave, and the other ends of the plurality of first conductor wires
The external terminal is connected to the connection portion on one end side, and another external terminal is connected to the other end side of the second portion. For this reason, when another external terminal is used as a terminal for applying the reference potential of the potential of the control electrode, the first
Due to the feedback effect caused by the inductance of the portion, a rapid increase in the main current is suppressed. As a result, the oscillation phenomenon of the potential of the control electrode is suppressed.

In the device according to the fourteenth aspect, the first part and the second part
Since a fifth conductor wire is provided for connecting the first and second portions to each other, the position of the fifth conductor wire is adjusted at the final stage of the manufacturing process of the device, so that the strength of the feedback action is finely uniform between individuals. Can be adjusted.

In the device according to the fifteenth aspect, the plurality of switching elements are insulated gate type switching elements which are liable to cause oscillation, but the oscillation is suppressed, so that the control is easy. By utilizing the advantage of the insulated gate type switching element, it can be widely used for application to an application device for controlling a large current.

In the device according to the sixteenth aspect, at least two of the plurality of bonding pads partitioned from each other are made of a conductor that does not relay the second wiring pattern, that is, a conductor through which the main current does not flow. Through two or more second conductor wires and a third wiring pattern,
Since they are electrically connected to each other, the potential is made uniform among the plurality of bonding pads. As a result, even when the load of the switching element is short-circuited, the oscillation phenomenon at the potential of the control electrode of the switching element is suppressed.

In the device according to the seventeenth aspect, since the switching element is divided into a plurality of unit switching elements having the same configuration, the current capacity can be increased while suppressing the size of the unit switching element. . In addition, two or more bonding pads of the plurality of bonding pads belonging to each unit switching element are connected to each other through two or more second conductor wires and the third wiring pattern, and the plurality of unit switching elements are connected to each other. Connections are made between them as well. Therefore, the oscillation of each unit switching element is effectively suppressed while increasing the current capacity.

In the device according to the eighteenth aspect, since one end of the second conductor wire is connected to all of the plurality of bonding pads, the effect of suppressing oscillation is further enhanced.

In the device according to the nineteenth aspect, bonding pads that are closest to each other between adjacent unit switching elements are electrically connected to each other through two or more second conductor wires and a third wiring pattern. Therefore, oscillation of each unit switching element is suppressed. Further, since the third wiring pattern can be set narrow, the size of the device can be reduced.

In the device according to the twentieth aspect, at least two of the plurality of bonding pads partitioned from each other are made of a conductor that does not relay the second wiring pattern, that is, a conductor through which a main current does not flow. Since the plurality of bonding pads are electrically connected to each other through a certain second conductive wire, the potential is equalized among the plurality of bonding pads. As a result, even when the load of the switching element is short-circuited, the oscillation phenomenon at the potential of the control electrode of the switching element is suppressed.

In the device according to the twenty-first aspect, since the switching element is divided into a plurality of unit switching elements having the same configuration, the current capacity can be increased while suppressing the size of the unit switching element. . In addition, two or more bonding pads among the plurality of bonding pads belonging to each unit switching element are connected through the second conductor wire, and the connection is similarly made between the plurality of unit switching elements. . Therefore, the oscillation of each unit switching element is effectively suppressed while increasing the current capacity.

In the device according to the twenty-second aspect, since the second conductor wire connects all of the plurality of bonding pads to each other, the effect of suppressing oscillation is further enhanced.

In the device according to the twenty-third aspect, each of the plurality of bonding pads partitioned from each other is connected to the first wiring pattern through only one of the plurality of first conductor wires. Therefore, even when the load of the switching element is short-circuited, the magnitude of the main current flowing through the switching element is limited by the resistance of the plurality of first conductor wires, so that the oscillation phenomenon at the potential of the control electrode is suppressed. .

In the device according to the twenty-fourth aspect, since the intermediate portion of the plurality of first conductor wires is connected to the other electrode of the diode, a conductor wire for connecting between the switching element and the diode is separately provided. No need to set up. That is, by reducing the number of conductor wires in the entire device,
The number of manufacturing steps and manufacturing costs can be reduced.

In the device according to the twenty-fifth aspect, the second and the third
Since the wiring patterns are arranged on opposite sides of the switching element and extend along the direction in which the plurality of bonding pads are arranged, the first conductor wires and the second conductor wires may interfere with each other. And can be easily arranged. Further, it is possible to reduce the inductive coupling between the first conductor wire and the second conductor wire, thereby increasing the effect of suppressing oscillation.

In the device according to the twenty-sixth aspect, since the third wiring pattern is adjacent to the switching element without interposing another wiring pattern, the second conductor wire can be set shorter. Thereby, the inductance of the conductor electrically connecting the plurality of bonding pads is reduced, so that the effect of equalizing the potential among the plurality of bonding pads can be enhanced.

In the device according to the twenty-seventh aspect, since the first conductor wire and the second conductor wire are disposed so as to be substantially orthogonal to each other, inductive coupling between them is suppressed low, thereby suppressing oscillation. The effect is enhanced.

In the device according to the twenty-eighth aspect, the third conductor wire is connected to the other main electrode of the switching element at a portion farther from one end of the plurality of first conductor wires than the second wiring pattern. Inductive coupling between the conductor wire and the third conductor wire is further reduced, and the effect of suppressing oscillation is further enhanced. Further, the first conductor wire and the third conductor wire can be easily arranged without interfering with each other.

In the device according to the twenty-ninth aspect, since the second wiring pattern extends along the direction in which the plurality of bonding pads are arranged, it is possible to easily arrange the plurality of first conductor wires without interfering with each other. Can be.

In the device according to the thirtieth aspect, since the switching element is an insulated gate type switching element which is liable to cause oscillation, the oscillation is suppressed, so that the control is easy. By utilizing the advantages of the switching element of the type, it can be widely used for application devices for controlling a large current.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a device according to a first embodiment.

FIG. 2 is an external perspective view of the device according to the first embodiment.

FIG. 3 is a plan sectional view of the device of the first embodiment.

FIG. 4 is a plan sectional view of the device according to the second embodiment.

FIG. 5 is a plan sectional view of an apparatus according to a third embodiment.

FIG. 6 is a plan sectional view of an apparatus according to a fourth embodiment.

FIG. 7 is a plan sectional view of an apparatus according to a fifth embodiment.

FIG. 8 is a circuit diagram of a part of the device according to the fifth embodiment.

FIG. 9 is a plan sectional view of an apparatus according to a sixth embodiment.

FIG. 10 is a schematic diagram of a part of the device according to the sixth embodiment.

FIG. 11 is a circuit diagram of a part of the device according to the sixth embodiment.

FIG. 12 is a plan sectional view of an apparatus according to a seventh embodiment.

FIG. 13 is a schematic view of a part of the device according to the seventh embodiment.

FIG. 14 is a schematic view of a part of the device according to the seventh embodiment.

FIG. 15 is a circuit diagram of a part of the device according to the seventh embodiment.

FIG. 16 is a plan view of the IGBT of each embodiment.

FIG. 17 is a plan sectional view of the device according to the eighth embodiment.

FIG. 18 is a plan sectional view of the device of the ninth embodiment.

FIG. 19 is a plan sectional view of the device of the tenth embodiment.

FIG. 20 is a plan sectional view of the device of the eleventh embodiment.

FIG. 21 is a plan sectional view of a device according to another example of the eleventh embodiment.

FIG. 22 is a plan sectional view of the device of the twelfth embodiment.

FIG. 23 is a plan sectional view of the device of the thirteenth embodiment.

FIG. 24 is a plan sectional view of the device of the fourteenth embodiment.

FIG. 25 is a plan sectional view of the device of the fifteenth embodiment.

FIG. 26 is a plan sectional view of the device of the sixteenth embodiment.

FIG. 27 is a plan sectional view of the device of the seventeenth embodiment.

FIG. 28 is a plan sectional view of a conventional device.

[Explanation of symbols]

2 substrate, 3 IGBT (switching element), 4 diode, 15 conductor wire (first conductor wire), 17
Conductor wire (fourth conductor wire), 21 wiring pattern (first wiring pattern), 22 wiring pattern (first wiring pattern, second wiring pattern), 23 wiring pattern (second wiring pattern), 23a first portion, 23b Second part, 24, 25 wiring pattern (fourth wiring pattern), 26, 27 wiring pattern (third wiring pattern), 30 voltage clamp element, 32 gate wiring (control electrode wiring), 34 emitter pad (bonding pad), 40, 41 slit, 50, 51 conductor wire (fifth conductor wire), EE, OUT external terminal, S
1, S2 external terminal, W1 to W4 conductor wire (second conductor wire), W5 to W10 conductor wire (third conductor wire).

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Hideo Matsumoto 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation F-term (reference) 5H007 CA01 HA03 HA04 5H740 BA11 MM10 PP03

Claims (30)

[Claims] A substrate having a main surface; a first wiring pattern disposed on the main surface; and a first wiring pattern disposed on the first wiring pattern, whereby one main electrode is electrically connected to each other. A plurality of switching elements connected to the second wiring pattern disposed on the main surface; one end connected to the other main electrode of the plurality of switching elements, and the other end connected to the second wiring pattern. A plurality of connected first conductor wires, an external terminal connected to the second wiring pattern, and electrically connecting the other main electrode and the outside of the plurality of switching elements through the second wiring pattern; A conductor that electrically connects the other main electrodes of the plurality of switching elements without relaying the second wiring pattern. 2. One end of the conductor is connected to a third wiring pattern disposed on the main surface, isolated from the second wiring pattern, and the other main electrode of the plurality of switching elements. 2. The semiconductor device according to claim 1, further comprising: a plurality of second conductor wires having the other end connected to the third wiring pattern. 3. The second wiring pattern extends along a direction in which the plurality of switching elements are arranged, and the third wiring pattern and the second wiring pattern sandwich the plurality of switching elements. Extends on the opposite side along the arrangement direction of the plurality of switching elements,
The semiconductor device according to claim 2. 4. The semiconductor device according to claim 3, wherein said third wiring pattern is adjacent to said plurality of switching elements without interposing another wiring pattern. 5. The semiconductor device according to claim 2, wherein said third wiring pattern has a repeated bent portion. 6. The semiconductor device according to claim 1, wherein said conductor includes a third conductor wire directly connecting said other main electrodes of said plurality of switching elements. 7. The second wiring pattern extends along an arrangement direction of the plurality of switching elements, and the plurality of first conductor wires are arranged in a direction substantially perpendicular to the arrangement direction. The semiconductor device according to claim 6, wherein the third conductor wire is disposed along the arrangement direction. 8. The plurality of first conductor wires are connected to the plurality of first conductor wires.
8. The semiconductor device according to claim 7, wherein a portion of the conductor wire farther from the second wiring pattern than the one end is connected to the other main electrode of the plurality of switching elements. 9. 9. A plurality of fourth wiring patterns each having one end connected to a fourth wiring pattern disposed on the main surface and control electrodes of the plurality of switching elements, and having the other end connected to the fourth wiring pattern. 6. The semiconductor according to claim 2, further comprising: a four-conductor wire; and a voltage clamp element having one end connected to the third wiring pattern and the other end connected to the four wiring patterns. 7. apparatus. 10. A substrate having a main surface, a first wiring pattern disposed on the main surface, and one of the main electrodes electrically connected to each other by being disposed on the first wiring pattern. A plurality of switching elements connected to the second wiring pattern disposed on the main surface; one end connected to the other main electrode of the plurality of switching elements, and the other end connected to the second wiring pattern. A plurality of connected first conductor wires, an external terminal connected to the second wiring pattern, and electrically connecting the other main electrode and the outside of the plurality of switching elements through the second wiring pattern; A semiconductor device comprising: a voltage clamp element electrically connected between control electrodes of the plurality of switching elements and the other main electrode. 11. A substrate having a main surface, a first wiring pattern disposed on the main surface, and being disposed on the first wiring pattern, one main electrode is electrically connected to each other. A plurality of switching elements connected to the plurality of switching elements; a second wiring pattern disposed on the main surface so as to extend along an arrangement direction of the plurality of switching elements; A plurality of first conductor wires each having one end connected to an electrode and the other end connected to the second wiring pattern; and connecting the other main electrode of the plurality of switching elements to the outside connected to the second wiring pattern. External terminals electrically connected through the second wiring pattern, and the same number of switching elements as the plurality of switching elements are arranged on the first wiring pattern, whereby one electrode is connected to each other. A plurality of diodes electrically connected to each other and arranged between the plurality of switching elements and the second wiring pattern so as to be adjacent to the plurality of switching elements in a one-to-one relationship; A plurality of second conductor wires, one ends of which are connected to the other electrodes of the plurality of switching elements, and one ends of which are connected to the other main electrodes of the plurality of switching elements; An intermediate portion is connected to at least a part of the other electrode, and the other end is connected to the second wiring pattern, so that all the other main electrodes of the plurality of switching elements are connected to the second wiring pattern. A plurality of third conductor wires that are electrically connected without being relayed. 12. The second wiring pattern extends along the direction in which the plurality of switching elements are arranged, and the second wiring pattern has a connecting portion left at one end in the arrangement direction. A slit extending along the arrangement direction is formed so as not to leave a connection portion on a side, and the other ends of the plurality of first conductor wires are closer to the plurality of switching elements than the slits. One part is connected to the second wiring pattern, the external terminal is connected to the second wiring pattern at the connection part on the one end side, and the semiconductor device is more than the slit. The other end of the second portion far from the switching element is connected to the second wiring pattern, and the other main electrodes of the plurality of switching elements and the outside are connected to the second wiring pattern. Another external terminal electrically connected via pattern, further comprising Claim 1
The semiconductor device according to claim 11. 13. A substrate having a main surface, a first wiring pattern disposed on the main surface, and being disposed on the first wiring pattern, one main electrode is electrically connected to each other. A plurality of switching elements connected to the plurality of switching elements, disposed on the main surface so as to extend along the arrangement direction of the plurality of switching elements, the other end side leaving a connecting portion at one end side in the arrangement direction A second wiring pattern in which a slit extending along the arrangement direction is formed so as not to leave a connection portion, and one end is connected to the other main electrode of the plurality of switching elements, and A plurality of first conductor wires, the other ends of which are connected to the second wiring pattern in a first portion close to the switching element; and the connection portion on the one end side is connected to the second wiring pattern, An external terminal for electrically connecting the other main electrode of the number of switching elements to the outside through the second wiring pattern; and the other end side in a second portion farther from the plurality of switching elements than the slit. And a further external terminal connected to the second wiring pattern and electrically connecting the other main electrodes of the plurality of switching elements to the outside through the second wiring pattern. 14. The semiconductor device according to claim 12, further comprising a fifth conductor wire having one end connected to said first portion and the other end connected to said second portion. 15. The switching element according to claim 1, wherein each of the plurality of switching elements is an insulated gate switching element.
The semiconductor device according to claim 14. 16. A substrate having a main surface, a first wiring pattern disposed on the main surface, and one main electrode disposed on the first wiring pattern so that one main electrode is provided in the first wiring pattern. A switching element having a plurality of bonding pads electrically connected to the other main electrode and separated by control electrode wiring, a second wiring pattern disposed on the main surface, and a plurality of bonding pads. A plurality of first conductor wires, one ends of which are connected to each other and the other end of which is connected to the second wiring pattern; and the other main electrode of the switching element and the outside which are connected to the second wiring pattern and which are connected to the second wiring pattern. An external terminal electrically connected through a wiring pattern, a third wiring pattern provided on the main surface in isolation from the second wiring pattern, and a plurality of bonding pads. Semiconductor device provided is connected to one end to the two or more bonding pads, and the third two or more second conductor wire and the other end to the wiring pattern is connected, the. 17. The switching element is divided into a plurality of unit switching elements having the same configuration, and each of the plurality of unit switching elements has at least two of the plurality of bonding pads. The one ends of the two or more second conductor wires are connected to two or more bonding pads of the at least two bonding pads for each of the plurality of unit switching elements. The semiconductor device according to claim 16. 18. The semiconductor device according to claim 16, wherein said one ends of said two or more second conductor wires are connected to all of said plurality of bonding pads. 19. The semiconductor device according to claim 19, wherein the plurality of bonding pads are arranged in one direction, and the switching element is divided into a plurality of unit switching elements having the same configuration as each other, and is arranged along the one direction. Each of the plurality of unit switching elements has at least two of the plurality of bonding pads, and the one end of the two or more second conductor wires is connected to one of the plurality of unit switching elements. 17. The semiconductor device according to claim 16, wherein each of the semiconductor devices is connected to at least one bonding pad occupying a position closest to a unit switching element located next to itself. 20. A substrate having a main surface, a first wiring pattern provided on the main surface, and one main electrode arranged on the first wiring pattern so that one main electrode is provided in the first wiring pattern. A switching element having a plurality of bonding pads electrically connected to the other main electrode and separated by control electrode wiring, a second wiring pattern disposed on the main surface, and a plurality of bonding pads. A plurality of first conductor wires, one ends of which are connected to each other and the other end of which is connected to the second wiring pattern; and the other main electrode of the switching element and the outside which are connected to the second wiring pattern and which are connected to the second wiring pattern. An external terminal electrically connected through a wiring pattern; and a second conductor wire connecting two or more bonding pads of the plurality of bonding pads to each other. Semiconductor device. 21. The switching element is divided into a plurality of unit switching elements having the same configuration, and each of the plurality of unit switching elements has at least two of the plurality of bonding pads. The second conductive wire connects two or more bonding pads of the at least two bonding pads to each other for each of the plurality of unit switching elements, and the plurality of unit switching elements. 21. The semiconductor device according to claim 20, wherein the bonding pads belonging to each of the semiconductor devices are connected to each other. 22. The second conductive wire connects all of the plurality of bonding pads to one another.
22. The semiconductor device according to claim 21. 23. A substrate having a main surface, a first wiring pattern provided on the main surface, and one main electrode provided on the first wiring pattern so that one main electrode is provided in the first wiring pattern. A switching element having a plurality of bonding pads electrically connected to the other main electrode and separated by control electrode wiring; a second wiring pattern provided on the main surface; and the plurality of bonding pads. One end is connected to the plurality of bonding pads in one-to-one correspondence.
A plurality of first conductor wires, the other ends of which are connected to a wiring pattern; and a plurality of first conductor wires, which are connected to the second wiring pattern, and electrically connect the other main electrode of the switching element to the outside through the second wiring pattern. A semiconductor device, comprising: an external terminal; wherein the plurality of bonding pads and the second wiring pattern are connected only by the plurality of first conductor wires. 24. An electrode disposed on the first wiring pattern, whereby one electrode is electrically connected to the one main electrode of the switching element, and between the switching element and the second wiring pattern. 24. The semiconductor device according to claim 23, further comprising a diode disposed, wherein an intermediate portion of the plurality of first conductor wires is connected to the other electrode of the diode. 25. The plurality of bonding pads are arranged along one direction, the second wiring pattern extends along the one direction, and the third wiring pattern is connected to the switching element. 19. The semiconductor device according to claim 16, wherein the second wiring pattern extends along the one direction on a side opposite to the second wiring pattern.
The semiconductor device according to any one of the above. 26. The semiconductor device according to claim 25, wherein the third wiring pattern is adjacent to the switching element without sandwiching another wiring pattern. 27. The semiconductor device according to claim 27, wherein the plurality of bonding pads are arranged along one direction, the second wiring pattern extends along the one direction, and the plurality of first conductor wires are arranged along the one direction. 23. The semiconductor device according to claim 20, wherein the semiconductor device is disposed in a direction substantially orthogonal to the direction, and the second conductor wire is disposed along the one direction. 28. The switching device according to claim 28, wherein the second conductor wire is connected to the other main electrode of the switching element at a portion farther from the second wiring pattern than the one end of the plurality of first conductor wires. 28. The semiconductor device according to 27. 29. The method according to claim 23, wherein the plurality of bonding pads are arranged along one direction, and the second wiring pattern extends along the one direction. Semiconductor device. 30. The semiconductor device according to claim 16, wherein said switching element is an insulated gate switching element.