JP2002076247A - Stacked semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem that conventionally a stacked semiconductor device may have connection reliability lowered, because semiconductor chips are aligned by fitting protrusions and recessed provided in via pads or through infrared recognition. SOLUTION: The center of the second dummy via 13 in a second semiconductor chip 4 is arranged, to correspond to the center of the first dummy via 12 in a first semiconductor chip 2, and center of the third dummy via 14 in a third semiconductor chip 7 is arranged to correspond to the center of the first dummy via 12 in the first semiconductor chip 2 and center of the second dummy via 13 in the second semiconductor chip 4, and the chips are stacked with high positional accuracy. Therefore, a stacked semiconductor device, where connection reliability of respective semiconductor chips is enhanced, can be realized.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stacked semiconductor device in which a plurality of semiconductor chips are stacked and mounted in a three-dimensional direction, and a method of manufacturing the same. In particular, the stacked semiconductor chips are accurately aligned. The present invention relates to a stacked semiconductor device having high connection reliability and a method for manufacturing the same.

[0002]

2. Description of the Related Art Conventionally, in a stacked semiconductor device in which a plurality of semiconductor chips are stacked in a three-dimensional direction, electrodes provided on each semiconductor chip are electrically connected to each other by through vias on the front and back surfaces thereof. It was.

FIG. 6 is a view showing the structure of a conventional stacked semiconductor device, FIG. 6 (a) is a plan view, and FIG. 6 (b) is a view showing the main parts A-A1 in FIG. 6 (a). It is sectional drawing. In FIG. 6A, the illustration of the via pad is omitted.

As shown in FIG. 6, a conventional stacked semiconductor device has a first electrode pad formed on its main surface and a first through hole for signal connection formed on the first electrode pad. A first semiconductor chip 2 having a via 1, a second electrode pad formed on the main surface thereof, and a second through via 3 for signal connection formed on the second electrode pad; A second semiconductor chip 4 having the following structure, a third electrode pad 5 formed on the main surface thereof, and a third through via 6 for signal connection formed on the third electrode pad 5. The second semiconductor chip 4 is mounted on the first semiconductor chip 2, and the third semiconductor chip 7 is mounted on the second semiconductor chip 4. This constitutes a stacked semiconductor device having an original structure.

The via pad 8a on the surface of the first through via 1 of the first semiconductor chip 2 and the second semiconductor chip 4
Is connected to the via pad 9b on the back surface of the second through via 3, and the via pad 9a on the surface of the second through via 3 of the second semiconductor chip 4 and the third through via 6 of the third semiconductor chip 7 are connected. Is connected to the via pad 10b on the back surface of the semiconductor chip, and the semiconductor chips are electrically connected to each other by vias for signal connection. 10a is a via pad on the surface of the third through via 6 of the third semiconductor chip 7. The connection between the via pad of each semiconductor chip and the via pad is made by a conductive material 11 such as solder. Although not shown, the space between the semiconductor chips may be filled with a sealing resin.

In the conventional stacked semiconductor device, the first, second, and third through vias 1, 3, and 6 each have a conductive material formed on the inner wall thereof to electrically connect the electrodes on the front surface and the back surface of the semiconductor chip. Is connected to In addition to the through via, there may be a filled via filled with a conductive material. The first semiconductor chip 2, the second semiconductor chip 4, and the third semiconductor chip 7 are each a semiconductor integrated circuit chip.

In the conventional stacked semiconductor device, the via pad 8b on the back surface of the first through via 1 of the first semiconductor chip 2 becomes an external electrode when mounted on a substrate, and is secondarily mounted by connecting to the substrate electrode. Things.

Further, in the manufacture of the conventional stacked semiconductor device, the alignment at the time of connecting the respective semiconductor chips is performed as follows.
Irregularities corresponding to the via pads of the through vias of each semiconductor chip are formed, and the concave and convex shapes are connected by alignment by fitting. For example, the via pad 8a of the first through via 1 of the first semiconductor chip 2 has a convex shape,
The via pads 9b of the second through vias 3 of the second semiconductor chip 4 stacked and mounted thereon are connected to each other by forming the via pads 9b into a concave shape and fitting each other with a convex shape. As another means, a wiring on a semiconductor chip is transparently recognized by infrared rays, and a through via to be connected to each semiconductor chip is aligned and connected based on the recognition data.

[0009]

However, in the above-mentioned conventional stacked semiconductor device, the positioning of the semiconductor chips at the time of stacking and mounting is performed by fitting the unevenness of the via pads into each other. Dedicated design and processing are required, and there is a risk of complicating the design of the semiconductor chip. Further, in the manufacturing process, there is a possibility that the reliability of the connection may be reduced due to the physical alignment, which is the alignment by fitting the uneven shape between the via pads. In addition, alignment by infrared transmission has a problem that the equipment cost for alignment increases.

It is an object of the present invention to provide a stacked semiconductor device and a method of manufacturing the same in which the positioning of each semiconductor chip when stacked and mounted is easy and high accuracy, and the connection reliability is improved. It is an object of the present invention to provide a stacked semiconductor device and a method for manufacturing the same, in which the position of each semiconductor chip is reliably recognized and aligned by a dummy via provided in a stacked state, and complicated chip design and the like are not required.

[0011]

In order to solve the above-mentioned conventional problems, a stacked semiconductor device according to the present invention comprises a first electrode pad formed on a main surface thereof and a first electrode pad formed on the first electrode pad. A first semiconductor chip having a first via for signal connection formed in the vicinity thereof, a second electrode pad formed on a main surface thereof, and on or in the vicinity of the second electrode pad A second semiconductor chip having a second via for signal connection formed in the first semiconductor chip, and a third semiconductor chip formed on the main surface of the second semiconductor chip.
A third electrode pad, and a third via for signal connection formed on or near the third electrode pad.
Wherein the second semiconductor chip is mounted on the first semiconductor chip, and the third semiconductor chip is mounted on the second semiconductor chip. , The first semiconductor chip, the second
The semiconductor chip and the third semiconductor chip respectively have a first dummy via, a second dummy via, and a third dummy via, and the center of the first dummy via of the first semiconductor chip has the second semiconductor chip. The center of the second dummy via is arranged correspondingly, and the center of the first dummy via of the first semiconductor chip and the second center of the second semiconductor chip are further arranged.
Is a stacked semiconductor device in which the center of the third dummy via of the third semiconductor chip is arranged corresponding to the center of the dummy via.

More specifically, there is provided a stacked semiconductor device in which the diameter of the second dummy via is larger than the diameter of the first dummy via, and the diameter of the third dummy via is larger than the diameter of the second dummy via.

The first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are stacked semiconductor devices, each being the same semiconductor chip.

Further, the first dummy via, the second dummy via, and the third dummy via are filled with a fixing material, and the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are fixed by the fixing material. Is a stacked semiconductor device.

As described above, in the stacked semiconductor device of the present invention, the center of the second dummy via of the second semiconductor chip is arranged corresponding to the center of the first dummy via of the first semiconductor chip. Since the center of the third dummy via of the third semiconductor chip is arranged corresponding to the center of the first dummy via of the first semiconductor chip and the center of the second dummy via of the second semiconductor chip, the positional accuracy is improved. It is possible to realize a stacked semiconductor device that is well stacked and has improved reliability of connection between semiconductor chips in chip stacking.

Further, according to the method of manufacturing a stacked semiconductor device of the present invention, a first electrode pad formed on a main surface thereof and a first electrode pad formed on or near the first electrode pad for signal connection are formed. A first semiconductor chip having one via and a first dummy via having a first diameter formed on the main surface thereof has a second electrode pad formed on the main surface thereof. A second via for signal connection formed on or near the second electrode pad, and a second dummy via of a second diameter formed on the main surface thereof. Stacking semiconductor chips, recognizing the position of the first dummy via from the second dummy via, aligning the center of the first dummy via with the center of the second dummy via, Connection between the first via and the second via And a third electrode pad formed on the main surface of the second semiconductor chip, and a third via for signal connection formed on or near the third electrode pad. A third semiconductor chip having a third dummy via having a third diameter formed on the main surface thereof, and stacking the first dummy via and the second below the third dummy via under the third dummy via. While recognizing the position of the dummy via, the first dummy via is located at the center of the third dummy via.
And aligning the centers of the dummy vias and the second dummy vias to connect the second vias to the third vias. This is a method of manufacturing a stacked semiconductor device in which dummy vias always located below are sequentially recognized and aligned.

More specifically, a method of manufacturing a stacked semiconductor device in which the diameter of the second dummy via is larger than the diameter of the first dummy via and the diameter of the third dummy via is larger than the diameter of the second dummy via. It is.

Further, the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are each a method of manufacturing a stacked semiconductor device in which the same semiconductor chip is used.

Further, the first dummy via, the second dummy via, and the third dummy via are filled with a fixing material, and the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are fixed with the fixing material. This is a method of manufacturing a stacked semiconductor device further including a step.

As described above, in the method of manufacturing a stacked semiconductor device according to the present invention, the semiconductor chips to be stacked are provided with positioning dummy vias in addition to the signal connection vias, so that the center position of each dummy via is provided. Can be stacked with high positional accuracy, so that a stacked semiconductor device with high reliability of connection between the semiconductor chips can be obtained. In other words, for one semiconductor chip, the diameter of the dummy via of the semiconductor chip stacked and mounted thereon is larger than the diameter of the dummy via of the lower semiconductor chip. In some cases, the alignment accuracy is improved by always recognizing the dummy vias below, and the reliability of the connection between the semiconductor chips can be improved. In addition, by filling the dummy vias with a fixing material after lamination of the semiconductor chips, the semiconductor chips can be securely fixed and the connection stability between signal connection vias can be improved.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of a stacked semiconductor device according to the present invention and a method for manufacturing the same will be described with reference to the drawings.

First, the stacked semiconductor device of this embodiment will be described. 1A and 1B are views showing a stacked semiconductor device according to the present embodiment, FIG. 1A is a plan view, and FIG. 1B is a cross-sectional view taken along a line BB of FIG. 1A. FIG. 1
In (a), illustration of via pads is omitted.

As shown in FIG. 1, the stacked semiconductor device of this embodiment has a first electrode pad formed on its main surface and a signal formed on or near the first electrode pad. A first semiconductor chip 2 having a first through via 1 for connection, a second electrode pad formed on the main surface thereof, and formed on or near the second electrode pad. A second semiconductor chip 4 having a second through via 3 for signal connection, a third electrode pad 5 formed on the main surface thereof, and a third electrode pad 5 on or near the third electrode pad 5 A third semiconductor chip 7 having the formed third through via 6 for signal connection;
A second semiconductor chip 4 is mounted thereon, and a third semiconductor chip 7 is mounted on the second semiconductor chip 4 to constitute a three-dimensional stacked semiconductor device.

The via pad 8a on the surface of the first through via 1 of the first semiconductor chip 2 and the second semiconductor chip 4
Is connected to the via pad 9b on the back surface of the second through via 3, and the via pad 9a on the surface of the second through via 3 of the second semiconductor chip 4 and the third through via 6 of the third semiconductor chip 7 are connected. Is connected to the via pad 10b on the back surface of the semiconductor chip, and the semiconductor chips are electrically connected to each other by vias for signal connection. The connection between the via pad of each semiconductor chip and the via pad is made by a conductive material 11 such as solder or conductive adhesive, but the via pads may be connected by metal bonding. 10a is the third through via 6 of the third semiconductor chip 7.
Via pad on the surface. The first, second, and third through vias 1, 3, and 6 each have a conductive material formed on the inner wall thereof, and electrically connect the electrode on the front surface of the semiconductor chip to the back surface in the chip. . In addition, a filled via filled with a conductive material other than the through via may be used.

Although not shown in the present embodiment,
A sealing resin may be filled between the semiconductor chips to increase confidentiality, or a heat-radiating sealing resin may be filled to take measures against heat radiation.

In the stacked semiconductor device of the present embodiment, the via pad 8b on the back surface of the first through via 1 of the first semiconductor chip 2 becomes an external electrode when the substrate is mounted on a substrate, and is connected to the substrate electrode. The following will be implemented.

Here, the stacked semiconductor device of this embodiment is
Each semiconductor chip has penetrated dummy vias around the chip,
For example, it is provided at each corner.

FIG. 2 is a sectional view taken along the line C--C1 in FIG.

As shown in FIG. 2, the stacked semiconductor device of the present embodiment has a first semiconductor chip 2, a second semiconductor chip 4, and a third semiconductor chip having a different configuration from a through via for signal connection. 7 has a first dummy via 12, a second dummy via 13, and a third dummy via 14 at each corner portion of each semiconductor chip, respectively. The center of the second dummy via 13 of the second semiconductor chip 4 is arranged corresponding to the center, and the center of the third dummy via 14 of the third semiconductor chip 7 is further arranged thereon. They are stacked with high positional accuracy. In the present embodiment, the diameter of the second dummy via 13 is larger than the diameter of the first dummy via 12, and the diameter of the third dummy via 14 is larger than the diameter of the second dummy via 13.

With this configuration, when the second semiconductor chip 4 is stacked on the first semiconductor chip 2, the first semiconductor chip 2 located below the second dummy via 13 of the second semiconductor chip 4. The first dummy via 12 is recognized and aligned, and the third dummy via 12
When the semiconductor chips 7 are stacked, the third semiconductor chip 7
By recognizing and aligning the first dummy via 12 of the first semiconductor chip 2 and the second dummy via 13 of the second semiconductor chip 4 located therebelow from the third dummy via 14, the three The semiconductor chips can be aligned with extremely high positional accuracy, and the reliability of connection between the semiconductor chips in chip stacking can be improved.

That is, in the stacked semiconductor device of the present embodiment, the diameter of the dummy via of the semiconductor chip stacked and mounted on one semiconductor chip is larger than the diameter of the dummy via of the lower semiconductor chip. When the alignment is performed when stacking the semiconductor chips, the alignment accuracy is improved by always recognizing the lower dummy vias sequentially, and the reliability of the connection between the semiconductor chips can be improved. . In the present embodiment, the number of semiconductor chips is three. However, the number of semiconductor chips to be stacked may be four or more since the dummy vias below are always recognized at the time of alignment. .

In this embodiment, as shown in FIG.
The first, second, and third dummy vias 12, 13, and 14 are the first
The semiconductor chip 2, the second semiconductor chip 4, and the third semiconductor chip 7 constitute an alignment portion when the semiconductor chips are stacked, and after the semiconductor chips are aligned and stacked and mounted, dummy vias are formed. The semiconductor chips are fixed with each other by filling a fixing material 15 such as a sealing resin or an adhesive. With this structure, the connection reliability of the stacked semiconductor chip can be further improved. In particular, by fixing the semiconductor chips at each corner of the semiconductor chip, the stability of connection between the through vias for signal connection can be improved. After the semiconductor chips are stacked and mounted, a sealing resin may be injected into the gaps between the semiconductor chips from the dummy vias to fix the chips.

In the stacked semiconductor device of the present embodiment, the first semiconductor chip 2, the second semiconductor chip 4, and the third semiconductor chip 7 are semiconductor integrated circuit chips, respectively. , The second semiconductor chip 4 and the third semiconductor chip 7 are preferably the same type and the same size. This is because only by changing the diameter size of the dummy via provided in each semiconductor chip, when stacking the semiconductor chips, the through vias for signal connection can be accurately connected by aligning the dummy vias. It is. Alternatively, when the first semiconductor chip 2, the second semiconductor chip 4, and the third semiconductor chip 7 are of different sizes, the arrangement of the electrode pads and the through vias of the semiconductor chip is set in accordance with the dummy vias, and each dummy via is set. By simply performing the above positioning, the through vias of the respective semiconductor chips are designed to be aligned, and the through vias for signal connection can be accurately connected by the alignment between the dummy vias.

Next, a method of manufacturing the stacked semiconductor device of the present embodiment will be described. FIG. 3 is a plan view showing the method for manufacturing the stacked semiconductor device of the present embodiment, showing a state after the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are stacked, respectively. FIG. 11 is a plan view showing a state where a third semiconductor chip is aligned. FIG. 4 is a plan view illustrating the method for manufacturing the stacked semiconductor device of the present embodiment, and is an enlarged plan view of one dummy via portion in a state where the semiconductor chips are aligned.

As shown in FIGS. 3 and 4, a third dummy via 14 is provided at each corner of the third semiconductor chip 7, and the third dummy via 14 is stacked thereunder. The second dummy via 1 of the second semiconductor chip
Since the diameter of the third dummy via 14 is larger than that of the third dummy via 14,
Can recognize the second dummy via 13. Further, since the second dummy via 13 has a larger diameter than the first dummy via 12 of the first semiconductor chip stacked thereunder, the first dummy via 12 can be recognized from the second dummy via 13. As a result, the centers of the second dummy via 13 and the third dummy via 14 can be aligned with respect to the first dummy via 12.

That is, the second dummy via 13 of the second semiconductor chip is aligned with the first dummy via 12 of the first semiconductor chip with high center accuracy, and the third
By aligning the third dummy vias 14 of the semiconductor chip with the first dummy vias 12 of the first semiconductor chip and the second dummy vias 13 of the second semiconductor chip with good center accuracy, all the semiconductor chips are It is possible to match each other with high positional accuracy.

A method for manufacturing the stacked semiconductor device of this embodiment using the above-described positioning means using dummy vias will be described with reference to FIG.

First, as shown in FIG. 5 (a), a first electrode pad formed on the main surface and a first signal connection formed on or near the first electrode pad are formed. A first semiconductor chip 2 having a through via 1 and a first dummy via 12 having a first diameter formed at each corner on the main surface is formed on the main surface. Second
Electrode pad, a second through via 3 for signal connection formed on or near the second electrode pad, and a second diameter size second via formed at each corner on the main surface. The second semiconductor chip 4 having two dummy vias 13 is stacked, and the second dummy via 13 is connected to the first dummy via 1.
2 and the center of the first dummy via 12 is aligned with the center of the second dummy via 13 to align the first through via 1 and the second through via 3 with the conductive material 11. And metal connection between via pads.

Next, as shown in FIG. 5B, with respect to the second semiconductor chip 4, a third electrode pad formed on the main surface thereof and on or near the third electrode pad are formed. A third semiconductor chip 7 having a third through via 6 for signal connection formed in the above and a third dummy via 14 having a third diameter formed in each corner on the main surface of the third semiconductor chip 7 The first dummy via 12 and the second dummy via 13 are located at the center of the third dummy via 14 while the positions of the first dummy via 12 and the second dummy via 13 below the third dummy via 14 are recognized. By aligning and aligning the centers and connecting the second through vias 3 and the third through vias 6 in the same manner as described above, the dummy vias that are always lower when the semiconductor chips are stacked are aligned. Sequentially recognize the position The Align accuracy is improved, in which it is possible to obtain a stacked semiconductor device with improved reliability of the connection between the semiconductor chips.

Of course, as described above, the first dummy via 12
The second diameter size of the second dummy via 13 is larger than the first diameter size, and the third diameter size of the third dummy via 14 is larger than the second diameter size of the second dummy via 13. The ratios are 10 [%] or more, preferably about 20 [%]. In the present embodiment, the first dummy via 12 is 2
0 [μmφ], the second dummy via 13 is 25 [μm
φ], and the third dummy via 14 is 30 [μmφ].

After the first, second, and third semiconductor chips 2, 4, and 7 are stacked, the first, second, and third dummy vias 12, 13, and 14 are filled with a fixing material to connect the dummy vias. May be connected to fix each semiconductor chip.

When connecting the semiconductor chips, the first dummy via 12 or the third dummy via 14 may be connected between the semiconductor chips after the sealing resin is interposed, or after the connection between the semiconductor chips. May be used to fill the space between the semiconductor chips with the sealing resin.

As described above, in the stacked semiconductor device and the method of manufacturing the same according to the present embodiment, dummy corner vias for positioning are provided separately from vias for signal connection at each corner of the semiconductor chips to be stacked, so that positional accuracy is improved. It is possible to obtain a stacked semiconductor device which is stacked and has high connection reliability between the semiconductor chips. In addition, by filling the dummy vias with a fixing material after lamination of the semiconductor chips, the semiconductor chips can be securely fixed and the connection stability between signal connection vias can be improved.

[0044]

As described above, in the stacked semiconductor device of the present invention, the center of the first dummy via of the first semiconductor chip corresponds to the center of the second dummy via of the second semiconductor chip. The third semiconductor chip is located at the center of the first dummy via of the first semiconductor chip and the center of the second dummy via of the second semiconductor chip.
Since the centers of the dummy vias are arranged corresponding to each other, it is possible to realize a stacked semiconductor device in which the semiconductor chips are stacked with high positional accuracy and the connection reliability between the semiconductor chips in chip stacking is improved.

In the method of manufacturing a stacked semiconductor device according to the present invention, the diameter of the dummy via of the semiconductor chip stacked on one semiconductor chip is larger than that of the dummy via of the lower semiconductor chip. With this configuration, it is possible to improve the alignment accuracy by always recognizing the dummy vias below at the time of alignment when stacking semiconductor chips, thereby improving the reliability of connection between semiconductor chips. is there. In addition, by filling the dummy vias with a fixing material after lamination of the semiconductor chips, the semiconductor chips can be securely fixed and the connection stability between signal connection vias can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a stacked semiconductor device according to an embodiment of the present invention;

FIG. 2 is a sectional view showing a stacked semiconductor device according to one embodiment of the present invention;

FIG. 3 is a plan view showing a method for manufacturing a stacked semiconductor device according to one embodiment of the present invention.

FIG. 4 is a plan view showing a method for manufacturing a stacked semiconductor device according to one embodiment of the present invention.

FIG. 5 is a sectional view showing the method of manufacturing the stacked semiconductor device according to the embodiment of the present invention;

FIG. 6 is a diagram showing a conventional stacked semiconductor device.

[Description of Signs] 1 First through via 2 First semiconductor chip 3 Second through via 4 Second semiconductor chip 5 Third electrode pad 6 Third through via 7 Third semiconductor chip 8a, 8b Via pad 9a, 9b Via pad 10a, 10b Via pad 11 Conductive material 12 First dummy via 13 Second dummy via 14 Third dummy via 15 Adhesive material

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Kazuhiko Matsumura 1-1, Kochi-cho, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. (72) Inventor Yuichiro Yamada 1-1-1, Kochi-cho, Takatsuki-shi, Osaka Matsushita Electronics Inside (72) Inventor Fumito Ito 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation Inside (72) Inventor Takahiro Kumakawa 1-1, Sachimachi, Takatsuki-shi, Osaka Matsushita Electronics Corporation

Claims (8)

[Claims] 1. A first semiconductor having a first electrode pad formed on a main surface thereof, and a first via for signal connection formed on or near the first electrode pad. A chip, a second electrode pad formed on the main surface thereof,
A second semiconductor chip having a second via for signal connection formed on or near the second electrode pad, a third electrode pad formed on a main surface thereof, A third semiconductor chip having a third via for signal connection formed on or near the third electrode pad, wherein the second semiconductor chip is mounted on the first semiconductor chip. , The third semiconductor chip on the second semiconductor chip.
Wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip each include a first dummy via, a second dummy via, and a third dummy via. A center of the second dummy via of the second semiconductor chip is arranged corresponding to a center of the first dummy via of the first semiconductor chip;
Further, the center of the third dummy via of the third semiconductor chip is arranged corresponding to the center of the first dummy via of the first semiconductor chip and the center of the second dummy via of the second semiconductor chip. Characteristic stacked semiconductor device. 2. The method according to claim 1, wherein the diameter of the second dummy via is larger than the diameter of the first dummy via, and the diameter of the third dummy via is larger than the diameter of the second dummy via. Stacked semiconductor device. 3. The stacked semiconductor device according to claim 1, wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are the same semiconductor chip. 4. A first dummy via, a second dummy via,
2. The semiconductor device according to claim 1, wherein a fixing material is filled in the third dummy via, and the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are fixed by the fixing material.
3. The stacked semiconductor device according to item 1. 5. A first electrode pad formed on the main surface, a first via for signal connection formed on or near the first electrode pad, and formed on the main surface. A first semiconductor chip having a first dummy via having a first diameter size, a second electrode pad formed on a main surface thereof, and a second electrode pad on or near the second electrode pad A second semiconductor chip having a second via for signal connection formed on the second semiconductor chip and a second dummy via of a second diameter formed on the main surface thereof, and And the position of the first dummy via is recognized from
Connecting the first via and the second via by aligning the center of the first dummy via with the center of the second dummy via, and connecting the first via to the second via; A third electrode pad formed on the main surface, a third via for signal connection formed on or near the third electrode pad, and a third via formed on the main surface. A third semiconductor chip having a third dummy via having a diameter of 3 is stacked, and the positions of the first dummy via and the second dummy via below the third dummy via are recognized. 3
The center of the first dummy via and the center of the second dummy via are aligned with the center of the dummy via, and the second via is aligned.
And a step of connecting the third via to the third via, and at the time of positioning when stacking the semiconductor chips, a dummy via located below is always recognized in order to perform positioning. Device manufacturing method. 6. The method according to claim 5, wherein the diameter of the second dummy via is larger than the diameter of the first dummy via, and the diameter of the third dummy via is larger than the diameter of the second dummy via. A method for manufacturing a stacked semiconductor device. 7. The method according to claim 5, wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are the same semiconductor chip. 8. A first dummy via, a second dummy via,
6. The method according to claim 5, further comprising the step of filling a third dummy via with a fixing material and fixing the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip with the fixing material. A method for manufacturing a stacked semiconductor device.