JP2002025076A - Data reproducer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data reproducer which is capable of rapidly and most adequately making various kinds of regulation, such as boost voltage regulation, in such a manner that the number of errors of the signal reproducing the data recorded on a recording medium is minimized. SOLUTION: The data recorded on the main surface of a recording medium 50 is read by an optical pickup 52 and the reproduced RR signal is subjected to waveform equalizing with an equalizer 81, following which binarized data is formed in a binarizing circuit 82. A clock signal PCLK is formed from the binarized data and data demodulation is carried out in a data demodulation circuit 86 by the binarized data (delay signal S2) synchronized therewith. In such data reproduction, the error number is increased by delaying a delay signal S2 by a signal delay regulating circuit 84, by which the extreme value of the error number is made to appear in a characteristic chart (profile) indicating the relation between the boost voltage value and the error number. The boost voltage value corresponding to this extreme value is set as a regulation parameter for the boost regulation of the equalizer 81 for performing waveform equalization.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a data reproducing apparatus, and more particularly to a data reproducing apparatus suitable for reproducing data recorded on a recording medium such as an optical disk.

[0002]

BACKGROUND ART Problems to be Solved by the Invention CD (Co
mpact Disc) and DVD (Digital Versatile Disc / Digit)
Recording media (information recording media) such as optical disks such as al Video Disc) have become indispensable for multimedia informationization. A data reproducing apparatus that generates a reproduction signal by reproducing data recorded on such a recording medium,
It is required to reproduce data without errors.

Therefore, in a data reproducing apparatus, a reproduced signal generated by reading data recorded on a recording medium is amplified and passed through a high-frequency emphasizing filter (equalizer).
By improving the quality of the reproduced signal by converting the value into an error and correcting the error through an error correction circuit.

FIG. 8 shows an outline of the configuration of a conventional data reproducing apparatus.

In this data reproducing apparatus, a reproduced signal (RF signal) detected by a pickup (not shown)
Is amplified by the preamplifier 10, absorbs the output drop, and keeps the gain constant.
C), the signal is input to a high-frequency emphasizing filter (equalizer) 12 that boosts the vicinity of the high-frequency component of the RF signal whose amplitude is extremely reduced due to removal of high-frequency noise of the RF signal and intersymbol interference.

[0006] The equalizer 12 performs the waveform equalization by boosting in this manner, whereby the fluctuation (jitter) in the time direction is obtained.
Improves the accuracy of detecting digital information caused by dull components and waveforms.

When the waveform is equalized by the equalizer 12, it is binarized by the binarization circuit 14,
Input to L18. The PLL 18 stores the binarized data 16
From the clock signal 20.
And the binarized synchronization data 22 from the binarized data 16. Thereafter, the clock signal 20 and the binary synchronization data 2
2 is sent to the error correction circuit 24. The error correction circuit 24 detects an error in the binary synchronization data 22,
The error is corrected within the range by a given error correction method.

The equalizer 12 is composed of a filter circuit composed of a combination of several low-pass filters capable of varying the cutoff frequency (fc) and suppressing a group delay fluctuation, and a boost circuit capable of varying the boost amount.
In order to suppress the group delay characteristic at the time of boosting, the cutoff frequencies of the boost circuit and the low-pass filter are almost the same.

In the case of an optical disk, for example, an RF signal input to a data reproducing apparatus having such a configuration is used to reduce laser power due to laser noise in a pickup, noise in a photodetection system, circuit noise such as a preamplifier, or mechanical factors. Such noise increases, and furthermore, disk noise mainly due to disk characteristics, noise due to waveform interference, asymmetry, crosstalk, etc., causes fluctuations in the time direction (hereinafter referred to as jitter). As described above, the equalizer 12 has a role of removing high-frequency noise and boosting the high-frequency component of the RF signal reduced by intersymbol interference with respect to these noises. At this time, if the boost amount is small, the waveform interference of the high frequency component of the RF signal increases and the jitter increases. On the contrary, if the boost amount is large, the jitter due to the phase distortion of the low frequency component of the RF signal increases.

Therefore, the boost amount is optimally adjusted so as to minimize the jitter amount, and various techniques relating to a data reproducing apparatus for performing such an optimal adjustment of the boost amount have been proposed.

For example, in Japanese Patent Application Laid-Open No. 11-328858, entitled "Boost adjustment method for high-frequency emphasis filter,"
A clock signal 20 extracted from the binary data 16 by a circuit
The jitter amount is minimized by detecting the phase error of the binarized data 16 with reference to and adjusting the boost amount according to the phase error width by the equalizer 12.
Here, there is a boost voltage as an adjustment parameter for adjusting the boost amount.

By the way, the recording medium on which the data to be reproduced is recorded as described above is required to have a large capacity in accordance with the recent development of information processing technology. As a result, the density of the data recorded on the recording medium is increased,
Reproduction speed is increasing. Therefore, the frequency of the clock signal extracted in the PLL circuit increases,
There is a problem that the phase error width to be adjusted to minimize the jitter amount becomes narrow, and it becomes difficult to specify the value of the boost amount corresponding to this phase error width.

Further, the actually detected phase error width and the boost voltage value at which the number of errors in the demodulated data is minimized are:
An offset has occurred. Therefore, in order to perform the optimal boost adjustment, there is also a problem that it is necessary to correct the adjustment parameter.

On the other hand, by adjusting the boost amount so as to minimize the number of errors in the binary synchronization data 22 without adjusting the boost amount corresponding to the phase error width, the jitter amount can be reduced. It is also possible to minimize it.

However, it is known that when the number of errors is small, there is a characteristic that the extreme value of the boost voltage does not appear as an adjustment parameter.

FIG. 9 is a characteristic diagram (profile) showing the relationship between the number of errors and the boost voltage.

Here, each measurement point is a value obtained by counting the number of errors when reproducing data recorded in a predetermined amount of clusters for each of the six types of optical disks. This counting takes tens of seconds at each point.

As described above, it can be seen that the number of errors and the extreme value at which the number of errors is minimum depend on the optical disk to be reproduced. The number of errors measured at each point is a measured value for several tens of seconds, and is a time greatly exceeding the actually allowable boost adjustment time.

This is because when the time for counting the number of errors is reduced, the number of errors counted is reduced,
This means that the variation in the number of errors to be counted becomes large, and that the appearance of an extreme value of the number of errors in the characteristic becomes more and more difficult. Therefore,
In some cases, it takes a long time (adjustment time) to specify the boost voltage to be set as the adjustment parameter, or the boost voltage itself cannot be specified due to saturation of the number of errors.

The present invention has been made in view of the above technical problems, and an object of the present invention is to minimize the number of errors in a signal obtained by reproducing data recorded on a recording medium. An object of the present invention is to provide a data reproducing apparatus capable of performing various adjustments such as a boost voltage adjustment in a short time and in an optimum manner.

[0021]

According to the present invention, there is provided a data reproducing apparatus for reading data recorded on a recording medium and generating a reproduced signal. Error adding means for adding an error to the reproduction signal so that an extreme value of the error number appears in a profile between the given adjustment parameter and an adjustment parameter of the adjustment parameter in a state where the extreme value of the error number appears. Means for calculating a value of an adjustment parameter when the number of errors reaches an extreme value by changing the value.

Here, the number of errors is a parameter equivalent to the error rate. For example, the error number is obtained by multiplying a given sampling number by the error rate, although not particularly limited. Therefore, instead of obtaining the value of the adjustment parameter based on the extreme value of the number of errors, obtaining the value of the adjustment parameter based on the extreme value of the error rate is also included in the present invention.

Here, the profile represents, for example, a characteristic indicating a relationship between the number of errors and a given adjustment parameter, and is not limited to its expression or display method.

Further, the extreme value means not only the minimum value but also the maximum value, and it is sufficient that the adjustment parameter corresponding to at least one of the extreme values can be specified according to the type of the adjustment target by the adjustment parameter.

According to the present invention, an error is added so that an extreme value of the error number appears in a profile between the error number of the reproduction signal and a given adjustment parameter, and the extreme value of the error number appears. The value of the adjustment parameter in the state is determined by changing the value of the adjustment parameter in the state. With this, even if the number of errors is small,
Since the number of errors can be remarkably fluctuated with respect to the change of the adjustment parameter, the search range of the adjustment parameter when the number of errors becomes an extreme value can be narrowed, and the search time can be shortened accordingly. .

Further, the invention is characterized in that the adjustment parameter is a parameter for adjusting a boost amount of a high frequency component of the reproduction signal.

In this manner, the optimum value of the boost voltage value as the above-mentioned adjustment parameter can be searched for in a short time, and it is necessary to adjust the boost amount using the phase error width as in the related art. Since the correction which has been described above becomes unnecessary, the configuration can be simplified.

Further, in the present invention, the adjustment parameter is a parameter for performing focus balance adjustment control of a pickup for reading data recorded on a main surface of the recording medium.

Here, the focus balance adjustment control of the pickup means, for example, in the case of an optical disk device, the adjustment of the focus position of the pickup for reading data recorded on the recording layer on the main surface of the recording medium in the optical axis direction. To do.

In this manner, even when the number of errors is small, the number of errors can be remarkably changed with respect to a change in the adjustment parameter. The search range can be narrowed, the search time can be shortened accordingly, and optimal focus balance adjustment control of the pickup can be performed so as to minimize the number of errors.

Further, in the present invention, the adjustment parameter is a parameter for performing a track balance adjustment control of a pickup for reading data recorded on a main surface of the recording medium.

Here, the track balance adjustment control of the pickup means, for example, in the case of an optical disk device, the irradiation position of the pickup for reading data recorded on the main surface of the recording medium is adjusted and controlled in the radial direction of the recording medium. That means.

In this manner, even when the number of errors is small, the number of errors can be remarkably changed with respect to the change of the adjustment parameter. The search range can be narrowed, the search time can be shortened accordingly, and the optimal pickup track balance adjustment control for minimizing the number of errors can be performed.

Further, the present invention is characterized by including a boost means for boosting a high frequency component of the reproduction signal based on the adjustment parameter.

Here, the boost means means an equalizer or the like which performs waveform equalization by boosting a high frequency component of a reproduced signal.

Further, the present invention is characterized in that it includes a focus servo control means for performing focus balance adjustment control of the pickup based on the adjustment parameter.

Further, the present invention is characterized by including a track servo control means for performing a track balance adjustment control of the pickup based on the adjustment parameter.

In this way, it is possible to integrate circuit elements for reproducing data recorded at high density at high speed, thereby improving noise resistance and reducing cost. Become.

Further, according to the present invention, the reproduced signal is a signal synchronized with a reproduced clock signal extracted from data recorded on the main surface of the recording medium, and the error adding means includes the error number in the profile. The error is added by delaying the reproduction signal by a given amount with respect to the reproduction clock signal so that the extreme value of

Here, the reproduction clock signal refers to a clock signal extracted from the edge of the reproduction signal, and is a reference signal for performing data demodulation.

In this way, even when the control of extracting the reproduced clock signal from the reproduced signal becomes unstable,
Since the reliability of data reproduction can be ensured by adjusting the phase of the reproduction signal, and a given amount of delay can be given to the phase adjustment of the reproduction signal to increase the number of errors. Simplification can be achieved by sharing control,
Since the number of errors can be remarkably fluctuated with respect to the change of the adjustment parameter, the search range of the adjustment parameter when the number of errors becomes an extreme value can be narrowed, and the search time can be shortened accordingly. .

Further, according to the present invention, the reproduced signal is reproduced by reading data recorded on a main surface of the recording medium by a pickup, and the error adding means changes a focus balance adjustment of the pickup. In this case, the error is added.

Further, according to the present invention, the reproduction signal is obtained by reading data recorded on a main surface of the recording medium by a pickup and reproducing the data, and the error adding means changes a track balance adjustment of the pickup. In this case, the error is added.

Further, the present invention is characterized in that the error adding means adds the error by adjusting the amplitude of the reproduction signal.

Here, adjusting the amplitude of the reproduced signal means, for example, controlling the amplification factor of a preamplifier for amplifying the signal reproduced from the data recorded on the recording medium, so that the number of errors increases. To maintain or attenuate the amplitude level.

In this way, the number of errors can be easily increased, and an extreme value of the number of errors can appear in a profile between the number of errors of the reproduction signal and a given adjustment parameter. Even when the number of errors is small, the number of errors can be remarkably changed with respect to the change of the adjustment parameter, so that the search range of the adjustment parameter when the number of errors becomes an extreme value can be narrowed, and the corresponding Search time can be reduced. Further, optimal data reproduction can be performed without providing a special additional circuit.

[0047]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below in detail with reference to the drawings.

1. Optical disc device to which the data reproducing device of the present embodiment is applied The data reproducing device of the present embodiment is applied to an optical disc device that reproduces data recorded on an optical disc as a recording medium.

FIG. 1 shows an example of the configuration of an optical disk device to which the data reproducing apparatus of the present embodiment is applied.

This optical disk device includes a disk motor 51 (spindle motor) for rotating a rotating shaft on which an optical disk (recording medium) 50 such as a CD or DVD is mounted.

An optical pickup 52 (optical head) is arranged below the optical disk 50.
2 is provided with a carriage 53 which moves in the radial direction of the optical disk 50.

The carriage 53 can be moved in the radial direction of the optical disk 50 by a feed mechanism (not shown), and the feed mechanism is driven by a feed motor 54.

The optical pickup 52 includes a semiconductor laser and a photodetector (not shown). Then, the laser beam from the semiconductor laser is applied to the main surface of the optical disk 50 via the objective lens 55, and the reflected light is received by the light receiving portion of the photodetector divided into four or two.

The objective lens 55 of the optical pickup 52 is
The optical disk 50 is held so as to be movable along the optical axis direction (vertical direction) and finely movable in the radial direction of the optical disk 50. And the focus actuator 5
6 moves the objective lens 55 in the optical axis direction, and the tracking actuator 57 moves the objective lens 55 in the radial direction of the optical disc 50.

A detection signal from a photodetector (not shown) of the optical pickup 52 is supplied to a signal generation circuit 60, which generates an RF signal, a focus error signal FE, and a tracking error signal T based on the detection signal.
Generate E.

The RF signal from the signal generating circuit 60 is supplied to a data reproducing circuit (data reproducing device) 61. The data reproducing circuit 61 exchanges necessary data with the servo controller 62 and the system controller 63. At this time, the data reproducing circuit 61 performs signal processing such that the number of errors in data obtained by amplifying the RF signal and performing waveform equalization is minimized.

The focus error signal FE from the signal generation circuit 60 is supplied to the focus actuator driver 65 via the focus equalizer 64, and the focus actuator driver 65 drives the focus actuator 56. Thus, the objective lens 55 moves in the optical axis direction so that focus is always achieved, and the minute spot of the laser beam is
On the recording layer.

The tracking error signal TE from the signal generation circuit 60 is supplied to a tracking actuator driver 67 via a tracking equalizer 66, and the tracking actuator driver 67 drives the tracking actuator 57. This allows
The tracking state is always maintained, the objective lens 55 moves in the radial direction of the optical disk 50, and the track on the recording layer of the optical disk 50 is tracked by the light beam.

Further, the tracking error signal TE from the signal generation circuit 60 is supplied to a feed motor driver 69 via a tracking equalizer 66 and a feed equalizer 68, and the feed motor driver 69
The feed motor 54 is driven so that the feed motor 54 rotates intermittently.

A control signal is supplied from the servo controller 62 to the disk equalizer 70, and the disk motor driver 71 drives the disk motor 51 according to the control signal.

Further, the servo controller 62 receives various control signals from the system controller 63,
Focus equalizer 64, tracking equalizer 6
6. Feed equalizer 68 and disk equalizer 7
For 0, a required control signal is supplied.

As shown in FIG. 1, a servo controller 72 includes a servo controller 62, a focus equalizer 64, a tracking equalizer 66, a feed equalizer 68, and a disk equalizer 70.

Incidentally, such a signal generation circuit 60, a data reproduction circuit 61, a system controller 63, a focus actuator driver 65, a tracking actuator driver 67, and a feed motor driver 6
9, disk motor driver 71, servo control unit 72
It is particularly desirable that the components be integrated.

2. Data Reproducing Apparatus (Data Reproducing Circuit) of the Present Embodiment FIG. 2 shows an example of the configuration of the data reproducing circuit 61 of the present embodiment.

In the data reproducing circuit 61, an RF signal obtained by optically reading data recorded on an optical disk (recording medium) 50 by an optical pickup 52 and reproducing the data is input to a preamplifier 80.

The preamplifier 80 amplifies the RF signal and outputs it to the equalizer 81.

The equalizer 81 absorbs the decrease in the output of the RF signal, keeps the gain constant, removes the high frequency noise of the RF signal, and removes the vicinity of the high frequency component of the RF signal whose amplitude has extremely decreased due to the intersymbol interference. Is boosted (rise) to equalize the waveform.

The output of the equalizer 81 is supplied to a binarizing circuit 82
Is binarized.

The binarizing circuit 82 binarizes the output of the equalizer 81 with a given threshold value and supplies the binarized data to the edge detection signal generating circuit 83 and the signal delay adjusting circuit 84.

The edge detection signal generation circuit 83 detects the rising and falling edges of the binary data,
Each time an edge is detected, an edge detection signal S1 consisting of a pulse of a given width is generated.

The signal delay adjusting circuit 84 generates a delay signal S2 in which the rising and falling edges of the binary data are delayed by delay times td1 and td2, respectively. These delay times td1, td2
Are individually set or adjusted.

The edge detection signal S1 generated by the edge detection signal generation circuit 83 is supplied to the PLL circuit 85.

The PLL circuit 85 includes a phase comparator, a charge pump, and a voltage controlled oscillator (VCO) (not shown). The falling edge of the edge detection signal S1 and the rising edge of the clock signal PLCK output from its own oscillation are output. Are controlled so that their edges (phases) coincide with each other. Thereby, the PLL circuit 85 extracts the clock signal PCLK from the clock information included in the edge of the binary data.

The delay signal S 2 generated by the signal delay adjusting circuit 84 and the clock signal PCLK extracted by the PLL circuit 85 are output to the data demodulation circuit 86.

Data demodulation circuit 86 synchronizes with clock signal PLCK output from PLL circuit 85, demodulates data from delay signal S2 output from signal delay adjustment circuit 84, and generates demodulated signal S3.

The demodulated signal S 3 demodulated by the data demodulation circuit 86 is subjected to error correction by an ECC circuit 87 according to a given error correction method, counts the number of errors, and outputs the result to the controller 88.

The controller 88 comprises a CPU, a memory, and the like (not shown). The signal delay adjusting circuit 84 determines the delay times td1 and td2 according to a control program stored in the memory, and the ECC circuit 87 counts the delay times td1 and td2. A boost voltage value which is an adjustment parameter of the equalizer 81 is determined from the number of errors.

This boost voltage value is converted into an analog signal by the D / A converter 89, and the corresponding boost voltage value is applied to the equalizer 81.

FIG. 3 shows a signal delay adjusting circuit 8 according to this embodiment.
4 shows an example of the configuration of FIG.

The signal delay adjusting circuit 84 includes a rising edge detecting circuit 100 and a falling edge detecting circuit 10
1, includes programmable delay elements 102 and 103, and a synthesis circuit 104.

The rising edge detection circuit 100 detects the rising edge of the binarized data binarized by the binarization circuit 82 and generates a rising edge detection signal having a given pulse width.

The falling edge detecting circuit 101 detects the falling edge of the binarized data binarized by the binarizing circuit 82 and generates a falling edge detection signal having a given pulse width. .

The programmable delay element 102 delays the rising edge detection signal generated by the rising edge detection circuit 100 by the delay time td1 generated by the controller 88.

The programmable delay element 103 delays the falling edge detection signal generated by the falling edge detection circuit 101 by the delay time td2 generated by the controller 88.

The synthesizing circuit 104 has the delay times td 1 and td 1 by the programmable delay elements 102 and 103, respectively.
Each edge detection signal delayed by d2 is synthesized and output to the data demodulation circuit 86 as a delay signal S2.

In the data reproducing circuit of this embodiment having such a configuration, the delay signal S2 delayed by the signal delay adjusting circuit 84 is synchronized with the clock signal PCLK extracted from the binary data by the PLL circuit 85. Then, the occurrence of bit shift can be suppressed, and the number of errors can be minimized.

The preamplifier 80, the equalizer 81,
Binarization circuit 82, data demodulation circuit 86, ECC circuit 8
7. The controller 88 and the D / A converter 89 are optional components.

In addition, since each part of the data reproducing circuit 61 is integrated, noise resistance is improved,
This is desirable in that cost can be reduced.

FIGS. 4A to 4D show an example of an operation timing representing the relationship between the clock signal PCLK and the delay signal S2 in the present embodiment.

That is, as shown in FIG. 4A, when the timing of the rising edge of the binarized data binarized by the binarization circuit 82 is F1 and the timing of the falling edge is F2, The edge detection signal S1 generated by the edge detection signal generation circuit 83 as shown in FIG.
Is the rising edge timing F1 of the binarized data.
From the position has a given pulse width T1. Further, it has a given pulse width T1 from the position of the falling edge timing F2 of the binarized data.

In the PLL circuit 85, the rising edge of the clock signal PCLK which has a window as shown in FIG. 4C and is oscillated and output, and the falling edge of the edge detection signal S1 shown in FIG. And the phase of the clock signal PCLK is controlled such that the edges (phases) match.

The signal delay adjusting circuit 84 includes the controller 8
8, the delay times td1 and td2 are separately set. As a result, the timing of the rising edge of the delay time S2 is a timing delayed by the delay time td1 from the timing F1 of the rising edge of the binary data. Further, the timing of the falling edge of the delay time S2 is a timing delayed by the delay time td2 from the timing F2 of the falling edge of the binary data.

Here, the edge of the clock signal PCLK and the delay signal S2 delayed by the delay times td1 and td2
, The occurrence of bit shift of data read from the recording medium can be suppressed.

By the way, in the data reproducing circuit of the present embodiment, the delay signal S2 generated by the signal delay adjusting circuit 84 is arbitrarily offset from the clock signal PCLK, thereby intentionally setting the error number. The feature is that it is important to increase. As a result, the number of errors that occur according to the search range of the boost voltage increases, and an extreme value that minimizes the number of errors can appear. Therefore, it is possible to easily specify the boost voltage value corresponding to the extreme value of the error number.

FIGS. 5A to 5D show another example of the operation timing representing the relationship between the clock signal PCLK and the delay signal S2 in the present embodiment.

At the time of the first adjustment, FIG.
(B), the edge of the clock signal PCLK,
The control is performed so that the phase of the delay signal S2 coincides with the phase of the edge. That is, the controller 88 outputs the clock signal P
The delay times td1 and td2 are set in the signal delay adjustment circuit 84 so as to match the phase of the edge of CLK. The delayed signal S2 includes a jitter component due to the various factors described above, and it is considered that the delayed signal S2 has a bit shift (jitter) distribution 120 as shown in FIG. Therefore, when the edge of the delay signal S2 coincides with the center position of the window of the clock signal PCLK as in the first adjustment, the number of errors is reduced by the bit shift distribution 120 shown in FIG. 5C. Will be minimal.

On the other hand, at the time of the second adjustment, FIG.
(B) and the clock signal PCL as shown in FIG.
The phase between the edge of K and the edge of the delay signal S2 is controlled to have a phase difference DLY. That is, the signal delay adjustment circuit 84 is controlled so that the controller 88 has a phase difference DLY with respect to the edge of the clock signal PCLK.
, Delay times td1 and td2 are set.

As a result, as shown in FIG. 5C, the position of the bit shift distribution 122 is shifted with respect to the center of the window of the clock signal PCLK, and the number of errors corresponding to the broken line portion 124 occurs.

FIG. 6 is a characteristic diagram (profile) showing the relationship between the boost voltage as an adjustment parameter of the equalizer 81 and the number of errors.

Here, the relationship between the boost voltage when the phase difference DLY of the delay signal S2 with respect to the clock signal PCLK is changed and the number of errors obtained by counting the delay signal S2 after data demodulation is shown.

Delay signal S with respect to clock signal PCLK
When there is no phase difference DLY of 2 or “1 nsec (nanosecond)”, the number of errors counted after data demodulation is substantially constant for a boost voltage in a specific range. Therefore, the extreme value of the number of errors cannot be specified, and the boost voltage that minimizes the number of errors cannot be specified. Further, even if the boost voltage can be specified, a time for counting the number of errors or a time for searching for a boost voltage to be adjusted is wasted.

However, as the phase difference DLY of the delay signal S2 with respect to the clock signal PCLK increases, the number of errors counted after data demodulation can be increased. That is, the larger the phase difference DLY, the larger the number of errors, but together with this, an extreme value of the number of errors appears.

Therefore, by selecting the boost voltage corresponding to the emerged extreme value as the adjustment parameter value, it is possible to specify the adjustment parameter which was originally not possible easily or in a short time.

Further, since the number of errors increases, the counting time of the number of errors can be reduced, and more optimal adjustment parameters can be set.

The controller 88 executes a process of selecting a boost voltage value as the above-mentioned adjustment parameter in accordance with a program including the following processing contents.

FIG. 7 shows a controller 88 according to this embodiment.
An example of a process of selecting a boost voltage value as an adjustment parameter by (firmware operating on a controller) will be described.

First, the controller 88 sets given delay times td1 and td2 for the signal delay adjusting circuit 84.

By the delay times td1 and td2, PL
Delay signal S2 is set to have a phase difference by a given delay value DLY with respect to clock signal PCLK extracted by L circuit 85 (step S10).

Subsequently, the controller 88 sets a given high boost voltage value X to the boost voltage Y applied to the equalizer 81 (Y = X) (step S11). Thus, the D / A converter 89 is provided in the equalizer 81.
The boost voltage value X is applied via the
Performs waveform equalization with a boost amount corresponding to this.

Thereafter, the number of errors in the demodulated signal S3 output from the data demodulation circuit 86 is obtained (step S1).
2).

The number of errors may be obtained by obtaining the number of errors counted by the ECC circuit 87 for performing a given error correction on the demodulated signal S3, or by using the controller 8
8 may count the number of errors in the demodulated signal S3.

The controller 88 stores the number of errors acquired in step S12 as a count value A (step S13).

Next, the boost voltage Y applied to the equalizer 81 is reduced by a given amount Δy, and a voltage value “Y−Δy” is set to the boost voltage Y (step S14). Thus, the D / A converter 89 is provided in the equalizer 81.
, A boost voltage value “Y−Δy” is applied, and the equalizer 81 performs a boost corresponding to the boost voltage value to perform waveform equalization.

Then, as in step S12, the number of errors in the demodulated signal S3 output from the data demodulation circuit 86 is obtained (step S15).

The controller 88 stores the number of errors obtained in step S15 as a count value B (step S16).

Next, the controller 88 proceeds to step S1.
3 and the absolute value of “AB” is calculated from the count values A and B stored in step S16, and it is determined whether the absolute value is smaller than a given ΔN (step S17).

When it is determined that the absolute value of “AB” is equal to or greater than the given ΔN (step S17: N), the flow returns to step S14 to further reduce the boost voltage applied to the equalizer 81 by Δy ( Step S14), the count value B of the number of errors is updated again.

When it is determined that the absolute value of “AB” is smaller than the given ΔN (step S17: Y), (X + Y) / 2 is set as the boost voltage value that minimizes the number of errors (step S17). S18).

In this way, the controller 88 reduces the boost voltage value at a given interval Δy until the difference between the error number at a given high boost voltage value and the error number falls within the range of ΔN. And a boost voltage value that minimizes the number of errors.

As described above, the data reproducing circuit (data reproducing apparatus) of the present embodiment reads the data recorded on the main surface of the recording medium 50 by the optical pickup 52 and amplifies the RF signal reproduced by the preamplifier 80. After the equalizer 81 performs waveform equalization, the binarization circuit 82 generates binarized data. The PLL circuit 85 extracts the clock signal PCLK from the binary data, and performs data demodulation in the data demodulation circuit 86 using the binary data (delay signal S2) synchronized with the clock signal PCLK. In such a data reproduction process, the delay signal S2 is delayed by the signal delay adjustment circuit 84 to increase the number of errors, so that the number of errors in the characteristic diagram (profile) showing the relationship between the boost voltage value and the number of errors is increased. Make the value appear. Then, the boost voltage value corresponding to the extreme value is set as an adjustment parameter for performing the boost adjustment of the equalizer 81 that performs the waveform equalization. Accordingly, even when the number of errors is small, the number of errors can be remarkably changed by changing the boost voltage value as an adjustment parameter, so that the search range of the boost voltage value can be narrowed. The boost adjustment time can be shortened accordingly. Further, unlike the case where the boost adjustment is performed based on the phase error width as in the related art, it is not necessary to perform the correction.

3. Others The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the present invention.

For example, the data reproducing apparatus of the present embodiment
It is desirable to apply the present invention to an optical disk device, but it is also possible to apply the present invention to other electronic devices. in this case,
The present invention is not limited to the method of optically reading and reproducing data recorded on a recording medium.

In the data reproducing apparatus according to the present embodiment, the number of errors is increased by delaying the signal with the signal delay adjusting circuit in accordance with the characteristic diagram (profile) of the number of errors and the boost voltage value, and Although the boost voltage of the equalizer for equalizing the waveform of the RF signal read by the optical pickup is adjusted so as to be an extreme value, the present invention is not limited to this.

For example, according to a characteristic diagram (profile) of the number of errors and the focus balance adjustment value, the number of errors is increased by delaying with a signal delay adjustment circuit.
The focus balance adjustment control may be performed by controlling the focus equalizer or the focus actuator / driver of the optical disk device so that the extreme value of the number of appearing errors is obtained. Thereby, even when the number of errors is small, the number of errors can be remarkably changed with respect to the change of the adjustment parameter, so that the search range of the adjustment parameter when the number of errors becomes an extreme value can be narrowed. Therefore, the search time can be shortened by that much, and the focus balance adjustment control of the pickup can be optimally controlled so that the number of errors is minimized.

Similarly, according to a characteristic diagram (profile) of the number of errors and the track balance adjustment value, the number of errors is increased by delaying the signal with a signal delay adjustment circuit so that the number of errors appears to be an extreme value. Furthermore, it is also possible to control the tracking equalizer or the tracking actuator driver of the optical disk device to perform the track balance adjustment control. Thereby, even when the number of errors is small, the number of errors can be remarkably changed with respect to the change of the adjustment parameter, so that the search range of the adjustment parameter when the number of errors becomes an extreme value can be narrowed. Therefore, the search time can be shortened by that much, and the optimum pickup track balance adjustment control for minimizing the number of errors can be performed.

Furthermore, in the data reproducing apparatus according to the present embodiment, in order to make an extreme value of the number of errors appear in a characteristic diagram (profile) of the number of errors and each adjustment parameter, a signal delay adjustment circuit performs data demodulation. Although the number of errors is increased by delaying the signal, the present invention is not limited to this.

For example, the number of errors may be increased by controlling the focus equalizer or the focus actuator driver of the optical disk device and performing focus balance adjustment control in the defocus direction. Similarly, the number of errors can be increased by controlling the tracking equalizer or the tracking actuator driver of the optical disk device and performing the track balance adjustment control in the direction in which the tracking error occurs. Further, the RF input to the data reproducing device
By controlling the amplitude level such as by attenuating the signal, the number of errors in the signal to be subjected to data demodulation may be increased.

As described above, when performing focus balance adjustment control, track balance adjustment control, reproduction signal amplitude control, etc., the number of errors can be easily increased, and optimal data can be obtained without providing a special additional circuit. Playback can be performed.

In the data reproducing apparatus of the present embodiment, the number of errors is counted by the ECC circuit or the controller, but the present invention is not limited to this. The number of errors counted outside the data reproducing apparatus may be notified.

Further, the data reproducing apparatus according to the present embodiment has been described as including the ECC circuit, but is not limited to this.

Further, in the data reproducing apparatus of the present embodiment, each section in the apparatus is controlled by the controller, but the inside of the data reproducing apparatus may be controlled by the system controller of the optical disk apparatus.

Further, in the data reproducing apparatus according to the present embodiment, the number of errors is a parameter equivalent to the error rate. For example, the number of errors multiplied by the number of samplings in a given time is the number of errors. Therefore, performing the above-described control according to the characteristic diagram (profile) based on the error rate is included in the present invention.

In the data reproducing apparatus of the present embodiment, the number of errors is increased so that the minimum value appears as the extreme value of the number of errors. However, the maximum value appears according to the type of the control target. The same can be applied to such a case.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a configuration of an optical disk device to which a data reproducing device according to an embodiment is applied.

FIG. 2 is a block diagram illustrating an example of a configuration of a data reproduction circuit according to the present embodiment.

FIG. 3 is a block diagram illustrating an example of a configuration of a signal delay adjustment circuit according to the embodiment;

FIGS. 4A to 4D are timing charts showing an example of a relationship between a clock signal PCLK and a delay signal S2 in the present embodiment.

FIGS. 5A to 5D are timing charts showing an example of a relationship between a clock signal PCLK and a delay signal S2 in the embodiment.

FIG. 6 is a characteristic diagram (profile) showing a relationship between a boost voltage as an equalizer adjustment parameter and the number of errors.

FIG. 7 is a flowchart illustrating an example of a process of selecting a boost voltage value as an adjustment parameter by the controller according to the embodiment.

FIG. 8 is a block diagram showing an outline of a configuration of a conventional data reproducing apparatus.

FIG. 9 is a characteristic diagram (profile) showing a relationship between the number of errors and a boost voltage.

[Explanation of symbols]

 Reference Signs List 50 optical disk (recording medium) 51 disk motor (spindle motor) 52 optical pickup 53 carriage 54 feed motor 55 objective lens 56 focus actuator 57 tracking actuator 60 signal generation circuit 61 data reproduction circuit 62 server controller 63 system controller 64 focus equalizer 65 focus actuator Driver 66 Tracking equalizer 67 Tracking actuator driver 68 Feed equalizer 69 Feed motor driver 70 Disk equalizer 71 Disk motor driver 72 Servo control unit 80 Preamplifier 81 Equalizer 82 Binarization circuit 83 Edge detection signal generation circuit 84 Signal delay adjustment circuit 85 PLL circuit 86 Data demodulation circuit 87 ECC circuit 88 Controller 89 D / A converter

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) G11B 20/18 570 G11B 20/18 570D 572 572C 572F

Claims (11)

[Claims] 1. A data reproducing apparatus for reading data recorded on a recording medium and generating a reproduced signal, comprising: a pole of the number of errors in a profile between the number of errors of the reproduced signal and a given adjustment parameter. Error adding means for adding an error to the reproduction signal so that a value appears; and adjusting when the number of errors becomes an extreme value by changing a value of an adjustment parameter in a state where the extreme value of the error number appears. A data reproducing apparatus, comprising: means for obtaining a value of a parameter; 2. The data reproducing apparatus according to claim 1, wherein the adjustment parameter is a parameter for adjusting a boost amount of a high frequency component of the reproduction signal. 3. The data reproducing apparatus according to claim 1, wherein the adjustment parameter is a parameter for performing a focus balance adjustment control of a pickup that reads data recorded on a main surface of the recording medium. 4. The data reproducing apparatus according to claim 1, wherein the adjustment parameter is a parameter for performing a track balance adjustment control of a pickup for reading data recorded on a main surface of the recording medium. 5. The data reproducing apparatus according to claim 1, further comprising a boost unit that boosts a high-frequency component of the reproduction signal based on the adjustment parameter. 6. The data reproducing apparatus according to claim 3, further comprising a focus servo control unit that performs focus balance adjustment control of the pickup based on the adjustment parameter. 7. The data reproducing apparatus according to claim 4, further comprising: a track servo control unit that performs a track balance adjustment control of the pickup based on the adjustment parameter. 8. The reproduction signal according to claim 1, wherein the reproduction signal is a signal synchronized with a reproduction clock signal extracted from data recorded on a main surface of the recording medium. The error is added by delaying the reproduced signal by a given amount with respect to the reproduced clock signal so that an extreme value of the number of errors appears in the profile. apparatus. 9. The reproduction signal according to claim 1, wherein the reproduction signal is obtained by reading out data recorded on a main surface of the recording medium by a pickup and reproducing the data. A data reproducing apparatus for adding the error by changing a focus balance adjustment of a pickup. 10. The reproduction signal according to claim 1, wherein the reproduction signal is obtained by reading data recorded on a main surface of the recording medium by a pickup and reproducing the data. A data reproducing apparatus for adding the error by changing a track balance adjustment of a pickup. 11. The data reproducing apparatus according to claim 1, wherein the error adding unit adds the error by adjusting an amplitude of the reproduction signal.