JP2001344981A - Non-volatile semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory in which a write-in time can be shortened when continuous data is written and burden of an external host can be reduced, as for non-volatile semiconductor memory such as flash memory. SOLUTION: This device is provided with plural memory cells consisting of MOSFET which has a control gate and a floating gate and which performs write-in or erasion by injecting or discharging electric charges in/from a floating gate. The plural memory cells are constituted so that they are segmented for each prescribed sector and write-in operation is performed for each sector. Further, the device is provided with a register which can accumulate data being twice the data quantity processed by write-in operation at a time and constituted so that write-in data for the other sector is taken in externally and accumulated in the register while write-in data inputted externally and accumulated in the register is written in one sector.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a writing method in a nonvolatile semiconductor memory device, and more particularly to a technique useful when applied to a flash memory.

[0002]

2. Description of the Related Art In a nonvolatile semiconductor memory device such as a flash memory, an M
Since the OSFET is used as a storage element and writing and erasing are performed by injecting or discharging electric charges to the floating gate by applying an electric field between the control gate and the semiconductor substrate, a high voltage of, for example, 10 V or more is used for data writing and erasing. I need. In general, in a flash memory, a large-capacity memory array is realized by connecting storage elements in one row of the memory array to the same word line.
Writing is often performed using one row of storage elements connected to the same word line as one unit (hereinafter, referred to as a sector).

Generally, a flash memory is configured to operate based on a command input from a host such as a CPU. For example, when writing data to the flash memory, as shown in the time chart of FIG. 11, first, the host issues a write request command “1stCom” followed by addresses “SA1” and “SA”.
2 ”and write data“ DataIn ”are transferred.The flash memory is provided with an address buffer and a register for storing write data for one sector.
The above address is stored in an address buffer, and the write data is stored in a register.

Then, a write start command “2n
When "dCom" is input, as shown in the flowchart of FIG. 12, write preparation such as activation of the booster circuit in the flash memory is performed (step J1), and the process waits until the internal power supply is turned on (step J2). The application of the write bias voltage to the word line specified by the address stored in the address buffer (step J3) and the write verify (step J4) are repeated, and when the write is confirmed, the booster circuit is stopped and the internal power supply is stopped. Waits for to fall (step J5), and then
There is a method of setting a flag indicating the end of writing in an internal status register (step J6) to end a series of writing operations.

[0005]

When writing data to a flash memory, a relatively large amount of data may be written continuously over a plurality of sectors. However, in the above-described conventional flash memory, even when data is written in a plurality of sectors, the data write process for one sector has to be repeated by the number of sectors. That is, data transfer for one sector and data write processing must be alternately and repeatedly performed, and the time required for data write for K sectors is the time required for data write for one sector W ≒ Y (1 This is K times the data transfer time for a sector) + X (one write operation time), and the time required for data transfer occupies a considerable portion.

In the conventional flash memory, even when data is written in a plurality of sectors, the booster circuit is started and stopped every time a write operation is performed in one sector to raise or lower the internal voltage. Was. therefore,
Each time one sector is written, it takes a rise time α (about 100 μs) of the internal power supply when the booster circuit is activated and a fall time β (about 50 μs) of the internal power supply when the booster circuit is stopped. In the case of writing, the required writing time includes an extra time of (α + β) × K.

An external control device (hereinafter simply referred to as a host) such as a microprocessor for externally writing data to a flash memory, when writing data over a plurality of sectors, requires one data write per sector. Command input, address input, data transfer, and the end of writing must be repeatedly determined.
There is also a disadvantage that the host is not easily released from the data writing process, and the load on the host is large, and the throughput of the system is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device capable of shortening the write time when performing continuous data write processing, reducing the load on the host, and improving the system throughput. is there.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The outline of a typical invention among the inventions disclosed in the present application is as follows.

That is, a plurality of memory cells each including a MOSFET having a control gate and a floating gate and writing and erasing data by injecting or discharging electric charges into and from the floating gate are provided. In a nonvolatile semiconductor memory device which is divided into sectors and is configured to be able to perform a write operation for each sector, the nonvolatile semiconductor memory device includes a register capable of accumulating data of twice or more the data amount handled in one write operation. While writing the data written in the above-mentioned register and stored in the above-mentioned register to one sector, the writing data to the other sector can be taken in from outside and stored in the above-mentioned register.

According to such means, in continuous write processing over a plurality of sectors, write data of the next sector can be input during the write operation of the semiconductor memory device. The time required for comprehensive write processing including data input and write operation can be reduced. Also, since the writing process time is shortened,
The waiting time on the host side for causing the semiconductor memory device to perform the writing process is also reduced.

Desirably, a control capable of discriminating a first write command (for example, a continuous write command) and a second write command (for example, a normal write command) input from the outside and executing a write process corresponding to each command. When the first write command is input, while the already read data is being written, the write data of another sector is externally fetched, while the second write command is input. Is configured to perform a write process based on the next second write command after writing of data by the command is completed.

With such a configuration, the continuous writing process and the normal writing process can be selectively executed separately from each other.

Further, a booster circuit for generating an internal voltage higher than an external power supply voltage used for the write operation is provided, and when writing to a plurality of sectors, the booster operation of the booster circuit is activated at the first write operation. Thereafter, the boosting operation is continued until the writing to the other sector is completed, and the boosting operation of the boosting circuit is stopped after the writing operation for all the plurality of sectors is completed.

According to such means, the rise time and fall time of the internal power supply by the booster circuit are included only once each in the continuous writing process, so that the internal power supply is turned on every time. It is possible to reduce the time required for comprehensive write processing as compared with the method of increasing.

Preferably, a first write command (for example, a continuous boost write command) input from the outside and a second
And a control unit capable of executing a write process corresponding to each of the write commands (for example, a normal write command). When a first write command is input, data is being written to a plurality of sectors. While the boost operation is continued, when the second write command is input, the boost circuit is activated at the start of writing to the corresponding sector, and the boost operation is stopped after the writing of the sector is completed. I do.

With this configuration, it is possible to selectively execute the above-described continuous step-up write process and the normal write process separately.

More preferably, an address counter for generating a continuous sector address is provided, and when sequentially writing data to a plurality of sectors having continuous addresses, the address of the first sector input from the outside is stored in the address counter. It is preferable that the address of the next sector be set and generated by the address counter.

With such a configuration, it is possible to omit the address input of sectors other than the first sector, and accordingly,
Further, the writing time can be reduced, and the load on the host side for performing the writing process can be reduced.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing a preferred embodiment of a flash memory to which the present invention is applied.

In FIG. 1, reference numeral 1 denotes a flash memory as a nonvolatile semiconductor memory device, which is formed on one semiconductor chip such as single crystal silicon. Reference numeral 11 denotes a memory array in which memory cells as nonvolatile storage elements each composed of a MOSFET having a floating gate between a control gate and a semiconductor substrate are arranged in a matrix. In this memory array 11, writing and reading of data are performed in units of sectors each composed of a row of memory cells connected to the same word line, and data is erased in units of blocks, that is, in units of a plurality of sectors sharing a well region. It has become. At the center of the memory array 11, a write data register 9 composed of, for example, a flip-flop type sense latch is provided so that write data for one sector is temporarily stored.
When rewriting only a part of data of a certain sector, the data of the sector is once read into the write data register 9, desired bit data in the write data register 9 is rewritten, and then the write data of one sector is written. The processing is performed in such a manner that the whole is written to the original sector of the memory array 11.

Reference numeral 12 denotes a decoder circuit for forming a signal for selecting a word line in the memory array 11 according to an externally input address signal. Reference numeral 13 denotes a Y address of one sector of data read from the memory array 11. A corresponding unit of data such as 1 byte (8 bits) or 1 word (16 bits) is selected and sense amplifier 14 is selected.
, A write control circuit for applying a write voltage to a memory cell in accordance with the data stored in the write data register 15a to perform a write, and 16 a write control input from the outside. An input register for temporarily storing data; 17 an address counter for automatically generating a continuous address; 18 a booster circuit for generating an internal power supply necessary for writing and erasing a memory cell at a voltage higher than the external input voltage Vcc; Reference numeral 20 denotes a system control circuit that controls the entire chip based on a control signal input from the outside.

In addition, the flash memory 1 of this embodiment
An address buffer 21 and an I / O buffer 22 for inputting and outputting an address signal and a data signal, a control signal input buffer 23 to which a control signal supplied from an external CPU or the like to the control circuit 20 is input, Power supply terminal 2 to which supplied power supply voltage Vcc and ground potential GND are applied
4, 25 are provided.

In the flash memory 1 of this embodiment, although not particularly limited, the system control circuit 20
Includes a register for holding a command given from an external CPU or the like, a sequencer for decoding a command, and sequentially forming and outputting a control signal for each circuit in the memory in order to execute a process corresponding to the command. Yes,
When a command is given, it is configured to decode the command and automatically start a corresponding process.

The control signals input from the host, such as an external CPU, to the flash memory 1 of this embodiment include:
For example, there are a reset signal, a chip select signal, a write control signal, an output control signal, a command or a command enable signal for indicating data input or address input, and a system clock. The command code input from the host to the flash memory 1 of this embodiment includes a normal write command for instructing a normal write process for performing writing for each sector, a continuous write command for instructing a continuous write process described later, and a continuous write command. There are a continuous boost write command for starting the boost write process, a reset command indicating the end of the continuous write process and the continuous boost write process, and an address generation command for performing a continuous write process based on the address generated by the address counter.

In this embodiment, the input register 16 is configured to have a capacity that is a multiple of the data capacity handled in one write process. Such an input register 16
Can be configured by a flip-flop similar to a general register, but for example, an SRAM or a DRAM in consideration of a data fetching speed and a chip occupation area (cost).
Can also be configured. The size of the input register 16 required in the continuous writing process shown in FIGS. 2 and 3 is a capacity of at least two sectors, the size required in the continuous writing process shown in FIG.
The size required in the continuous writing process shown in (1) is the capacity of K sectors (K is an integer of 2 or more) that can be continuously written.

Next, the writing process of the flash memory 1 will be described. The ordinary writing process is the same as that described in the related art, so that the description is omitted. The flash memory 1 of this embodiment is characterized by a continuous writing process for continuously writing large-sized data over a plurality of sectors.

FIG. 2 is a time chart showing a first embodiment of the continuous writing process of the flash memory 1 of the embodiment.

In the continuous writing process of the present embodiment, the continuous writing command "1s"
tCom ”is input and the processing is started.
Continues the continuous writing process of performing the data writing and the data transfer in parallel until a reset command “ResetCom” is subsequently input by this continuous writing command.

Next, input of write destination addresses "SA1" and "SA2" from the host and write data "DataIn" are performed.
1 ". The command and the address have a small amount of data, so that the transfer time is negligible. In comparison with that, the data transfer time Y for one write data transfer
Takes a time on the order of 100 μs to ms, depending on the data transfer format. The write data is temporarily stored in the input register 16.

When one transfer of the write data is completed,
A write start command “2ndCom” instructing the start of writing to the memory array 11 is sent from the host. Then
The write data stored in the input register 16 is shifted to the write input register 16 in the memory array 11 and a write operation is started. That is, the application of the write bias voltage and the write verify according to the data to the memory cells in the designated sector are repeated. One write time X is equal to the flash memory 1 regardless of the data amount.
Ms (milliseconds)
It takes time to order.

In the continuous write process, the transfer process of the next write data is performed in parallel during the write operation to this one sector. For example, the system control circuit 20 sets a flag for receiving the next data transfer in an internal status register at the time of starting the write operation to the memory array 11, and changes the ready / busy signal R / B to low level. Then, after confirming the status register flag, the host side performs the next address input and transfer of write data “DataIn2”. The write data transferred during the write operation is stored in a vacant area of the input register 16 or is overwritten on an area in which the write data that has been transferred to the write register 15a is stored until the write operation is completed. .

Next, when the data write operation for one sector is completed, the system control circuit 20 changes the ready / busy signal R / B to a high level. Then, after confirming the flag setting of the status register, the host outputs the write address “SA1, SA2” of the write data “DataIn2” transferred for the second time and the write start command “2ndCom” for starting the write operation. Hereinafter, the above operation is repeated until the data writing of the last sector is completed.

In the last write processing Tend, there is no next write data, so no data transfer is performed. And
When the writing is completed or during the writing, a reset command “ResetCom” is input from the host side, and the system control circuit 20 of the flash memory 1 recognizes the end of the continuous writing process. When the reset command is input and the write operation is completed, the system control circuit 20 stops the operation of the booster circuit 18.

The continuous writing process of the embodiment shown in FIG. 2 is based on the assumption that the writing time X is longer than the single data transfer time Y. The second and subsequent data transfer times Y are included in the writing time X. Therefore, ignoring the address input and command input time, the total write processing time is about “Y + X × K”. In a conventional write process in which data transfer and a write operation are alternately performed, the total time is “(Y +
X) × K, which is shortened by “Y × (K−1)”.

FIG. 3 shows a time chart of a second embodiment of the continuous writing process.

The continuous write processing of this embodiment is based on the assumption that the data transfer time Y for one time, that is, one sector is longer than the write time X. In this case, since one write operation is completed during one data transfer, the host does not need to confirm the data transfer start timing or the write start command input timing with the status register, etc. The transfer and write start commands can be continuously performed for K sectors.

In this example, when continuous writing processing for K sectors is performed, since the data writing time X for the second and subsequent times is included in the data transfer time Y, the total time is about "Y".
× K + X ”. This means that the time “X × (K−1)” is reduced as compared with the conventional method in which data transfer and writing are alternately performed.

FIG. 4 is a time chart of a third embodiment of the continuous writing process.

In the continuous writing process of this embodiment, the capacity of one sector is large and the writing time X of one sector is 1
This is an effective method for a flash memory in which the transfer time Y of data for a sector takes about twice or more. In the continuous writing process of this embodiment, the data amount handled in one data transfer or one writing process is set to half the capacity of one sector (N / 2 bytes), and instead, writing to one sector is performed twice. This is done separately.
In this case, the capacity of the input register 16 is
5 (N bytes). When a normal one-sector write process is performed in this flash memory, the data size handled in one data transfer or one write process may be a capacity of one sector.

In the continuous write processing of this embodiment, the data amount handled in one data transfer or one write processing is set to half the capacity of one sector (N / 2 bytes), and the write time is reduced to the data size. Since the number of write operations is independent, the number of write operations is doubled, but one data transfer time Y / 2 is equivalent to one write time X. Therefore, the second and subsequent write times X are equal to the data transfer time Y / 2 and becomes invisible, and the total time required for the writing process is approximately “Y / 2 × 2
K + X = Y × K + X ”. In the conventional case where data transfer and writing are alternately performed, the total time is “(Y + X)
× K ”, which means that the time“ X × (K−1) ”has been shortened, and the input register 16 has a capacity of one sector.

FIG. 5 shows a time chart of the fourth embodiment of the continuous writing process.

In the continuous writing process of this embodiment, the host is released from the writing process quickly by increasing the capacity of the address buffer 21 and the input register 16 to reduce the load on the host. Therefore, in this embodiment, when the number of continuously writable sectors is K, the size of the input register 16 must be K times the sector capacity.

In this continuous writing process, following the command "1stCom" of the continuous writing process from the host, the addresses of the K sectors to be written continuously are input collectively. These address data are stored in the address buffer or the input register 16 for the address, and are sent to the address decoder one by one under the control of the system control circuit 20 in accordance with the write processing for each sector.

After the input of the address data is completed, the write data “Data” for one sector to be written first is next written.
In1 ”is transferred, and then the write start command“ 2ndCo
m ”is input and the flow shifts to the write operation.

When the operation shifts to the write operation, in this embodiment, the transfer from the next second write data to the last K-th write data "DataIn2 to DataInK" is performed collectively. These write data are stored in the input register 16 one by one.

When the operation shifts to the write operation, the second and subsequent write data sequentially transferred to the input register 16 and the second and subsequent addresses stored in the address buffer or the address input register 16 are used. The second to K-th writings are executed one by one. When all the writing to the sector specified by the previously input address is completed, a write end flag is set in the status register, and the host side is notified that the next writing process is possible.

According to such a continuous writing process, the time required for the writing process is “Y + X × K”, which is equivalent to the continuous writing process of FIG. 2, but the host side continuously transfers data for K sectors at the maximum. Therefore, the flash memory 1 can be released from the write process before the flash memory 1 completes the write operation, that is, in the data transfer time “Y × K”. Thereby, the load on the host side can be reduced.

In this writing process, the size of the input register 16 is set to the capacity of the sector in which continuous writing is possible. However, the input register 16 is overwritten with a new writing data in the storage area of the writing data where writing has been completed. By effectively using 16, it is possible to make the size of the input register 16 smaller than the capacity of a continuously writable sector and perform the same processing as the above-described writing processing. In addition, continuous writing can be performed in the above-described manner even when writing data to a number of sectors smaller than K. In the above-described continuous writing process, there are some modified examples in the arrangement configuration of the input register 16 and the data transfer method. Can be considered. An example is shown below.

FIG. 6 is a configuration diagram showing a first modification of the arrangement configuration of the input register 16.

In this modification, data registers 1 to 3 each having a capacity of one sector are arranged along the word line direction.
The data registers K are arranged side by side on one side of the memory array 11. Then, after storing the data in the data register, the data is finally stored in the write data register 15a while shifting the data by one sector in the data line direction. According to such a configuration, the write data register 15a
There is an effect that data transfer to the memory can be performed at high speed in sector units.

FIG. 7 shows a second arrangement of the input register 16.
It is a block diagram which shows a modification.

In this modification, the K data registers shown in FIG. 6 are arranged on both sides of the memory array 11 in half. The write data is stored in the input register 16 alternately in the blocks on both sides.
The write data is alternately transferred from the data registers on both sides to the write data register 15a to perform a write process on the memory array 11, and the write data register 15
After the data transfer to the data register a, the write data stored in the data register on the transfer side is shifted one by one to the inner data register. Also in this embodiment, an effect is obtained that data transfer from the input register 16 to the write data register 15a can be performed at high speed in sector units.

Next, a description will be given of a continuous boosting write process in which the boosting circuit 18 is continuously boosted when data writing over a plurality of sectors is performed continuously.

FIG. 8 is a time chart showing the operation of the continuous boost writing process, and FIG. 9 is a flowchart showing the flow of a control procedure of the continuous boost writing process executed by the system control circuit 20.

The continuous step-up write processing is started when a continuous step-up write command "1stCom" for instructing the continuous step-up write processing is input from the host. The system control circuit 20 continues the continuous step-up writing process for continuously driving the step-up circuit 18 until a reset command “ResetCom” is input after this continuous step-up write command.

After the above command "1stCom",
Write destination address “SA1”, “SA2” from host
, Transfer of write data “DataIn1”, and input of a write start command “2ndCom” for instructing start of writing to the memory array 11 are sequentially performed.

When the first write start command “2ndCom” is input after the input of the continuous boost write command “1stCom”, the control shown in FIG. 9A is performed by the system control circuit 20 of the flash memory 1. That is, first, preparations are made for a write process such as activation of the booster circuit 18 and data transfer from the input register 16 to the write data register 15a (step S1), and then the process waits until the internal power supply is turned on (step S2). When the internal power supply is turned on, the application of the write bias (step S3) and the write verify (step S4) are repeated to write to the designated sector. Then, when the writing is confirmed, for example, a writing operation completion flag is set in the status register, and a ready / busy signal R / B is output, for example, so that the state can be shifted to the next writing process (step S).
5).

In a normal write command, the operation of the booster circuit 18 is stopped at this time. However, in the case of a continuous boost write command, the booster circuit 18 is not stopped. Moreover,
In the case of this command, FIG.
(B), as shown in FIG. 9 (b), without input of the continuous boost write command “1stCom”, the address “SA” of the next sector
1 "," SA2 ", write data" Da "of the next sector
The transfer of “taIn2” and the input of a write start command “2ndCom” for instructing the start of writing of the write data are sequentially performed.

Then, the system control circuit 20 prepares for write processing such as storing input write data in the write data register 15a (step S6), and then applies a write bias voltage to the word line (step S7). )
Writes to the specified sector. Thereafter, a write verify is performed (step S8), and when the write is confirmed, for example, a flag of a write operation completion is set in a status register, for example, so that the state can be shifted to the next write processing (step S9).

After the above write processing, FIG.
(C), when the reset command “ResetCom” is input from the host side as shown in FIG. 9 (c) (step S13)
The system control circuit 20 stops the booster circuit 18 and waits for the fall of the internal power supply (step S14), and sets a flag indicating the end of the writing process in the status register (step S15).

According to such a continuous boost writing process,
Since the rise and fall of the internal power supply are performed only once each in the write processing for K sectors, the normal write including the rise and fall time γ (= α + β) of the internal power supply is performed. Assuming that the time is X, the time required for the write processing of the K sector is “(Y + X) × K−γ × (K−1)”, and the normal rise and fall of the internal power supply is performed every time one sector is written. From the time ((Y + X) × K) required to perform write processing for K sectors in the write processing, “γ × (K−
1) ".

Note that this continuous step-up write processing is performed in accordance with FIGS.
It can be applied to the continuous writing process of FIG. When the continuous boost writing process is applied to the continuous writing process, a command for the continuous boost writing process is not separately provided as a command code sent from the host.
Only a command for a continuous write process is provided, and when a continuous write command is input, a process in which the above-described continuous boost write process and the continuous write process are combined as described below is performed. Can be done.

FIG. 10 is a time chart showing an example of a write process in which the continuous write process of FIG. 2 and the above-mentioned continuous boost write process are combined.

In this writing process, the internal power supply (the booster circuit 18) is turned on at the time of writing the first sector, and after the writing is completed, the internal power supply is not turned off, and the second and subsequent writing processes are performed as it is. After the writing of the sector is completed, the internal power supply is turned off. The time required for the writing process is “Y + X × K−γ × (K−1)”, which is reduced by “(Y + γ) × (K−1)” as compared with the normal writing process.

Further, in the above-described embodiment, a case has been described in which an address is input each time during the above-described continuous writing process. However, an address counter is provided for row-related sector addresses, and data is stored in continuous sectors. When performing writing, an address generation command and an address are input when writing the first sector, and when writing data for the second and subsequent times, data is written to the sector specified by the address automatically generated by the address counter. May be performed.

The provision of such an address automatic generation function in the memory eliminates the need for the second and subsequent address inputs from the host, thereby further reducing the time for write processing and reducing the load on the host.

As described above, according to the flash memory 1 of the present embodiment, in a continuous write process over a plurality of sectors, the time of the total write process including the data input and the write operation is reduced. The effect that can be obtained is obtained. Further, since the write processing time is shortened, the load on the host side for performing the write processing in the flash memory 1 can also be reduced.

The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

For example, in the above embodiment, the continuous writing process and the normal writing process can be selectively executed by discriminating them by the command code input from the host. However, only the continuous writing process is performed without performing the normal writing process. It is good also as composition which performs. When writing data of one sector in such a configuration, a reset command may be input after the first data transfer. Further, the present invention can be similarly applied to a memory capable of storing multi-valued data of two or more values in one memory cell.

In the above description, the invention made by the present inventor has been mainly described with respect to a flash memory which is a field of application as a background. However, the present invention is not limited to this, and has a control gate and a floating gate. It can be widely used in a nonvolatile semiconductor memory device having a memory array composed of nonvolatile storage elements and writing data in a unit larger than the data unit at the time of reading.

[0074]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, according to the present invention, in continuous write processing over a plurality of sectors, there is an effect that it is possible to shorten the time of the comprehensive write processing including the data input and the write operation. Further, since the write processing time is shortened, there is an effect that the waiting time on the host side for causing the nonvolatile semiconductor memory device to perform the write processing can be shortened.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a preferred embodiment of a flash memory to which the present invention is applied.

FIG. 2 is a time chart illustrating a first example of a continuous write process of the flash memory according to the embodiment;

FIG. 3 is a time chart showing a second example of the continuous writing process of the flash memory according to the embodiment.

FIG. 4 is a time chart showing a third example of the continuous writing process of the flash memory according to the embodiment.

FIG. 5 is a time chart showing a fourth example of the continuous writing process of the flash memory of the embodiment.

FIG. 6 is a configuration diagram showing a first modification of the arrangement configuration of the input register 16;

FIG. 7 is a configuration diagram illustrating a second modification of the arrangement configuration of the input register 16;

FIG. 8 is a time chart illustrating an operation of a continuous boost writing process of the flash memory according to the embodiment.

FIG. 9 is a flowchart illustrating a flow of a control procedure of a continuous boost write process executed by the system control circuit of the flash memory according to the embodiment.

FIG. 10 is a time chart showing an example in which a continuous boost write process is applied to the continuous write process of FIG. 2;

FIG. 11 is a time chart showing a conventional write operation of a flash memory.

FIG. 12 is a flowchart showing a flow of a control procedure of a conventional flash memory write operation.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Flash memory 9 Write data register 11 Memory array 12 Decoder circuit 13 Y gate 15 Write control circuit 16 Input register 17 Address counter 18 Boost circuit 20 System control circuit (control unit)

 ──────────────────────────────────────────────────の Continued on the front page (72) Inventor Toshifumi Noda 6-16-16 Shinmachi, Ome-shi, Tokyo 3 Inside the Device Development Center, Hitachi, Ltd. (72) Inventor Hiroshi Sato 6--16 Shinmachi, Ome-shi, Tokyo 3 F-term in Hitachi, Ltd. Device Development Center (reference) 5B025 AA03 AB01 AC01 AD01 AD04 AD10 AE05

Claims (5)

[Claims] 1. A MOS having a control gate and a floating gate, wherein data is written and erased by injecting or discharging electric charges into or from the floating gate.
In a nonvolatile semiconductor memory device including a plurality of memory cells made of FETs, the plurality of memory cells are divided into predetermined sectors and a write operation can be performed for each sector, and the plurality of memory cells are handled in one write operation. A register capable of storing data twice or more the amount of data is provided, and while write data input from outside and stored in the register is written to one sector, write data to another sector is written from outside. A nonvolatile semiconductor memory device configured to be able to take in and store in a register. And a control unit that identifies a first write command and a second write command input from the outside and can execute a write process corresponding to each command, wherein the first write command is input. In this case, while writing the data that has already been read, the write data of another sector is taken in from the outside, while if the second write command is input, the data writing by the command is terminated. 2. The apparatus according to claim 1, wherein a write process based on a second write command is performed.
14. The nonvolatile semiconductor memory device according to claim 1. 3. A MOS having a control gate and a floating gate, wherein data is written and erased by injecting or discharging charges into or from the floating gate.
A plurality of memory cells each composed of an FET, the plurality of memory cells are divided into predetermined sectors, and each sector is configured to be capable of a write operation, and a booster circuit generates an internal voltage higher than an external power supply voltage. In the nonvolatile semiconductor memory device used for the write operation, when writing to a plurality of sectors, the boosting operation of the booster circuit is started at the time of the first write operation, and then the write operation to the other sector is completed. A non-volatile semiconductor memory device characterized in that the boosting operation is continued and the boosting operation of the boosting circuit is stopped after the writing operation of all the plurality of sectors is completed. 4. A control unit capable of identifying a first write command and a second write command input from the outside and executing a write process corresponding to each command, wherein the first write command is input. In this case, while the data is being written to the plurality of sectors, the boosting operation is continued while the second
4. When a write command is input, the booster circuit is activated at the start of writing to the corresponding sector, and the boosting operation is stopped after the writing of the sector is completed. 14. The nonvolatile semiconductor memory device according to claim 1. 5. An address counter for generating a continuous sector address, wherein when sequentially writing data to a plurality of sectors having continuous addresses, the address of the first sector input from the outside is set in the address counter. ,
2. The address of the next sector is configured to be generated by the address counter.
5. The nonvolatile semiconductor memory device according to any one of items 1 to 4.