JP2001284548A - Semiconductor memory device and producing method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent oxidization between the lower electrode of a capacitor and a plug. SOLUTION: A hole 18 is formed on an insulating film 17, a barrier metal layer 19a is formed on the inner surface of the hole 18 and the upper surface of the insulating film 17, and a tungsten layer 19b is formed on the barrier metal layer 19a inside the hole 18 by CVD. Then, the tungsten layer 19b and the barrier metal layer 19a are removed from the upper surface of the insulating film 17 by either grinding or etching, the tungsten layer 19b is left inside the hole 18 in the state of making a recessed part 18a existent at the upper part inside the hole 18, and a contact metal layer 19c is formed inside the insulating film 17 and the recessed part 18a. Then, the contact metal layer 19c is removed from the upper surface of the insulating film 17 and left only inside the recessed part 18a by either grinding or etching, a ferroelectric capacitor 20 is formed thereon and further, the capacitor 20 is annealed in the oxygen-containing atmosphere.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly, to a semiconductor memory device including a ferroelectric and a high dielectric capacitor and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, FeRAM has been used as a memory device such as an IC card. As a cell structure of the FeRAM, for example, there is one having a structure as shown in FIG. In FIG. 1, a MOS transistor 2 is provided on a silicon substrate 1.
Is formed, and a capacitor Q is formed thereon.

The MOS transistor 2 has a gate electrode (word line) 2b formed on a silicon substrate 1 via a gate insulating film 2a, and an impurity diffusion layer 2c formed on the silicon substrate 1 on both sides of the gate electrode 2b. , 2d. In addition, a polysilicon plug 5 is buried in a hole 4 formed in the SiO ₂ interlayer insulating film 3 covering the MOS transistor 2, and the plug 5 is connected to the impurity diffusion layer 2 c of the silicon substrate 1. A first iridium oxide (IrO ₂ ) film 6a partially connected to the plug 5 is formed on the SiO ₂ interlayer insulating film 3, and a first iridium (Ir) film 6b is formed thereon. A second iridium oxide film 6c,
A PZT ferroelectric film 7, a third iridium oxide film 8a, and a second iridium film 8b are sequentially formed.

The first IrO ₂ film 6a, the first Ir film 6b, and the second IrO ₂ film 6c are patterned into a predetermined size to form the lower electrode 6 of the capacitor Q, and a PZT ferroelectric material. The film 7 is patterned into a predetermined size to form a capacitor Q
And a third iridium oxide film 8
a, the second iridium film 8b is also patterned into a predetermined size to form the upper electrode 8 of the capacitor Q.

The structure in which the capacitor Q is formed directly above the polysilicon plug 5 is described in, for example, 1999, Symp
osium on VLSI Technology Digest of Technical Paper
s, pp. 141-142. Polysilicon, which is a material of a plug described in this document, has a higher resistance than tungsten, and is not suitable for mixed mounting with a logic device.

[0006]

SUMMARY OF THE INVENTION The present inventor has attempted to employ, as a plug material, tungsten which has a low resistance and is easily mixed with a logic. In a semiconductor device having a design rule of 0.35 μm generation or later, the area where the plug contacts the impurity diffusion region of the MOS transistor is significantly reduced, and the surface contact resistance between the plug and the impurity diffusion region reaches, for example, 1 kΩ level, and the yield is deteriorated. It is said that it is indispensable to reduce the resistance at the contact surface by using a so-called salicide technique for converting the surface of the impurity diffusion region into a high melting point metal silicide.

However, if the process is simplified and plugs are to be formed in one step at a time in different regions of a memory cell device, a logic device, or the like, all the regions where the plugs are to be formed on the same semiconductor substrate surface are made of high melting point metal silicide. I have to do it. In this case, the design rule is 0.35 μm
The miniaturization introduced in future generations of devices will also reduce the width of the window in which the plug is built, while the thickness of the interlayer dielectric will maintain the insulation performance and avoid mutual interference between wiring layers. However, there is no other way but to secure a certain thickness, and as a result, the opening of the plug hole is narrow and the depth is high, resulting in a high aspect ratio. It is not possible to form tungsten for such high aspect ratio holes using sputtering.

For example, as shown in FIG. 2A, a barrier metal film 9 is formed along the upper surface of the interlayer insulating film 3 and the inner surface of the hole 4.
Is formed, a tungsten film 10 is formed on the barrier metal film 9. However, if the tungsten film 10 is to be filled with a high aspect ratio hole by sputtering, the void 10a is formed in the hole 4.
Inevitably occur.

When the tungsten on the SiO2 insulating film is to be removed by CMP in a state where the void 10a is present, as shown in FIG. And the reliability decreases. Alternatively, as shown in FIG.
After forming the T ferroelectric film 7 and the like, when the capacitor Q is heated at a high temperature of 500 to 700 ° C. in an oxygen atmosphere for PZT characteristic development, the void 10 a ruptures and the layer forming material is Scattering can cause catastrophic damage to device performance, which in turn can reduce yield.

On the other hand, it is impossible to use a high-temperature and high-pressure sputtering method for a fine device in order to prevent the generation of voids. Excessive temperatures and pressures can stress other areas of the device and reduce yield. If extra heat is applied, silicidation will proceed deeply until the metal penetrates below the source / drain regions formed by, for example, introducing shallow impurities to speed up the logic device, possibly causing junction breakdown. Is also expensive.

[0011] Tungsten to be used as a plug is more easily oxidized than polysilicon, and if an IrO ₂ film is formed directly on tungsten, the contact resistance increases. Therefore, as the bottom layer of the lower electrode, further TiN under the IrO ₂ film, WN, TaN,
A conductive film of Ta, AlSiN or TaSiN is formed, and IrO ₂
It is conceivable to reduce the contact resistance between the film and the tungsten plug.

However, as shown in FIG. 3, when a material film which is easily oxidized, for example, a TiN film 6d is employed as the lowermost layer of the lower electrode, the PZT ferroelectric film 7 is recovered from the damage caused by the etching to prevent the oxygen atmosphere from being damaged. When annealing is performed, oxygen is supplied from the side direction of the TiN film 6d to oxidize the TiN film 6d, so that the thickness of the side portion increases and the capacitor constituent film is distorted. For example, 700 in an oxygen atmosphere
When annealing is performed at 20 ° C. for 20 minutes, the TiN film 6 d is oxidized inward from the side surface by about 0.2 μm.

[0013] The oxidation occurs, the film thickness of the peripheral portion of the TiN film 6d is locally increased, IrO ₂ film 6a thereon
Etc. are impaired. Such oxidation occurs when any of WN, TaN, Ta, AlSiN is used instead of TiN. Here, the Ir film 6b constituting the lower electrode 6 is made of PZT
Since it has a function of absorbing oxygen passing through the ferroelectric film 7, it has a function of suppressing oxidation of the underlying film 6d of TiN, WN, TaN, Ta, AlSiN, TaSiN, and W. Oxidation from water cannot be suppressed.

An object of the present invention is to provide a semiconductor memory device capable of forming a tungsten plug while suppressing the generation of voids and preventing oxidation between a capacitor lower electrode and a plug, and a method of manufacturing the same. It is in.

[0015]

SUMMARY OF THE INVENTION An object of the present invention is to provide an insulating film formed on a semiconductor substrate, a hole formed in the insulating film, and a recess in the hole. A tungsten layer, a capacitor composed of a lower electrode having iridium oxide formed on an insulating film, a ferroelectric film and an upper electrode, and a contact resistance between the lower electrode and the tungsten layer embedded in the recess of the hole. The problem is solved by a semiconductor memory device having a reduced contact metal layer.

In the above-described semiconductor memory device, the semiconductor memory device may include an iridium layer formed on the contact metal layer in the recess. Further, the above-mentioned problems include a step of forming an insulating film on a semiconductor substrate, a step of forming a hole in the insulating film, a step of forming a barrier metal layer on the inner surface of the hole and the upper surface of the insulating film, Forming a tungsten layer on the layer by a CVD method, filling the tungsten layer into the hole, removing the tungsten layer and the barrier metal layer from the upper surface of the insulating film by either polishing or etching back, Leaving a tungsten layer in the hole with a recess in the upper portion of the inside, forming a contact metal layer in the insulating film and the recess, and polishing or etching back the contact metal layer on the insulating film. A step of removing from the concave portion and leaving only in the concave portion, a lower electrode, a ferroelectric layer, and an upper electrode formed on the hole and having iridium oxide. It is solved by a method of manufacturing a semiconductor memory device and a step of forming a Ranaru capacitor. In this case, the capacitor may be annealed in an oxygen-containing atmosphere after the formation of the capacitor.

In the method for manufacturing a semiconductor memory device described above, before or after removing the contact layer from the insulating film, a step of forming an iridium layer on the contact layer;
The method may further include a step of removing the iridium layer from the insulating film by any one of the etch backs and leaving the iridium layer only on the contact metal layer in the concave portion. Note that the contact metal described above is selected from titanium nitride, tungsten nitride, tantalum nitride, tantalum, aluminum silicon nitride, and tantalum silicon nitride.

According to the present invention described above, the contact metal layer formed between the tungsten layer forming the plug in the hole of the insulating film and the lower electrode of the capacitor is buried in the upper part of the hole. Thus, even if the capacitor is annealed in an oxygen-containing atmosphere, the contact metal layer does not come into contact with oxygen, and an increase in the thickness of the contact metal layer is prevented.

In addition, iridium is buried on the contact metal layer in the hole. This eliminates the need for adopting a structure in which an iridium layer is sandwiched between iridium oxide layers as a capacitor lower electrode as in the related art, and the lower electrode is composed of only iridium oxide, thereby reducing the number of capacitor layers and reducing the number of capacitor layers. Coverage is improved.

Further, when a tungsten layer is formed in a hole of an insulating film, a CVD method is employed. Therefore, generation of voids in the tungsten layer in the holes is prevented.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention. (First Embodiment) FIG. 4A is a sectional view showing an FeRAM cell according to a first embodiment of the present invention. In FIG. 4A, a LOCOS layer 12 for defining a memory cell region is formed on a surface of a silicon (semiconductor) substrate 11,
In the memory cell region, a gate electrode 13a also serving as a word line WL is formed on the silicon substrate 11 via a gate insulating film 13b. Also, on both sides of the gate electrode 13a in the silicon substrate 11, an impurity diffusion layer 13c,
13d is formed. The gate electrode 13, the impurity diffusion layers 13c and 13d, etc.
Constituting No. 3.

MOS transistor 13, silicon substrate 1
1. The LOCOS layer 12 is a first insulating film 1 made of SiO2.
4. Covered by the second insulating film 15, the first and second insulating films 14 and 15 have the first hole 16 formed first.
And the bit line BL is connected to the first impurity diffusion layer 13c. Further, a third insulating film 17 made of SiO2 is formed on the bit line BL and the second insulating film 15.

The first to third insulating films 14, 15, 1
7, a second hole 18 is formed on the second impurity diffusion layer 13d. On the inner surface of the second hole 18, a barrier metal film 19a having a two-layer structure in which titanium and titanium nitride are sequentially formed is formed. In the second hole 18, a tungsten film 19b and a A plug 19 made of a contact metal layer 19c formed thereon is buried. Contact metal layer 19c
Are, for example, titanium nitride (TiN), tungsten nitride (W
N), tantalum nitride (TaN), tantalum (Ta), aluminum silicon nitride (AlSiN), or tantalum silicon nitride (TaSiN).

Further, on the third insulating film 17, FIG.
As shown in FIG. 2B, a lower electrode 21, a ferroelectric film 22, and an upper electrode 23 constituting the capacitor 20 are sequentially formed.
The lower electrode 21 is a contact metal layer 1 of the plug 19.
9c. The lower electrode 21 includes a first iridium oxide (IrO ₂ ) layer 21 a connected to the plug 19,
A first iridium (Ir) layer 21 sequentially formed thereon
b and the second iridium oxide layer 21c.
As the ferroelectric film 22, a film such as PZT, PLZT, or STB is applied. The upper electrode 23 is composed of a third iridium oxide layer 23a and a second iridium layer 23b formed in order from the bottom.

Further, the capacitor 20 and the third insulating film 17
An insulating protective film 24 is formed thereon, and a hole 2 is formed thereon.
A wiring 25 connected to the upper electrode 23 of the capacitor 20 through 4a is formed. In the memory cell having the above structure, the contact metal layer 19 made of TiN or the like is formed on the tungsten layer 19b forming the plug 19.
c, the first iridium oxide layer 21a and the tungsten layer 1a are formed by the contact metal layer 19c.
The electrical resistance during 9b is reduced. Moreover, the contact metal 19c, which is easily oxidized, is formed in the second hole 1
8 and is isolated from the outside by the capacitor 20, so that the ferroelectric film 22 of the capacitor 20
Is no longer oxidized when oxygen is annealed.

In the lower electrode 21, the first iridium oxide film 21a is omitted and the first iridium layer 21 is formed.
b may be formed directly on the third insulating film 17. The formation of the above-described plug 19 will be described in the following second and third embodiments. (Second Embodiment) FIGS. 5A to 5D show a second embodiment of the present invention.
FIG. 5 is a cross-sectional view illustrating a step of forming a plug of the memory cell according to the embodiment, and is a cross-sectional view taken along line II of FIG. 4.

The steps up to the state shown in FIG. 5A will be described. First, after the first to third insulating films 14, 15, and 17 covering the silicon substrate 11 are sequentially formed, the impurity diffusion layers 13d are patterned by photolithography.
A hole 18 having a diameter of 500 nm is formed on the substrate. The third insulating film 17 made of SiO2 is formed by a plasma CVD method using TEOS gas.

Subsequently, a 10-nm-thick titanium layer and a 50-nm-thick titanium nitride layer are successively formed on the inner surface of the hole 18 and the third insulating film 17 by sputtering, and this is used as a barrier metal layer 19a. . Further, a tungsten layer 19b is formed on the barrier metal layer 19a by CVD using tungsten hexafluoride (WF ₆ ) gas to form a hole 1
Embed in 8. As the growth conditions of the tungsten layer 19c, the growth atmosphere pressure is 0.8 Torr and the growth temperature is 40
0 ° C., and the gas flow rate of the WF ₆ gas was 300 sccm,
The flow rate of hydrogen (H ₂ ) gas is set to 3 slm, and no void is generated in the tungsten layer 19 c in the hole 18.

Next, as shown in FIG. 5B, the tungsten layer 19b and the barrier metal layer 19a on the third insulating film 17 are removed by a CMP method, and a dishing portion 18a is formed on the inside of the hole 18. I do. In order to form the dishing portion 18a, a soft polishing cloth such as SUBA400 (Rotel) is used in the CMP method.
Subsequently, as shown in FIG.
One of N, WN, TaN, Ta, AlSiN, and TaSiN is used as a contact metal layer 19c in the dishing portion 18a and the third metal.
It is formed on the upper surface of the insulating film 17.

Next, as shown in FIG. 5 (d), the contact metal layer 19c is polished and flattened by using OC1000 (Rotel) as a hard polishing cloth to obtain a third
The contact metal layer 19c is removed from the upper surface of the insulating film 17, and the contact metal layer 19c is left so as to fill the dishing portion 18a. Hall 1
The formation of the plug 19 in 8 is completed.

Thereafter, the IrO ₂ layer 21a, Ir layer 21b and IrO ₂ layer 21 constituting the lower electrode 21 as shown in FIG.
c is formed in order, a ferroelectric film 22 is formed thereon, and further thereon, IrO ₂ layers 23 a and Ir forming an upper electrode 23 are formed.
The layer 23b is formed in order. IrO ₂ layers 21a, 21c, 23
a and the Ir layers 21b and 23b are formed by sputtering.
PZT constituting the ferroelectric film 22 is formed by a sol-gel method.

After the PZT is formed, annealing is performed in an oxygen atmosphere to crystallize the PZT. Further, the lower electrode 21, the PZT ferroelectric film 22, the upper electrode 2
After the films 3 were formed, they were patterned by photolithography into the shape of a capacitor as shown in FIG. 4B, and then the capacitor 20 was annealed in an oxygen atmosphere at a temperature of about 700.degree. To recover.

As shown in FIG. 4B, the memory cell formed by the above steps has a tungsten layer 19b forming the plug 19 and an IrO ₂ forming the lower electrode 21.
Since contact metal layer 19c formed between layers 21a is completely buried in hole 18, contact metal layer 19c is not oxidized even if high-temperature annealing is performed in an oxygen-containing atmosphere after formation of the capacitor. . As a result, lifting around the lower electrode 21 after the capacitor is formed as shown in FIG. 3 is eliminated.

Further, since the tungsten layer 19b constituting the plug 19 is formed by the CVD method, voids are not generated in the tungsten layer 19b in the hole 18, so that contamination of the plug 19 and contamination of the plug 19 can be prevented. Rupture is prevented. (Third Embodiment) In this embodiment, a method of forming a plug different from that of the second embodiment will be described with reference to FIGS. 6 (a) to 6 (d). In FIG. 6, the same reference numerals as those in FIG. 5 indicate the same elements.

First, as shown in FIG. 6A, first to third insulating films 14, 15, 17 covering the silicon substrate 11 are sequentially formed, and then patterned by photolithography to form the impurity diffusion layer 13d. A hole 18 is formed thereon. Subsequently, a titanium layer and a titanium nitride layer are successively formed on the inner surface of the hole 18 and the third insulating film 17 by sputtering, and this is used as a barrier metal layer 19a. Further, C
A tungsten layer 19b is formed on the barrier metal layer 19a by the VD method and buried in the hole 18.

The method and conditions for forming these layers are the same as in the second embodiment. Next, as shown in FIG. 6B, the tungsten layer 19b and the barrier metal layer 19a on the third insulating film 17 are removed by etch-back, and a trench 18 having a depth of about 200 nm is formed above the hole 18.
b is formed. As the etching conditions in this case, for example,
A mixed gas of SF ₆ and N ₂ is used.

Subsequently, as shown in FIG. 6C, any one of TiN, WN, TaN, Ta, AlSiN, and TaSiN is used as a contact metal layer 19c by a sputtering method.
8 a and on the upper surface of the third insulating film 17. Next, as shown in FIG.
The contact metal layer 19c is removed from the upper surface of the third insulating film 17 by polishing and flattening the contact metal layer 19c using (Rotel).
The contact metal layer 19c is left so that dishing does not occur in the dishing portion 18a.

Thus, the formation of the plug 19 in the hole 18 is completed. Thereafter, the capacitor 20 is formed by the steps described in the second embodiment. According to the above steps, as shown in FIG. 4B, the tungsten layer 19b forming the plug 19 and the Ir forming the lower electrode 21 are formed.
Contact metal layer 19c formed between O ₂ layers 21a
Is buried in the hole 18, so that the contact metal layer 19c is not oxidized even if high-temperature annealing is performed in an oxygen-containing atmosphere after the formation of the capacitor. Therefore, lifting around the lower electrode 21 after the capacitor is formed as shown in FIG. 3 is eliminated.

Since the tungsten layer 19b constituting the plug 19 is formed by the CVD method, no void is generated in the tungsten layer 19b in the hole 18 and
The contamination of the plug 19 with the waste and the rupture of the plug 19 during heating are prevented. (Fourth Embodiment) FIG. 7A is a sectional view showing an FeRAM cell according to a first embodiment of the present invention, and the same reference numerals as those in FIG. 4A indicate the same elements.

In FIG. 7A, an LO for partitioning a memory cell region is provided on the surface of a silicon (semiconductor) substrate 11.
A COS layer 12 is formed, and a gate electrode 13a also serving as a word line WL is provided in a silicon substrate 11 in the memory cell region.
It is formed thereover via a gate insulating film 13b. Further, impurity diffusion layers 13c and 13d are formed on both sides of the gate electrode 13a in the silicon substrate 11.
The gate electrode 13 and the impurity diffusion layers 13c and 13d
Etc. constitute the MOS transistor 13.

MOS transistor 13, silicon substrate 1
1. The LOCOS layer 12 is a first insulating film 1 made of SiO2.
4. Covered by the second insulating film 15, the first and second insulating films 14 and 15 have the first hole 16 formed first.
And the bit line BL is connected to the first impurity diffusion layer 13c. Further, a third insulating film 17 made of SiO2 is formed on the bit line BL and the second insulating film 15.

Then, the first to third insulating films 14, 15, 1
7, a second hole 18 is formed on the second impurity diffusion layer 13d. On the inner surface of the second hole 18, a barrier metal film 30 a having a two-layer structure in which titanium and titanium nitride are formed in this order is formed. In the second hole 18, a tungsten film 30 b and a tungsten film 30 b are formed. The contact metal layer 30c and the iridium layer 30d formed thereon are sequentially formed, and the plugs 30 are buried in the holes 18. The contact metal layer 30c is formed of, for example, any one of TiN, WN, TaN, Ta, AlSiN, and TaSiN.

Further, on the third insulating film 17, FIG.
As shown in (b), a lower electrode 32, a ferroelectric film 33, and an upper electrode 34 constituting the capacitor 31 are sequentially formed. The lower electrode 32 is made of a first iridium oxide (IrO ₂ ) layer, and the ferroelectric film 33 is made of PZT, PLZT, S
The upper electrode 34 includes an iridium oxide layer 34a and an iridium layer 3 formed in this order from the bottom.
4b.

Further, the capacitor 31 and the third insulating film 17
An insulating protective film 24 is formed thereon, and a hole 2 is formed thereon.
The wiring 25 connected to the upper electrode 34 of the capacitor 31 through 4a is formed. In the memory cell having the above structure, the contact metal layer 30 made of TiN or the like is formed on the tungsten layer 30b forming the plug 30.
Since c and the iridium layer 30d are formed, the electrical resistance between the iridium layer 30d and the tungsten layer 30b is reduced by the contact metal layer 19c. Moreover,
The contact metal 30c, which is easily oxidized,
The contact metal layer 30c is not oxidized when the ferroelectric film 33 of the capacitor 31 is subjected to oxygen annealing because it is formed only in the hole 18 and is shielded from the outside by the capacitor 31.

Further, in order to prevent oxidation of contact metal layer 30c, iridium layer 30 formed thereon is
Since d is also left only in the hole 18, iridium oxide formed for improving the adhesion between iridium and the third insulating film is further unnecessary. The formation of the plug 30 will be described in the following fifth and sixth embodiments. (Fifth Embodiment) FIGS. 8A to 8D show a fifth embodiment of the present invention.
FIG. 8 is a cross-sectional view illustrating a step of forming a plug of the memory cell according to the embodiment, and is a cross-sectional view taken along line II-II of FIG. 7.

The steps up to the state shown in FIG. 8A will be described. This step is the same as that described in the second embodiment. That is, after the first to third insulating films 14, 15, and 17 covering the silicon substrate 11 are sequentially formed, the impurity diffusion layer 13 is patterned by photolithography.
A hole 18 is formed on d. Subsequently, a titanium layer and a titanium nitride layer are successively formed on the inner surface of the hole 18 and the third insulating film 17 by sputtering, and this is used as a barrier metal layer 30a. Further, a tungsten layer 30b is formed on the barrier metal layer 30a by the CVD method to form a hole 1
Embed in 8.

Next, as shown in FIG. 8B, the tungsten layer 30b and the barrier metal layer 30a on the third insulating film 17 are removed by etch back, and the holes 18 are removed.
A recess 18c having a depth of about 300 nm is formed on the inside.
Subsequently, as shown in FIG.
Any of N, WN, TaN, Ta, AlSiN, and TaSiN is used as a contact metal layer 30c in the recess 18c and the third insulating film 1
7, after forming on the upper surface, an iridium layer 30d is formed to a thickness of 300 nm by a sputtering method.

Next, as shown in FIG. 8 (d), the contact metal layer 30c and the iridium layer 30d are polished and flattened by using IC1000 (Rotel) as a hard polishing cloth, so that the third insulating layer is formed. The layers 30c and 30d are removed from the upper surface of the film 17, and the layers 30c and 30d are left so as to fill the concave portions 18a. Thus, the formation of the plug 30 in the hole 18 is completed.

Thereafter, an IrO ₂ layer constituting the lower electrode 32 as shown in FIG. 7B is formed, and the ferroelectric film 3 is formed thereon.
3 is formed, and Ir is further formed thereon to form the upper electrode 34.
O ₂ layer 34a, an Ir layer 34b are sequentially formed. The IrO ₂ layer and the Ir layer are formed by a sputtering method, and PZT constituting the ferroelectric film 33 is formed by a sol-gel method.

After the PZT is formed, annealing is performed in an oxygen atmosphere to crystallize the PZT. Further, the lower electrode 32, the PZT ferroelectric film 33, and the upper electrode 3
After the films 4 are formed, they are patterned by photolithography into the shape of the capacitor 31 as shown in FIG. 7 (b).
1 is annealed at a temperature of about 700 ° C. to recover the capacitor characteristics.

As shown in FIG. 7B, the memory cell formed by the above steps has a tungsten layer 30b forming the plug 30 and an IrO ₂ forming the lower electrode 32.
Since the contact metal layer 19c formed between the layers is completely buried in the hole 18, the contact metal layer 30c is not oxidized even if high-temperature annealing is performed in an oxygen-containing atmosphere after formation of the capacitor. As a result, lifting around the lower electrode 21 after the capacitor is formed as shown in FIG. 3 is eliminated.

Further, since the iridium layer 30d constituting the lower electrode of the capacitor in the first embodiment is buried in the hole 18, it is not necessary to form the iridium oxide film formed as the lowermost layer of the lower electrode. Thus, the capacitor can be made thinner. Further, since the tungsten layer 30b constituting the plug 30 is formed by the CVD method, voids are not generated in the tungsten layer 30b in the hole 18, and contaminants are mixed into the plug 30 and the plug 30 is ruptured when heated. Is prevented. (Sixth Embodiment) In this embodiment, a method of forming a plug different from that of the fifth embodiment will be described with reference to FIGS. 9 and 10, the same reference numerals as those in FIG. 8 indicate the same elements.

First, as shown in FIG. 9A, first to third insulating films 14, 15, 17 covering the silicon substrate 11 are sequentially formed, and then patterned by photolithography to form the impurity diffusion layer 13d. A hole 18 is formed thereon. Subsequently, a titanium layer and a titanium nitride layer are successively formed on the inner surface of the hole 18 and the third insulating film 17 by sputtering, and this is used as a barrier metal layer 30a. Further, a tungsten layer 30b is formed on the barrier metal layer 30a by CV.
It is formed by the method D and buried in the hole 18.

The method and conditions for forming these layers are the same as in the second embodiment. Next, as shown in FIG. 9B, the tungsten layer 30b and the barrier metal layer 30a on the third insulating film 17 are removed by polishing, and the holes 18 are removed.
Leave only within. During the polishing, a hard polishing cloth
C1000 (Rotel) is used. Next, FIG.
As shown in (1), the upper portion of the tungsten layer 30b and the barrier metal layer 30a in the hole 18 is removed by etch back to form a concave portion 18d having a depth of about 300 nm. As an etching condition in this case, for example, an argon gas is used.

Then, as shown in FIG. 9D, any one of TiN, WN, TaN, Ta, AlSiN, and TaSiN is used as a contact metal layer 30c by sputtering to form the inside of the recess 18d and the upper surface of the third insulating film 17. To a thickness of 300 nm. Next, as shown in FIG. 10A, the contact metal layer 30c is polished to leave only in the recess 18d.

Further, as shown in FIG. 10B, an iridium layer 30d is formed by a sputtering method so as to completely fill the recess 18d. Then, the iridium layer 30d formed on the third insulating film 17 is polished and removed as shown in FIG. Thus, the formation of the plug 30 in the hole 18 is completed. Thereafter, the capacitor 20 is formed by the steps described in the fifth embodiment.

According to the above steps, as shown in FIG. 7B, the tungsten layer 30 forming the plug 30 is formed.
b and the contact metal layer 30c formed between the IrO ₂ layers constituting the lower electrode 32 is buried in the hole 18, so that a high-temperature annealing treatment in an oxygen-containing atmosphere after the formation of the capacitor is performed. Even if this is done, the contact metal layer 19c will not be oxidized. Accordingly, lifting around the lower electrode 32 after the capacitor is formed as shown in FIG. 3 is eliminated.

Since the iridium layer 30d constituting the lower electrode of the capacitor in the first embodiment is buried in the hole 18, the iridium oxide film formed as the lowermost layer of the lower electrode is not required. Thus, the capacitor can be made thinner.

[0059]

As described above, according to the present invention, the contact metal layer formed between the tungsten layer forming the plug in the hole of the insulating film and the lower electrode of the capacitor is buried in the upper part of the hole. Therefore, even if the capacitor is annealed in an oxygen-containing atmosphere, the contact metal layer does not come into contact with oxygen, and an increase in the thickness of the contact metal layer can be prevented.

Since iridium is buried on the contact metal layer in the hole, it is not necessary to adopt a structure in which the iridium layer is sandwiched between the iridium oxide layers as the capacitor lower electrode as in the prior art. By using only iridium, the number of layers of the capacitor can be reduced, and the coverage on the insulating film can be improved.

Further, since the CVD method is used when forming the tungsten layer in the hole of the insulating film, it is possible to prevent the void from being generated in the tungsten layer in the hole.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a memory cell showing a conventional technique.

FIG. 2 is a cross-sectional view illustrating a process of forming a plug of a memory cell according to the related art.

FIG. 3 is a cross-sectional view showing a state of a conventional memory cell capacitor after oxygen annealing.

FIG. 4 is a sectional view of a memory cell according to the first embodiment of the present invention.

FIG. 5 is a sectional view showing a step of forming a memory cell plug according to a second embodiment of the present invention.

FIG. 6 is a cross-sectional view showing a step of forming a memory cell plug according to a third embodiment of the present invention.

FIG. 7 is a sectional view of a memory cell according to a fourth embodiment of the present invention.

FIG. 8 is a sectional view showing a step of forming a memory cell plug according to a fifth embodiment of the present invention.

FIG. 9 is a sectional view (No. 1) showing a step of forming a memory cell plug according to a sixth embodiment of the present invention.

FIG. 10 is a sectional view (part 2) illustrating a step of forming a memory cell plug according to the sixth embodiment of the present invention.

[Explanation of symbols]

11: silicon substrate (semiconductor substrate) 12: LOCOS,
13 ... MOS transistor, 14 ... first insulating film, 15 ...
2nd insulating film, 17 ... third insulating film, 18 ... hole, 18a
... Dicing portions, 18b, 18c recesses, 19 plugs, 19a barrier metal layers, 19b tungsten layers, 19c contact metal layers, 20 capacitors
21: lower electrode, 21a, 21c: iridium oxide layer,
21b: iridium layer, 22: ferroelectric layer, 23: upper electrode, 23a: iridium oxide layer, 23b: iridium layer, 30: plug, 30a: barrier metal layer, 30b ...
Tungsten layer, 30c ... contact metal layer, 30d
... Iridium layer, 31 ... Capacitor, 32 ... Lower electrode,
33: ferroelectric layer; 34: upper electrode.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Akio Ito 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kelly Andrew 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture No. 1 F-term in Fujitsu Limited (reference) 5F083 FR02 GA21 JA14 JA15 JA36 JA39 JA40 JA42 MA17 NA08 PR21 PR22 PR33 PR39 PR40

Claims (7)

[Claims] An insulating film formed on a semiconductor substrate; a hole formed in the insulating film; a tungsten layer formed so as to have a recess in an upper portion of the hole; A capacitor comprising a lower electrode having iridium oxide formed thereon, a ferroelectric film and an upper electrode; and a contact buried in the recess of the hole to reduce contact resistance between the lower electrode and the tungsten layer. A semiconductor memory device having a metal layer. 2. The semiconductor memory device according to claim 1, further comprising an iridium layer formed on said contact metal layer in said recess. 3. The semiconductor memory device according to claim 1, wherein said contact metal is selected from titanium nitride, tungsten nitride, tantalum nitride, tantalum, aluminum silicon nitride, and tantalum silicon nitride. . A step of forming an insulating film on the semiconductor substrate; a step of forming a hole in the insulating film; a step of forming a barrier metal layer on the inner surface of the hole and on the upper surface of the insulating film; Forming a tungsten layer on the barrier metal layer by a CVD method and filling the tungsten layer in the hole; and polishing or etching back the tungsten layer and the barrier metal layer on the insulating film. Removing the tungsten layer from the hole and leaving the tungsten layer in the hole in a state where the concave portion exists in the upper portion of the hole; forming a contact metal layer in the insulating film and the concave portion; polishing and etching back Removing the contact metal layer from above the insulating film and leaving it only in the recess by any one of: Forming a capacitor comprising a lower electrode having iridium oxide, a ferroelectric layer, and an upper electrode. 5. A step of forming an iridium layer on the contact layer before or after removing the contact layer from the insulating film; and polishing the iridium layer from above the insulating film by any of polishing and etchback. 5. The method of manufacturing a semiconductor memory device according to claim 4, further comprising a step of removing and leaving only on said contact metal layer in said concave portion. 6. The method according to claim 4, wherein the capacitor is annealed in an oxygen-containing atmosphere after the formation of the capacitor. 7. The semiconductor memory device according to claim 4, wherein said contact metal is selected from titanium nitride, tungsten nitride, tantalum nitride, tantalum, aluminum silicon nitride, and tantalum silicon nitride. Manufacturing method.