JP2001281694A - Semiconductor device and method of manufacture for the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance operational characteristics and reliability of a semiconductor device, and to realize the improvement of a yield by suppressing the generation of corrosion which is called electric corrosion at the time of forming a metal wiring and a transparent electrode. SOLUTION: A wiring material has a three or more layered structure, consisting of a thin-film layer consisting of oxidation resistant metal, a thin-film layer formed thereon and consisting of or essentially of aluminum and 9 thin- film layer formed thereon and consisting of oxidation resistant metal and metal oxide is used for transparent electrode material. After the wiring is formed, an oxygen plasma treating method and a thermal oxidation treating method are used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit formed of thin film transistors (hereinafter, referred to as TFTs) on a substrate having an insulating surface, and a method for manufacturing the same. In particular, the present invention relates to an electro-optical device typified by a liquid crystal display device in which a pixel portion and a driver circuit provided therearound are provided on the same substrate, and a technology that can be suitably used for an electronic device equipped with the electro-optical device. provide. In this specification, a semiconductor device generally refers to a device that functions by utilizing semiconductor characteristics, and includes the above-described electro-optical device and an electronic device including the electro-optical device in its category.

[0002]

2. Description of the Related Art In an electro-optical device typified by an active matrix type liquid crystal display device, a technique has been developed in which a switching element and an active circuit are formed using TFTs. In a TFT, a semiconductor film is formed over a substrate such as glass by a vapor deposition method or the like, and the semiconductor film is formed as an active layer. For the semiconductor film, a material mainly containing silicon such as silicon or silicon / germanium is preferably used. Such a semiconductor film is formed by the manufacturing method.
They could be classified into silicon films and crystalline silicon films represented by polycrystalline silicon.

A TFT using an amorphous semiconductor (typically amorphous silicon) film as an active layer has a field effect transfer of several cm ² / Vsec or more due to electronic physical factors caused by an amorphous structure or the like. It was impossible to get a degree. For this reason, in an active matrix type liquid crystal display device, a switching element (pixel T) for driving liquid crystal in a pixel portion is used.
Although it can be used as FT), it has not been possible to form a drive circuit for displaying images. Therefore, the driver circuit uses a TAB (Tape Automated Bonding) method or a COG (Chip on Glass) method to drive ICs.
Techniques for implementing such methods have been used.

On the other hand, in a TFT using a semiconductor film having a crystal structure (hereinafter, referred to as a crystalline semiconductor) film (typically, crystalline silicon or polycrystalline silicon) as an active layer, high field-effect mobility can be obtained. Therefore, various functional circuits can be formed on the same glass substrate, and the pixel TF
In addition to T, a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and the like can be realized in a driving circuit. Such a circuit has been formed based on a CMOS circuit composed of an n-channel TFT and a p-channel TFT. Based on the mounting technology of such a driving circuit, in order to promote a reduction in the weight and thickness of a liquid crystal display device, a crystalline semiconductor layer in which a driving circuit in addition to a pixel portion can be integrally formed on the same substrate is used as an active layer. It has become clear that the TFT described above is suitable.

[0005]

From the viewpoint of the characteristics of the TFT, it is better to apply a crystalline semiconductor layer to the active layer. There is a problem that the manufacturing process becomes complicated and the number of processes increases. It is clear that an increase in the number of steps not only causes an increase in manufacturing cost, but also causes a reduction in manufacturing yield.

[0006] In order to reduce the manufacturing cost and achieve the yield, reducing the number of steps can be applied as one means. Here, specifically, the reduction of the number of photomasks required for manufacturing a TFT will be described. A photomask is used in a photolithography technique to form a resist pattern used as a mask in an etching step on a substrate. Therefore, the use of a single photomask means that, in addition to the steps of film formation and etching in the preceding and subsequent steps, a resist peeling, cleaning, drying step, and the like are added, and in the photolithography step, It means that complicated processes such as resist coating, pre-baking, exposure, development, and post-baking are performed.

FIG. 20A is an overall view of a conventional TFT structure. This TFT structure is used for an active matrix substrate using a transparent electrode. With this active matrix substrate, a transmission type liquid crystal display device can be manufactured. In this TFT structure, wiring and
Pay attention to the contact of the transparent electrode. Here, the transparent electrode is in contact with the wiring so as to be folded over the wiring. This is hereinafter referred to as a direct contact structure. The advantage of the direct contact structure is that a step of providing an opening in an interlayer film formed on a wiring, laminating a transparent electrode, and contacting the surface of the wiring with acrylic, and providing an opening. Can be omitted. However, depending on the wiring material and the transparent electrode material, a phenomenon called electrolytic corrosion may occur. Electrolytic corrosion means that when electrodes of a plurality of different materials are immersed in an electrolytic solution, the immersed electrodes dissolve into the electrolytic solution due to a difference in ionization tendency. An aluminum (Al) film and a transparent electrode film are laminated, immersed in a developing solution during a patterning and etching process, and an optical microscope photograph at this time is shown in FIG. A square pixel can be seen in the right half of FIG. 22, where the white portion is electrolytic corrosion.
This causes conduction failure due to a change in the shape when fine processing is performed.

The present invention is a technique for solving this problem. In an electro-optical device and a semiconductor device typified by an active matrix type liquid crystal display device manufactured using a TFT, the structure and material of the TFT are appropriately adjusted. It is intended to realize an improvement in yield by adopting such a structure.

[0009]

SUMMARY OF THE INVENTION In the present invention, a structure of a wiring material for preventing the occurrence of the electrolytic corrosion is determined, and a manufacturing method thereof is studied. That is, in the above structure, the wiring material is composed of a thin film layer made of a heat-resistant metal, aluminum or a thin film containing aluminum as a main component (hereinafter also referred to as Al) formed thereon, and a heat-resistant material formed thereon. And a thin film layer made of a metal, and using a metal oxide as a transparent electrode material. The heat-resistant metal is Ti, TiN, C
r, Mo, W, TiW are known. As the metal oxide, ITO is mainly known, and other metal oxides such as GZO, AZO,
Alternatively, there are indium oxides in which appropriate impurities are dissolved in solid form, and these can also be used. Hereinafter, these metal oxides will be referred to as ITO as a representative.

As a more suitable condition, a Ti film having a thickness of 50 to 150 nm is formed as a wiring material, and a titanium nitride (TiN) film having a thickness of 50 to 150 nm is formed thereon. An Al film is formed to a thickness of 300 to 400 nm on top of this, and then a Ti film or titanium nitride (Ti
N) It is preferable to form a film with a thickness of 100 to 200 nm to form a laminated structure, and to use ITO as a transparent electrode material. The thicknesses of Ti and TiN used here are determined based on practical experience of the barrier metal, and Al is determined based on a balance between flatness and resistance value.

FIG. 20B shows a boundary portion between the wiring laminated structure (hereinafter also referred to as wiring) manufactured as an example of the above and the transparent electrode material. The wiring is formed from a lower layer in the order of a Ti film, a titanium nitride (TiN) film, an Al film, and a Ti film, and an ITO film is formed as a transparent electrode material. However, A
1 is formed by sputtering with a target in which 2% of Si forms a solid solution, and the film also contains Si. FIG. 23 shows an optical microscope photograph of the substrate on which this structure is formed. In FIG. 23, the pattern is clear and no electrolytic corrosion has occurred. With this structure, when a circuit having a contact size of 10 μm and a chain of 100 contacts is manufactured, the electric resistance at both ends of the circuit is 4.88 to 9.00.
× 10 ⁴ Ω. Improvement of the resistance value can be expected by changing the film thickness of Al, but this value is considered to be sufficient for practical use. That is, it is shown that both the appearance and the electrical characteristics are good.

In order to find out why this electrolytic corrosion does not occur,
The structure was observed by TEM. This is shown in FIG.
However, due to the TEM technique, in FIG. 21, the resin is formed on the ITO film. 211, 212, 21 in FIG.
3, 214 are Al＼ITO contact parts, 215 is Ti＼I
TO contact portion, 216 near Ti＼TiN interface, 217
Is a TiN-ITO contact portion, and 218 is a Ti-ITO contact portion. Reference numeral 2101 denotes an Al film, 2102 denotes an ITO film, 2103 denotes an uppermost Ti film, 2104 denotes a TiN film, and 2105 denotes a lowermost Ti film. Al @ IT
Regarding the interface of O, EDX measurement results at 211 to 218 in FIG. 21 are shown in FIGS. A
Is an entire spectrum view, and B is a partially enlarged view of A. The EDX measurement results of 2101 to 2105 are shown in FIGS. A is the whole spectrum, B is A
FIG.

[0013] In the TEM photograph, an opaque thing is observed at the interface between Al and ITO, which indicates that an altered layer has been formed. In FIGS. 24 to 28, the O peak clearly appears, indicating that the altered layer is an oxide film. Also,
Cl is detected at the interface of Al @ ITO. It is considered that Cl plasma was used for dry etching to form wiring, and this remained in the film.

Table 1 shows the results of the EDX measurement at each point shown in FIGS.

[0015]

[Table 1]

In Table 1, 211-4 (Al @ ITO)
Focusing on the oxygen concentration at the boundary, 2101 (Al layer)
It can be seen that the concentration is higher than that in. Since the measurement spot is small, the concentration is biased. However, from 211 and 213, it can be determined that there is a portion where the oxygen concentration is 25% or more.
2102 (ITO layer) has an In concentration of about 50% and an oxygen concentration of about 40%. That is, it is considered that about 5: 4 forms a solid solution.

On the other hand, even in the case of 211 to 214, Al＼I
The information of ITO was picked up due to the unevenness at the TO boundary, and the concentration of In was found. However, the In concentration was 2% or less, and the oxygen concentration was too large to be obtained from the information of ITO alone. I understand. The reason why an oxide layer is formed is considered to be that, in addition to the low oxidation resistance of Al, oxygen flows during the ITO sputter deposition, so that it easily reacts with oxygen plasma. Also, if O ₂ ashing, that is, a process using oxygen plasma is performed after the wiring etching for the purpose of removing the resist, an oxide layer is expected to be formed.

On the other hand, a TEM photograph shows that a clear oxide layer is not formed at the Ti-ITO interface as much as at the Al-ITO interface. 29. Ti＼ITO contact portion in FIG. 29, Ti＼ in FIG.
An O peak appears in the vicinity of the TiN interface and in the contact portion of TiN @ ITO in FIG. 31. At the same time, an In peak also appears quite strongly, so this O can be said to be from ITO.

As described above, an oxide layer is formed at the interface between the Al cross section and ITO, but it is considered that the contact resistance is low because the oxide layer is not easily formed at the interface between Ti or TiN and ITO. Advantages of the above-mentioned wiring / ITO structure include
It is difficult to cause an electric contact due to the small area of the Al-ITO interface. According to 214 in Table 1, the In concentration is 1.6 atomic%, and it can be seen that the Al @ ITO interface can be measured similarly to 211, but the oxygen concentration is lower than 211.

The portion having a high oxygen concentration is alumina,
It is considered that valence electrons are less likely to move than 1 and that electrolytic corrosion is less likely to occur. However, as the area of the Al-ITO interface increases, a large portion of the Al-ITO interface having a low oxygen concentration tends to be formed, and it is considered that electrolytic corrosion occurs therefrom. Therefore, the substrate on which Al and ITO are laminated is Al
(4) It is considered that the electrode contact occurred because the ITO interface was too wide.

If an oxide layer at the boundary between Al and ITO cannot be formed sufficiently for the purpose of preventing electrolytic corrosion, a treatment using oxygen plasma is performed after the wiring is etched to oxidize the Al end portion to remove I.
An oxide layer can be formed by forming TO.

When the wiring is etched by plasma, Cl may be used as an etching gas.
In some cases, treatment with CF ₄ plasma is performed due to the progress of corrosion. At this time, a means for adding O ₂ for the purpose of oxidizing the Al end is also effective.

In addition, when forming ITO, O
_A method of performing reactive sputtering film formation in which ₂ flows is effective.
Normally, pre-sputtering is often performed before sputtering film formation by providing a shutter between a target and a substrate to generate plasma. There is also a method of oxidizing the oxide film on the Al end by increasing the pre-sputtering time or increasing the O ₂ flow rate only in the pre-sputtering stage.

Alternatively, a method is conceivable in which a thermal oxide film is formed on Al in an atmosphere containing oxygen in a temperature range where hillocks do not appear in the wiring. In the structure of the TEM photograph, it has been confirmed that hillocks do not appear even when heated at 400 ° C. for 4 hours in the air. If the wiring / ITO structure is formed by such means, while using Al for the wiring and lowering the resistance, a small-area insulating layer at the Al / ITO interface prevents electric corrosion, and Ti (TiN) / ITO is used. Electrical contact can be made.

Using such means, the structure of the present invention is as follows.
In a semiconductor device in which a pixel TFT provided in a pixel portion and a driver circuit provided around the pixel portion over the same substrate, a pixel electrode provided in the pixel portion has a light-transmitting property and is formed on an interlayer insulating film. A conductive metal wiring formed at least through an opening provided in an interlayer insulating film provided above a gate electrode of the pixel TFT, the conductive metal wiring being connected to the pixel TFT; The wiring is composed of a thin film layer made of a heat-resistant metal, a thin film composed mainly of aluminum or aluminum formed thereon, and a thin film layer made of a heat-resistant metal formed thereon, and a transparent electrode. Using a metal oxide as a material, at the boundary between the aluminum or the film containing aluminum as a main component and the metal oxide, the aluminum concentration is 70 atomic% or less and the oxygen concentration is 25 atomic% or more. It is characterized in that a region is formed.

Another aspect of the present invention is a semiconductor device in which liquid crystal is sandwiched between a pair of substrates, wherein one of the substrates includes a pixel TFT provided in a pixel portion and a driving circuit around the pixel portion. In the above, the pixel electrode provided in the pixel portion has a light-transmitting property, is formed on an interlayer insulating film, and passes through at least an opening provided in the interlayer insulating film provided above the gate electrode of the pixel TFT. And a conductive metal wiring connected to the pixel TFT, the conductive metal wiring comprising, as a main component, a thin film layer made of a heat-resistant metal and aluminum or aluminum formed thereon. And a thin film layer made of a heat-resistant metal formed thereon, and using a metal oxide as a transparent electrode material,
A region where the aluminum concentration is 70 atomic% or less and the oxygen concentration is 25 atomic% or more is formed at a boundary between the aluminum or the film containing aluminum as a main component and the metal oxide, and a transparent conductive film is formed. The second substrate and the second interlayer insulating film are bonded to each other via at least one columnar spacer formed so as to overlap an opening provided in the second interlayer insulating film.

The structure of the method for manufacturing a semiconductor device according to the present invention includes a pixel TFT provided in a pixel portion and a semiconductor device provided with a driver circuit around the pixel portion on the same substrate.
A first step of forming an interlayer insulating film above the TFT of the drive circuit and the pixel TFT, a second step of forming a conductive metal wiring connected to the pixel TFT, and the conductive metal wiring A third step of forming a light-transmitting pixel electrode on the interlayer insulating film, the third electrode step being connected to an interlayer insulating film between the second and third steps. When the wiring is etched with plasma, O ₂ is added as a finishing treatment, or when forming a transparent conductive film made of a metal oxide, the substrate is exposed to an oxygen plasma atmosphere in a film forming chamber, or a sputter film is formed. When the transparent conductive film made of the metal oxide is formed by the method described above, the O ₂ flow rate is increased only in the pre-sputtering step, and the substrate is exposed to an oxygen plasma atmosphere. In an oxygen atmosphere,
The method is characterized in that the edge of Al is oxidized by using a method of forming a thermal oxide film.

According to another aspect of the invention, in a method for manufacturing a semiconductor device in which liquid crystal is sandwiched between a pair of substrates, a pixel TFT provided in a pixel portion and a driving circuit provided around the pixel portion are provided. A first step of forming an interlayer insulating film above the TFT of the driving circuit and the pixel TFT, and connecting to the pixel TFT via an opening provided in the interlayer insulating film. A second step of forming a conductive metal wiring, a third step of forming a pixel electrode made of a transparent conductive film connected to the metal wiring on the interlayer insulating film, and A fourth step of forming;
A fifth step of bonding the one substrate and the other substrate via at least one columnar spacer formed so as to overlap with the opening, and between the second and third steps After the wiring is etched, a process using oxygen plasma is performed, or when the wiring is etched with plasma, O ₂ is added as a finishing process, or when forming a transparent conductive film made of a metal oxide, the substrate is placed in a film forming chamber. Exposing the substrate to an oxygen plasma atmosphere by increasing the O ₂ flow rate only during the pre-sputtering step when exposing the substrate to an oxygen plasma atmosphere or forming a transparent conductive film made of the metal oxide by sputtering film formation, or a temperature at which hillocks do not appear in the wiring. In the region, the edge of Al is oxidized using a method of forming a thermal oxide film on Al in an oxygen atmosphere.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail with reference to the following examples.

[Embodiment 1] FIGS. 1 to 4 show an embodiment of the present invention.
This will be described with reference to FIG. Here, the pixel TFT and the storage capacitor of the pixel portion and the T of a driving circuit provided around the pixel portion are used.
A method for simultaneously manufacturing FTs will be described in detail according to steps.

In FIG. 1A, a substrate 101 is made of a glass substrate such as barium borosilicate glass or aluminoborosilicate glass typified by Corning # 7059 glass or # 1737 glass, etc., and polyethylene terephthalate (PET). ), Polyethylene naphthalate (P
EN), a plastic substrate having no optical anisotropy such as polyethersulfone (PES) can be used. When a glass substrate is used, heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. Then, a base film 102 made of an insulating film such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on the surface of the substrate 101 where a TFT is to be formed, in order to prevent impurity diffusion from the substrate 101. For example,
Plasma CVD SiH ₄ at, NH _3, N ₂ O silicon oxynitride film 102a made from 10 to 200 nm (preferably 50 to 100 nm), as well SiH4, silicon oxynitride hydrogenated is prepared from N2O film 102b 50 to
The layer is formed to have a thickness of 200 nm (preferably 100 to 150 nm). Here, the base film 102 has a two-layer structure; however, the base film 102 may be a single-layer film of the insulating film or a stack of two or more layers.

The silicon oxynitride film is a conventional parallel plate type
It is formed by a plasma CVD method. Silicon oxynitride
The film 102a is made of SiH_FourTo 10 SCCM, NH_ThreeTo 100 SCC
M, N _TwoO was introduced into the reaction chamber at 20 SCCM, and the substrate temperature was 3
25 ° C, reaction pressure 40Pa, discharge power density 0.41W / c
m^TwoAnd the discharge frequency was 60 MHz. On the other hand, hydrogen oxynitride
The silicon film 102b is made of SiH_FourTo 5 SCCM, N_TwoO to 12
0 SCCM, H_TwoInto the reaction chamber as 125 SCCM
Temperature 400 ° C, reaction pressure 20Pa, discharge power density 0.41
W / cm^TwoAnd the discharge frequency was 60 MHz. These films are
Change the temperature and change the reaction gas
It can also be done.

The silicon oxynitride film 102a manufactured in this manner has a density of 9.28 × 10 ²² / cm ³ , 7.13% of ammonium hydrogen fluoride (NH ₄ HF ₂ ) and ammonium fluoride (NH ₄ HF ₂ ). 20% of a mixed solution containing 15.4% of NH ₄ F) (trade name: LAL500, manufactured by Stella Chemifa).
The etching rate at a temperature of ° C. is as low as about 63 nm / min, and the film is dense and hard. Use of such a film as a base film is effective in preventing an alkali metal element from a glass substrate from diffusing into a semiconductor layer formed thereover.

Next, 25 to 80 nm (preferably 30 to 80 nm)
Semiconductor layer 103 having a thickness of 60 nm and having an amorphous structure.
a is formed by a known method such as a plasma CVD method or a sputtering method. For example, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. The semiconductor film having an amorphous structure includes an amorphous semiconductor layer and a microcrystalline semiconductor film, and a compound semiconductor film having an amorphous structure such as an amorphous silicon germanium film may be used. Further, both the base film 102 and the amorphous semiconductor layer 103a can be formed continuously. For example, as described above, the silicon oxynitride film 102a and the hydrogenated silicon oxynitride film 102b
Is continuously formed by a plasma CVD method, and then the reaction gas is Si.
H _4, N ₂ O, be switched from H ₂ only SiH ₄ and H ₂ or SiH _4, once can be continuously formed without exposure to the atmosphere. As a result, the hydrogenated silicon oxynitride film 102b
To prevent contamination of the surface of the TFT
And variations in threshold voltage can be reduced.

Then, a crystallization step is performed to form a crystalline semiconductor layer 103b from the amorphous semiconductor layer 103a. Laser annealing, thermal annealing (solid phase growth), or rapid thermal annealing (RTA)
Law) can be applied. When a glass substrate or a plastic substrate having low heat resistance as described above is used, it is particularly preferable to apply a laser annealing method. RT
In the method A, an infrared lamp, a halogen lamp, a metal halide lamp, a xenon lamp, or the like is used as a light source. Alternatively, according to the technique disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652, the crystalline semiconductor layer 10 is formed by a crystallization method using a catalytic element.
3b can also be formed. First, in the crystallization process,
It is preferable to release hydrogen contained in the amorphous semiconductor layer, and heat treatment is performed at 400 to 500 ° C. for about one hour to reduce the amount of hydrogen contained to 5 atomic% or less and then crystallize. It is good because it can be prevented.

In the step of forming an amorphous silicon film by plasma CVD, SiH 4 and argon (Ar) are used as reaction gases, and the substrate temperature during film formation is 400 to 450 ° C.
When formed, the hydrogen concentration in the amorphous silicon film can be reduced to 5 atomic% or less. In such a case, heat treatment for releasing hydrogen becomes unnecessary.

When crystallization is performed by laser annealing, a pulse oscillation type or continuous emission type excimer laser or argon laser is used as the light source. When a pulse oscillation type excimer laser is used, laser annealing is performed by processing the laser beam into a linear shape. Laser annealing conditions are appropriately selected by the practitioner, for example,
The laser pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 500 mJ / cm ² (typically 300
４００400 mJ / cm ² ). Then, a linear beam is irradiated over the entire surface of the substrate, and the superposition rate (overlap rate) of the linear beam at this time is set to 80 to 98%. In this manner, as shown in FIG.
3b can be obtained.

Then, a first layer is formed on the crystalline semiconductor layer 103b.
Lithography using a photomask (PM1)
A resist pattern is formed using the
By dividing the crystalline semiconductor layer into islands by etching, FIG.
Forming island-shaped semiconductor layers 104 to 108 as shown in FIG.
I do. CF for dry etching of crystalline silicon film _Four
And O_TwoIs used.

In order to control the threshold voltage (Vth) of the TFT, an impurity element imparting a p-type is added to such an island-like semiconductor layer in an amount of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atomic / cm ³ . The concentration may be added to the entire surface of the island-shaped semiconductor layer. As an impurity element that imparts p-type to a semiconductor, an element belonging to Group 13 of the periodic table such as boron (B), aluminum (Al), or gallium (Ga) is known. As the method, an ion implantation method or an ion doping method (or an ion shower doping method) can be used, but the ion doping method is suitable for treating a large-area substrate. In the ion doping method, diborane (B ₂ H ₆ ) is used as a source gas and boron (B) is added. The implantation of such an impurity element is not always necessary and may be omitted. However, it is a method preferably used for keeping the threshold voltage of the n-channel TFT within a predetermined range.

The gate insulating film 109 is formed of an insulating film containing silicon with a thickness of 40 to 150 nm by a plasma CVD method or a sputtering method. In this embodiment, 12
It is formed from a silicon oxynitride film with a thickness of 0 nm. A silicon oxynitride film formed by adding O ₂ to SiH ₄ and N ₂ O is a preferable material for this application because the fixed charge density in the film is reduced. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when a silicon oxide film is used, tetraethyl ortho-silicate (TEO) is formed by a plasma CVD method.
S) and O ₂ were mixed, the reaction pressure was 40 Pa, and the substrate temperature was 30.
It can be formed by discharging at a high-frequency (13.56 MHz) power density of 0.5 to 0.8 W / cm ² at 0 to 400 ° C. The silicon oxide film thus manufactured can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 ° C.

Then, as shown in FIG. 1D, a first conductive film 110 and a second conductive film 111 for forming a gate electrode are formed over the gate insulating film 109. In this embodiment, the first conductive film 110 is formed of Ta to a thickness of 50 to 100 nm, and the second conductive film is formed of W to a thickness of 100 to 300 nm.

The Ta film is formed by a sputtering method, and a Ta target is sputtered with Ar. In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relaxed and the film can be prevented from peeling. The resistivity of the α-phase Ta film is about 20 μΩcm and can be used for the gate electrode, but the resistivity of the β-phase Ta film is about 180 μΩcm and is not suitable for the gate electrode. α phase T
If a tantalum nitride having a crystal structure close to the α phase of Ta is formed on a base of Ta with a thickness of about 10 to 50 nm in order to form the a film, a Ta film of the α phase can be easily obtained. .

When a W film is formed, it is formed by a sputtering method using W as a target. Alternatively, it can be formed by a thermal CVD method using tungsten hexafluoride (WF ₆ ). In any case, it is necessary to lower the resistance in order to use it as a gate electrode.
It is desirable to set the resistance to Ωcm or less. The resistivity of the W film can be reduced by enlarging the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is inhibited and the resistance is increased. From this, when using the sputtering method,
By using a W target having a purity of 99.9999% and forming a W film with sufficient care so as not to mix impurities from the gas phase during film formation, the resistivity is 9 to 20 μΩc.
m can be realized.

Next, as shown in FIG. 6B, masks 112 to 117 made of resist are formed, and a first etching process for forming a gate electrode is performed. Although there is no limitation on the etching method, preferably, the ICP (Inductively Coupling) is used.
led Plasma (inductively coupled plasma) using an etching method, mixing CF ₄ and Cl ₂ in an etching gas,
~ 2 Pa, preferably 1 Pa at a pressure of 50
The plasma is generated by supplying 0 W RF (13.56 MHz) power. 100W RF on substrate side (sample stage)
(13.56 MHz) Power is applied and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, both the W film and the Ta film are etched to the same extent.

Under the above-mentioned etching conditions, the shape of the resist mask is made appropriate, so that the ends of the first conductive layer and the second conductive layer are tapered due to the effect of the bias voltage applied to the substrate side. Become. The angle of the tapered portion is 15 to 45 °. In order to perform etching without leaving a residue on the gate insulating film, the etching time may be increased by about 10 to 20%. Since the selectivity of the silicon oxynitride film to the W film is 2 to 4 (typically 3), the exposed surface of the silicon oxynitride film is etched by about 20 to 50 nm by the over-etching process. Thus, the first shape conductive layers 118 to 123 (the first conductive layers 118a to 118a) each including the first conductive layer and the second conductive layer are formed by the first etching process.
23a and the second conductive layers 118b to 123b) are formed. Reference numeral 130 denotes a gate insulating film, and a region which is not covered with the first shape conductive layers 118 to 123 is etched to a thickness of about 20 to 50 nm to form a thinned region.

Then, a first doping process is performed to add an impurity element imparting n-type. The doping may be performed by an ion doping method or an ion implantation method. The condition of the ion doping method is that the dose is 1 × 10 ^{13 to} 5 × 10
^{It is performed at 14} atoms / cm ² and an acceleration voltage of 60 to 100 keV. An element belonging to Group 15 of the periodic table, typically phosphorus (P) or arsenic (As) is used as the n-type impurity element. Here, phosphorus (P) is used. In this case, the conductive layer 1
Reference numerals 18 to 123 serve as masks for the impurity element imparting n-type, and the first impurity regions 124 to 12 are self-aligned.
9 is formed. An impurity element imparting n-type is added to the first impurity regions 124 to 129 in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ atomic / cm ³ .

Next, a second etching process is performed as shown in FIG. Similarly, using an ICP etching method, CF ₄ , Cl _2, and O ₂ are mixed as an etching gas, and a 500 W RF power (13.56 MHz) is applied to the coil electrode at a pressure of 1 Pa.
Is supplied to generate plasma. An RF (13.56 MHz) power of 50 W is applied to the substrate side (sample stage), and a lower self-bias voltage is applied than in the first etching process. Under these conditions, the W film is anisotropically etched, and Ta, which is the first conductive layer, is anisotropically etched at a lower etching rate to form the second shape conductive layers 1118 to 1123 (first Conductive layers 1118a to 112
3a and second conductive layers 1118b to 1123b) are formed. Reference numeral 1130 denotes a gate insulating film, and a region which is not covered by the second shape conductive layers 1118 to 1123 is further 20 to
A thin region is formed by etching about 50 nm.

The etching reaction of the W film or the Ta film by the mixed gas of CF ₄ and Cl ₂ can be inferred from the generated radical or ionic species and the vapor pressure of the reaction product.
Comparing the vapor pressures of fluorides and chlorides of W and Ta, W
WF ₆ is extremely high and other WC
l ₅ , TaF ₅ and TaCl ₅ are comparable. Therefore, C
With the mixed gas of F ₄ and Cl ₂ , both the W film and the Ta film are etched. However, when an appropriate amount of O ₂ is added to this mixed gas, CF 4 and O ₂ react to form CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure increases. On the other hand, in Ta, the increase in the etching rate is relatively small even if F increases. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ .
Since the oxide of Ta does not react with fluorine or chlorine,
The etching rate of the a film decreases. Therefore, the W film and Ta
It is possible to make a difference in the etching rate with the film, and it is possible to make the etching rate of the W film larger than that of the Ta film.

Then, a second doping process is performed as shown in FIG. In this case, an impurity element imparting n-type is doped under a condition of a high acceleration voltage with a lower dose than in the first doping process. For example, if the acceleration voltage is 7
The operation is performed at 0 to 120 keV and at a dose of 1 × 10 ¹³ / cm ² , and a new impurity region is formed inside the first impurity region formed in the island-shaped semiconductor layer in FIG. The doping is performed using the second shape conductive layers 1118 to 1123 as a mask for an impurity element.
Doping is performed so that the impurity element is also added to the region below a to 1123a. Thus, the second conductive layer 11
18a to 1123a and third impurity regions 131 to 131
136 and second impurity regions 1131 to 1136 between the first impurity region and the third impurity region.
The impurity element imparting n-type is 1 × in the second impurity region.
So as to have a concentration of 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ ,
1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ^{3 in} the third impurity region
Concentration. Thus, the second impurity region and the third impurity region are collectively called an LDD region. This is the same in the case of the P-type using boron as an impurity.

Then, high-concentration p-type impurity regions 140 and 141 serving as a source region and a drain region are formed in the island-shaped semiconductor layers 104 and 106 forming the p-channel TFT. Here, an impurity element imparting p-type is added using the gate electrodes 1118a and 1123a as masks to form a high-concentration p-type impurity region in a self-aligned manner. At this time, n
Island-shaped semiconductor layers 105, 10 forming a channel type TFT
7 and 108, resist masks 137 to 139 are formed using a third photomask (PM3), and the entire surface is covered. The impurity regions 140 and 141 formed here are formed by an ion doping method using diborane (B ₂ H ₆ ).
The boron (B) concentration of the high concentration p-type impurity regions 140a and 141a that do not overlap with the gate electrode is 3 × 10 ²⁰
３3 × 10 ²¹ atomic / cm ³ . Further, the impurity regions 140b and 141b overlapping with the first gate electrode
Is formed as a low-concentration p-type impurity region substantially because the impurity element is added through the gate insulating film and the first gate electrode, and at least 1.5 × 10 ¹⁹ atomic / cm ³
The above concentration is set. This high-concentration p-type impurity region 140
a, 141a and low-concentration p-type impurity regions 140b, 1b
Phosphorus (P) is added to the high concentration p-type impurity regions 140a and 141a in the previous step.
At a concentration of 10 ²⁰ to 1 × 10 ²¹ atomic / cm ³ , the low-concentration p-type impurity regions 140b and 141b have a concentration of 1 × 10 ¹⁶ to 1 × 1.
Although it is contained at a concentration of 0 ¹⁹ atomic / cm ^3, the concentration of boron (B) added in this step is 1.5 times the concentration of phosphorus (P).
From the p-channel type T
There was no problem in functioning as the source and drain regions of the FT.

Thereafter, as shown in FIG. 4A, the first interlayer insulating film 142 is formed on the gate electrode and the gate insulating film.
To form The first interlayer insulating film may be formed using a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or a stacked film combining these. In any case, the first
Is formed from an inorganic insulating material. The thickness of the first interlayer insulating film 142 is 100 to 200 nm. Here, when a silicon oxide film is used, TEOS and O ₂ are mixed by a plasma CVD method, and a reaction pressure of 40 P
a, a substrate temperature of 300 to 400 ° C., and a high frequency (13.5
6 MHz) It can be formed by discharging at a power density of 0.5 to 0.8 W / cm ² . When a silicon oxynitride film is used, SiH ₄ , N ₂ O, NH ₃
A silicon oxynitride film made from SiH ₄ ,
N ₂ O may be formed by a silicon oxynitride film made from. The production conditions in this case are a reaction pressure of 20 to 200 Pa,
The substrate can be formed at a substrate temperature of 300 to 400 ° C. and a high frequency (60 MHz) power density of 0.1 to 1.0 W / cm ² .
Alternatively, a hydrogenated silicon oxynitride film formed from SiH ₄ , N ₂ O, and H ₂ may be used. Similarly, a silicon nitride film can be formed from SiH ₄ and NH ₃ by a plasma CVD method.

Thereafter, a step of activating the n-type or p-type imparting impurity element added at each concentration is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method or a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, the oxygen concentration is 1 ppm or less,
Preferably in a nitrogen atmosphere of 0.1 ppm or less 400 ~
The heat treatment is performed at 700 ° C., typically 500 to 600 ° C. In this embodiment, the heat treatment is performed at 550 ° C. for 4 hours.
When a plastic substrate having a low heat-resistant temperature is used as the substrate 101, a laser annealing method is preferably applied (FIG. 4B).

Following the activation step, the atmosphere gas is changed
And in an atmosphere containing 3 to 100% hydrogen,
Heat treatment at 450 ° C. for 1 to 12 hours to form an island-shaped semiconductor layer
Is carried out. This process was thermally excited
10 in the island-like semiconductor layer due to hydrogen¹⁶-10¹⁸/cm^ThreeNo da
This is a step of terminating the ringing bond. Other hydrogenation
As a means, plasma hydrogenation (excited by plasma
Using hydrogen). In any case, the island
Defect density in the semiconductor layers 104 to 108 is 10 ¹⁶/cm^ThreeLess than
It is preferable to set the hydrogen content to 0.01 to
It was good to give about 0.1 atomic%.

When the activation and hydrogenation steps are completed,
A second interlayer insulating film 143 made of an organic insulating material is used for 1.
It is formed with an average thickness of 0 to 2.0 μm. As the organic resin material, polyimide, acrylic, polyamide, polyimide amide, BCB (benzocyclobutene), or the like can be used. For example, in the case of using a polyimide of a type that is thermally polymerized after being applied to a substrate, it is formed by firing at 300 ° C. in a clean oven. In the case of using acrylic, after using a two-pack type, mixing the main material and the curing agent, applying the entire surface of the substrate using a spinner, and preheating at 80 ° C. for 60 seconds on a hot plate. Then, it can be formed by firing in a clean oven at 250 ° C. for 60 minutes.

As described above, the surface can be satisfactorily planarized by forming the second interlayer insulating film with the organic insulating material. In addition, since organic resin materials generally have a low dielectric constant, parasitic capacitance can be reduced. But,
Since it has hygroscopicity and is not suitable as a protective film, it is preferable to use it in combination with a silicon oxide film, a silicon oxynitride film, a silicon nitride film, or the like formed as the first interlayer insulating film 142 as in this embodiment.

After that, using a fourth photomask (PM4), a resist mask having a predetermined pattern is formed, and a contact hole reaching a source region or a drain region formed in each island-shaped semiconductor layer is formed. The formation of the contact hole is performed by a dry etching method. In this case, the second interlayer insulating film 143 made of an organic resin material is first etched by using a mixed gas of CF ₄ , O ₂ , and He as an etching gas.
The first interlayer insulating film 142 is etched as F ₄ and O ₂ . Furthermore, in order to increase the selectivity with the island-shaped semiconductor layer,
Switching the etching gas to CHF ₃ to change the gate insulating film 1
By etching 30, a contact hole can be formed well.

Then, a conductive metal film is formed by a sputtering method or a vacuum evaporation method, a resist mask pattern is formed using a fifth photomask, and a source wiring and a drain wiring are formed by etching. This structure will be described in detail with reference to FIG. 6B taking the drain wiring 256 as an example.
6a is formed to a thickness of 50 to 150 nm, and a contact is formed with the semiconductor film forming the source or drain region of the island-shaped semiconductor layer. An Al film 256b is formed on the Ti film 256a to have a thickness of 300 to 400 nm,
i film 256c or titanium nitride (TiN) film
It is formed to a thickness of 200 nm and has a structure having three or more layers by combining three layers or combining Ti and TiN. afterwards,
A resist mask pattern is formed using a fifth photomask, and a source wiring and a drain wiring 2 are formed by etching.
56 is formed. At this time, as described in Means for Solving the Problems, a process using oxygen plasma and a thermal oxidation process are performed to form an oxide film 258 at the end of the Al layer. afterwards,
A transparent conductive film is formed over the entire surface, and a pixel electrode 257 is formed by patterning and etching using a sixth photomask. The pixel electrode 257 is formed on a second interlayer insulating film made of an organic resin material.
A portion overlapping the drain wiring 256 of FIG. 4 is provided to form an electrical connection. The material of the transparent conductive film is made of indium oxide (In ₂ O ₃ ) or indium oxide tin oxide alloy (In
₂ O ₃ —SnO ₂ ; ITO) or the like can be formed by a sputtering method or a vacuum evaporation method and used. The etching of such a material is performed using a hydrochloric acid-based solution.

In this manner, a substrate having a TFT of a driving circuit and a pixel TFT of a pixel portion on the same substrate can be completed by using six photomasks. The driving circuit includes a first p-channel TFT (A) 200a, a first n-channel TFT (A) 201a, and a second p-channel TFT (A) 201a.
FT (A) 202a, second n-channel TFT (A)
203a, a pixel TFT 204 in the pixel portion, and a storage capacitor 20
5 are formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

First p-channel TFT of drive circuit
(A) 200a has a structure in which a channel forming region 206, an LDD region 207, a source region 208 including a high-concentration p-type impurity region, and a drain region 209 are provided in the island-shaped semiconductor layer 104. First n-channel TFT
(A) 201a includes a channel forming region 210 in the island-shaped semiconductor layer 105, an LDD region 211 formed of a low-concentration n-type impurity region and overlapping the gate electrode 119, a source region 212 formed of a high-concentration n-type impurity region, and a drain. Area 21
Three. For a channel length of 3 to 7 μm, the LDD region overlapping with the gate electrode 119 is Lov, and the length in the channel length direction is 0.1 to 1.5 μm, preferably 0.3 to 0.8 μm. The length of Lov is controlled from the thickness of the gate electrode 119 and the angle θ1 of the tapered portion.

The LDD region will be described with reference to FIG. FIG. 15A shows a part of the TFT in the stage of FIG. 4C, and B is a partially enlarged view of the TFT.
The first impurity region 1901 is formed at the tapered portion of the second gate electrode 1902 having the second shape, and the second impurity region 1903 is formed at the first gate electrode 1904 having the second shape.
Is formed under the tapered portion of. At this time, the concentration distribution of phosphorus (P) in the LDD region increases as the distance from the channel forming region 1906 increases, as indicated by the curve 1905. The rate of this increase depends on the conditions such as the acceleration voltage and dose in ion doping, the angle θ1 and length 1907 of the tapered portion of the second gate electrode, and the angle θ2 and length 1908 of the tapered portion of the first gate electrode. It depends on. As described above, by forming the end portion of the gate electrode into a tapered shape and adding the impurity element through the tapered portion, the concentration of the impurity element gradually changes in the semiconductor layer existing under the tapered portion. An impurity region can be formed. n-channel type T
By forming such an LDD region in the FT, a high electric field generated in the vicinity of the drain region can be alleviated, hot carriers can be prevented from being generated, and deterioration of the TFT can be prevented. This forming method is the same for a p-channel TFT.

In FIG. 4C, the n-channel TFT and the p-channel TFT of the driving circuit have a single gate structure in which one gate electrode is provided between a pair of source and drain, and the pixel TFT has a double gate structure. However, each of these TFTs may have a single-gate structure or a multi-gate structure in which a plurality of gate electrodes are provided between a pair of sources and drains.

FIG. 7 is a top view showing almost one pixel of the pixel portion. The cross section AA ′ shown in the drawing corresponds to the cross-sectional view of the pixel portion shown in FIG. In the pixel TFT 204, the gate electrode 122 intersects the island-shaped semiconductor layer 108 thereunder via a gate insulating film (not shown), and further extends over a plurality of island-shaped semiconductor layers to serve also as a gate wiring. . Although not shown, FIG.
The source region, the drain region, and the LDD region described in (C) are formed. 230 is a source wiring 148
231 is a contact portion between the drain wiring 153 and the drain region 227. The storage capacitor 205 is formed in a region where the capacitor wiring 123 overlaps with the semiconductor layers 228 and 229 extending from the drain region 227 of the pixel TFT 204 via a gate insulating film. In this structure, an impurity element for controlling valence electrons is not added to the semiconductor layer 228.

The above configuration enables the structure of the TFT constituting each circuit to be optimized according to the specifications required by the pixel TFT and the driving circuit, thereby improving the operation performance and reliability of the semiconductor device. . Further, the gate electrode is formed of a conductive material having heat resistance, thereby facilitating activation of the LDD region, the source region, and the drain region.

Further, when forming an LDD region overlapping with the gate electrode via a gate insulating film, the impurity element added for the purpose of controlling the conductivity type is given a concentration gradient so that the LDD region is formed.
By forming the region, it can be expected that the effect of relaxing the electric field particularly near the drain region is enhanced.

In the case of an active matrix type liquid crystal display device, the first p-channel type TFT (A) 200a and the first
The n-channel TFT (A) 201a is used for forming a shift register circuit, a buffer circuit, a level shifter circuit, and the like that place importance on high-speed operation. FIG. 4C illustrates these circuits as logic circuit portions. The LDD region 211 of the first n-channel type TFT (A) 201a has a structure that emphasizes hot carrier measures. Further, in order to increase the breakdown voltage and stabilize the operation, FIG.
As shown in the figure, the TFT of this logic circuit portion is composed of a first p-channel TFT (B) 200b and a first n-channel TFT (B).
FT (B) 201b may be used. This TFT is
The TFT has a double gate structure in which two gate electrodes are provided between a pair of source and drain. Such a TFT can be manufactured in the same manner by using the steps of this embodiment. The first p-channel type TFT (B) 200b includes LDD regions 237a, 237a,
37b, source region 23 made of high concentration p-type impurity region
8 and drain regions 239 and 240. In the first n-channel type TFT (B) 201b,
Channel formation regions 241a and 241b are formed in the island-shaped semiconductor layer.
LDD regions 242a and 242b formed of low-concentration n-type impurity regions and overlapping gate electrode 119; source region 243 and drain region 24 formed of high-concentration n-type impurity regions
4, 245. Channel length is 3-7
The length in the channel length direction is set to 0.1 to 1.5 μm, preferably 0.3 to 0.8 μm, with the LDD region overlapping with the gate electrode as Lov.

The sampling circuit composed of an analog switch includes a second p-channel TFT (A) 202a and a second n-channel TFT
(A) 203a can be applied. Since the sampling circuit places importance on measures against hot carriers and low off-current operation, as shown in FIG. 5B, the TFT of this circuit is divided into a second p-channel TFT (B) 202b and a second n-channel TFT. (B) It may be formed of 203b. The second p-channel type TFT (B) 202b has a triple gate structure in which three gate electrodes are provided between a pair of sources and drains. Such a TFT is similarly manufactured by using the steps of this embodiment. it can. Second p-channel TFT
(B) An LDD region 247 formed of an island-shaped semiconductor layer and including channel formation regions 246 a, 246 b, and 246 c and a low-concentration p-type impurity region overlaps the gate electrode 120.
a, 247b, 247c, a source region 249 composed of a high-concentration p-type impurity region, and drain regions 250 to 252. Second n-channel TFT
(B) In 203b, LDD regions 254a and 254 formed in the island-shaped semiconductor layer with channel formation regions 253a and 253b and low-concentration n-type impurity regions and overlapping the gate electrode 121 are provided.
b, Source region 255 formed of high concentration n-type impurity region
And drain regions 256 and 257.

As described above, whether the structure of the gate electrode of the TFT is a single gate structure or a multi-gate structure in which a plurality of gate electrodes are provided between a pair of source and drain is determined according to the characteristics of the circuit. It is only necessary for the person to choose appropriately. Then, by using the active matrix substrate completed in this embodiment, a transmission type liquid crystal display device can be manufactured.

[Embodiment 2] The method of manufacturing an active matrix substrate in the present invention is not limited to a top gate type TFT, but may be applied to a TFT having an inverted stagger structure. FIG. 20 shows a TFT having an inverted staggered structure formed by a known technique, and a wiring and ITO of the present invention formed. 291 and the wiring indicated by the dotted line and IT
By applying the present invention to the contact portion of O as shown in FIG. 20B, electrolytic corrosion can be prevented.

[Embodiment 3] In this embodiment, another manufacturing method of the crystalline semiconductor layer for forming the active layer of the TFT of the active matrix substrate shown in Embodiments 1 and 2 will be described. The crystalline semiconductor layer is formed by crystallizing an amorphous semiconductor layer by a thermal annealing method, a laser annealing method, an RTA method, or the like. In addition, a catalytic element disclosed in JP-A-7-130652 is used. A crystallization method can also be applied. An example in that case will be described with reference to FIG.

As shown in FIG. 8A, in the same manner as in the first embodiment, a base film 1102a,
102b, 25 semiconductor layers 1103 having an amorphous structure
It is formed with a thickness of about 80 nm. The amorphous semiconductor layer includes an amorphous silicon (a-Si) film, an amorphous silicon / germanium (a-SiGe) film, and an amorphous silicon carbide (a-Si) film.
C) film, amorphous silicon tin (a-SiSn) film and the like can be applied. These amorphous semiconductor layers contain 0.1% of hydrogen.
It may be formed so as to contain about 40 atomic%. For example, an amorphous silicon film is formed with a thickness of 55 nm. Then, a layer 1104 containing a catalyst element is formed by a spin coating method in which an aqueous solution containing a catalyst element of 10 ppm by weight is applied by rotating the substrate with a spinner. The catalytic elements include nickel (Ni), germanium (Ge), iron (Fe), palladium (Pd), tin (Sn), and lead (P
b), cobalt (Co), platinum (Pt), copper (Cu),
Gold (Au) or the like. Layer 11 containing this catalytic element
In 04, the catalyst element layer may be formed to a thickness of 1 to 5 nm by a printing method, a spray method, a bar coater method, a sputtering method or a vacuum evaporation method other than the spin coating method.

Then, in the crystallization step shown in FIG. 8B, first, a heat treatment is performed at 400 to 500 ° C. for about 1 hour to reduce the hydrogen content of the amorphous silicon film to 5 atomic% or less. If the hydrogen content of the amorphous silicon film has this value from the beginning after film formation, this heat treatment is not always necessary. Then, thermal annealing is performed in a nitrogen atmosphere at 550 to 600 ° C. for 1 to 8 hours using a furnace annealing furnace. Through the above steps, a crystalline semiconductor layer 1105 made of a crystalline silicon film can be obtained (FIG. 8).
(C)). However, when the crystalline semiconductor layer 1105 formed by this thermal annealing is macroscopically observed with an optical microscope, an amorphous region may be locally observed to remain locally. Similarly, in Raman spectroscopy, an amorphous component having a broad peak at 480 cm ^-1 is observed. Therefore, increasing the crystallinity by treating the crystalline semiconductor layer 1105 by the laser annealing method described in Embodiment 1 after the thermal annealing can be applied as an effective means.

FIG. 9 shows an embodiment of a crystallization method using a catalytic element, in which a layer containing the catalytic element is formed by sputtering. First, as in the first embodiment,
Base films 1202 a and 1202 are formed on a glass substrate 1201.
b, 25-80 semiconductor layers 1203 having an amorphous structure
It is formed with a thickness of nm. Then, an oxide film (not shown) of about 0.5 to 5 nm is formed on the surface of the semiconductor layer 1203 having an amorphous structure. For the oxide film having such a thickness, a corresponding film may be positively formed by a plasma CVD method, a sputtering method, or the like. The surface of the semiconductor layer 1203 having a crystalline structure may be exposed, or the semiconductor layer 1 having an amorphous structure may be exposed to a solution containing aqueous hydrogen peroxide (H ₂ O ₂ ).
203 may be formed by exposing the surface. Alternatively, ozone is generated by irradiating ultraviolet light in an atmosphere containing oxygen,
Semiconductor layer 12 having an amorphous structure in the ozone atmosphere
03 can also be formed.

As described above, the layer 1204 containing the catalytic element is formed by the sputtering method on the semiconductor layer 1203 having a thin oxide film on the surface and having an amorphous structure. The thickness of this layer is not limited, but may be about 10 to 100 nm. For example, with Ni as a target, Ni
Forming a film is an effective method. In the sputtering method, a part of the high-energy particles composed of the catalyst element accelerated by an electric field also fly to the substrate side, and an oxide formed near the surface of the semiconductor layer 1203 having an amorphous structure or on the surface of the semiconductor layer. Driven into the film. The ratio varies depending on the plasma generation conditions and the bias state of the substrate, but preferably, the amount of the catalytic element implanted into the vicinity of the surface of the semiconductor layer 1203 having an amorphous structure or into the oxide film is reduced to 1%.
The density is preferably set to about × 10 ¹¹ to 1 × 10 ¹⁴ atom / cm ² .

After that, the layer 1204 containing the catalyst element is selectively removed. For example, when this layer is formed of a Ni film, it can be removed with a solution such as nitric acid, or can be treated with an aqueous solution containing hydrofluoric acid to obtain a Ni film.
The oxide film formed over the film and the semiconductor layer 1203 having an amorphous structure can be removed at the same time. In any case, the amount of the catalyst element in the vicinity of the surface of the semiconductor layer 1203 having an amorphous structure is set to be about 1 × 10 ¹¹ to 1 × 10 ¹⁴ atom / cm ² . Then, as shown in FIG. 9B, FIG.
The crystallization step by thermal annealing is performed in the same manner as described above to obtain the crystalline semiconductor layer 1205 (FIG. 8).
(C)).

The crystalline semiconductor layers 1105 and 1205 manufactured in FIG. 8 or FIG.
In this manner, the active matrix substrate can be completed in the same manner as in the first embodiment. However, when a catalyst element that promotes silicon crystallization is used in the crystallization step, a trace amount (1 × 10 ¹⁷ to 1 × 10 ¹⁷⁾ is contained in the island-shaped semiconductor layer.
× 10 ¹⁹ atomic / cm ³ ) of the catalytic element remains. Of course, the TFT can be completed in such a state, but it is more preferable to remove the remaining catalyst element from at least the channel formation region. One of the means for removing the catalytic element is a means utilizing a gettering action by phosphorus (P).

The gettering process using phosphorus (P) for this purpose can be performed simultaneously in the activation step described with reference to FIG. This will be described with reference to FIG. The concentration of phosphorus (P) necessary for gettering may be substantially the same as the impurity concentration of the high-concentration n-type impurity region. The element can be segregated into the impurity region containing phosphorus (P) at that concentration (the direction of the arrow shown in FIG. 10). As a result, a catalyst element of about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atomic / cm ³ segregated in the impurity region. The TFT thus manufactured has a low off-current value and high crystallinity, so that a high field-effect mobility can be obtained and good characteristics can be achieved.

[Embodiment 4] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described. First,
As shown in FIG. 11A, a spacer including a columnar spacer is formed on the active matrix substrate in the state of FIG. 4C. The spacer may be provided by scattering particles of several μm, but here, a method of forming a resin film over the entire surface of the substrate and then patterning the resin film is adopted. Although the material of such a spacer is not limited, for example, JSR
After applying by a spinner using NN700 manufactured by KK, a predetermined pattern is formed by exposure and development. Further, it is cured by heating at 150 to 200 ° C. in a clean oven or the like.

The arrangement of the spacers may be determined arbitrarily. Preferably, as shown in FIG. 11A, the pixel portion overlaps the contact portion 231 of the drain wiring 153 (pixel electrode) to cover the portion. Like columnar spacer 4
06 is preferably formed. Since the flatness of the contact portion 231 is impaired and the liquid crystal is not well aligned in this portion, the columnar spacer 406 is formed in such a manner that the contact portion 231 is filled with the resin for the spacer, so that disclination or the like is performed. Can be prevented.
The spacers 405a to 405 are also provided on the TFT of the driving circuit.
5e is formed in advance. This spacer may be formed over the entire surface of the drive circuit portion, or may be provided so as to cover the source wiring and the drain wiring as shown in FIG.

After that, an alignment film 407 is formed. Usually, a polyimide resin is used for the alignment film of the liquid crystal display element. After forming the alignment film, a rubbing treatment was performed so that the liquid crystal molecules were aligned with a certain pretilt angle. The area not rubbed in the rubbing direction from the end of the columnar spacer 406 provided in the pixel portion was set to 2 μm or less. In the rubbing treatment, generation of static electricity often poses a problem, but the effect of protecting the TFT from static electricity can be obtained by the spacers 405a to 405e formed on the TFT of the driving circuit. Although not described in the drawing, after forming the alignment film 407 first, the spacers 406, 40
5a to 405e may be formed.

The opposing substrate 401 on the opposing side has a light shielding film 40
2. A transparent conductive film 403 and an alignment film 404 are formed.
The light-shielding film 402 includes a Ti film, a Cr film, an Al film,
It is formed with a thickness of 300 nm. Then, the active matrix substrate on which the pixel portion and the driver circuit are formed and the counter substrate are attached with a sealant 408. A filler (not shown) is mixed in the sealant 408, and the two substrates are bonded at a uniform interval by the filler and the spacers 406 and 405a to 405e. After that, a liquid crystal material 409 is injected between the two substrates. A known liquid crystal material may be used as the liquid crystal material. For example, in addition to the TN liquid crystal, a thresholdless antiferroelectric mixed liquid crystal exhibiting electro-optical response in which the transmittance continuously changes with respect to an electric field can be used. In this thresholdless antiferroelectric mixed liquid crystal,
Some exhibit a V-shaped electro-optical response characteristic. Thus, the active matrix liquid crystal display device shown in FIG. 11B is completed.

FIG. 12 is a top view of such an active matrix substrate, and is a top view showing a positional relationship between a pixel portion and a driving circuit portion, a spacer, and a sealant. A scanning signal driving circuit 605 and an image signal driving circuit 606 are provided as driving circuits around the pixel portion 604 on the glass substrate 101 described in Embodiment 1. In addition, other CPU
A signal processing circuit 607 such as a memory and a memory may be added. These drive circuits are connected to an external input / output terminal 602 by a connection wiring 603. Pixel section 6
In 04, a pixel is formed by intersecting a group of gate wirings 608 extending from the scanning signal driving circuit 605 and a group of source wirings 609 extending from the image signal driving circuit 606 in a matrix. Capacity 2
05 is provided.

In FIG. 11, the columnar spacer 406 provided in the pixel portion may be provided for all the pixels, but is provided every several to several tens of pixels arranged in a matrix as shown in FIG. May be. That is, the ratio of the number of spacers to the total number of pixels constituting the pixel portion is 20 to
It can be 100%. Further, the spacers 405a to 405e provided in the drive circuit portion may be provided so as to cover the entire surface or may be provided in accordance with the positions of the source and drain wirings of each TFT. In FIG. 12, the arrangement of the spacers provided in the drive circuit portion is indicated by 610 to 612. The sealant 619 shown in FIG. 12 is outside the pixel portion 604 and the scanning signal driving circuit 605, the image signal driving circuit 606, and other signal processing circuits 607 on the substrate 101, and is higher than the external input / output terminal 602. Formed inside.

The structure of such an active matrix type liquid crystal display device will be described with reference to the perspective view of FIG. FIG.
In 3, the active matrix substrate is a glass substrate 1
01, a pixel portion 604, a scanning signal driving circuit 605, an image signal driving circuit 606, and another signal processing circuit 607. The pixel portion 604 includes a pixel T
An FT 204 and a storage capacitor 205 are provided, and a driving circuit provided around the pixel portion is configured based on a CMOS circuit. From the scanning signal driving circuit 605 and the image signal driving circuit 606, a gate wiring 122 and a source wiring 148 extend to the pixel portion 604 and are connected to the pixel TFT 204. In addition, flexible printed wiring boards (Fl
An exible printed circuit (FPC) 613 is connected to the external input terminal 602 and used to input image signals and the like. The FPC 613 is firmly bonded by a reinforcing resin 614. The connection wiring 603 is connected to each drive circuit. Further, a light shielding film and a transparent electrode, not shown, are provided on the counter substrate 401.

The liquid crystal display device having such a structure can be formed using the active matrix substrate shown in the first embodiment. When the active matrix substrate described in Embodiment 1 is used, a transmission type liquid crystal display device can be obtained.

Embodiment 5 FIG. 14 shows an example of the circuit configuration of the active matrix substrate shown in Embodiments 1 and 2.
FIG. 3 is a diagram illustrating a circuit configuration of a direct-view display device. This active matrix substrate includes an image signal driving circuit 606, scanning signal driving circuits (A) and (B) 605, and a pixel portion 604. Note that the driving circuits described in this specification include an image signal driving circuit 606 and a scanning signal driving circuit 605.
Is a generic term that includes

The image signal driving circuit 606 includes a shift register circuit 501a, a level shifter circuit 502a, a buffer circuit 503a, and a sampling circuit 504.
Each of the scanning signal driving circuits (A) and (B) 185 includes a shift register circuit 501b, a level shifter circuit 502b, and a buffer circuit 503b.

The shift register circuits 501a and 501b have a drive voltage of 5 to 16 V (typically 10 V), and the TFT of the CMOS circuit forming this circuit is shown in FIG.
Of the first p-channel TFT (A) 200a and the first n
It is formed of a channel type TFT (A) 201a. Or,
The first p-channel TFT (B) 20 shown in FIG.
0b and the first n-channel TFT (B) 201b. Also, level shifter circuits 502a, 502
b and the buffer circuits 503a and 503b have a drive voltage of 14
Since the voltage becomes as high as １６16 V, a multi-gate TFT structure as shown in FIG. Forming a TFT with a multi-gate structure increases the breakdown voltage, which is effective in improving the reliability of the circuit.

The sampling circuit 504 is composed of an analog switch and has a drive voltage of 14 to 16 V. However, since the polarity is alternately inverted and the off-current value needs to be reduced, the sampling circuit 504 shown in FIG. And the second p-channel TFT (A) 202a and the second n-channel TFT
(A) It is desirable to form it with 203a. Alternatively, a second p-channel TFT (B) 200b and a second n-channel TFT (B) 201b illustrated in FIG. 5B may be formed in order to effectively reduce the off-state current.

The driving voltage of the pixel portion is 14 to 16 V, and it is required to further reduce the off-current value as compared with the sampling circuit from the viewpoint of low power consumption.
The multi-gate structure is basically used like the pixel TFT 204 shown in FIG.

The structure of this embodiment can be easily realized by manufacturing a TFT according to the steps shown in the first and second embodiments. In the present embodiment, only the configuration of the pixel portion and the driving circuit is shown. However, according to the steps of the first and second embodiments, a signal dividing circuit, a frequency dividing circuit, a D / A converter, a γ correction circuit An operational amplifier circuit, a signal processing circuit such as a memory circuit or an arithmetic processing circuit, or a logic circuit can be formed over the same substrate. As described above, the present invention can realize a semiconductor device including a pixel portion and a driver circuit over the same substrate, for example, a liquid crystal display device including a signal control circuit and a pixel portion.

[Embodiment 6] In the present invention, no electrolytic corrosion occurs.
This determines the laminated structure of the conductive metal wiring and the ITO film, and can be applied as a means for increasing the mechanical strength of the conductive metal wiring. In this embodiment, the mechanical strength is increased by forming a conductive metal wiring, which is a terminal portion for connecting the flexible printed circuit board, on the glass substrate on the ITO film. The reason why ITO is used is that when a liquid crystal display device or an EL display device is manufactured on the glass substrate, the film is formed after the conductive metal wiring is formed, so that the number of steps is not increased. This step will be described with reference to FIG.

FIGS. 16A and 16B show an interlayer insulating film 270.
The steps of forming 1, 2702, and 2703 are described. The interlayer insulating film is formed for the purpose of imparting insulation and adhesion.
If this is achieved on glass, it need not be.
In (C), a conductive metal wiring 2704 is formed.
The conductive metal wiring is formed so as to have a structure of three or more layers as in the first embodiment. In the case where the Al oxide layer 2705 is not sufficiently formed, oxygen plasma or thermal oxidation may be used.
In (D), an ITO film 2706 is formed on the conductive metal wiring. In this example, the ITO film is also left in a portion where the conductive metal wiring is not formed. (E)
A spacer 2707 is formed in a portion other than a portion to be a terminal. From this state, the flexible printed circuit board can be bonded by a known technique.

[Embodiment 7] An active matrix substrate, a liquid crystal display device, and an E manufactured according to the present invention are manufactured.
The L-type display device can be used for various electro-optical devices. The present invention can be applied to all electronic devices incorporating such an electro-optical device as a display medium. Examples of the electronic device include a personal computer, a digital camera, a video camera, a portable information terminal (such as a mobile computer, a mobile phone, and an electronic book), and a navigation system.

FIG. 17A shows a portable information terminal, which comprises a main body 2201, an image input section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention can be applied to the display device 2205 and other signal control circuits.

[0095] Such portable information terminals are often used not only indoors but also outdoors. In order to enable long-term use, no backlight is used, and a reflective liquid crystal display device that uses external light is suitable as a low-power-consumption type, but a backlight is provided when the surroundings are dark. A transmissive liquid crystal display device is suitable. Against this background, a hybrid type liquid crystal display device having both the reflection type and the transmission type features has been developed, but the present invention can also be applied to such a hybrid type liquid crystal display device. The display device 2205 includes a touch panel 3002 and a liquid crystal display device 300
3. It is composed of an LED backlight 3004. The touch panel 3002 is provided to simplify the operation of the portable information terminal. In the configuration of the touch panel 3002, a light emitting element 3100 such as an LED is provided at one end, and a light receiving element 3200 such as a photodiode is provided at the other end, and an optical path is formed between the two. When the optical path is interrupted by pressing the touch panel 3002, the light receiving element 3200
Since the output of the light-emitting element changes, the light-emitting element and the light-receiving element are arranged in a matrix on the liquid crystal display device using this principle, so that the element can function as an input medium.

FIG. 17B shows a structure of a pixel portion of a hybrid type liquid crystal display device. The drain wiring 2 is formed on the pixel TFT 204 and the second interlayer insulating film on the storage capacitor 205.
63 and a pixel electrode 262 are provided. Such a configuration can be formed by applying the first embodiment. At this time, the drain wiring has a laminated structure as shown in Embodiment 1, and is configured to also serve as a pixel electrode. Pixel electrode 2
Reference numeral 62 is formed using the transparent conductive film material described in the first embodiment. By manufacturing the liquid crystal display device 3003 from such an active matrix substrate, the liquid crystal display device 3003 can be suitably used for a portable information terminal.

FIG. 18A shows a personal computer, which comprises a main body 2001 having a microprocessor, a memory, and the like, an image input unit 2002, a display device 2003, and a keyboard 2004. The present invention relates to a display device 20.
03 and other signal processing circuits can be formed.

FIG. 18B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, an operation switch 2104, a battery 2105, and an image receiving unit 21.
06. The present invention can be applied to the display device 2102 and other signal control circuits.

FIG. 18D shows a player using a recording medium on which a program is recorded (hereinafter, referred to as a recording medium).
403, a recording medium 2404, and operation switches 2405. The recording medium is a DVD (Digital Versati
le Disc) and compact disc (CD)
Playback of music programs, video display, information display via video games and the Internet, and the like can be performed.
The present invention can be suitably used for the display device 2402 and other signal control circuits.

FIG. 18E shows a digital camera, which comprises a main body 2501, a display device 2502, an eyepiece section 2503, operation switches 2504, and an image receiving section (not shown). The present invention can be applied to the display device 2502 and other signal control circuits.

FIG. 19A shows a front type projector, which comprises a light source optical system, a display device 2601, and a screen 2602. The present invention can be applied to a display device and other signal control circuits. FIG. 19B illustrates a rear projector, which includes a main body 2701, a light source optical system and a display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to a display device and other signal control circuits.

FIG. 19C shows the light source optical system and the display device 26 shown in FIGS. 19A and 19B.
01 and 2702 are shown as examples. A light source optical system and display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802 and 2804 to 2806, a dichroic mirror 2803, a beam splitter 2807, a liquid crystal display device 2808, a phase difference plate 2809, and a projection optical system 2810.
It consists of. The projection optical system 2810 includes a plurality of optical lenses. FIG. 19C illustrates a liquid crystal display device 2808.
Although an example of a three-plate system using three is shown, the present invention is not limited to such a system, and a single-plate optical system may be used. An optical path indicated by an arrow in FIG. 19C may be provided with a suitable optical lens, a film having a polarizing function, a film for adjusting a phase, an IR film, or the like. FIG. 19D shows the light source optical system 2 shown in FIG. 19C.
801 is a diagram showing an example of the structure of FIG. In this embodiment,
The light source optical system 2801 includes a reflector 2811 and a light source 28.
12, a lens array 2813, 2814, a polarization conversion element 2815, and a condenser lens 2816. FIG.
The light source optical system shown in FIG. 9D is an example, and is not limited to the illustrated configuration.

Although not shown here, the present invention can also be applied to a navigation system, a reading circuit of an image sensor, and the like. As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. Further, the electronic apparatus of the present embodiment can be realized by using the techniques of Embodiments 1 to 4.

[0104]

According to the present invention, in the manufacture of a semiconductor device using a transparent conductive film, the yield can be improved and the number of steps can be reduced.

According to the method for manufacturing a semiconductor device of the present invention,
P-channel TFT and N-channel TFT for drive circuit
In addition, an active matrix substrate having an LDD structure in which a pixel TFT overlaps with a gate electrode can be manufactured using five photomasks. From such an active matrix substrate, a transmission type liquid crystal display device can be manufactured with six photomasks.

[0106]

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 2 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 3 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 4 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 5 is a cross-sectional view illustrating a structure of a TFT of a driver circuit.

FIG. 6 is a cross-sectional view illustrating a configuration of a pixel TFT.

FIG. 7 is a top view illustrating pixels in a pixel portion.

FIG. 8 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG. 9 is a cross-sectional view illustrating a manufacturing process of a crystalline semiconductor layer.

FIG. 10 is a cross-sectional view illustrating a manufacturing process of a pixel TFT and a TFT of a driver circuit.

FIG. 11 is a cross-sectional view illustrating a manufacturing process of an active matrix liquid crystal display device.

FIG. 12 is a top view illustrating input / output terminals, wiring, circuit arrangement, spacers, and sealants of a liquid crystal display device.

FIG. 13 is a perspective view illustrating a structure of a liquid crystal display device.

FIG. 14 is a block diagram illustrating a circuit configuration of a liquid crystal display device.

15A and 15B are a cross-sectional view of a TFT and a diagram illustrating a configuration of an LDD region.

FIG. 16 is a cross-sectional view showing a step of manufacturing a wiring / ITO laminated structure in an FPC connection portion.

FIG. 17 illustrates an example of a portable information terminal.

FIG. 18 illustrates an example of a semiconductor device.

FIG. 19 illustrates a configuration of a projection-type liquid crystal display device.

FIG. 20 is a cross-sectional view illustrating a structure of a pixel portion in an inverted staggered TFT.

FIG. 21 is a TEM photograph of an ITO / wiring laminated sample structure according to the present invention.

FIG. 22 is an optical microscope photograph when an aluminum film and an ITO film are laminated, patterned, and etched.

FIG. 23 is an optical microscope photograph when an ITO / wiring laminate according to the present invention is formed.

FIG. 24 shows E at the thin film boundary and interface in the present invention.
DX measurement results.

FIG. 25 shows E at the thin film boundary and interface in the present invention.
DX measurement results.

FIG. 26 shows E at the thin film boundary and interface in the present invention.
DX measurement results.

FIG. 27 shows E at the thin film boundary and interface in the present invention.
DX measurement results.

FIG. 28 shows E at the thin film boundary and interface in the present invention.
DX measurement results.

FIG. 29 shows E at the thin film boundary and interface in the present invention.
DX measurement results.

FIG. 30 shows E at the thin film boundary and interface in the present invention.
DX measurement results.

FIG. 31 shows E at a thin film boundary and an interface in the present invention.
DX measurement results.

FIG. 32 shows the result of EDX measurement in a thin film according to the present invention.

FIG. 33 shows the result of EDX measurement in a thin film according to the present invention.

FIG. 34 shows the result of EDX measurement in a thin film according to the present invention.

FIG. 35 shows the result of EDX measurement in a thin film according to the present invention.

FIG. 36 shows the results of EDX measurement in a thin film according to the present invention.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/78 616J (72) Inventor Kengo Akimoto 398 Hase, Atsugi-shi, Kanagawa Japan Semiconductor Energy Laboratory F Term (reference) 2H092 GA50 GA51 HA04 HA06 JA24 JA46 KA03 KA04 KA05 KA12 KB04 KB13 MA08 MA14 MA19 MA30 NA27 NA29 PA03 PA06 5C094 AA42 AA43 BA03 BA43 CA19 CA24 DA14 DA15 EA04 EA07 EB02 FB12 FB14 A10 HA10 BB04 CC02 DD01 DD02 DD13 DD14 DD15 DD17 EE04 EE14 EE22 EE23 EE28 EE44 FF02 FF04 FF12 FF28 FF30 FF36 GG01 GG02 GG13 GG28 GG32. NN72 NN78 PP01 PP02 PP03 PP34 PP35 QQ09 QQ11 QQ24 QQ25 QQ28

Claims (13)

[Claims] In a semiconductor device having a pixel portion, a pixel electrode provided in the pixel portion has a light-transmitting property, is formed on an insulating film, is connected to a conductive metal wiring, The wiring includes a first conductive layer made of a heat-resistant metal, aluminum formed on the first conductive layer or a second conductive layer containing aluminum as a main component, and a wiring formed on the second conductive layer. And a third conductive layer made of a heat-resistant metal formed on the substrate, wherein the heat-resistant metal is Ti, Cr, M
o, one or more elements selected from W as a main component, the pixel electrode is in contact with the surface and end of the third conductive layer, the pixel electrode, the first conductive layer, The aluminum concentration at the boundary between the second conductive layer and the pixel electrode in contact with the end of the second conductive layer is 70 at.
A semiconductor device, wherein a region having an atomic concentration of 25 atomic% or less and an oxygen concentration of 25 atomic% or more is formed. 2. A semiconductor device having a liquid crystal sandwiched between a pair of substrates, wherein one of the substrates has a pixel portion, a pixel electrode provided in the pixel portion has a light transmitting property, and is provided on an insulating film. And is connected to a conductive metal wiring. The conductive metal wiring mainly includes a first conductive layer made of a heat-resistant metal, and aluminum or aluminum formed on the first conductive layer. A second conductive layer as a component, a third conductive layer made of a heat-resistant metal formed on the second conductive layer,
Wherein the heat-resistant metal contains one or more elements selected from Ti, Cr, Mo, and W as main components, and the pixel electrode has a surface and an edge of a thin film layer made of the third heat-resistant metal. Contact, the pixel electrode, the thin film layer made of the first heat-resistant metal, contact the end of the second thin film, at the boundary between the second conductive layer and the pixel electrode, A region in which the aluminum concentration is 70 atomic% or less and the oxygen concentration is 25 atomic% or more is formed, and the region is provided on the other substrate on which the transparent conductive film is formed and on the second interlayer insulating film. A semiconductor device, which is bonded via at least one columnar spacer formed so as to overlap with an opening. 3. A semiconductor device to which a flexible printed circuit board is connected, wherein the conductive metal wiring comprises a first conductive layer made of a heat-resistant metal, and aluminum or aluminum formed on the first conductive layer. And a third conductive layer made of a heat-resistant metal formed on the second conductive layer, wherein the heat-resistant metal is Ti, Cr, Mo. , W as a main component, a transparent conductive film is formed on the conductive metal wiring, and the transparent conductive film contacts a surface and an end of the third conductive layer. And the transparent conductive film is
The first conductive layer, in contact with the end of the second conductive layer, at the boundary between the second conductive layer and the pixel electrode, the aluminum concentration is 70 atomic% or less, and the oxygen concentration is A semiconductor device, wherein a region of 25 atomic% or more is formed and bonded to the flexible printed circuit board. 4. The semiconductor device according to claim 1, wherein the semiconductor device is a personal computer, a video camera, a portable information terminal, a digital camera, a digital video disc player, and a projector. Semiconductor device. 5. The TiN film according to any one of claims 1 to 4, wherein the first conductive layer has a thickness of 50 to 150 nm and a TiN film having a thickness of 50 to 150 nm stacked on the Ti film having a thickness of 50 to 150 nm. The second conductive layer is formed of aluminum or a film containing aluminum as a main component with a thickness of 300 to 400 nm, and the third conductive layer is formed of a Ti film or a titanium nitride film of 100 nm.
A semiconductor device formed to a thickness of 200 nm. 6. A method for manufacturing a semiconductor device having a pixel TFT, comprising: a first step of forming an interlayer insulating film made of an insulating material above a driving circuit; and forming an opening provided in the interlayer insulating film. A conductive metal wiring connected to the pixel TFT through a second step of forming a thin film layer made of a heat-resistant metal; and a thin film mainly composed of aluminum or aluminum on the thin film layer made of the heat-resistant metal. A third step of forming a layer, and a fourth step of forming a thin film layer made of a heat-resistant metal on the aluminum or the thin film layer containing aluminum as a main component, wherein the heat-resistant metal comprises: A fifth step of forming a pixel electrode connected to the conductive metal wiring on the interlayer insulating film, the method including a main component containing one or more elements selected from Ti, Cr, Mo, and W. When A method for manufacturing a semiconductor device that. 7. A method for manufacturing a semiconductor device in which a liquid crystal is sandwiched between a pair of substrates, wherein one of the substrates includes a pixel TFT provided in a pixel portion and an interlayer insulating film formed on the one substrate above a driving circuit. A second step of forming a thin film layer made of a heat-resistant metal on a conductive metal wiring connected to the pixel TFT through an opening provided in the interlayer insulating film; A third step of forming a thin film layer mainly composed of aluminum or aluminum on the thin film layer composed of heat-resistant metal, and a thin film composed of heat-resistant metal on the thin film layer mainly composed of aluminum or aluminum. Forming a pixel electrode connected to the conductive metal wiring on the interlayer insulating film, and forming at least a transparent conductive film on the other substrate. No. And a seventh step of bonding the one substrate and the other substrate through at least one columnar spacer formed so as to overlap the opening. Method. 8. A method for manufacturing a semiconductor device to which a flexible printed circuit is connected, wherein the conductive metal wiring is formed by a first step of forming a thin film layer made of a heat-resistant metal, and a step of forming the thin film layer made of the heat-resistant metal. A second step of forming a thin film layer mainly composed of aluminum or aluminum thereon, and a third step of forming a thin film layer made of a heat-resistant metal on the thin film layer mainly composed of aluminum or aluminum. And a fifth step of forming a transparent conductive film on the conductive metal wiring, and a fifth step of bonding the flexible printed circuit board and the semiconductor device. Of manufacturing a semiconductor device. 9. The method according to claim 6, wherein after the conductive metal wiring is formed, the substrate is exposed to an air atmosphere, and then a process using oxygen plasma is performed. Alternatively, the concentration of aluminum is 70 atomic% at the end of the thin film layer mainly containing aluminum.
A method for manufacturing a semiconductor device, wherein a region having an oxygen concentration of 25 atomic% or more is formed as follows. 10. The method according to claim 6, wherein after forming the conductive metal wiring and immediately before forming the pixel electrode, the conductive metal wiring is formed in a chamber in which the pixel electrode is formed. A method for manufacturing a semiconductor device, comprising: treating a conductive metal wiring using oxygen plasma. 11. The conductive metal wiring according to claim 6, wherein said conductive metal wiring is formed by etching with plasma and then said conductive metal wiring is formed by fluorine plasma and oxygen plasma while maintaining a reduced pressure atmosphere. A method for manufacturing a semiconductor device, comprising performing processing using a semiconductor device. 12. The method for manufacturing a semiconductor device according to claim 6, wherein the conductive metal wiring is formed and then heated in an atmosphere containing oxygen. 13. The semiconductor device according to claim 6, wherein the semiconductor device is a personal computer, a video camera, a portable information terminal, a digital camera,
A method for manufacturing a semiconductor device, which is a digital video disk player or a projector.