JP2001196596A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for improving the reliability of a semiconductor device, such as a thin-film transistor(TFT) superior in characteristics/reliability. SOLUTION: Related to the process of forming a semiconductor device such as a thin-film transistor on an insulating film, after a coat whose main component is aluminum nitride is formed, a semiconductor device, such as TFT is formed directly over it or formed with a film whose main component is silicon oxide film, etc., in-between. A thin-film integrated circuit, where the semiconductor device is integrated applied especially to an active matrix type liquid-crystal display, is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for improving the reliability of an insulated gate semiconductor device on a substrate and an integrated circuit in which many of them are formed. The semiconductor device according to the present invention includes a driving circuit such as an active matrix such as a liquid crystal display using a thin film transistor (TFT) or an image sensor, or an SOI integrated circuit or a conventional semiconductor integrated circuit (a microprocessor, a microcontroller, a microcomputer, or a semiconductor). Memory).

[0002]

2. Description of the Related Art In recent years, an insulating gate type semiconductor device (MI) has been formed on an insulating substrate or on a surface (insulating surface) separated from the semiconductor substrate by a thick insulating film even on a semiconductor substrate.
Research on forming SFETs has been actively conducted. In particular, a semiconductor device in which a semiconductor layer (active layer) is a thin film is called a thin film transistor (TFT). In such a semiconductor device, it is difficult to obtain an element having good crystallinity such as a single-crystal semiconductor. Usually, a non-single-crystal semiconductor which has crystallinity but is not a single crystal is used.

In such a non-single-crystal semiconductor, the defect density is large, and the defect is filled by neutralizing the defect with an element such as hydrogen or fluorine. For example, such a process is realized by hydrogenation. Was. But,
The bond between hydrogen and a semiconductor element (such as silicon) was weak, and was decomposed by thermal energy of one hundred and several tens of degrees Celsius. For this reason, when a voltage and a current are applied for a long time and the semiconductor locally generates heat, hydrogen is easily released, and the characteristics are remarkably deteriorated. In particular, in a TFT for controlling a large current, for example, in a monolithic active matrix circuit having an active matrix circuit and a peripheral circuit for driving the same, the driver TFT of the peripheral circuit has a channel width of 200 μm or more, so that a large current can be generated. Turning on / off was a major heat source.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is intended to quickly dissipate local heat generated during use of a device and to uniformly heat the entire thin film circuit device. It is an object to provide a structure of the device and a method for manufacturing such a semiconductor device.

[0005]

According to a first aspect of the present invention, there is provided a thin film semiconductor device in which a film mainly composed of aluminum nitride is formed on a substrate and a semiconductor film mainly composed of silicon is directly or indirectly formed thereon. And a wiring such as a metal or a semiconductor directly or indirectly provided thereon. The present invention also relates to a method for manufacturing a thin film semiconductor device having such a configuration.
Is a process of forming a film containing aluminum nitride as a main component on a substrate, particularly a glass substrate having poor heat conductivity and good heat insulation, and directly or indirectly forming a semiconductor film containing silicon as a main component on the glass substrate. The method is characterized by including a forming step and a step of directly or indirectly forming a wiring of metal, semiconductor, or the like thereon.

Aluminum nitride has extremely excellent thermal conductivity and is transparent (visible band gap: 6.2 eV) to visible light and near-ultraviolet light, so that it is suitable for purposes requiring transparency. Aluminum nitride is sputtered, reactive sputtered, MOCVD (metal organic chemical vapor deposition)
And a plasma CVD method. In order to obtain an aluminum nitride film by a reactive sputtering method, it is preferable to use aluminum as a target in a nitrogen atmosphere. As in the present invention, for sufficient heat radiation, the thickness of the aluminum nitride is preferably from 500 to 5 μm, typically from 1,000 to 5,000. 5
Aluminum nitride having a thickness of μm or more was easily peeled off and was not suitable for use.

Further, since the aluminum nitride film has a blocking effect on mobile ions such as sodium, it also has an effect of preventing these ions from entering the semiconductor device from the substrate. The ratio of nitrogen to aluminum in the aluminum nitride film may be a stoichiometric ratio or a non-stoichiometric ratio as long as there is no problem in heat conduction.
Typically, the ratio of nitrogen to aluminum is preferably (aluminum / nitrogen) = 0.9 to 1.4, and the thermal conductivity is 0.6 W / cmK or more (the thermal conductivity of the aluminum nitride single crystal is 2W / cmK), favorable results were obtained.

[0008] The stress of the coating may be optimized by changing the ratio of nitrogen to aluminum. Further, by adding a small amount of boron, silicon, carbon, oxygen, etc. in an amount of 0.01 to 20 atomic% in addition to nitrogen and aluminum, it is possible to match, optimize, and minimize stress distortion with a substrate. is there. The coating containing aluminum nitride as a main component may be crystalline or amorphous.

For the purpose of improving the thermal conductivity, it is usually considered to use a diamond-based material (for example, a polycrystalline diamond thin film, a hard carbon film, a diamond-like carbon film, etc.). In such a minute region, a diamond-based material generally has poor adhesion to a silicon oxide-based material, so that a sufficient effect cannot be obtained. In addition, a silicon nitride film often used as a blocking layer and a passivation layer in an ordinary semiconductor process has a low thermal conductivity and is not suitable for implementing the present invention. Table 1 below
Next, the characteristics of the main thin film materials were compared. (O is excellent, Δ is medium, and X is inferior.)

[0010]

[Table 1]

In the present invention, heat generated from a metal or semiconductor wiring (gate wiring or the like) is transmitted to an underlying semiconductor film (active layer or the like), and also a current flows through the semiconductor film. Heat is generated, and the temperature of the semiconductor film rises. However, without staying there, the temperature is quickly transmitted to the aluminum nitride film thereunder. Hydrogen desorption is reduced. In particular, local deterioration due to local heat generation due to generation of hot carriers due to application of a high reverse bias voltage between the drain and channel of the TFT can be suppressed by soaking.

In the present invention, depositing a semiconductor film directly on an aluminum nitride film is advantageous in that although the adhesion is good, a semiconductor carrier is trapped in the aluminum nitride and a parasitic channel formed by the trapped carrier (capture center). Are apt to occur and, as a result, adversely affect the electrical characteristics of the semiconductor film, which is not preferable. There is no problem if such trapping centers can be removed, but if it cannot be easily removed, a material that is electrically and chemically preferable to a semiconductor film such as a silicon oxide film (a silicon oxide film is made of aluminum nitride Preferably, the density of the capture centers is only a few tens of minutes compared to the film) between the two films. Further, in the silicon oxide film, an effect of stress relaxation can be expected.

Further, a silicon nitride film is formed on aluminum nitride in a thickness of 100 to 1000, for example, 200, and a silicon oxide film is formed thereon in a thickness of 100 to 2,000, for example, 200.
・ It was good to form. In the present invention, as a material of the gate electrode, a simple substance such as silicon (including a substance whose conductivity is increased by doping impurities), aluminum, tantalum, chromium, tungsten, molybdenum, or an alloy thereof, or a multilayer thereof is used. A film may be used.
Further, as shown in the embodiment, the surface may be oxidized.

Further, aluminum nitride is not etched by a fluorine-based etchant, and is not etched by a method of etching a material used in a normal semiconductor process such as silicon oxide, silicon, or aluminum. It may be used as a stopper. That is, as the contact of the source and the drain of the TFT, not only the upper surface but also the side surface of the source and the drain can be used as the contact. For example, even when the contact hole is formed to extend from the source and the drain, the substrate is not etched by the aluminum nitride serving as an etching stopper.

As a result, the source and drain regions can be formed smaller than before, which is advantageous for circuit integration. On the other hand, this also means that the contact hole can be enlarged, and a more reliable contact can be obtained, which is advantageous for mass productivity and reliability.

[0016]

[Embodiment 1] FIG. 1 shows an example of manufacturing a TFT according to the present invention. First, a substrate (Corning 705)
9 glass substrate, size 300mm x 300mm or 100mm x 100mm) 101, thickness 2000
An aluminum nitride film 102 having a thickness of ５5000 · was deposited by a reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. The pressure during sputtering is 1 ×
Preferred results were obtained at 10-4 to 1 x 10-2 Torr. The film forming speed was 20 to 200 / min. Further, at the time of film formation, the substrate temperature may be raised to 100 to 500 ° C.

The aluminum nitride film 102 was formed on both sides of the substrate. This is because foreign elements such as sodium contained in the substrate or adhered to the surface after shipping are TFT
With the meaning of containing so as not to deteriorate the characteristics of
This has the effect of strengthening the substrate and making the surface less likely to be scratched.
In particular, when a TFT is used in an active matrix type liquid crystal display device, the surface on which the TFT is not provided comes into contact with the external environment, but this surface is apt to be finely scratched. And darken the screen.

Next, the glass substrate on which the aluminum nitride is formed is heated at 600 to 680 ° C., for example, 640 ° C. for 4 to 1 hour.
Annealing was performed for 2 hours in an atmosphere of nitrogen, ammonia (NH3), or nitrous oxide (N2O). And it cooled slowly at 0.01-0.5 degreeC / min, for example, 0.2 degreeC / min, and took out when the temperature fell to 350-450 degreeC. By this step, the substrate that was colored yellow immediately after the reactive sputtering became transparent, and the electrical insulation was improved. Furthermore, in this annealing step,
As a result of the thermal contraction of the glass substrate and the relaxation of the stress, the irreversible contraction was reduced. For this reason, in the subsequent heat treatment step, shrinkage of the substrate was eliminated, and mask displacement was significantly reduced.

After the above annealing, a silicon oxide film having a thickness of 2000 to 500.multidot. Was formed as a base oxide film 103 on the surface on which the TFT was to be formed. As a method of forming this oxide film,
Sputtering in an oxygen atmosphere and TEOS were decomposed and deposited by plasma CVD in an oxygen atmosphere. Further, the film thus formed may be annealed at 450 to 650 ° C.

Thereafter, as shown in FIG.
An amorphous silicon film is formed in a thickness of 100 to 1500, preferably 300 to 800 by a VD method or an LPCVD method.
Deposit and pattern this to form island-shaped silicon regions 104. And the thickness 200 ~ 1500
Preferably, 500 to 1000 silicon oxide 105 is formed. This silicon oxide film also functions as a gate insulating film. Therefore, sufficient care is required for its production. Here, TEOS is used as a raw material, and a substrate temperature of 1 with oxygen.
RF at 50-600 ° C., preferably 300-450 ° C.
Decomposed and deposited by plasma CVD. The pressure ratio between TEOS and oxygen is 1: 1 to 1: 3, and the pressure is 0.05 to 0.
The RF power was set to 100 to 250 W at 5 torr. Alternatively, decompression C using TEOS as a raw material together with ozone gas
The substrate temperature is set to 35 by the VD method or the normal pressure CVD method.
It formed as 0-600 degreeC, Preferably it was 400-550 degreeC. After film formation, 400 ~ in oxygen or ozone atmosphere
Annealed at 600 ° C. for 30 to 60 minutes.

Then, as shown in FIG. 1A, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
ec) was irradiated to crystallize the silicon region 104. Laser energy density is 200-400mJ /
cm 2, preferably 250 to 300 mJ / cm 2, and the substrate is irradiated with a laser at 300 to 500 mJ / cm 2.
Heated to ° C. The silicon film 1 thus formed
When the crystallinity of No. 04 was examined by Raman scattering spectroscopy, a relatively broad peak near 515 cm −1 was observed, unlike the peak of single crystal silicon (521 cm −1). Thereafter, annealing was performed at 350 ° C. for 2 hours in hydrogen.

Thereafter, an aluminum film having a thickness of 2000 to 1 μm was formed by an electron beam evaporation method, and this was patterned to form a gate electrode 106. Aluminum may be doped with scandium (Sc) by 0.15 to 0.2% by weight. Next, the substrate is
7, immersed in an ethylene glycol solution of 1 to 3% tartaric acid, and anodized using platinum as a cathode and the aluminum gate electrode as an anode. The anodization was completed by first increasing the voltage to 220 V with a constant current and maintaining the state for one hour. In the present embodiment, in the constant current state, the voltage rising speed is suitably 2 to 5 V / min. Thus, the anodic oxide 107 having a thickness of 1500 to 3500., for example, 2000, was formed. (FIG. 1 (B))

Thereafter, an impurity (phosphorus) was implanted into the island-like silicon film of each TFT in a self-aligned manner by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion as a mask. Phosphine (PH3) was used as a doping gas. Dose amount is 1-4 × 1
015 cm-2.

Further, as shown in FIG. 1C, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
ec) was applied to improve the crystallinity of the portion where the crystallinity was deteriorated by the introduction of the impurity region. The energy density of the laser was 150 to 400 mJ / cm2, preferably 200 to 250 mJ / cm2. Thus, N-type impurity (phosphorus) regions 108 and 109 were formed.
The sheet resistance in these regions was 200 to 800 Ω / □. In this step, instead of using a laser, a flash lamp is used in a short
C. (temperature of the silicon monitor) and then heating the sample, so-called RTP (rapid thermal process) may be used.

Then, an interlayer insulator 110 is formed on the entire surface.
Plasma CVD of TEOS as raw material and oxygen
Method, reduced pressure CVD method with ozone, or normal pressure CV
A silicon oxide film having a thickness of 3000 was formed by Method D. The substrate temperature was 250 to 450 ° C, for example, 350 ° C.
After the film formation, the silicon oxide film was mechanically polished to obtain a flat surface. Further, an ITO film was deposited by a sputtering method, and this was patterned to obtain a pixel electrode 111. (Fig. 1 (D))

Then, the interlayer insulator 110 is etched to form contact holes in the source / drain of the TFT as shown in FIG. 1E, and wires 112 and 113 of chromium or titanium nitride are formed. Was connected to the pixel electrode 111. In this case, FIG. 1 (F)
As shown in (1), the contact hole may be formed by protruding the source / drain region (island-like silicon). In this case, the area of the contact holes protruding from the island-shaped silicon was 30 to 70%. In this case, the contact is formed not only on the upper surface of the source / drain but also on the side surface. Hereinafter, such a contact is referred to as a top side contact. In the conventional structure, if an attempt is made to form a top side contact, the silicon oxide film underlying the portion other than the island-shaped silicon and further the substrate are etched by the step of etching the interlayer insulator, but in this embodiment, The aluminum nitride film 102 serves as an etching stopper, and the etching stops here.

In the normal case, the size of the contact hole needs to be smaller than that of the source / drain. However, in the case of the top side contact, the size of the island can be made smaller than that of the contact hole. As a result, the island can be miniaturized. On the contrary, since the contact hole can be enlarged, mass productivity and reliability can be improved. Finally, 300 ~
Annealing was performed at 400 ° C. for 0.1 to 2 hours to complete hydrogenation of silicon. Thus, the TFT was completed.
A large number of TFTs manufactured at the same time were arranged in a matrix to form an active matrix type liquid crystal display device.

Embodiment 2 FIG. 2 shows an example of manufacturing a TFT according to the present invention. First, on a substrate (NA35 glass manufactured by NH Techno Glass) 201, a thickness of 1000
An aluminum nitride film 202 of 5 μm was deposited by a reactive sputtering method. Targeting aluminum,
Sputtering was performed in an atmosphere of nitrogen and argon. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. The pressure during sputtering is 1 × 10
Preferred results were obtained at -4 to 1 x 10-2 Torr. The film forming speed was 20 to 200 / min. Further, at the time of film formation, the substrate temperature may be raised to 100 to 500 ° C.

Next, as the base oxide film 203, a thickness of 100
A silicon oxide film having a thickness of 1000 to 1000, for example, 500 was formed. As a method of forming the oxide film, a sputtering method in an oxygen atmosphere or TEOS was decomposed and deposited by a plasma CVD method in an oxygen atmosphere. Thereafter, this film is 550-700
For example, at 650 ° C. for 4 hours.
Annealing was performed in a nitrogen atmosphere containing 20% of O). As a result, the aluminum nitride film became transparent, and the silicon oxide film thereon could be densified.

Thereafter, an amorphous silicon film is formed by plasma CVD or LPCVD to a thickness of 200 to 150 nm.
0., preferably 300 to 800., and annealed in a nitrogen atmosphere at 600 ° C. for 48 hours. The crystalline silicon film thus obtained was patterned to form an island-shaped silicon region 204. Then, as the gate insulating film 207, a thickness of 200 to 1500.
000 silicon oxide was formed.

Then, a silicon film doped with phosphorus having a thickness of 2000.about.5 .mu.m is formed by a low pressure CVD method.
This was patterned to form a gate electrode 209 and a wiring 208. Thereafter, an impurity (phosphorus) was implanted in a self-aligned manner into the island-like silicon film of the TFT by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion as a mask. Phosphine (PH3) was used as a doping gas. Dose amount is 1-8 ×
It was 1015 cm-2.

Further, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated to improve the crystallinity of the portion where the crystallinity was deteriorated by introducing the impurity region. Laser energy density is 150
４００400 mJ / cm 2, preferably 200 to 250 m
J / cm2. Thus, N-type impurity (phosphorus) regions 205 and 206 were formed. The sheet resistance in these regions was 200 to 800 Ω / □. (Fig. 2 (A))

Thereafter, a plasma CVD method, a low pressure CVD method, or a normal pressure C
A silicon oxide film having a thickness of 3000 was formed by the VD method.
Further, a photoresist 211 was selectively formed. Such a photoresist is preferably formed at a portion where the wiring intersects or a portion where the wiring is provided with a contact. (FIG. 2B) Then, as shown in FIG.
1 as a mask, an interlayer insulator 210, a gate insulator 2
07, the underlying silicon oxide film 203 was etched.
The underlying silicon oxide film was etched, but the substrate was not etched with the aluminum nitride film as a stopper. For this reason, a flat surface was obtained. (Fig. 2 (C))

Then, a titanium film (having a thickness of 2
000.about.5 .mu.m), and patterning the same to form a wiring 212 connecting to the source and drain of the TFT.
213 were formed. Further, ITO was selectively formed to form a pixel electrode 214. Finally, the substrate thus treated was annealed in hydrogen at 1 atm and 350 ° C. for 30 minutes to complete the hydrogenation. Thus, the TFT was completed. A large number of TFTs manufactured at the same time were arranged in a matrix to form an active matrix type liquid crystal display device.

Embodiment 3 FIG. 3 shows an example of manufacturing a TFT according to the present invention. The TFT of this embodiment is a TFT of a peripheral circuit in a monolithic active matrix circuit having an active matrix circuit and a peripheral circuit for driving the active matrix circuit, particularly, a channel width of 200 to 800.
This relates to a driver TFT of μm. Such a driver TFT generates a large amount of heat because it controls a large current. Therefore, rapid heat dissipation by the base film of the present invention is desired.

First, the substrate (Corning 7059) 301
An aluminum nitride film 302 having a thickness of 2000 to 5000 * was deposited thereon by a reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. A favorable result was obtained when the pressure during sputtering was 1 × 10 −4 to 1 × 10 −2 Torr. The deposition rate is 20 to 200
Minutes. When forming the film, the substrate temperature is set to 100 to 50.
It may be raised to 0 ° C.

Next, as the base oxide film 303, a thickness of 100
A silicon oxide film of 0 to 2000 · was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere or a TE method
The OS may be a plasma CVD method in an oxygen atmosphere.
Thereafter, an amorphous silicon film was deposited at 1000 to 3000, preferably 1000 to 1500 by plasma CVD or LPCVD, and annealed in a nitrogen atmosphere at 600 ° C. for 48 hours. The crystalline silicon film thus obtained is patterned to form island-like silicon regions 3.
04 was formed. Then, as the gate insulating film 305,
200 to 1500 thickness, preferably 500 to 1000
-Silicon oxide was formed.

Then, an aluminum film having a thickness of 2000.about.5 .mu.m is formed by an electron beam evaporation method, patterned, and further subjected to an anodic oxidation treatment under the same conditions as in the first embodiment. And wiring 30
7 was formed. (FIG. 3A) After that, an impurity (phosphorus) was implanted in a self-aligned manner into the island-like silicon film of the TFT by ion doping (also called plasma doping) using the gate electrode portion as a mask. Phosphine (PH3
) Was used. The dose amount is 2 to 8 × 10 15 cm −2.
And (FIG. 3 (B))

Then, the underlying silicon oxide film 303 was etched. The etching was stopped by the aluminum nitride film 302 serving as a stopper. In this state, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec)
To improve the crystallinity of the portion where the crystallinity is deteriorated by the introduction of the impurity region. The energy density of the laser was 100 to 400 mJ / cm2, preferably 100 to 150 mJ / cm2. Since the silicon oxide film containing phosphorus and boron absorbs ultraviolet light,
As described above, after the through doping, a strong laser beam was required for performing the laser annealing subsequently. However, in this example, if the silicon oxide film (gate insulating film) was removed after the doping, the energy of the laser was small. For this reason, the throughput of the laser processing could be improved. Thus, N
Type impurity (phosphorus) regions 308 and 309 were formed. The sheet resistance in these regions was 200 to 800 Ω / □.
(FIG. 3 (C))

Thereafter, a plasma CVD method, a low pressure CVD method, or a normal pressure C
A silicon oxide film having a thickness of 2000 to 3000
Formed and an aluminum film (thickness 2000)
.About.5 μm), and patterning this to form TF
Wirings 311 and 312 connected to the source and drain of T were formed. The wiring 312 and the wiring 307 intersect as shown in the drawing. (FIG. 3 (C))

Finally, the substrate thus treated is
The hydrogenation was completed by annealing for 30 minutes in hydrogen at 350 ° C. at atmospheric pressure. Thus, the TFT was completed. Similarly, a P-channel TFT was manufactured by doping the impurity region with boron, and a CMOS circuit was manufactured. Typical field-effect mobilities of the N-channel type and the P-channel type are 80 to 150 cm 2 / Vs and 40 to 100 cm, respectively.
2 / Vs. The shift register manufactured with this TFT has a drain voltage of 17 V and a shift register of 11 MHz.
It was confirmed to work at z.

Further, a long time (up to 9
Even when a high voltage (> 20 V) was applied for 6 hours), deterioration of the characteristics was small. This is because heat locally generated in the TFT is quickly dissipated, and the elimination of hydrogen from the interface with the semiconductor film and the gate insulating film is suppressed. Actually, a long-time bias application state (gate voltage 11 V,
The state of heat generation at a drain voltage of 14 V) was confirmed by thermography (manufactured by Nippon Avionics, Inc.). As a result, a constant temperature increase was not observed in the TFT according to the present embodiment, and at most, the temperature rose only to about 50 ° C. . However, under the same conditions, a conventional TFT (having no aluminum nitride film as a base film) was heated to 100 ° C. or more in a short time, and the device characteristics were significantly deteriorated. Thus, the effect of the present invention was remarkably confirmed.

[Embodiment 4] This embodiment shows a method of forming a pixel portion of an active matrix type liquid crystal display.
4 and 5 show this embodiment. First, Corning 7059 was used as the substrate 401. The substrate is annealed at a temperature higher than the strain temperature before or after the formation of the base film, and then gradually cooled to a strain temperature or lower at 0.1 to 1.0 ° C./min. Substrate shrinkage in the accompanying process is small, and mask alignment is ready. For Corning 7059 substrate, 1-4 at 620-660 ° C.
After annealing for an hour, the temperature is gradually reduced at 0.03 to 1.0 ° C./min, preferably 0.1 to 0.3 ° C./min.
It is good to take out at the stage when the temperature has dropped to ° C. In this embodiment, after annealing at 630 ° C. for 4 hours, 0.2 ° C. /
Cooled in minutes.

Then, a thickness of 0.1 to 2 μm is formed on the substrate 401.
An aluminum nitride film 402 having a thickness of m, preferably 0.2 to 0.5 μm, for example 0.3 μm, was deposited by a reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. The pressure during sputtering is 1 × 10−4 to 1 ×
Preferred results were obtained at 10-2 Torr. The film forming speed was 20 to 200 / min. Further, at the time of film formation, the substrate temperature may be raised to 100 to 500 ° C. This aluminum nitride film 402 may be formed before the substrate annealing treatment. Thereafter, a very thin underlayer 403 of silicon oxide having a thickness of 0 to 1000, preferably 20 to 500, for example, 200 was formed by a sputtering method.

After the formation of the base film, an intrinsic (I-type) amorphous silicon film 404 having a thickness of 300 to 1500., for example, 1000, was formed by a plasma CVD method.
Further, the thickness is 200 to 20 by the plasma CVD method.
A mask film 405 of silicon oxide or silicon nitride of 00 ·, for example, 500 · was formed. Then, this mask film 40
Holes 406 were selectively formed in No. 5. Further, a nickel film 407 having a thickness of 5 to 200 、, for example, 20 に よ っ て was formed by a sputtering method. Instead of the nickel film, a nickel silicide film (chemical formula: NiSix, 0.4 ≦ x ≦ 2.
5, for example, x = 2.0). Copper, palladium, and the like other than nickel also have a catalytic action of crystallizing amorphous silicon, and may be used. (FIG. 4 (A))

Then, under an inert atmosphere (nitrogen or argon, atmospheric pressure) at 550 ° C. for 4 to 8 hours, for example, 8 hours
Anneal for hours to crystallize. In this step, nickel was introduced into the silicon film from the hole 406. Nickel catalytically acts on amorphous silicon to promote crystallization, so that the region 410 immediately below the hole 406 first crystallized. However, the crystallinity was random in this region. Thereafter, the crystallization spreads from the hole 406 to the periphery with the diffusion of nickel, and the crystallization progressed in the direction of the arrow in the figure, and the region 409 was crystallized. Area 4
In the case of 09, crystallization proceeds in one direction, so that good crystallinity was obtained. The region 408 is an uncrystallized region. The size of the crystallization region depended on the annealing time. Mask film 4
If 05 is thin, nickel will invade from other than the hole 406,
Since crystallization is started, for the purpose of obtaining good crystallinity,
Not preferred. Therefore, at least 500.times. Of the mask film 405 was required as in this embodiment.
(FIG. 4 (B))

After this step, the silicon film 404 was patterned by a known photolithography method to form a TFT island-shaped active layer 411. On this occasion,
At the portion to be the channel formation region, the tip of lateral crystal growth (that is, crystallized region 409 and uncrystallized region 408)
And the region 41 where nickel was directly introduced.
It is important that 0 (both have high nickel concentrations) not be present. By doing this,
Carriers moving between the source and the drain can be prevented from being affected by the nickel element in the channel formation region. In this embodiment, nickel is selectively introduced into the silicon film, and only the crystallization region 409 in the lateral direction is
Although used for the active layer of T, a silicon film crystallized by uniformly introducing nickel without using such selective introduction of nickel may be used. However, the characteristics of the TFT in this case are slightly inferior to those of the former.

4C shows a state during the etching of the silicon film 404. That is, the mask film and the photoresist 41 are formed on the island-shaped active layer 411.
There are two. In this etching step, the underlying silicon oxide film 403 was also etched. (FIG. 4C) After this step, it is necessary to remove the photoresist and further etch the mask film on the active layer 411. This is usually performed using a hydrofluoric acid-based etchant. However, in the conventional TFT process, only a silicon oxide film is used as a base film, so that when the mask film is etched, the base film is also used. There is a problem that etching is performed in the same manner (in this case, the underlying film is etched at least by a thickness of 500.times. Of the mask film). 500
The step of the thing was a major cause of disconnection of the gate electrode when the gate electrode was formed later. For this reason, it was necessary to make the mask film thin. However, if the mask film was too thin, there was an inconvenience in performing selective crystallization as described above.

However, in this embodiment, since the aluminum nitride film hardly etched by hydrofluoric acid was used as the base film, only the mask film could be selectively etched. The problem step was reduced only by adding the thickness t (= 200 ·) of the underlying silicon oxide film 403 to the thickness (1000 ·) of the silicon film, and the subsequent problem of disconnection of the gate electrode did not occur.

After the formation of the active layer,
In this case, infrared light having a peak at 0.8 to 1.4 μm was irradiated for 30 to 180 seconds to further promote crystallization of the active layer (light annealing (lamp annealing) step or RTP). Temperature is 800-1300 ° C, typically 9
The temperature was set to 00 to 1200 ° C, for example, 1100 ° C. This temperature is the temperature of the thermocouple in the single crystal silicon substrate set as a monitor at the same time, and is not the actual temperature of the substrate surface. Irradiation was performed in an H2 atmosphere to improve the condition of the surface of the active layer. In this step, since the active layer is selectively heated, heating of the glass substrate can be minimized. And, it is very effective in reducing defects and unbound bonds in the active layer. The problem at this time is that in the present embodiment, since the selective crystallization process is used, the absorption of infrared rays differs depending on the location of the silicon film. For example, the active layer 411
Among them, the phenomenon that the above-mentioned infrared ray was easily absorbed on the right side of the figure due to the large amount of the crystalline component, while the phenomenon that the infrared ray was hardly absorbed on the left side due to the large amount of the amorphous component was observed.

However, in this embodiment, since the aluminum nitride film having a good thermal conductivity is used as the base film, the heat absorbed by the silicon film by the above-mentioned irradiation with the infrared rays is transferred to a specific portion of the silicon film. Since the silicon film is immediately diffused through the base film without being accumulated, the silicon film is uniformly heated, and thermal distortion does not occur, thereby improving the uniformity of the silicon film. After that, a 1000-thick silicon oxide film 413 was formed as a gate insulating film by a plasma CVD method. TEO as source gas for CVD
S (tetraethoxysilane, Si (OC2H5)
4) The substrate temperature during film formation is 300 to 55 using oxygen and oxygen.
0 ° C., for example, 400 ° C.

The silicon oxide film 413 serving as the gate insulating film
After the film formation, optical annealing by irradiation of visible / near infrared light was performed again. By this annealing, the level mainly at the interface between the silicon oxide film 413 and the silicon active layer 411 and in the vicinity thereof could be eliminated. This is extremely useful for an insulating gate type field effect semiconductor device in which the interface characteristics between the gate insulating film and the channel formation region are extremely important.

Subsequently, by a sputtering method,
Aluminum (containing 0.01 to 0.2% of scandium) having a thickness of 3000 to 8000., for example, 5000, was formed. Then, the gate electrode and the wiring were formed by patterning the aluminum film. Further, the surface of the aluminum electrode and the wiring was anodized to form an oxide layer on the surface. This anodization is carried out when tartaric acid is 1 to 5
% In ethylene glycol solution. The thickness of the obtained oxide layer was 2000 ·. Thus, a gate electrode portion (that is, a gate electrode and an oxide layer around the gate electrode) 414 and a wiring portion 415 were formed. Alternatively, the gate electrode may be a single layer or a multilayer of a metal such as polycrystalline silicon, titanium, tungsten, or tantalum, or a silicide of such a metal. (FIG. 4 (D))

Next, an N-conductivity type is imparted in a self-aligned manner to the active layer region (constituting the source / drain and channel) by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion 414 as a mask. Impurities were added. Phosphine (P
H3) and an acceleration voltage of 60 to 90 kV, for example, 8
0 kV. The dose amount is 1 × 1015 to 8 × 1015
cm-2, for example, 2 * 1015 cm-2. As a result, N-type impurity regions 416 and 417 were formed.
In these impurity regions 416 and 417, silicide such as titanium may be formed.

Thereafter, annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used, but another laser may be used. The irradiation condition of the laser beam is such that the energy density is 200 to 400 mJ / cm2.
For example, 250 mJ / cm 2,
Irradiation was performed for 10 shots, for example, 2 shots. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation with the laser light.

This step may be performed by lamp annealing using visible / near infrared light. Visible and near-infrared light is crystallized silicon, or phosphorus or boron is 1019-1
The amorphous silicon added at 021 cm −3 is easily absorbed, and effective annealing comparable to thermal annealing at 1000 ° C. or higher can be performed. If phosphorus or boron is added, light is sufficiently absorbed even in the near infrared due to scattering of impurities. This can be fully guessed from the fact that it is black even with the naked eye. On the other hand, since it is hardly absorbed by the glass substrate, it is not necessary to heat the glass substrate to a high temperature, and the process can be performed in a short time. . In this embodiment, since the aluminum nitride film having high thermal conductivity is used as the base film, even in such an annealing process, thermal destruction in which heat is accumulated in one place does not occur. In particular, it is preferable to use an aluminum nitride film as a base film only by using a gate electrode made of thermally weak aluminum.

Thereafter, a silicon oxide film 418 having a thickness of 3000 to 8000., for example, 6000., was formed as an interlayer insulator by a plasma CVD method. As the interlayer insulator, polyimide or a two-layer film of silicon oxide and polyimide may be used. Further, an ITO film having a thickness of 800 was formed by a sputtering method, and was patterned to form a pixel electrode 419. Then, the interlayer insulator is etched with buffered hydrofluoric acid (HF / NH4F = 0.01 to 0.2, for example, 0.1) to form a contact hole 42.
2 and 423 are formed, and a metal material, for example, a multilayer film of titanium nitride and aluminum is used to form a TFT electrode / wiring 4.
20, 421 were formed. Lastly, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm to complete a semiconductor circuit having a complementary TFT. (FIG. 4E)

In this embodiment, in particular, the contact hole 42
2, 423 were formed at the ends of the active layer, and a part thereof was formed to protrude from the active layer. Even with such a shape,
In this embodiment, since the aluminum nitride film was used as the base film, the substrate was hardly overetched, and a TFT could be formed with good reproducibility. FIG. 5 (A) shows a sample manufactured according to the present invention. As shown in the top view of the TFT, the active layer 411 has a linear shape, and contact holes 422 and 423 are formed at both ends so as to protrude from the active layer. The distance between the active layer and the gate wiring 415 was set to be x1 and the distance between the active layer and the pixel electrode 419 was set to be x2. This is to prevent overlapping of lines due to misalignment. In this embodiment, since the area of the active layer is small, the area of the pixel electrode can be increased, and the area occupied by the wiring can be reduced.

FIG. 5B shows a state of the conventional TFT viewed from above, and FIG. 5C shows a cross section thereof. As is clear from FIG. The active layer is constricted and thin in the gate electrode portion, and thick in the source and drain regions. This is because the contact holes 522, 5
This is to ensure that the contact holes 23 are formed in the source 516 and the drain 517 of the active layer, and that the contact holes are formed in the active layer even if the contact holes are misaligned due to overetching.

However, in such a structure, the area of the active layer becomes large, so that the gate wiring 515 and the pixel electrode 519 are formed.
In order to prevent the overlap with the active layer, the wirings are formed apart from the active layer by x1 and x2, respectively, as is apparent from the drawing, the wiring becomes large and the area of the pixel electrode is reduced. The dotted rectangles in FIGS. 5A and 5B indicate the same area.
It can be seen that the area occupied by T and the wiring connected thereto is large, and the area of the pixel is small. Conversely, in this embodiment, the area occupied by the TFT and the wiring is small, and the area of the pixel is large. As described above, according to the present embodiment, it is possible to improve the ratio of pixels / wirings, and thereby to improve the aperture ratio of the liquid crystal display device and miniaturize the pixels. These all lead to an improvement in the quality of the liquid crystal display device.

[Embodiment 5] This embodiment shows a method of forming a pixel portion of an active matrix type liquid crystal display.
FIG. 6 shows this embodiment. First, Corning 7059 was used as the substrate 601. First, an aluminum nitride film 602 having a thickness of 0.1 to 2 μm, preferably 0.2 to 0.5 μm, for example, 0.3 μm, was deposited on the substrate 601 by the reactive sputtering method as in the fourth embodiment. After that, a very thin silicon oxide base film 603 having a thickness of 0 to 1000 、, preferably 20 to 500 、, for example, 200 に よ っ て was formed by a sputtering method. After the formation of the base film, an island-shaped crystalline silicon region 604 having a thickness of 300 to 1500 ·, for example, 800 · was formed. Furthermore, plasma CV
A silicon oxide film 605 having a thickness of 1000 · was formed as a gate insulating film by Method D. The source gas for CVD is T
EOS and oxygen were used.

Thereafter, an aluminum film (containing 1 wt% of Si or 0.1 to 0.3 wt% of Sc) having a thickness of 1000.about.3 μm, for example, 6000.about., Was formed by electron beam evaporation or sputtering. . Then, a photoresist (for example, OFPR8 manufactured by Tokyo Ohka)
00/30 cp) by spin coating.
If an aluminum oxide film having a thickness of 100 to 1000 is formed on the entire surface of the aluminum film by anodic oxidation before forming the photoresist, the adhesiveness with the photoresist is good, and By suppressing the current leakage, it was effective in forming the porous anodic oxide only on the side surfaces in the subsequent anodic oxidation step. Thereafter, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form a wiring 606 and a gate electrode 607. On these wirings and gate electrodes, the above-mentioned photoresist 60 is formed.
8, 609 are left, which function as a mask for anodizing prevention in a subsequent anodizing step. (FIG. 6
(A))

Then, the above wirings and gate electrodes are anodized by passing an electric current in an electrolytic solution to a thickness of 3000.about.25 μm.
m, for example, 0.5 μm thick anodic oxides 610, 61
No. 1 was formed on the side surface of the wiring and the gate electrode. Anodizing is
3 to 20% of an aqueous acid solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, etc.
V, for example, a constant current of 8 V was applied to the gate electrode. The anodic oxide thus formed was porous. In this embodiment, the oxalic acid solution (30
(−80 ° C.), the voltage was set to 8 V, and anodic oxidation was performed for 20 to 240 minutes. The thickness of the anodized oxide was controlled by the anodizing time and temperature. (FIG. 6 (B))

Next, the masks 608 and 609 were removed, and a current was again applied to the gate electrode and wiring in the electrolytic solution. This time, a PH · 7 ethylene glycol solution containing 3 to 10% tartaric acid, boric acid, and nitric acid was used. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. Therefore, the gate electrodes / wirings 606 and 607
Barrier-type anodic oxides 612, 61 on the top and side surfaces of
3 was formed. The thickness of the barrier-type anodic oxide was proportional to the applied voltage. In this embodiment, the voltage is 100
As a result, the thickness of the obtained barrier anodic oxide was 1200 ·. The thickness of the barrier type anodic oxide is arbitrary, but if it is too thin, there is a risk that aluminum will be eluted when the porous anodic oxide is etched later. Was.

It should be noted that although barrier-type anodic oxide can be obtained in a later step, a barrier-type anodic oxide is not formed outside the porous anodic oxide, but a porous anodic oxide is formed. A barrier-type anodic oxide is formed between the oxide and the gate electrode. (FIG. 6C) Thereafter, the silicon oxide film 605 is formed by a dry etching method.
Was etched. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by sufficiently increasing the selectivity between silicon and silicon oxide. For example, CF4 is used as an etching gas.
Is used, the anodic oxide is not etched. Therefore, the silicon oxide film 61 existing under the gate electrode and wiring is not used.
4,615 remained without being etched. Also in this etching step, since the aluminum nitride film 602 serves as a stopper, further etching does not proceed, and the step can be minimized.

Thereafter, the porous anodic oxides 612 and 613 were etched using a mixed acid of phosphoric acid, acetic acid and nitric acid. Then, the active layer 6 of the TFT is formed by ion doping.
In step 04, impurities were implanted in a self-aligned manner using the gate electrode portion (that is, the gate electrode and the surrounding anodic oxide film) and the gate insulating film 615 as a mask. In this case, various combinations of the impurity regions can be considered depending on the ion acceleration voltage and the dose. For example, when the acceleration voltage is 50 to
Set to a high 90 kV and set the dose to 1 × 1013 to 5
If it is as low as × 1014 cm −2, the regions 616 and 61
In FIG. 7, most of the impurity ions pass through the active layer and show the maximum concentration in the underlayer. Therefore, the regions 616, 61
7 is an extremely low-concentration impurity region. On the other hand, in the region 618 where the gate insulating film 615 is present, the high-speed ions are decelerated by the gate insulating film, so that the impurity concentration is maximized and a low-concentration impurity region can be formed.

On the contrary, the acceleration voltage is set as low as 5 to 30 kV, and the dose is set at 5 × 10 14 to 5 × 10 15 cm −2.
In other words, a large amount of impurity ions are implanted into the regions 616 and 617 to form a high-concentration impurity region. On the other hand, in the region 618 where the gate insulating film 615 is present, low-speed ions are blocked by the gate insulating film,
The implantation amount of impurity ions is low, so that a low-concentration impurity region can be formed. As described above, regardless of which method is used, the region 618 becomes a low-concentration impurity region, and in this embodiment, any method may be employed. In this manner, ion doping is performed to form an N-type low-concentration impurity region 618, and then a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) is irradiated to activate the impurity ions introduced into the active layer. Was done. (FIG. 6 (D))

Further, a coating of a suitable metal, for example, titanium, nickel, molybdenum, tungsten, platinum, palladium, etc., for example, a titanium film 619 having a thickness of 50 to 500.multidot.619 was formed on the entire surface by sputtering. As a result, the metal film (here, titanium film) 619 was formed in close contact with the high-concentration (or extremely low-concentration) impurity regions 616 and 617. (FIG. 6E)

Then, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) causes the metal film (here, titanium) to react with the silicon of the active layer.
Regions 620, 62 of metal silicide (here titanium silicide)
1 was formed. Laser energy density 200 ~ 4
00 mJ / cm2, preferably 250-300 mJ /
cm2 was appropriate. In addition, when the substrate was heated to 200 to 500 ° C. during laser irradiation, peeling of the titanium film could be suppressed.

Thereafter, the unreacted titanium film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at a ratio of 5: 2: 2. The titanium film other than the portion in contact with the exposed active layer (for example, the titanium film existing on the gate insulating film or the anodic oxide film) remains in a metal state as it is,
It can be removed by this etching. On the other hand, since titanium silicide 620 and 621 which is a metal silicide is not etched,
It could be left. In this embodiment, the silicide region 6
The sheet resistance of 20,621 was 10 to 50 Ω / □. On the other hand, 10 to 100 k
Ω / □.

Thereafter, an interlayer insulator 622 is formed on the entire surface.
A silicon oxide film having a thickness of 2000.about.1 .mu.
m, for example, 5000. Then, an ITO film was formed by a sputtering method, and this was patterned and etched to form a pixel electrode 623. Further, the interlayer insulator 622 was etched to form a contact hole. Also in this case, as in the first and fourth embodiments,
The pattern was such that the contact holes protruded from the sos / drain. As described above, such a pattern improves the mass productivity and reliability of the TFT.
Then, wirings / electrodes 624 and 625 were formed by a multilayer film of titanium nitride and aluminum having a thickness of 2000-1 μm, for example, 5000-. (FIG. 6 (F))

[0072]

According to the present invention, a highly reliable TFT showing sufficient reliability even when a voltage is applied for a long time can be manufactured. In addition, unprecedented degrees of freedom can be obtained in the arrangement of the active layer and the contacts, and miniaturization of the element can be realized. As described above, the present invention is an invention having a great industrial value, but the industrial impact is particularly great when a TFT is formed on a large-area substrate and used for an active matrix or a driving circuit.

Although not shown in the embodiments, the present invention may be used to form a so-called three-dimensional IC in which a semiconductor circuit is further stacked on a single crystal IC or another IC. In the embodiments, examples in which the present invention is used mainly for various LCDs have been described. However, it is needless to say that the present invention can be applied to other circuits required to be formed on an insulating substrate, such as an image sensor.

[Brief description of the drawings]

FIG. 1 shows a method for manufacturing a TFT according to the present invention. (Example 1)

FIG. 2 shows a method for manufacturing a TFT according to the present invention. (Example 2)

FIG. 3 shows a method for manufacturing a TFT according to the present invention. (Example 3)

FIG. 4 shows a method for manufacturing a TFT according to the present invention. (Example 4)

FIG. 5 shows a comparison between a TFT according to the present invention and a conventional TFT. (Example 4)

FIG. 6 shows a method for manufacturing a TFT according to the present invention. (Example 5)

[Explanation of symbols]

Reference Signs List 101 substrate 102 film containing aluminum nitride as a main component 103 film containing silicon oxide as a main component 104 island-shaped semiconductor region (silicon) 105 gate insulating film (silicon oxide) 106 gate electrode (aluminum) 107 anodic oxide (aluminum oxide) 108, 109 N-type impurity region 110 Interlayer insulator (silicon oxide) 111 Pixel electrode (ITO) 112, 113 Metal wiring (chromium or titanium nitride)

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] November 20, 2000 (200.11.
20)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Detailed description of the invention

[Correction method] Change

[Correction contents]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for improving the reliability of an insulated gate semiconductor device on a substrate and an integrated circuit in which many of them are formed. The semiconductor device according to the present invention includes a driving circuit such as an active matrix such as a liquid crystal display using a thin film transistor (TFT) or an image sensor, or an SOI integrated circuit or a conventional semiconductor integrated circuit (a microprocessor, a microcontroller, a microcomputer, or a semiconductor). Memory).

[0002]

2. Description of the Related Art In recent years, an insulating gate type semiconductor device (MI) has been formed on an insulating substrate or on a surface (insulating surface) separated from the semiconductor substrate by a thick insulating film even on a semiconductor substrate.
Research on forming SFETs has been actively conducted. In particular, a semiconductor device in which a semiconductor layer (active layer) is a thin film is called a thin film transistor (TFT). In such a semiconductor device, it is difficult to obtain an element having good crystallinity such as a single-crystal semiconductor. Usually, a non-single-crystal semiconductor which has crystallinity but is not a single crystal is used.

In such a non-single-crystal semiconductor, the defect density is large, and the defect is filled by neutralizing the defect with an element such as hydrogen or fluorine. For example, such a process is realized by hydrogenation. Was. But,
The bond between hydrogen and a semiconductor element (such as silicon) was weak, and was decomposed by thermal energy of one hundred and several tens of degrees Celsius. For this reason, when a voltage and a current are applied for a long time and the semiconductor locally generates heat, hydrogen is easily released, and the characteristics are remarkably deteriorated. In particular, in a TFT for controlling a large current, for example, in a monolithic active matrix circuit having an active matrix circuit and a peripheral circuit for driving the same, the driver TFT of the peripheral circuit has a channel width of 200 μm or more, so that a large current can be generated. Turning on / off was a major heat source.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is intended to quickly dissipate local heat generated during use of a device and to uniformly heat the entire thin film circuit device. It is an object to provide a structure of the device and a method for manufacturing such a semiconductor device.

[0005]

According to a first aspect of the present invention, there is provided a thin film semiconductor device in which a film mainly composed of aluminum nitride is formed on a substrate and a semiconductor film mainly composed of silicon is directly or indirectly formed thereon. And a wiring such as a metal or a semiconductor directly or indirectly provided thereon. The present invention also relates to a method for manufacturing a thin film semiconductor device having such a configuration.
Is a process of forming a film containing aluminum nitride as a main component on a substrate, particularly a glass substrate having poor heat conductivity and good heat insulation, and directly or indirectly forming a semiconductor film containing silicon as a main component on the glass substrate. The method is characterized by including a forming step and a step of directly or indirectly forming a wiring of metal, semiconductor, or the like thereon.

Aluminum nitride has extremely excellent thermal conductivity and is transparent (visible band gap: 6.2 eV) to visible light and near-ultraviolet light, so that it is suitable for purposes requiring transparency. Aluminum nitride is sputtered, reactive sputtered, MOCVD (metal organic chemical vapor deposition)
And a plasma CVD method. In order to obtain an aluminum nitride film by a reactive sputtering method, it is preferable to use aluminum as a target in a nitrogen atmosphere. As in the present invention, for the purpose of sufficiently releasing heat, the thickness of aluminum nitride is preferably 500 to 5 μm, typically 1000 to 5000 μm. 5
Aluminum nitride having a thickness of μm or more was easily peeled off and was not suitable for use.

Further, since the aluminum nitride film has a blocking effect on mobile ions such as sodium, it also has an effect of preventing these ions from entering the semiconductor device from the substrate. The ratio of nitrogen to aluminum in the aluminum nitride film may be a stoichiometric ratio or a non-stoichiometric ratio as long as there is no problem in heat conduction.
Typically, the ratio of nitrogen to aluminum is preferably (aluminum / nitrogen) = 0.9 to 1.4, and the thermal conductivity is 0.6 W / cmK or more (the thermal conductivity of the aluminum nitride single crystal is 2W / cmK), favorable results were obtained.

[0008] The stress of the coating may be optimized by changing the ratio of nitrogen to aluminum. Further, by adding a small amount of boron, silicon, carbon, oxygen, etc. in an amount of 0.01 to 20 atomic% in addition to nitrogen and aluminum, it is possible to match, optimize, and minimize stress distortion with a substrate. is there. The coating containing aluminum nitride as a main component may be crystalline or amorphous.

For the purpose of improving the thermal conductivity, it is usually considered to use a diamond-based material (for example, a polycrystalline diamond thin film, a hard carbon film, a diamond-like carbon film, etc.). In such a minute region, a diamond-based material generally has poor adhesion to a silicon oxide-based material, so that a sufficient effect cannot be obtained. In addition, a silicon nitride film often used as a blocking layer and a passivation layer in an ordinary semiconductor process has a low thermal conductivity and is not suitable for implementing the present invention. Table 1 below
Next, the characteristics of the main thin film materials were compared. (O is excellent, Δ is medium, and X is inferior.)

[0010]

[Table 1]

In the present invention, heat generated from a metal or semiconductor wiring (gate wiring or the like) is transmitted to an underlying semiconductor film (active layer or the like), and also a current flows through the semiconductor film. Heat is generated, and the temperature of the semiconductor film rises. However, without staying there, the temperature is quickly transmitted to the aluminum nitride film thereunder. Hydrogen desorption is reduced. In particular, local deterioration due to local heat generation due to generation of hot carriers due to application of a high reverse bias voltage between the drain and channel of the TFT can be suppressed by soaking.

In the present invention, depositing a semiconductor film directly on an aluminum nitride film is advantageous in that although the adhesion is good, a semiconductor carrier is trapped in the aluminum nitride and a parasitic channel formed by the trapped carrier (capture center). Are apt to occur and, as a result, adversely affect the electrical characteristics of the semiconductor film, which is not preferable. There is no problem if such trapping centers can be removed, but if they cannot be removed easily, a material that is electrically and chemically preferable to a semiconductor film such as a silicon oxide film (a silicon oxide film is an aluminum nitride film) (The density of the trapping centers is only one-tenth of the density of the trapping centers). Further, in the silicon oxide film, an effect of stress relaxation can be expected.

A silicon nitride film is formed on aluminum nitride in a thickness of 100 to 1000 °, for example, 200 °, and a silicon oxide film is formed thereon in a thickness of 100 to 2000 °, for example, 200 °.
Å You may have formed. In the present invention, as a material of the gate electrode, a simple substance such as silicon (including a substance whose conductivity is increased by doping impurities), aluminum, tantalum, chromium, tungsten, molybdenum, or an alloy thereof, or a multilayer thereof is used. A film may be used.
Further, as shown in the embodiment, the surface may be oxidized.

Further, aluminum nitride is not etched by a fluorine-based etchant, and is not etched by a method of etching a material used in a normal semiconductor process such as silicon oxide, silicon, or aluminum. It may be used as a stopper. That is, as the contact of the source and the drain of the TFT, not only the upper surface but also the side surface of the source and the drain can be used as the contact. For example, even when the contact hole is formed to extend from the source and the drain, the substrate is not etched by the aluminum nitride serving as an etching stopper.

As a result, the source and drain regions can be formed smaller than before, which is advantageous for circuit integration. On the other hand, this also means that the contact hole can be enlarged, and a more reliable contact can be obtained, which is advantageous for mass productivity and reliability.

[0016]

[Embodiment 1] FIG. 1 shows an example of manufacturing a TFT according to the present invention. First, a substrate (Corning 705)
9 glass substrate, size 300mm x 300mm or 100mm x 100mm) 101, thickness 2000
An aluminum nitride film 102 of ５5000 ° was deposited by a reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. The pressure during sputtering is 1 ×
Preferred results were obtained at 10 ^-4 to 1 × 10 ^-2 Torr. The deposition rate was 20-200 ° / min. Further, at the time of film formation, the substrate temperature may be raised to 100 to 500 ° C.

The aluminum nitride film 102 was formed on both sides of the substrate. This is because foreign elements such as sodium contained in the substrate or adhered to the surface after shipping are TFT
With the meaning of containing so as not to deteriorate the characteristics of
This has the effect of strengthening the substrate and making the surface less likely to be scratched.
In particular, when a TFT is used in an active matrix type liquid crystal display device, the surface on which the TFT is not provided comes into contact with the external environment, but this surface is apt to be finely scratched. And darken the screen.

Next, the glass substrate on which the aluminum nitride is formed is heated at 600 to 680 ° C., for example, 640 ° C. for 4 to 1 hour.
Annealing was performed for 2 hours in an atmosphere of nitrogen, ammonia (NH ₃ ), or nitrous oxide (N ₂ O). And
It was gradually cooled at a rate of 0.01 to 0.5 ° C / min, for example, 0.2 ° C / min, and was taken out when the temperature was lowered to 350 to 450 ° C. By this step, the substrate that was colored yellow immediately after the reactive sputtering became transparent, and the electrical insulation was improved. Further, in this annealing step, thermal shrinkage of the glass substrate occurred, and the stress was relaxed. As a result, irreversible shrinkage was reduced. For this reason, in the subsequent heat treatment step, shrinkage of the substrate was eliminated, and mask displacement was significantly reduced.

After the above-mentioned annealing, a silicon oxide film having a thickness of 2000 to 500.degree. As a method of forming this oxide film,
Sputtering in an oxygen atmosphere and TEOS were decomposed and deposited by plasma CVD in an oxygen atmosphere. Further, the film thus formed may be annealed at 450 to 650 ° C.

Thereafter, as shown in FIG.
An amorphous silicon film is formed at a temperature of 100 to 1500 °, preferably 300 to 800 ° by a VD method or an LPCVD method.
ÅThen, the island-like silicon region 104 was formed by patterning. And a thickness of 200 to 1500 mm,
Preferably, silicon oxide 105 of 500 to 1000 ° is formed. This silicon oxide film also functions as a gate insulating film. Therefore, sufficient care is required for its production. Here, TEOS is used as a raw material, and a substrate temperature of 1 with oxygen.
RF at 50-600 ° C., preferably 300-450 ° C.
Decomposed and deposited by plasma CVD. The pressure ratio between TEOS and oxygen is 1: 1 to 1: 3, and the pressure is 0.05 to 0.
The RF power was set to 100 to 250 W at 5 torr. Alternatively, decompression C using TEOS as a raw material together with ozone gas
The substrate temperature is set to 35 by the VD method or the normal pressure CVD method.
It formed as 0-600 degreeC, Preferably it was 400-550 degreeC. After film formation, 400 ~ in oxygen or ozone atmosphere
Annealed at 600 ° C. for 30 to 60 minutes.

Then, as shown in FIG. 1A, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
ec) was irradiated to crystallize the silicon region 104. Laser energy density is 200-400mJ /
cm ² , preferably 250 to 300 mJ / cm ² ,
During the laser irradiation, the substrate was heated to 300 to 500 ° C. The silicon film 104 thus formed
When the crystallinity of was investigated by Raman scattering spectroscopy, it was different from the single crystal silicon peak (521 cm ^-1 ).
A relatively broad peak was observed at around 515 cm ^-1 . Thereafter, annealing was performed at 350 ° C. for 2 hours in hydrogen.

Thereafter, an aluminum film having a thickness of 2000 to 1 μm was formed by an electron beam evaporation method, and this was patterned to form a gate electrode 106. Aluminum may be doped with scandium (Sc) by 0.15 to 0.2% by weight. Next, the substrate is adjusted to pH ≒.
7, immersed in an ethylene glycol solution of 1 to 3% tartaric acid, and anodized using platinum as a cathode and the aluminum gate electrode as an anode. The anodization was completed by first increasing the voltage to 220 V with a constant current and maintaining the state for one hour. In the present embodiment, in the constant current state, the voltage rising speed is suitably 2 to 5 V / min. Thus, anodic oxide 107 having a thickness of 1500-3500 °, for example, 2000 ° was formed. (FIG. 1 (B))

Thereafter, an impurity (phosphorus) was implanted into the island-like silicon film of each TFT in a self-aligned manner by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion as a mask. Phosphine (PH ₃ ) was used as a doping gas. Dose amount is 1-4 × 10
^{It was 15} cm ^-2 .

Further, as shown in FIG. 1C, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
ec) was applied to improve the crystallinity of the portion where the crystallinity was deteriorated by the introduction of the impurity region. The energy density of the laser was 150 to 400 mJ / cm ² , preferably 200 to 250 mJ / cm ² . Thus, N
Type impurity (phosphorus) regions 108 and 109 were formed. The sheet resistance in these regions was 200 to 800 Ω / □.
In this step, a so-called RTP (rapid thermal process) is used in which a flash lamp is used instead of a laser to quickly raise the temperature to 1000 to 1200 ° C. (temperature of a silicon monitor) and heat the sample.
May be used.

Then, an interlayer insulator 110 is formed on the entire surface.
Plasma CVD of TEOS as raw material and oxygen
Method, reduced pressure CVD method with ozone, or normal pressure CV
A silicon oxide film having a thickness of 3000 .ANG. Was formed by Method D. The substrate temperature was 250 to 450 ° C, for example, 350 ° C.
After the film formation, the silicon oxide film was mechanically polished to obtain a flat surface. Further, an ITO film was deposited by a sputtering method, and this was patterned to obtain a pixel electrode 111. (Fig. 1 (D))

Then, the interlayer insulator 110 is etched to form contact holes in the source / drain of the TFT as shown in FIG. 1E, and wires 112 and 113 of chromium or titanium nitride are formed. Was connected to the pixel electrode 111. In this case, FIG. 1 (F)
As shown in (1), the contact hole may be formed by protruding the source / drain region (island-like silicon). In this case, the area of the contact holes protruding from the island-shaped silicon was 30 to 70%. In this case, the contact is formed not only on the upper surface of the source / drain but also on the side surface. Hereinafter, such a contact is referred to as a top side contact. In the conventional structure, if an attempt is made to form a top side contact, the silicon oxide film underlying the portion other than the island-shaped silicon and further the substrate are etched by the step of etching the interlayer insulator, but in this embodiment, The aluminum nitride film 102 serves as an etching stopper, and the etching stops here.

In the normal case, the size of the contact hole needs to be smaller than that of the source / drain. However, in the case of the top side contact, the size of the island can be made smaller than that of the contact hole. As a result, the island can be miniaturized. On the contrary, since the contact hole can be enlarged, mass productivity and reliability can be improved. Finally, 300 ~
Annealing was performed at 400 ° C. for 0.1 to 2 hours to complete hydrogenation of silicon. Thus, the TFT was completed.
A large number of TFTs manufactured at the same time were arranged in a matrix to form an active matrix type liquid crystal display device.

Embodiment 2 FIG. 2 shows an example of manufacturing a TFT according to the present invention. First, a substrate (NA35 glass manufactured by NH Techno Glass Co., Ltd.) 201 having a thickness of 1000
An aluminum nitride film 202 of 5 μm was deposited by a reactive sputtering method. Targeting aluminum,
Sputtering was performed in an atmosphere of nitrogen and argon. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. The pressure during sputtering is 1 × 10
Preferred results were obtained at ^-4 to 1 × 10 ^-2 Torr. The deposition rate was 20-200 ° / min. Further, at the time of film formation, the substrate temperature may be raised to 100 to 500 ° C.

Next, as the base oxide film 203, a thickness of 100
A silicon oxide film having a thickness of about 1000 °, for example, 500 ° was formed. As a method of forming the oxide film, a sputtering method in an oxygen atmosphere or TEOS was decomposed and deposited by a plasma CVD method in an oxygen atmosphere. Thereafter, this film is 550-700
Nitrous oxide (N ₂ O) at 650 ° C. for 4 hours.
In a nitrogen atmosphere containing 20%. As a result, the aluminum nitride film became transparent, and the silicon oxide film thereon could be densified.

Thereafter, an amorphous silicon film is formed by plasma CVD or LPCVD to a thickness of 200 to 150 nm.
0 °, preferably 300-800 °, and annealed in a nitrogen atmosphere at 600 ° C. for 48 hours. The crystalline silicon film thus obtained was patterned to form an island-shaped silicon region 204. Then, as the gate insulating film 207, a thickness of 200 to 1500 °, preferably 500 to 1
000 ° of silicon oxide was formed.

Then, a phosphorus-added silicon film having a thickness of 2000 to 5 μm is formed by a low pressure CVD method.
This was patterned to form a gate electrode 209 and a wiring 208. Thereafter, an impurity (phosphorus) was implanted in a self-aligned manner into the island-like silicon film of the TFT by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion as a mask. Phosphine (PH ₃ ) was used as a doping gas. Dose amount is 1-8 ×
It was 10 ¹⁵ cm ^-2 .

Further, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated to improve the crystallinity of the portion where the crystallinity was deteriorated by introducing the impurity region. Laser energy density is 150
４００400 mJ / cm ² , preferably 200 to 250 mJ
/ Cm ² . Thus, the N-type impurity (phosphorus) region 2
05 and 206 were formed. The sheet resistance in these regions was 200 to 800 Ω / □. (Fig. 2 (A))

Thereafter, a plasma CVD method, a low pressure CVD method, or a normal pressure C
A silicon oxide film having a thickness of 3000 .ANG. Was formed by the VD method.
Further, a photoresist 211 was selectively formed. Such a photoresist is preferably formed at a portion where the wiring intersects or a portion where the wiring is provided with a contact. (FIG. 2 (B)) And as shown in FIG. 2 (C),
Using the photoresist 211 as a mask, the interlayer insulator 21 is used.
0, gate insulator 207, and underlying silicon oxide film 203
Was etched. The underlying silicon oxide film was etched, but the substrate was not etched with the aluminum nitride film as a stopper. For this reason, a flat surface was obtained. (Fig. 2 (C))

Then, a titanium film (having a thickness of 2
000Å-5 μm), and patterning the same to form a wiring 212 connected to the source and drain of the TFT.
213 were formed. Further, ITO was selectively formed to form a pixel electrode 214. Finally, the substrate thus treated was annealed in hydrogen at 1 atm and 350 ° C. for 30 minutes to complete the hydrogenation. Thus, the TFT was completed. A large number of TFTs manufactured at the same time were arranged in a matrix to form an active matrix type liquid crystal display device.

Embodiment 3 FIG. 3 shows an example of manufacturing a TFT according to the present invention. The TFT of this embodiment is a TFT of a peripheral circuit in a monolithic active matrix circuit having an active matrix circuit and a peripheral circuit for driving the active matrix circuit, particularly, a channel width of 200 to 800.
This relates to a driver TFT of μm. Such a driver TFT generates a large amount of heat because it controls a large current. Therefore, rapid heat dissipation by the base film of the present invention is desired.

First, the substrate (Corning 7059) 301
An aluminum nitride film 302 having a thickness of 2000 to 5000 ° was deposited thereon by a reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. A favorable result was obtained when the pressure during sputtering was 1 × 10 ⁻⁴ to 1 × 10 ⁻² Torr. The deposition rate was 20-200 ° / min. During the film formation, the substrate temperature is set to 100 to 500 ° C.
May be raised.

Next, as the base oxide film 303, a thickness of 100
A silicon oxide film of 0 to 2000 ° was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere or a TE method
The OS may be a plasma CVD method in an oxygen atmosphere.
Thereafter, an amorphous silicon film was deposited at 1000 to 3000 °, preferably 1000 to 1500 ° by plasma CVD or LPCVD, and annealed in a nitrogen atmosphere at 600 ° C. for 48 hours. The crystalline silicon film thus obtained is patterned to form island-like silicon regions 3.
04 was formed. Then, as the gate insulating film 305,
200 to 1500 mm thick, preferably 500 to 1000
珪 素 of silicon oxide was formed.

Then, an aluminum film having a thickness of 2000 to 5 μm is formed by an electron beam evaporation method, is patterned, and is further subjected to an anodic oxidation treatment under the same conditions as in the first embodiment. Wiring 30
7 was formed. (FIG. 3A) Thereafter, the TF is formed by ion doping (also called plasma doping).
Impurities (phosphorus) were implanted into the T island-like silicon film in a self-aligned manner using the gate electrode portion as a mask. Phosphine (PH ₃ ) was used as a doping gas. The dose amount was 2 to 8 × 1015 cm ⁻² . (FIG. 3 (B))

Then, the underlying silicon oxide film 303 was etched. The etching was stopped by the aluminum nitride film 302 serving as a stopper. In this state, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec)
To improve the crystallinity of the portion where the crystallinity is deteriorated by the introduction of the impurity region. The energy density of the laser is 100 to 400 mJ / cm ² , preferably 1
It was 00 to 150 mJ / cm ² . Since the silicon oxide film containing phosphorus or boron absorbs ultraviolet light, a strong laser beam was necessary for performing subsequent laser annealing after through doping as in Example 1.
However, in this example, if the silicon oxide film (gate insulating film) was removed after the doping, the energy of the laser was small. For this reason, the throughput of the laser processing could be improved. Thus, N-type impurity (phosphorus) regions 308 and 309 were formed. The sheet resistance in these regions was 200 to 800 Ω / □. (FIG. 3 (C))

Thereafter, a plasma CVD method, a low pressure CVD method, or a normal pressure C
The silicon oxide film is formed to a thickness of 2000 to 3000 に よ っ て by the VD method.
Formed and an aluminum film (thickness 2000)
Å-5 μm), and patterning this to form TF
Wirings 311 and 312 connected to the source and drain of T were formed. The wiring 312 and the wiring 307 intersect as shown in the drawing. (FIG. 3 (C))

Finally, the substrate thus treated is
The hydrogenation was completed by annealing for 30 minutes in hydrogen at 350 ° C. at atmospheric pressure. Thus, the TFT was completed. Similarly, a P-channel TFT was manufactured by doping the impurity region with boron, and a CMOS circuit was manufactured. N-channel type, a typical field-effect mobility of P-channel type, respectively, 80~150cm ² / Vs, 40~100cm ²
/ Vs. In addition, it was confirmed that the shift register manufactured with this TFT operates at 11 MHz at a drain voltage of 17 V.

Further, a long time (up to 9
Even when a high voltage (> 20 V) was applied for 6 hours), deterioration of the characteristics was small. This is because heat locally generated in the TFT is quickly dissipated, and the elimination of hydrogen from the interface with the semiconductor film and the gate insulating film is suppressed. Actually, a long-time bias application state (gate voltage 11 V,
The state of heat generation at a drain voltage of 14 V) was confirmed by thermography (manufactured by Nippon Avionics, Inc.). As a result, a constant temperature increase was not observed in the TFT according to the present embodiment, and at most, the temperature rose only to about 50 ° C. . However, under the same conditions, a conventional TFT (having no aluminum nitride film as a base film) was heated to 100 ° C. or more in a short time, and the device characteristics were significantly deteriorated. Thus, the effect of the present invention was remarkably confirmed.

[Embodiment 4] This embodiment shows a method of forming a pixel portion of an active matrix type liquid crystal display.
4 and 5 show this embodiment. First, Corning 7059 was used as the substrate 401. The substrate is annealed at a temperature higher than the strain temperature before or after the formation of the base film, and then gradually cooled to a strain temperature or lower at 0.1 to 1.0 ° C./min. Substrate shrinkage in the accompanying process is small, and mask alignment is ready. For Corning 7059 substrate, 1-4 at 620-660 ° C.
After annealing for an hour, the temperature is gradually reduced at 0.03 to 1.0 ° C./min, preferably 0.1 to 0.3 ° C./min.
It is good to take out at the stage when the temperature has dropped to ° C. In this embodiment, after annealing at 630 ° C. for 4 hours, 0.2 ° C. /
Cooled in minutes.

Then, a thickness of 0.1 to 2 μm is formed on the substrate 401.
An aluminum nitride film 402 having a thickness of m, preferably 0.2 to 0.5 μm, for example 0.3 μm, was deposited by a reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. The pressure during sputtering is 1 × 10 ^-4 to 1 × 1
Good results were obtained at 0 ^-2 Torr. The deposition rate is 2
It was 0-200Å / min. Further, at the time of film formation, the substrate temperature may be raised to 100 to 500 ° C. This aluminum nitride film 402 may be formed before the substrate annealing treatment. Thereafter, a very thin silicon oxide base film 403 having a thickness of 0 to 1000 °, preferably 20 to 500 °, for example, 200 ° was formed by a sputtering method.

After forming the base film, an intrinsic (I-type) amorphous silicon film 404 having a thickness of 300 to 1500 °, for example, 1000 ° was formed by a plasma CVD method.
Further, the thickness is 200 to 20 by the plasma CVD method.
A mask film 405 of 00Å, for example, 500Å silicon oxide or silicon nitride was formed. Then, this mask film 40
Holes 406 were selectively formed in No. 5. Further, a nickel film 407 having a thickness of 5 to 200 °, for example, 20 ° was formed by a sputtering method. Instead of the nickel film, a nickel silicide film (chemical formula: NiSix, 0.4 ≦ x ≦ 2.
5, for example, x = 2.0). Copper, palladium, and the like other than nickel also have a catalytic action of crystallizing amorphous silicon, and may be used. (FIG. 4 (A))

Then, under an inert atmosphere (nitrogen or argon, atmospheric pressure) at 550 ° C. for 4 to 8 hours, for example, 8 hours
Anneal for hours to crystallize. In this step, nickel was introduced into the silicon film from the hole 406. Nickel catalytically acts on amorphous silicon to promote crystallization, so that the region 410 immediately below the hole 406 first crystallized. However, the crystallinity was random in this region. Thereafter, the crystallization spreads from the hole 406 to the periphery with the diffusion of nickel, and the crystallization progressed in the direction of the arrow in the figure, and the region 409 was crystallized. Area 4
In the case of 09, crystallization proceeds in one direction, so that good crystallinity was obtained. The region 408 is an uncrystallized region. The size of the crystallization region depended on the annealing time. Mask film 4
If 05 is thin, nickel will invade from other than the hole 406,
Since crystallization is started, for the purpose of obtaining good crystallinity,
Not preferred. Therefore, the mask film 405 needs at least 500 ° as in this embodiment.
(FIG. 4 (B))

After this step, the silicon film 404 was patterned by a known photolithography method to form a TFT island-shaped active layer 411. On this occasion,
At the portion to be the channel formation region, the tip of lateral crystal growth (that is, crystallized region 409 and uncrystallized region 408)
And the region 41 where nickel was directly introduced.
It is important that 0 (both have high nickel concentrations) not be present. By doing this,
Carriers moving between the source and the drain can be prevented from being affected by the nickel element in the channel formation region. In this embodiment, nickel is selectively introduced into the silicon film, and only the crystallization region 409 in the lateral direction is
Although used for the active layer of T, a silicon film crystallized by uniformly introducing nickel without using such selective introduction of nickel may be used. However, the characteristics of the TFT in this case are slightly inferior to those of the former.

4C shows a state during the etching of the silicon film 404. That is, the mask film and the photoresist 41 are formed on the island-shaped active layer 411.
There are two. In this etching step, the underlying silicon oxide film 403 was also etched. (FIG. 4C) After this step, it is necessary to remove the photoresist and further etch the mask film on the active layer 411. This is usually performed using a hydrofluoric acid-based etchant. However, in the conventional TFT process, only a silicon oxide film is used as a base film, so that when the mask film is etched, the base film is also used. There is a problem that etching is performed in the same manner (in this case, the underlying film is etched at least by a thickness of 500 ° of the mask film). 500
The Å step was a major cause of disconnection of the gate electrode when the gate electrode was formed later. For this reason, it was necessary to make the mask film thin. However, if the mask film was too thin, there was an inconvenience in performing selective crystallization as described above.

However, in this embodiment, since the aluminum nitride film hardly etched by hydrofluoric acid was used as the base film, only the mask film could be selectively etched. The problem step was reduced only by adding the thickness t (= 200 °) of the underlying silicon oxide film 403 to the thickness (1000 °) of the silicon film, and the subsequent problem of disconnection of the gate electrode did not occur.

After the formation of the active layer,
In this case, infrared light having a peak at 0.8 to 1.4 μm was irradiated for 30 to 180 seconds to further promote crystallization of the active layer (light annealing (lamp annealing) step or RTP). Temperature is 800-1300 ° C, typically 9
The temperature was set to 00 to 1200 ° C, for example, 1100 ° C. This temperature is the temperature of the thermocouple in the single crystal silicon substrate set as a monitor at the same time, and is not the actual temperature of the substrate surface. Irradiation was performed in an H2 atmosphere to improve the condition of the surface of the active layer. In this step, since the active layer is selectively heated, heating of the glass substrate can be minimized. And, it is very effective in reducing defects and unbound bonds in the active layer. The problem at this time is that in the present embodiment, since the selective crystallization process is used, the absorption of infrared rays differs depending on the location of the silicon film. For example, the active layer 411
Among them, the phenomenon that the above-mentioned infrared ray was easily absorbed on the right side of the figure due to the large amount of the crystalline component, while the phenomenon that the infrared ray was hardly absorbed on the left side due to the large amount of the amorphous component was observed.

However, in this embodiment, since the aluminum nitride film having a good thermal conductivity is used as the base film, the heat absorbed by the silicon film by the above-mentioned irradiation with the infrared rays is transferred to a specific portion of the silicon film. Since the silicon film is immediately diffused through the base film without being accumulated, the silicon film is uniformly heated, and thermal distortion does not occur, thereby improving the uniformity of the silicon film. Thereafter, a silicon oxide film 413 having a thickness of 1000 ° was formed as a gate insulating film by a plasma CVD method. TEO as source gas for CVD
S (tetraethoxysilane, Si (OC ₂ H ₅ )
₄ ) Using oxygen and the substrate temperature during film formation is 300 to 550
° C, for example, 400 ° C.

The silicon oxide film 413 serving as the gate insulating film
After the film formation, optical annealing by irradiation of visible / near infrared light was performed again. By this annealing, the level mainly at the interface between the silicon oxide film 413 and the silicon active layer 411 and in the vicinity thereof could be eliminated. This is extremely useful for an insulating gate type field effect semiconductor device in which the interface characteristics between the gate insulating film and the channel formation region are extremely important.

Subsequently, by a sputtering method,
Aluminum (including 0.01 to 0.2% scandium) having a thickness of 3000 to 8000 °, for example, 5000 ° was formed. Then, the gate electrode and the wiring were formed by patterning the aluminum film. Further, the surface of the aluminum electrode and the wiring was anodized to form an oxide layer on the surface. This anodization is carried out when tartaric acid is 1 to 5
% In ethylene glycol solution. The thickness of the obtained oxide layer was 2000 °. Thus, a gate electrode portion (that is, a gate electrode and an oxide layer around the gate electrode) 414 and a wiring portion 415 were formed. Alternatively, the gate electrode may be a single layer or a multilayer of a metal such as polycrystalline silicon, titanium, tungsten, or tantalum, or a silicide of such a metal. (FIG. 4 (D))

Next, an N-conductivity type is imparted in a self-aligned manner to the active layer region (constituting the source / drain and channel) by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion 414 as a mask. Impurities were added. Phosphine (P
H ₃ ) and an acceleration voltage of 60 to 90 kV, for example, 80
kV. Dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ c
m ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result, N
Mold impurity regions 416 and 417 were formed. In these impurity regions 416 and 417, silicide such as titanium may be formed.

Thereafter, annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used, but another laser may be used. The irradiation condition of the laser beam is such that the energy density is 200 to 400 mJ / cm ² ,
For example, 250 mJ / cm ^2, and ² to 10
A shot, for example, two shots was irradiated. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation with the laser light.

This step may be performed by lamp annealing using visible / near infrared light. Visible and near-infrared light is crystallized silicon or phosphorus or boron in 10 ¹⁹ to 10
It is easily absorbed by amorphous silicon to which ²¹ cm ^{-3 is} added.
Effective annealing comparable to thermal annealing of 000 ° C. or more can be performed. If phosphorus or boron is added, light is sufficiently absorbed even in the near infrared due to scattering of impurities. This can be fully guessed from the fact that it is black even with the naked eye. On the other hand, since it is hardly absorbed by the glass substrate, it is not necessary to heat the glass substrate to a high temperature, and the process can be performed in a short time. . In this embodiment, since the aluminum nitride film having high thermal conductivity is used as the base film, even in such an annealing process, thermal destruction in which heat is accumulated in one place does not occur. In particular, it is preferable to use an aluminum nitride film as a base film only by using a gate electrode made of thermally weak aluminum.

Thereafter, a silicon oxide film 418 having a thickness of 3000 to 8000 Å, for example, 6000 Å was formed as an interlayer insulator by a plasma CVD method. As the interlayer insulator, polyimide or a two-layer film of silicon oxide and polyimide may be used. Further, an ITO film having a thickness of 800 ° was formed by a sputtering method, and was patterned to form a pixel electrode 419. Then, the interlayer insulator is etched with buffered hydrofluoric acid (HF / NH ₄ F = 0.01 to 0.2, for example, 0.1) to form a contact hole 42.
2 and 423 are formed, and a metal material, for example, a multilayer film of titanium nitride and aluminum is used to form a TFT electrode / wiring 4.
20, 421 were formed. Lastly, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm to complete a semiconductor circuit having a complementary TFT. (FIG. 4E)

In this embodiment, in particular, the contact hole 42
2, 423 were formed at the ends of the active layer, and a part thereof was formed to protrude from the active layer. Even with such a shape,
In this embodiment, since the aluminum nitride film was used as the base film, the substrate was hardly overetched, and a TFT could be formed with good reproducibility. FIG. 5 (A) shows a sample manufactured according to the present invention. As shown in the top view of the TFT, the active layer 411 has a linear shape, and contact holes 422 and 423 are formed at both ends so as to protrude from the active layer. Spacing of the active layer and the gate wiring 415 at a distance of x _1, also the distance between the active layer and the pixel electrode 419 is arranged to keep the x _2. This is to prevent overlapping of lines due to misalignment. In this embodiment, since the area of the active layer is small, the area of the pixel electrode can be increased, and the area occupied by the wiring can be reduced.

FIG. 5B shows a state of the conventional TFT viewed from above, and FIG. 5C shows a cross section thereof. As is clear from FIG. The active layer is constricted and thin in the gate electrode portion, and thick in the source and drain regions. This is because the contact holes 522, 5
This is to ensure that the contact holes 23 are formed in the source 516 and the drain 517 of the active layer, and that the contact holes are formed in the active layer even if the contact holes are misaligned due to overetching.

However, in such a structure, the area of the active layer becomes large, so that the gate wiring 515 and the pixel electrode 519 are formed.
In order to prevent overlap with the active layer, if the layers are formed apart from the active layer by x ₁ and x ₂ , respectively, the wiring becomes large and the area of the pixel electrode is reduced, as is apparent from the drawing. The dotted rectangles in FIGS. 5A and 5B indicate the same area.
It can be seen that the area occupied by T and the wiring connected thereto is large, and the area of the pixel is small. Conversely, in this embodiment, the area occupied by the TFT and the wiring is small, and the area of the pixel is large. As described above, according to the present embodiment, it is possible to improve the ratio of pixels / wirings, and thereby to improve the aperture ratio of the liquid crystal display device and miniaturize the pixels. These all lead to an improvement in the quality of the liquid crystal display device.

[Embodiment 5] This embodiment shows a method of forming a pixel portion of an active matrix type liquid crystal display.
FIG. 6 shows this embodiment. First, Corning 7059 was used as the substrate 601. First, an aluminum nitride film 602 having a thickness of 0.1 to 2 μm, preferably 0.2 to 0.5 μm, for example, 0.3 μm, was deposited on the substrate 601 by the reactive sputtering method as in the fourth embodiment. After that, a very thin silicon oxide base film 603 having a thickness of 0 to 1000 °, preferably 20 to 500 °, for example, 200 ° was formed by a sputtering method. After forming the base film, an island-shaped crystalline silicon region 604 having a thickness of 300 to 1500 °, for example, 800 ° was formed. Furthermore, plasma CV
A silicon oxide film 605 having a thickness of 1000 ° was formed as a gate insulating film by Method D. The source gas for CVD is T
EOS and oxygen were used.

Thereafter, an aluminum film (containing 1 wt% of Si or 0.1 to 0.3 wt% of Sc) having a thickness of 1000 to 3 μm, for example, 6000 °, was formed by electron beam evaporation or sputtering. Then, a photoresist (for example, OFPR8 manufactured by Tokyo Ohka)
00/30 cp) by spin coating.
If an aluminum oxide film having a thickness of 100 to 1000 ° is formed on the entire surface of the aluminum film by anodic oxidation before forming the photoresist, adhesion to the photoresist is good, and By suppressing the current leakage, it was effective in forming the porous anodic oxide only on the side surfaces in the subsequent anodic oxidation step. Thereafter, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form a wiring 606 and a gate electrode 607. On these wirings and gate electrodes, the above-mentioned photoresist 60 is formed.
8, 609 are left, which function as a mask for anodizing prevention in a subsequent anodizing step. (FIG. 6
(A))

Then, the above wirings and gate electrodes are anodized by passing an electric current in an electrolytic solution to a thickness of 3000 to 25 μm.
m, for example, 0.5 μm thick anodic oxides 610, 61
No. 1 was formed on the side surface of the wiring and the gate electrode. Anodizing is
3 to 20% of an aqueous acid solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, etc.
V, for example, a constant current of 8 V was applied to the gate electrode. The anodic oxide thus formed was porous. In this embodiment, the oxalic acid solution (30
(−80 ° C.), the voltage was set to 8 V, and anodic oxidation was performed for 20 to 240 minutes. The thickness of the anodized oxide was controlled by the anodizing time and temperature. (FIG. 6 (B))

Next, the masks 608 and 609 were removed, and a current was again applied to the gate electrode and wiring in the electrolytic solution. In this case, an ethylene glycol solution having a pH of 7 containing 3 to 10% tartaric acid, boric acid, and nitric acid was used. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. Therefore, the gate electrodes / wirings 606 and 607
Barrier-type anodic oxides 612, 61 on the top and side surfaces of
3 was formed. The thickness of the barrier type anodic oxide was proportional to the applied voltage. For example, an applied voltage of 100 V formed an anodic oxide of 1200 °. In this embodiment, the voltage is 100
V, the thickness of the resulting barrier anodic oxide was 1200 °. The thickness of the barrier type anodic oxide is arbitrary, but if it is too thin, there is a risk that aluminum will be eluted when the porous anodic oxide is etched later, so that 500 mm or more was preferred. .

It should be noted that although barrier-type anodic oxide can be obtained in a later step, a barrier-type anodic oxide is not formed outside the porous anodic oxide, but a porous anodic oxide is formed. A barrier-type anodic oxide is formed between the oxide and the gate electrode. (FIG. 6C) Thereafter, the silicon oxide film 605 was etched by a dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by sufficiently increasing the selectivity between silicon and silicon oxide. For example, when CF ₄ is used as an etching gas, the anodic oxide is not etched, and therefore, the silicon oxide films 614 and 615 existing under the gate electrode and the wiring remain without being etched. Also in this etching step, since the aluminum nitride film 602 serves as a stopper, further etching does not proceed, and the step can be minimized.

Then, using a mixed acid of phosphoric acid, acetic acid and nitric acid,
The porous anodic oxides 612, 613 were etched. So
Then, the active layer 6 of the TFT is formed by the ion doping method.
04 shows the gate electrode portion (that is, the gate electrode and its surroundings).
Anodic oxide film) and gate insulating film 615 as masks
The impurities were implanted in a self-aligned manner. In this case, ion
Varies depending on the acceleration voltage and dose
Combinations are conceivable. For example, if the acceleration voltage is
90 kV and set the dose to 1 × 10 ¹³~ 5x
10¹⁴cm^-2If you make it lower, the areas 616 and 617
Indicates that most impurity ions pass through the active layer
Indicates the maximum concentration. Therefore, the areas 616 and 617
An extremely low concentration impurity region is obtained. On the other hand, there is no gate above
In the region 618 where the edge film 615 exists, the gate insulating film
Therefore, high-speed ions are slowed down, and
Degree and the formation of low-concentration impurity regions
it can.

Conversely, if the acceleration voltage is set as low as 5 to 30 kV and the dose is set as large as 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² , many impurity ions are formed in the regions 616 and 617. Is implanted to form a high-concentration impurity region. On the other hand, in the region 618 where the gate insulating film 615 is present, low-speed ions are prevented by the gate insulating film, so that the amount of implanted impurity ions is low and a low-concentration impurity region can be formed. As described above, regardless of which method is used, the region 618 becomes a low-concentration impurity region, and in this embodiment, any method may be employed. In this manner, ion doping is performed, and the N-type low concentration impurity region 618 is formed.
Is formed, a KrF excimer laser (wavelength 248)
nm, pulse width of 20 nsec) to activate the impurity ions introduced into the active layer. (FIG. 6
(D))

Further, a coating of a suitable metal, for example, titanium, nickel, molybdenum, tungsten, platinum, palladium, etc., for example, a titanium film 619 having a thickness of 50 to 500 ° was formed on the entire surface by sputtering. As a result, the metal film (here, titanium film) 619 was formed in close contact with the high-concentration (or extremely low-concentration) impurity regions 616 and 617. (FIG. 6E)

Then, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) causes the metal film (here, titanium) to react with the silicon of the active layer.
Regions 620, 62 of metal silicide (here titanium silicide)
1 was formed. Laser energy density 200 ~ 4
00 mJ / cm ² , preferably 250 to 300 mJ / c
m ² was appropriate. In addition, when the substrate was heated to 200 to 500 ° C. during laser irradiation, peeling of the titanium film could be suppressed.

Thereafter, the unreacted titanium film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at a ratio of 5: 2: 2. The titanium film other than the portion in contact with the exposed active layer (for example, the titanium film existing on the gate insulating film or the anodic oxide film) remains in a metal state as it is,
It can be removed by this etching. On the other hand, since titanium silicide 620 and 621 which is a metal silicide is not etched,
It could be left. In this embodiment, the silicide region 6
The sheet resistance of 20,621 was 10 to 50 Ω / □. On the other hand, 10 to 100 k
Ω / □.

Thereafter, an interlayer insulator 622 is formed on the entire surface.
The silicon oxide film is formed to a thickness of 2000 to 1 μm by the CVD method.
m, for example, 5000 °. Then, an ITO film was formed by a sputtering method, and this was patterned and etched to form a pixel electrode 623. Further, the interlayer insulator 622 was etched to form a contact hole. Also in this case, as in the first and fourth embodiments,
The pattern was such that the contact holes protruded from the source / drain. As described above, such a pattern improves the mass productivity and reliability of the TFT.
Then, wirings / electrodes 624 and 625 were formed by a multilayer film of titanium nitride and aluminum having a thickness of 2000 to 1 μm, for example, 5000 °. (FIG. 6 (F))

[0072]

According to the present invention, a highly reliable TFT showing sufficient reliability even when a voltage is applied for a long time can be manufactured. In addition, unprecedented degrees of freedom can be obtained in the arrangement of the active layer and the contacts, and miniaturization of the element can be realized. As described above, the present invention is an invention having a great industrial value, but the industrial impact is particularly great when a TFT is formed on a large-area substrate and used for an active matrix or a driving circuit.

Although not shown in the embodiments, the present invention may be used to form a so-called three-dimensional IC in which a semiconductor circuit is further stacked on a single crystal IC or another IC. In the embodiments, examples in which the present invention is used mainly for various LCDs have been described. However, it is needless to say that the present invention can be applied to other circuits required to be formed on an insulating substrate, such as an image sensor. ────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] December 5, 2000 (200.12.
5)

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Detailed description of the invention

[Correction method] Change

[Correction contents]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method for improving the reliability of an insulated gate semiconductor device on a substrate and an integrated circuit in which many of them are formed. The semiconductor device according to the present invention includes a driving circuit such as an active matrix such as a liquid crystal display using a thin film transistor (TFT) or an image sensor, or an SOI integrated circuit or a conventional semiconductor integrated circuit (a microprocessor, a microcontroller, a microcomputer, or a semiconductor). Memory).

[0002]

2. Description of the Related Art In recent years, an insulating gate type semiconductor device (MI) has been formed on an insulating substrate or on a surface (insulating surface) separated from the semiconductor substrate by a thick insulating film even on a semiconductor substrate.
Research on forming SFETs has been actively conducted. In particular, a semiconductor device in which a semiconductor layer (active layer) is a thin film is called a thin film transistor (TFT). In such a semiconductor device, it is difficult to obtain an element having good crystallinity such as a single-crystal semiconductor. Usually, a non-single-crystal semiconductor which has crystallinity but is not a single crystal is used.

In such a non-single-crystal semiconductor, the defect density is large, and the defect is filled by neutralizing the defect with an element such as hydrogen or fluorine. For example, such a process is realized by hydrogenation. Was. But,
The bond between hydrogen and a semiconductor element (such as silicon) was weak, and was decomposed by thermal energy of one hundred and several tens of degrees Celsius. For this reason, when a voltage and a current are applied for a long time and the semiconductor locally generates heat, hydrogen is easily released, and the characteristics are remarkably deteriorated. In particular, in a TFT for controlling a large current, for example, in a monolithic active matrix circuit having an active matrix circuit and a peripheral circuit for driving the same, the driver TFT of the peripheral circuit has a channel width of 200 μm or more, so that a large current can be generated. Turning on / off was a major heat source.

[0004]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and is intended to quickly dissipate local heat generated during use of a device and to uniformly heat the entire thin film circuit device. It is an object to provide a structure of the device and a method for manufacturing such a semiconductor device.

[0005]

According to a first aspect of the present invention, there is provided a thin film semiconductor device in which a film mainly composed of aluminum nitride is formed on a substrate and a semiconductor film mainly composed of silicon is directly or indirectly formed thereon. And a wiring such as a metal or a semiconductor directly or indirectly provided thereon. The present invention also relates to a method for manufacturing a thin film semiconductor device having such a configuration.
Is a process of forming a film containing aluminum nitride as a main component on a substrate, particularly a glass substrate having poor heat conductivity and good heat insulation, and directly or indirectly forming a semiconductor film containing silicon as a main component on the glass substrate. The method is characterized by including a forming step and a step of directly or indirectly forming a wiring of metal, semiconductor, or the like thereon.

Aluminum nitride has extremely excellent thermal conductivity and is transparent (visible band gap: 6.2 eV) to visible light and near-ultraviolet light, so that it is suitable for purposes requiring transparency. Aluminum nitride is sputtered, reactive sputtered, MOCVD (metal organic chemical vapor deposition)
And a plasma CVD method. In order to obtain an aluminum nitride film by a reactive sputtering method, it is preferable to use aluminum as a target in a nitrogen atmosphere. As in the present invention, for the purpose of sufficiently releasing heat, the thickness of aluminum nitride is preferably 500 to 5 μm, typically 1000 to 5000 μm. 5
Aluminum nitride having a thickness of μm or more was easily peeled off and was not suitable for use.

Further, since the aluminum nitride film has a blocking effect on mobile ions such as sodium, it also has an effect of preventing these ions from entering the semiconductor device from the substrate. The ratio of nitrogen to aluminum in the aluminum nitride film may be a stoichiometric ratio or a non-stoichiometric ratio as long as there is no problem in heat conduction.
Typically, the ratio of nitrogen to aluminum is preferably (aluminum / nitrogen) = 0.9 to 1.4, and the thermal conductivity is 0.6 W / cmK or more (the thermal conductivity of the aluminum nitride single crystal is 2W / cmK), favorable results were obtained.

[0008] The stress of the coating may be optimized by changing the ratio of nitrogen to aluminum. Further, by adding a small amount of boron, silicon, carbon, oxygen, etc. in an amount of 0.01 to 20 atomic% in addition to nitrogen and aluminum, it is possible to match, optimize, and minimize stress distortion with a substrate. is there. The coating containing aluminum nitride as a main component may be crystalline or amorphous.

For the purpose of improving the thermal conductivity, it is usually considered to use a diamond-based material (for example, a polycrystalline diamond thin film, a hard carbon film, a diamond-like carbon film, etc.). In such a minute region, a diamond-based material generally has poor adhesion to a silicon oxide-based material, so that a sufficient effect cannot be obtained. In addition, a silicon nitride film often used as a blocking layer and a passivation layer in an ordinary semiconductor process has a low thermal conductivity and is not suitable for implementing the present invention. Table 1 below
Next, the characteristics of the main thin film materials were compared. (O is excellent, Δ is medium, and X is inferior.)

[0010]

[Table 1]

In the present invention, heat generated from a metal or semiconductor wiring (gate wiring or the like) is transmitted to an underlying semiconductor film (active layer or the like), and also a current flows through the semiconductor film. Heat is generated, and the temperature of the semiconductor film rises. However, without staying there, the temperature is quickly transmitted to the aluminum nitride film thereunder. Hydrogen desorption is reduced. In particular, local deterioration due to local heat generation due to generation of hot carriers due to application of a high reverse bias voltage between the drain and channel of the TFT can be suppressed by soaking.

In the present invention, depositing a semiconductor film directly on an aluminum nitride film is advantageous in that although the adhesion is good, a semiconductor carrier is trapped in the aluminum nitride and a parasitic channel formed by the trapped carrier (capture center). Are apt to occur and, as a result, adversely affect the electrical characteristics of the semiconductor film, which is not preferable. There is no problem if such trapping centers can be removed, but if they cannot be removed easily, a material that is electrically and chemically preferable to a semiconductor film such as a silicon oxide film (a silicon oxide film is an aluminum nitride film) (The density of the trapping centers is only one-tenth of the density of the trapping centers). Further, in the silicon oxide film, an effect of stress relaxation can be expected.

A silicon nitride film is formed on aluminum nitride in a thickness of 100 to 1000 °, for example, 200 °, and a silicon oxide film is formed thereon in a thickness of 100 to 2000 °, for example, 200 °.
Å You may have formed. In the present invention, as a material of the gate electrode, a simple substance such as silicon (including a substance whose conductivity is increased by doping impurities), aluminum, tantalum, chromium, tungsten, molybdenum, or an alloy thereof, or a multilayer thereof is used. A film may be used.
Further, as shown in the embodiment, the surface may be oxidized.

Further, aluminum nitride is not etched by a fluorine-based etchant, and is not etched by a method of etching a material used in a normal semiconductor process such as silicon oxide, silicon, or aluminum. It may be used as a stopper. That is, as the contact of the source and the drain of the TFT, not only the upper surface but also the side surface of the source and the drain can be used as the contact. For example, even when the contact hole is formed to extend from the source and the drain, the substrate is not etched by the aluminum nitride serving as an etching stopper.

As a result, the source and drain regions can be formed smaller than before, which is advantageous for circuit integration. On the other hand, this also means that the contact hole can be enlarged, and a more reliable contact can be obtained, which is advantageous for mass productivity and reliability.

[0016]

[Embodiment 1] FIG. 1 shows an example of manufacturing a TFT according to the present invention. First, a substrate (Corning 705)
9 glass substrate, size 300mm x 300mm or 100mm x 100mm) 101, thickness 2000
An aluminum nitride film 102 of ５5000 ° was deposited by a reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. The pressure during sputtering is 1 ×
Preferred results were obtained at 10 ^-4 to 1 × 10 ^-2 Torr. The deposition rate was 20-200 ° / min. Further, at the time of film formation, the substrate temperature may be raised to 100 to 500 ° C.

The aluminum nitride film 102 was formed on both sides of the substrate. This is because foreign elements such as sodium contained in the substrate or adhered to the surface after shipping are TFT
With the meaning of containing so as not to deteriorate the characteristics of
This has the effect of strengthening the substrate and making the surface less likely to be scratched.
In particular, when a TFT is used in an active matrix type liquid crystal display device, the surface on which the TFT is not provided comes into contact with the external environment, but this surface is apt to be finely scratched. And darken the screen.

Next, the glass substrate on which the aluminum nitride is formed is heated at 600 to 680 ° C., for example, 640 ° C. for 4 to 1 hour.
Annealing was performed for 2 hours in an atmosphere of nitrogen, ammonia (NH ₃ ), or nitrous oxide (N ₂ O). And
It was gradually cooled at a rate of 0.01 to 0.5 ° C / min, for example, 0.2 ° C / min, and was taken out when the temperature was lowered to 350 to 450 ° C. By this step, the substrate that was colored yellow immediately after the reactive sputtering became transparent, and the electrical insulation was improved. Further, in this annealing step, thermal shrinkage of the glass substrate occurred, and the stress was relaxed. As a result, irreversible shrinkage was reduced. For this reason, in the subsequent heat treatment step, shrinkage of the substrate was eliminated, and mask displacement was significantly reduced.

After the above-mentioned annealing, a silicon oxide film having a thickness of 2000 to 500.degree. As a method of forming this oxide film,
Sputtering in an oxygen atmosphere and TEOS were decomposed and deposited by plasma CVD in an oxygen atmosphere. Further, the film thus formed may be annealed at 450 to 650 ° C.

Thereafter, as shown in FIG.
An amorphous silicon film is formed at a temperature of 100 to 1500 °, preferably 300 to 800 ° by a VD method or an LPCVD method.
ÅThen, the island-like silicon region 104 was formed by patterning. And a thickness of 200 to 1500 mm,
Preferably, silicon oxide 105 of 500 to 1000 ° is formed. This silicon oxide film also functions as a gate insulating film. Therefore, sufficient care is required for its production. Here, TEOS is used as a raw material, and a substrate temperature of 1 with oxygen.
RF at 50-600 ° C., preferably 300-450 ° C.
Decomposed and deposited by plasma CVD. The pressure ratio between TEOS and oxygen is 1: 1 to 1: 3, and the pressure is 0.05 to 0.
The RF power was set to 100 to 250 W at 5 torr. Alternatively, decompression C using TEOS as a raw material together with ozone gas
The substrate temperature is set to 35 by the VD method or the normal pressure CVD method.
It formed as 0-600 degreeC, Preferably it was 400-550 degreeC. After film formation, 400 ~ in oxygen or ozone atmosphere
Annealed at 600 ° C. for 30 to 60 minutes.

Then, as shown in FIG. 1A, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
ec) was irradiated to crystallize the silicon region 104. Laser energy density is 200-400mJ /
cm ² , preferably 250 to 300 mJ / cm ² ,
During the laser irradiation, the substrate was heated to 300 to 500 ° C. The silicon film 104 thus formed
When the crystallinity of was investigated by Raman scattering spectroscopy, it was different from the single crystal silicon peak (521 cm ^-1 ).
A relatively broad peak was observed at around 515 cm ^-1 . Thereafter, annealing was performed at 350 ° C. for 2 hours in hydrogen.

Thereafter, an aluminum film having a thickness of 2000 to 1 μm was formed by an electron beam evaporation method, and this was patterned to form a gate electrode 106. Aluminum may be doped with scandium (Sc) by 0.15 to 0.2% by weight. Next, the substrate is adjusted to pH ≒.
7, immersed in an ethylene glycol solution of 1 to 3% tartaric acid, and anodized using platinum as a cathode and the aluminum gate electrode as an anode. The anodization was completed by first increasing the voltage to 220 V with a constant current and maintaining the state for one hour. In the present embodiment, in the constant current state, the voltage rising speed is suitably 2 to 5 V / min. Thus, anodic oxide 107 having a thickness of 1500-3500 °, for example, 2000 ° was formed. (FIG. 1 (B))

Thereafter, an impurity (phosphorus) was implanted into the island-like silicon film of each TFT in a self-aligned manner by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion as a mask. Phosphine (PH ₃ ) was used as a doping gas. Dose amount is 1-4 × 10
^{It was 15} cm ^-2 .

Further, as shown in FIG. 1C, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 ns)
ec) was applied to improve the crystallinity of the portion where the crystallinity was deteriorated by the introduction of the impurity region. The energy density of the laser was 150 to 400 mJ / cm ² , preferably 200 to 250 mJ / cm ² . Thus, N
Type impurity (phosphorus) regions 108 and 109 were formed. The sheet resistance in these regions was 200 to 800 Ω / □.
In this step, a so-called RTP (rapid thermal process) is used in which a flash lamp is used instead of a laser to quickly raise the temperature to 1000 to 1200 ° C. (temperature of a silicon monitor) and heat the sample.
May be used.

Then, an interlayer insulator 110 is formed on the entire surface.
Plasma CVD of TEOS as raw material and oxygen
Method, reduced pressure CVD method with ozone, or normal pressure CV
A silicon oxide film having a thickness of 3000 .ANG. Was formed by Method D. The substrate temperature was 250 to 450 ° C, for example, 350 ° C.
After the film formation, the silicon oxide film was mechanically polished to obtain a flat surface. Further, an ITO film was deposited by a sputtering method, and this was patterned to obtain a pixel electrode 111. (Fig. 1 (D))

Then, the interlayer insulator 110 is etched to form contact holes in the source / drain of the TFT as shown in FIG. 1E, and wires 112 and 113 of chromium or titanium nitride are formed. Was connected to the pixel electrode 111. In this case, FIG. 1 (F)
As shown in (1), the contact hole may be formed by protruding the source / drain region (island-like silicon). In this case, the area of the contact holes protruding from the island-shaped silicon was 30 to 70%. In this case, the contact is formed not only on the upper surface of the source / drain but also on the side surface. Hereinafter, such a contact is referred to as a top side contact. In the conventional structure, if an attempt is made to form a top side contact, the silicon oxide film underlying the portion other than the island-shaped silicon and further the substrate are etched by the step of etching the interlayer insulator, but in this embodiment, The aluminum nitride film 102 serves as an etching stopper, and the etching stops here.

In the normal case, the size of the contact hole needs to be smaller than that of the source / drain. However, in the case of the top side contact, the size of the island can be made smaller than that of the contact hole. As a result, the island can be miniaturized. On the contrary, since the contact hole can be enlarged, mass productivity and reliability can be improved. Finally, 300 ~
Annealing was performed at 400 ° C. for 0.1 to 2 hours to complete hydrogenation of silicon. Thus, the TFT was completed.
A large number of TFTs manufactured at the same time were arranged in a matrix to form an active matrix type liquid crystal display device.

Embodiment 2 FIG. 2 shows an example of manufacturing a TFT according to the present invention. First, a substrate (NA35 glass manufactured by NH Techno Glass Co., Ltd.) 201 having a thickness of 1000
An aluminum nitride film 202 of 5 μm was deposited by a reactive sputtering method. Targeting aluminum,
Sputtering was performed in an atmosphere of nitrogen and argon. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. The pressure during sputtering is 1 × 10
Preferred results were obtained at ^-4 to 1 × 10 ^-2 Torr. The deposition rate was 20-200 ° / min. Further, at the time of film formation, the substrate temperature may be raised to 100 to 500 ° C.

Next, as the base oxide film 203, a thickness of 100
A silicon oxide film having a thickness of about 1000 °, for example, 500 ° was formed. As a method of forming the oxide film, a sputtering method in an oxygen atmosphere or TEOS was decomposed and deposited by a plasma CVD method in an oxygen atmosphere. Thereafter, this film is 550-700
Nitrous oxide (N ₂ O) at 650 ° C. for 4 hours.
In a nitrogen atmosphere containing 20%. As a result, the aluminum nitride film became transparent, and the silicon oxide film thereon could be densified.

Thereafter, an amorphous silicon film is formed by plasma CVD or LPCVD to a thickness of 200 to 150 nm.
0 °, preferably 300-800 °, and annealed in a nitrogen atmosphere at 600 ° C. for 48 hours. The crystalline silicon film thus obtained was patterned to form an island-shaped silicon region 204. Then, as the gate insulating film 207, a thickness of 200 to 1500 °, preferably 500 to 1
000 ° of silicon oxide was formed.

Then, a phosphorus-added silicon film having a thickness of 2000 to 5 μm is formed by a low pressure CVD method.
This was patterned to form a gate electrode 209 and a wiring 208. Thereafter, an impurity (phosphorus) was implanted in a self-aligned manner into the island-like silicon film of the TFT by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion as a mask. Phosphine (PH ₃ ) was used as a doping gas. Dose amount is 1-8 ×
It was 10 ¹⁵ cm ^-2 .

Further, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was irradiated to improve the crystallinity of the portion where the crystallinity was deteriorated by introducing the impurity region. Laser energy density is 150
４００400 mJ / cm ² , preferably 200 to 250 mJ
/ Cm ² . Thus, the N-type impurity (phosphorus) region 2
05 and 206 were formed. The sheet resistance in these regions was 200 to 800 Ω / □. (Fig. 2 (A))

Thereafter, a plasma CVD method, a low pressure CVD method, or a normal pressure C
A silicon oxide film having a thickness of 3000 .ANG. Was formed by the VD method.
Further, a photoresist 211 was selectively formed. Such a photoresist is preferably formed at a portion where the wiring intersects or a portion where the wiring is provided with a contact. (FIG. 2 (B)) And as shown in FIG. 2 (C),
Using the photoresist 211 as a mask, the interlayer insulator 21 is used.
0, gate insulator 207, and underlying silicon oxide film 203
Was etched. The underlying silicon oxide film was etched, but the substrate was not etched with the aluminum nitride film as a stopper. For this reason, a flat surface was obtained. (Fig. 2 (C))

Then, a titanium film (having a thickness of 2
000Å-5 μm), and patterning the same to form a wiring 212 connected to the source and drain of the TFT.
213 were formed. Further, ITO was selectively formed to form a pixel electrode 214. Finally, the substrate thus treated was annealed in hydrogen at 1 atm and 350 ° C. for 30 minutes to complete the hydrogenation. Thus, the TFT was completed. A large number of TFTs manufactured at the same time were arranged in a matrix to form an active matrix type liquid crystal display device.

Embodiment 3 FIG. 3 shows an example of manufacturing a TFT according to the present invention. The TFT of this embodiment is a TFT of a peripheral circuit in a monolithic active matrix circuit having an active matrix circuit and a peripheral circuit for driving the active matrix circuit, particularly, a channel width of 200 to 800.
This relates to a driver TFT of μm. Such a driver TFT generates a large amount of heat because it controls a large current. Therefore, rapid heat dissipation by the base film of the present invention is desired.

First, the substrate (Corning 7059) 301
An aluminum nitride film 302 having a thickness of 2000 to 5000 ° was deposited thereon by a reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. A favorable result was obtained when the pressure during sputtering was 1 × 10 ⁻⁴ to 1 × 10 ⁻² Torr. The deposition rate was 20-200 ° / min. During the film formation, the substrate temperature is set to 100 to 500 ° C.
May be raised.

Next, as the base oxide film 303, a thickness of 100
A silicon oxide film of 0 to 2000 ° was formed. As a method for forming this oxide film, a sputtering method in an oxygen atmosphere or a TE method
The OS may be a plasma CVD method in an oxygen atmosphere.
Thereafter, an amorphous silicon film was deposited at 1000 to 3000 °, preferably 1000 to 1500 ° by plasma CVD or LPCVD, and annealed in a nitrogen atmosphere at 600 ° C. for 48 hours. The crystalline silicon film thus obtained is patterned to form island-like silicon regions 3.
04 was formed. Then, as the gate insulating film 305,
200 to 1500 mm thick, preferably 500 to 1000
珪 素 of silicon oxide was formed.

Then, an aluminum film having a thickness of 2000 to 5 μm is formed by an electron beam evaporation method, is patterned, and is further subjected to an anodic oxidation treatment under the same conditions as in the first embodiment. Wiring 30
7 was formed. (FIG. 3A) Thereafter, the TF is formed by ion doping (also called plasma doping).
Impurities (phosphorus) were implanted into the T island-like silicon film in a self-aligned manner using the gate electrode portion as a mask. Phosphine (PH ₃ ) was used as a doping gas. The dose amount was 2 to 8 × 1015 cm ⁻² . (FIG. 3 (B))

Then, the underlying silicon oxide film 303 was etched. The etching was stopped by the aluminum nitride film 302 serving as a stopper. In this state, a KrF excimer laser (wavelength 248 nm, pulse width 20 nsec)
To improve the crystallinity of the portion where the crystallinity is deteriorated by the introduction of the impurity region. The energy density of the laser is 100 to 400 mJ / cm ² , preferably 1
It was 00 to 150 mJ / cm ² . Since the silicon oxide film containing phosphorus or boron absorbs ultraviolet light, a strong laser beam was necessary for performing subsequent laser annealing after through doping as in Example 1.
However, in this example, if the silicon oxide film (gate insulating film) was removed after the doping, the energy of the laser was small. For this reason, the throughput of the laser processing could be improved. Thus, N-type impurity (phosphorus) regions 308 and 309 were formed. The sheet resistance in these regions was 200 to 800 Ω / □. (FIG. 3 (C))

Thereafter, a plasma CVD method, a low pressure CVD method, or a normal pressure C
The silicon oxide film is formed to a thickness of 2000 to 3000 に よ っ て by the VD method.
Formed and an aluminum film (thickness 2000)
Å-5 μm), and patterning this to form TF
Wirings 311 and 312 connected to the source and drain of T were formed. The wiring 312 and the wiring 307 intersect as shown in the drawing. (FIG. 3 (C))

Finally, the substrate thus treated is
The hydrogenation was completed by annealing for 30 minutes in hydrogen at 350 ° C. at atmospheric pressure. Thus, the TFT was completed. Similarly, a P-channel TFT was manufactured by doping the impurity region with boron, and a CMOS circuit was manufactured. N-channel type, a typical field-effect mobility of P-channel type, respectively, 80~150cm ² / Vs, 40~100cm ²
/ Vs. In addition, it was confirmed that the shift register manufactured with this TFT operates at 11 MHz at a drain voltage of 17 V.

Further, a long time (up to 9
Even when a high voltage (> 20 V) was applied for 6 hours), deterioration of the characteristics was small. This is because heat locally generated in the TFT is quickly dissipated, and the elimination of hydrogen from the interface with the semiconductor film and the gate insulating film is suppressed. Actually, a long-time bias application state (gate voltage 11 V,
The state of heat generation at a drain voltage of 14 V) was confirmed by thermography (manufactured by Nippon Avionics, Inc.). As a result, a constant temperature increase was not observed in the TFT according to the present embodiment, and at most, the temperature rose only to about 50 ° C. . However, under the same conditions, a conventional TFT (having no aluminum nitride film as a base film) was heated to 100 ° C. or more in a short time, and the device characteristics were significantly deteriorated. Thus, the effect of the present invention was remarkably confirmed.

[Embodiment 4] This embodiment shows a method of forming a pixel portion of an active matrix type liquid crystal display.
4 and 5 show this embodiment. First, Corning 7059 was used as the substrate 401. The substrate is annealed at a temperature higher than the strain temperature before or after the formation of the base film, and then gradually cooled to a strain temperature or lower at 0.1 to 1.0 ° C./min. Substrate shrinkage in the accompanying process is small, and mask alignment is ready. For Corning 7059 substrate, 1-4 at 620-660 ° C.
After annealing for an hour, the temperature is gradually reduced at 0.03 to 1.0 ° C./min, preferably 0.1 to 0.3 ° C./min.
It is good to take out at the stage when the temperature has dropped to ° C. In this embodiment, after annealing at 630 ° C. for 4 hours, 0.2 ° C. /
Cooled in minutes.

Then, a thickness of 0.1 to 2 μm is formed on the substrate 401.
An aluminum nitride film 402 having a thickness of m, preferably 0.2 to 0.5 μm, for example 0.3 μm, was deposited by a reactive sputtering method. Sputtering was performed in an atmosphere of nitrogen and argon with aluminum as a target. When the proportion of nitrogen was 20% or more, a coating having good thermal conductivity was obtained. The pressure during sputtering is 1 × 10 ^-4 to 1 × 1
Good results were obtained at 0 ^-2 Torr. The deposition rate is 2
It was 0-200Å / min. Further, at the time of film formation, the substrate temperature may be raised to 100 to 500 ° C. This aluminum nitride film 402 may be formed before the substrate annealing treatment. Thereafter, a very thin silicon oxide base film 403 having a thickness of 0 to 1000 °, preferably 20 to 500 °, for example, 200 ° was formed by a sputtering method.

After forming the base film, an intrinsic (I-type) amorphous silicon film 404 having a thickness of 300 to 1500 °, for example, 1000 ° was formed by a plasma CVD method.
Further, the thickness is 200 to 20 by the plasma CVD method.
A mask film 405 of 00Å, for example, 500Å silicon oxide or silicon nitride was formed. Then, this mask film 40
Holes 406 were selectively formed in No. 5. Further, a nickel film 407 having a thickness of 5 to 200 °, for example, 20 ° was formed by a sputtering method. Instead of the nickel film, a nickel silicide film (chemical formula: NiSix, 0.4 ≦ x ≦ 2.
5, for example, x = 2.0). Copper, palladium, and the like other than nickel also have a catalytic action of crystallizing amorphous silicon, and may be used. (FIG. 4 (A))

Then, under an inert atmosphere (nitrogen or argon, atmospheric pressure) at 550 ° C. for 4 to 8 hours, for example, 8 hours
Anneal for hours to crystallize. In this step, nickel was introduced into the silicon film from the hole 406. Nickel catalytically acts on amorphous silicon to promote crystallization, so that the region 410 immediately below the hole 406 first crystallized. However, the crystallinity was random in this region. Thereafter, the crystallization spreads from the hole 406 to the periphery with the diffusion of nickel, and the crystallization progressed in the direction of the arrow in the figure, and the region 409 was crystallized. Area 4
In the case of 09, crystallization proceeds in one direction, so that good crystallinity was obtained. The region 408 is an uncrystallized region. The size of the crystallization region depended on the annealing time. Mask film 4
If 05 is thin, nickel will invade from other than the hole 406,
Since crystallization is started, for the purpose of obtaining good crystallinity,
Not preferred. Therefore, the mask film 405 needs at least 500 ° as in this embodiment.
(FIG. 4 (B))

After this step, the silicon film 404 was patterned by a known photolithography method to form a TFT island-shaped active layer 411. On this occasion,
At the portion to be the channel formation region, the tip of lateral crystal growth (that is, crystallized region 409 and uncrystallized region 408)
And the region 41 where nickel was directly introduced.
It is important that 0 (both have high nickel concentrations) not be present. By doing this,
Carriers moving between the source and the drain can be prevented from being affected by the nickel element in the channel formation region. In this embodiment, nickel is selectively introduced into the silicon film, and only the crystallization region 409 in the lateral direction is
Although used for the active layer of T, a silicon film crystallized by uniformly introducing nickel without using such selective introduction of nickel may be used. However, the characteristics of the TFT in this case are slightly inferior to those of the former.

4C shows a state during the etching of the silicon film 404. That is, the mask film and the photoresist 41 are formed on the island-shaped active layer 411.
There are two. In this etching step, the underlying silicon oxide film 403 was also etched. (FIG. 4C) After this step, it is necessary to remove the photoresist and further etch the mask film on the active layer 411. This is usually performed using a hydrofluoric acid-based etchant. However, in the conventional TFT process, only a silicon oxide film is used as a base film, so that when the mask film is etched, the base film is also used. There is a problem that etching is performed in the same manner (in this case, the underlying film is etched at least by a thickness of 500 ° of the mask film). 500
The Å step was a major cause of disconnection of the gate electrode when the gate electrode was formed later. For this reason, it was necessary to make the mask film thin. However, if the mask film was too thin, there was an inconvenience in performing selective crystallization as described above.

However, in this embodiment, since the aluminum nitride film hardly etched by hydrofluoric acid was used as the base film, only the mask film could be selectively etched. The problem step was reduced only by adding the thickness t (= 200 °) of the underlying silicon oxide film 403 to the thickness (1000 °) of the silicon film, and the subsequent problem of disconnection of the gate electrode did not occur.

After the formation of the active layer,
In this case, infrared light having a peak at 0.8 to 1.4 μm was irradiated for 30 to 180 seconds to further promote crystallization of the active layer (light annealing (lamp annealing) step or RTP). Temperature is 800-1300 ° C, typically 9
The temperature was set to 00 to 1200 ° C, for example, 1100 ° C. This temperature is the temperature of the thermocouple in the single crystal silicon substrate set as a monitor at the same time, and is not the actual temperature of the substrate surface. Irradiation was performed in an H2 atmosphere to improve the condition of the surface of the active layer. In this step, since the active layer is selectively heated, heating of the glass substrate can be minimized. And, it is very effective in reducing defects and unbound bonds in the active layer. The problem at this time is that in the present embodiment, since the selective crystallization process is used, the absorption of infrared rays differs depending on the location of the silicon film. For example, the active layer 411
Among them, the phenomenon that the above-mentioned infrared ray was easily absorbed on the right side of the figure due to the large amount of the crystalline component, while the phenomenon that the infrared ray was hardly absorbed on the left side due to the large amount of the amorphous component was observed.

However, in this embodiment, since the aluminum nitride film having a good thermal conductivity is used as the base film, the heat absorbed by the silicon film by the above-mentioned irradiation with the infrared rays is transferred to a specific portion of the silicon film. Since the silicon film is immediately diffused through the base film without being accumulated, the silicon film is uniformly heated, and thermal distortion does not occur, thereby improving the uniformity of the silicon film. Thereafter, a silicon oxide film 413 having a thickness of 1000 ° was formed as a gate insulating film by a plasma CVD method. TEO as source gas for CVD
S (tetraethoxysilane, Si (OC ₂ H ₅ )
₄ ) Using oxygen and the substrate temperature during film formation is 300 to 550
° C, for example, 400 ° C.

The silicon oxide film 413 serving as the gate insulating film
After the film formation, optical annealing by irradiation of visible / near infrared light was performed again. By this annealing, the level mainly at the interface between the silicon oxide film 413 and the silicon active layer 411 and in the vicinity thereof could be eliminated. This is extremely useful for an insulating gate type field effect semiconductor device in which the interface characteristics between the gate insulating film and the channel formation region are extremely important.

Subsequently, by a sputtering method,
Aluminum (including 0.01 to 0.2% scandium) having a thickness of 3000 to 8000 °, for example, 5000 ° was formed. Then, the gate electrode and the wiring were formed by patterning the aluminum film. Further, the surface of the aluminum electrode and the wiring was anodized to form an oxide layer on the surface. This anodization is carried out when tartaric acid is 1 to 5
% In ethylene glycol solution. The thickness of the obtained oxide layer was 2000 °. Thus, a gate electrode portion (that is, a gate electrode and an oxide layer around the gate electrode) 414 and a wiring portion 415 were formed. Alternatively, the gate electrode may be a single layer or a multilayer of a metal such as polycrystalline silicon, titanium, tungsten, or tantalum, or a silicide of such a metal. (FIG. 4 (D))

Next, an N-conductivity type is imparted in a self-aligned manner to the active layer region (constituting the source / drain and channel) by an ion doping method (also referred to as a plasma doping method) using the gate electrode portion 414 as a mask. Impurities were added. Phosphine (P
H ₃ ) and an acceleration voltage of 60 to 90 kV, for example, 80
kV. Dose amount is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ c
m ⁻² , for example, 2 × 10 ¹⁵ cm ⁻² . As a result, N
Mold impurity regions 416 and 417 were formed. In these impurity regions 416 and 417, silicide such as titanium may be formed.

Thereafter, annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used, but another laser may be used. The irradiation condition of the laser beam is such that the energy density is 200 to 400 mJ / cm ² ,
For example, 250 mJ / cm ^2, and ² to 10
A shot, for example, two shots was irradiated. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation with the laser light.

This step may be performed by lamp annealing using visible / near infrared light. Visible and near-infrared light is crystallized silicon or phosphorus or boron in 10 ¹⁹ to 10
It is easily absorbed by amorphous silicon to which ²¹ cm ^{-3 is} added.
Effective annealing comparable to thermal annealing of 000 ° C. or more can be performed. If phosphorus or boron is added, light is sufficiently absorbed even in the near infrared due to scattering of impurities. This can be fully guessed from the fact that it is black even with the naked eye. On the other hand, since it is hardly absorbed by the glass substrate, it is not necessary to heat the glass substrate to a high temperature, and the process can be performed in a short time. . In this embodiment, since the aluminum nitride film having high thermal conductivity is used as the base film, even in such an annealing process, thermal destruction in which heat is accumulated in one place does not occur. In particular, it is preferable to use an aluminum nitride film as a base film only by using a gate electrode made of thermally weak aluminum.

Thereafter, a silicon oxide film 418 having a thickness of 3000 to 8000 Å, for example, 6000 Å was formed as an interlayer insulator by a plasma CVD method. As the interlayer insulator, polyimide or a two-layer film of silicon oxide and polyimide may be used. Further, an ITO film having a thickness of 800 ° was formed by a sputtering method, and was patterned to form a pixel electrode 419. Then, the interlayer insulator is etched with buffered hydrofluoric acid (HF / NH ₄ F = 0.01 to 0.2, for example, 0.1) to form a contact hole 42.
2 and 423 are formed, and a metal material, for example, a multilayer film of titanium nitride and aluminum is used to form a TFT electrode / wiring 4.
20, 421 were formed. Lastly, annealing was performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm to complete a semiconductor circuit having a complementary TFT. (FIG. 4E)

In this embodiment, in particular, the contact hole 42
2, 423 were formed at the ends of the active layer, and a part thereof was formed to protrude from the active layer. Even with such a shape,
In this embodiment, since the aluminum nitride film was used as the base film, the substrate was hardly overetched, and a TFT could be formed with good reproducibility. FIG. 5 (A) shows a sample manufactured according to the present invention. As shown in the top view of the TFT, the active layer 411 has a linear shape, and contact holes 422 and 423 are formed at both ends so as to protrude from the active layer. Spacing of the active layer and the gate wiring 415 at a distance of x _1, also the distance between the active layer and the pixel electrode 419 is arranged to keep the x _2. This is to prevent overlapping of lines due to misalignment. In this embodiment, since the area of the active layer is small, the area of the pixel electrode can be increased, and the area occupied by the wiring can be reduced.

FIG. 5B shows a state of the conventional TFT viewed from above, and FIG. 5C shows a cross section thereof. As is clear from FIG. The active layer is constricted and thin in the gate electrode portion, and thick in the source and drain regions. This is because the contact holes 522, 5
This is to ensure that the contact holes 23 are formed in the source 516 and the drain 517 of the active layer, and that the contact holes are formed in the active layer even if the contact holes are misaligned due to overetching.

However, in such a structure, the area of the active layer becomes large, so that the gate wiring 515 and the pixel electrode 519 are formed.
In order to prevent overlap with the active layer, if the layers are formed apart from the active layer by x ₁ and x ₂ , respectively, the wiring becomes large and the area of the pixel electrode is reduced, as is apparent from the drawing. The dotted rectangles in FIGS. 5A and 5B indicate the same area.
It can be seen that the area occupied by T and the wiring connected thereto is large, and the area of the pixel is small. Conversely, in this embodiment, the area occupied by the TFT and the wiring is small, and the area of the pixel is large. As described above, according to the present embodiment, it is possible to improve the ratio of pixels / wirings, and thereby to improve the aperture ratio of the liquid crystal display device and miniaturize the pixels. These all lead to an improvement in the quality of the liquid crystal display device.

[Embodiment 5] This embodiment shows a method of forming a pixel portion of an active matrix type liquid crystal display.
FIG. 6 shows this embodiment. First, Corning 7059 was used as the substrate 601. First, an aluminum nitride film 602 having a thickness of 0.1 to 2 μm, preferably 0.2 to 0.5 μm, for example, 0.3 μm, was deposited on the substrate 601 by the reactive sputtering method as in the fourth embodiment. After that, a very thin silicon oxide base film 603 having a thickness of 0 to 1000 °, preferably 20 to 500 °, for example, 200 ° was formed by a sputtering method. After forming the base film, an island-shaped crystalline silicon region 604 having a thickness of 300 to 1500 °, for example, 800 ° was formed. Furthermore, plasma CV
A silicon oxide film 605 having a thickness of 1000 ° was formed as a gate insulating film by Method D. The source gas for CVD is T
EOS and oxygen were used.

Thereafter, an aluminum film (containing 1 wt% of Si or 0.1 to 0.3 wt% of Sc) having a thickness of 1000 to 3 μm, for example, 6000 °, was formed by electron beam evaporation or sputtering. Then, a photoresist (for example, OFPR8 manufactured by Tokyo Ohka)
00/30 cp) by spin coating.
If an aluminum oxide film having a thickness of 100 to 1000 ° is formed on the entire surface of the aluminum film by anodic oxidation before forming the photoresist, adhesion to the photoresist is good, and By suppressing the current leakage, it was effective in forming the porous anodic oxide only on the side surfaces in the subsequent anodic oxidation step. Thereafter, the photoresist and the aluminum film were patterned and etched together with the aluminum film to form a wiring 606 and a gate electrode 607. On these wirings and gate electrodes, the above-mentioned photoresist 60 is formed.
8, 609 are left, which function as a mask for anodizing prevention in a subsequent anodizing step. (FIG. 6
(A))

Then, the above wirings and gate electrodes are anodized by passing an electric current in an electrolytic solution to a thickness of 3000 to 25 μm.
m, for example, 0.5 μm thick anodic oxides 610, 61
No. 1 was formed on the side surface of the wiring and the gate electrode. Anodizing is
3 to 20% of an aqueous acid solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, etc.
V, for example, a constant current of 8 V was applied to the gate electrode. The anodic oxide thus formed was porous. In this embodiment, the oxalic acid solution (30
(−80 ° C.), the voltage was set to 8 V, and anodic oxidation was performed for 20 to 240 minutes. The thickness of the anodized oxide was controlled by the anodizing time and temperature. (FIG. 6 (B))

Next, the masks 608 and 609 were removed, and a current was again applied to the gate electrode and wiring in the electrolytic solution. In this case, an ethylene glycol solution having a pH of 7 containing 3 to 10% tartaric acid, boric acid, and nitric acid was used. A better oxide film was obtained when the temperature of the solution was lower than room temperature around 10 ° C. Therefore, the gate electrodes / wirings 606 and 607
Barrier-type anodic oxides 612, 61 on the top and side surfaces of
3 was formed. The thickness of the barrier type anodic oxide was proportional to the applied voltage. For example, an applied voltage of 100 V formed an anodic oxide of 1200 °. In this embodiment, the voltage is 100
V, the thickness of the resulting barrier anodic oxide was 1200 °. The thickness of the barrier type anodic oxide is arbitrary, but if it is too thin, there is a risk that aluminum will be eluted when the porous anodic oxide is etched later, so that 500 mm or more was preferred. .

It should be noted that although barrier-type anodic oxide can be obtained in a later step, a barrier-type anodic oxide is not formed outside the porous anodic oxide, but a porous anodic oxide is formed. A barrier-type anodic oxide is formed between the oxide and the gate electrode. (FIG. 6C) Thereafter, the silicon oxide film 605 was etched by a dry etching method. In this etching, a plasma mode of isotropic etching or a reactive ion etching mode of anisotropic etching may be used. However, it is important to prevent the active layer from being etched deeply by sufficiently increasing the selectivity between silicon and silicon oxide. For example, when CF ₄ is used as an etching gas, the anodic oxide is not etched, and therefore, the silicon oxide films 614 and 615 existing under the gate electrode and the wiring remain without being etched. Also in this etching step, since the aluminum nitride film 602 serves as a stopper, further etching does not proceed, and the step can be minimized.

Then, using a mixed acid of phosphoric acid, acetic acid and nitric acid,
The porous anodic oxides 612, 613 were etched. So
Then, the active layer 6 of the TFT is formed by the ion doping method.
04 shows the gate electrode portion (that is, the gate electrode and its surroundings).
Anodic oxide film) and gate insulating film 615 as masks
The impurities were implanted in a self-aligned manner. In this case, ion
Varies depending on the acceleration voltage and dose
Combinations are conceivable. For example, if the acceleration voltage is
90 kV and set the dose to 1 × 10 ¹³~ 5x
10¹⁴cm^-2If you make it lower, the areas 616 and 617
Indicates that most impurity ions pass through the active layer
Indicates the maximum concentration. Therefore, the areas 616 and 617
An extremely low concentration impurity region is obtained. On the other hand, there is no gate above
In the region 618 where the edge film 615 exists, the gate insulating film
Therefore, high-speed ions are slowed down, and
Degree and the formation of low-concentration impurity regions
it can.

Conversely, if the acceleration voltage is set as low as 5 to 30 kV and the dose is set as large as 5 × 10 ^{14 to} 5 × 10 ¹⁵ cm ⁻² , many impurity ions are formed in the regions 616 and 617. Is implanted to form a high-concentration impurity region. On the other hand, in the region 618 where the gate insulating film 615 is present, low-speed ions are prevented by the gate insulating film, so that the amount of implanted impurity ions is low and a low-concentration impurity region can be formed. As described above, regardless of which method is used, the region 618 becomes a low-concentration impurity region, and in this embodiment, any method may be employed. In this manner, ion doping is performed, and the N-type low concentration impurity region 618 is formed.
Is formed, a KrF excimer laser (wavelength 248)
nm, pulse width of 20 nsec) to activate the impurity ions introduced into the active layer. (FIG. 6
(D))

Further, a coating of a suitable metal, for example, titanium, nickel, molybdenum, tungsten, platinum, palladium, etc., for example, a titanium film 619 having a thickness of 50 to 500 ° was formed on the entire surface by sputtering. As a result, the metal film (here, titanium film) 619 was formed in close contact with the high-concentration (or extremely low-concentration) impurity regions 616 and 617. (FIG. 6E)

Then, irradiation with a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) causes the metal film (here, titanium) to react with the silicon of the active layer.
Regions 620, 62 of metal silicide (here titanium silicide)
1 was formed. Laser energy density 200 ~ 4
00 mJ / cm ² , preferably 250 to 300 mJ / c
m ² was appropriate. In addition, when the substrate was heated to 200 to 500 ° C. during laser irradiation, peeling of the titanium film could be suppressed.

Thereafter, the unreacted titanium film was etched with an etching solution in which hydrogen peroxide, ammonia and water were mixed at a ratio of 5: 2: 2. The titanium film other than the portion in contact with the exposed active layer (for example, the titanium film existing on the gate insulating film or the anodic oxide film) remains in a metal state as it is,
It can be removed by this etching. On the other hand, since titanium silicide 620 and 621 which is a metal silicide is not etched,
It could be left. In this embodiment, the silicide region 6
The sheet resistance of 20,621 was 10 to 50 Ω / □. On the other hand, 10 to 100 k
Ω / □.

Thereafter, an interlayer insulator 622 is formed on the entire surface.
The silicon oxide film is formed to a thickness of 2000 to 1 μm by the CVD method.
m, for example, 5000 °. Then, an ITO film was formed by a sputtering method, and this was patterned and etched to form a pixel electrode 623. Further, the interlayer insulator 622 was etched to form a contact hole. Also in this case, as in the first and fourth embodiments,
The pattern was such that the contact holes protruded from the source / drain. As described above, such a pattern improves the mass productivity and reliability of the TFT.
Then, wirings / electrodes 624 and 625 were formed by a multilayer film of titanium nitride and aluminum having a thickness of 2000 to 1 μm, for example, 5000 °. (FIG. 6 (F))

[0072]

According to the present invention, a highly reliable TFT showing sufficient reliability even when a voltage is applied for a long time can be manufactured. In addition, unprecedented degrees of freedom can be obtained in the arrangement of the active layer and the contacts, and miniaturization of the element can be realized. As described above, the present invention is an invention having a great industrial value, but the industrial impact is particularly great when a TFT is formed on a large-area substrate and used for an active matrix or a driving circuit.

Although not shown in the embodiments, the present invention may be used to form a so-called three-dimensional IC in which a semiconductor circuit is further stacked on a single crystal IC or another IC. In the embodiments, examples in which the present invention is used mainly for various LCDs have been described. However, it is needless to say that the present invention can be applied to other circuits required to be formed on an insulating substrate, such as an image sensor.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/092 H01L 21/90 C 27/08 331 27/08 321F H04N 5/335

Claims (3)

[Claims] An aluminum nitride film formed on a substrate; a silicon oxide film formed on the aluminum nitride film; a crystalline semiconductor film formed on the silicon oxide film;
A semiconductor device comprising: a gate insulating film formed on the crystalline semiconductor film; and a metal or semiconductor wiring and electrode formed on the gate insulating film. 2. The semiconductor device according to claim 1, wherein said aluminum nitride film contains 0.01 to 20 atomic% of an element of boron, silicon, carbon or oxygen. 3. An aluminum nitride film formed on a substrate, a crystalline semiconductor film formed on the aluminum nitride film, a gate insulating film formed on the crystalline semiconductor film, and the gate insulating film A semiconductor device having a metal or semiconductor wiring and an electrode formed thereon, wherein the aluminum nitride film contains 0.01 to 20 atomic% of an element of boron, silicon, carbon or oxygen. apparatus.