JP2001189661A - Encoding device and decoding device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To continuously encode/decode symbols within one cycle by preventing the disorder of pipeline processing in an arithmetic encoder/decoder. SOLUTION: When normalizing processing occurs, a pipeline is disordered because of necessity to update a context RAM 701. Then, Qe (next) 714 and 715, which are to be outputted when normalization occurs and the context RAM 701 is updated, are previously stored in a Qe ROM 702 and a present Qe 713 and the Qe (next) 714 and 715 are parallel outputted. When normalization occurs and the same context is continued, a control circuit 709 controls a selector 706 and selects any one of Qe (next) 714 and 715.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding device and a decoding device, and more particularly to an entropy prediction encoding device and a decoding device.

[0002]

2. Description of the Related Art A method of predicting a coded symbol based on the state of neighboring pixels that have already been coded and arithmetically coding a prediction result based on a probability estimation value of the coded symbol determined for each state is a method of compressing the compression ratio. It is known that they exhibit the most excellent characteristics from the point of view. QM-coder, which is an encoder adopted in JBIG (ITU recommendation T.82), is one example.

As shown in FIG. 8, a QM-coder includes a context generation unit 200, a context table (context memory) 210, a probability estimator 220, and an arithmetic encoder 230.
And

[0004] The context generation unit 200 detects 1024 states formed by 10 pixels around the coded pixel.
FIG. 10 shows an example of the template. In the figure, "?" Indicates a pixel to be encoded, and 10 pixels indicated by "x" are reference pixels. When the encoding of one pixel is completed, the template is shifted to the right by one as shown by the dotted line in FIG. 10, and the encoding of the next pixel is performed.

Each state is called a context (hereinafter, referred to as S), and a predicted value MPS (s) of a dominant symbol is defined for each context.
(That is, for the coded symbol of interest, the MPS
Is predicted to be "1", then MPS (S) = 1)
And the state number of the probability estimator are read from the context memory and output to the probability estimator 220.

[0006] The probability estimator 220 outputs the region width Qe (s) of the inferior symbol to the arithmetic coder 230 from these pieces of information. Here, Qe is “probability of LPS occurring”, and in this specification, this may be referred to as “probability of occurrence of coded symbol” or simply “probability estimate”. The area width Qe (s) of the inferior symbol means a width corresponding to the occurrence probability of LPS, which is calculated by multiplying the occurrence probability of LPS by the width of the agenda.

[0007] Arithmetic encoder 230 executes an arithmetic coding operation from the coded symbol, the predicted value MPS (s) of the dominant symbol and the region width Qe (s), and outputs a code.

As shown in FIG. 9, in arithmetic coding, a number line having an initial value of 0 to 1 is divided into an area width of a superior symbol (MPS) and an area width of an inferior symbol (LPS). The encoding target symbol sequence is made to correspond to a representative point in the divided area. The representative point is set at the bottom of the partial section.

When the coded symbol and the predicted value are the same, the MPS width is selected for encoding the next symbol, and otherwise the LPS width is selected. As described above, a representative point is provided in this area width, and the binary point indicates the sign.

In the arithmetic coding operation, when the area width becomes smaller than the predetermined value, the doubling process is repeated until the area width becomes equal to or more than the predetermined value (specifically, 1/2 of the initial value) in order to prevent the precision of the decimal point. . This processing is called normalization processing.

The normalization process is also performed when LPS is encoded. In other words, when the LPS width is selected with the estimation deviated, the LPS width is always smaller than 1/2 of the initial value, so that the normalization is performed every time.

When the normalization processing is performed, the MPS value and the state number (ST) in the context table 210 of FIG. 8 are updated. The update of the state number is performed by the probability estimation unit 22.
The “next state number” written in “0” is realized by overwriting in the context table 210 (this overwriting is indicated by an arrow RX in FIG. 8).

By updating the context table 210, the next context is the same as the previous context (that is, even if the template of FIG. 10 is shifted to the right by one, the arrangement of the reference pixels 1 and 0 is the same as the previous context. Was)
The value of Qe (S) generated will be different. As a result, a value more suitable for the probability distribution of the information source is selected. That is, the adaptation to the image to be encoded is performed.

If each unit of the arithmetic encoder shown in FIG. 8 performs one process in one clock, the arithmetic code process can be a pipeline process. By using the pipeline, very high-speed arithmetic code processing without waste is realized.

[0015]

When arithmetic code processing is pipelined, if normalization processing occurs on the way, the pipeline may be disturbed, wasteful waiting time may increase, and processing efficiency may decrease. is there.

In particular, it is considered that normalization occurs at a considerable frequency and that the pipeline is likely to be disordered in an image pattern having continuity in context. A similar problem occurs in the case of decoding.

According to the present invention, there is provided an encoding / decoding apparatus capable of removing the disturbance of the pipeline and continuously executing symbol encoding and decoding in one cycle irrespective of an image pattern or an arithmetic encoding state. The purpose is to provide.

[0018]

SUMMARY OF THE INVENTION In one aspect of the present invention, a current probability estimate and a probability estimate after normalization has occurred and a table has been updated are simultaneously supplied to the encoder. Is configured to select one of them according to the state of.

In one embodiment of the present invention, a probability estimator (Qe
In addition to the conventional Qe value, Qe after transition by normalization is output to the output of the ROM) at the same time.

Normalization occurs and the context table (Qe
ROM), the probability estimate (Qe) that would be output if updated was also output in parallel with the current estimate, so that even if normalization occurs and the context is continuous, its update The subsequent probability estimate (Qe) only needs to be selected by the selector and supplied to the encoder.

Therefore, even if the symbols immediately after the occurrence of the normalization have the same context, it is not necessary to reread the Qe ROM, and the pipeline is not disturbed.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In one embodiment of the present invention, the occurrence probability of a coded symbol is estimated from the state of an already coded symbol sequence, and the estimated value (eg, Qe) and the predicted value of the symbol (eg, , MPS value) to an encoder for encoding the current probability estimation value (Qe).
And an updated probability estimate (next Qe) after the occurrence of a predetermined situation (next Qe), and according to the state of the encoder, the current probability estimate or the updated probability estimate Choose one to prevent pipeline disruption.

That is, in the entropy coding apparatus, when it is necessary to update a parameter for maintaining accuracy or adapting to an input image, a probability estimation value that will be output after the parameter is updated ( The future probability estimation value) is output in parallel with the current estimation value (probability estimation value output in normal processing), and when a predetermined situation occurs (for example, the parameter needs to be updated). In the case where the reading and writing of the RAM conflict due to the continuous context), the future estimated value is supplied to the encoder instead of the current estimated value. This eliminates the need to wait for encoding while updating the parameters by turning the loop, and prevents disturbance of the pipeline.

In order to facilitate understanding of the features of the present invention, first, the configuration and operation of an arithmetic encoder having a pipeline configuration to which the present invention is not applied (a comparative example considered by the inventor of the present invention) will be described. This will be described with reference to FIGS.

FIG. 16 is a block diagram showing a circuit configuration example of the arithmetic encoder of the comparative example.

The context generator 400 outputs the context index S (signal 409) to the context RAM 401 as address information according to the state of the reference pixel. Note that the arrangement of the coded symbols and the reference pixels (x) is as shown in FIG.

The context RAM 401 stores 1 bit of the predicted value MPS (S) of the coded symbol and 7 bits of the state number of the probability estimator for each context.

The context RAM 401 is composed of a dual-port RAM (2-port RAM) so that reading of a context and updating of the context content can be executed in the same cycle if the context is different.

The probability estimator 402 is a state transition table and does not need to be rewritten. Therefore, the probability estimator 402 is usually constituted by a ROM (hereinafter referred to as a Qe ROM). Of course, this may be configured with RAM.

The state number 410 of the probability estimator is output from the context RAM 401. Qe ROM4 as its address
Access 02. Then, the probability estimation value Qe (S) 416 according to the context (S) and the state number 44 of the next state transition destination
1 is output.

There are two systems of the state number 441 of the next state transition destination when normalization occurs due to LPS encoding and when M
This is because the state number of the transition destination differs between the case where normalization occurs and the case where the agende falls below 1/2 of the initial value due to the encoding of the PS. The selector 404 selects one of the two state numbers according to the situation where the normalization has occurred.

When the estimation is continuously deviated, the Qe ROM 402 sets the MPS value switch signal 412 to active (ie, “1”). In this state, the exclusive OR circuit 405 functions as an inverter.

That is, the exclusive OR circuit 405
, The current MPS value is input via the timing adjustment circuit 406. When the input MPS value is “1”, the output 414 of the exclusive OR circuit 405 becomes “0”, and the
When the S value is “0”, the output 414 of the exclusive OR circuit 405 becomes “1”, and the MPS value is updated.

The updated next state number and MPS value are written to the context RAM 401. The write address is a normalized index circuit (timing adjustment circuit) 40
Given by 7. That is, the context RAM 401 is overwritten using the context index three clocks earlier as an address variable.

In the arithmetic encoder 403, the encoded symbol, MPS
Perform encoding operation using (S) and Qe (S).

As described above, when encoding is executed and normalization occurs, the contents of the context RAM 401 are updated.
As described above, the contents to be updated are the state number (signal 413) of the probability estimator and the predicted value MPS (S) of the symbol (signal 414).

The two types of transition destinations 411 are MPS normalized, L
The signal 413 is selected by the selector 404 according to the PS normalization. Here, the "MPS normalization" was estimated,
This is a normalization process that occurs when the orgen falls below 1/2 of the initial value as a result of dividing the number line. The “LPS normalization” is a normalization process that occurs inevitably due to incorrect estimation.

As described above, the new predicted value (signal 414) is obtained by combining the current predicted value MPS (S) and the switch flag signal 412 (in the figure).
It is made by taking exclusive logical operation with switch-MPS). The address signal of the context RAM when updating the content is indicated by reference numeral 415 in the figure.

In FIG. 16, a context generator 400,
The context RAM 401, the Qe ROM 402, and the arithmetic code arithmetic unit 403 are all internally configured so that predetermined processing can be executed in one cycle.

In FIG. 16, reference numerals 406 and 407 are delay elements for adjusting the timing of the pipeline. 1D is 1 clock delay, 2D is 2 clock delay, 3D
Represents a delay of 3 clocks. Timing control circuit 408
Thus, a necessary control signal is supplied to each unit.

FIG. 19 shows an example (general) of a state transition table serving as a probability estimator. This table is
As shown in the figure, from the left side, a state number (Qe-index), a probability estimation value (Qe), a next transition destination number, and a flag (switch-MPS) indicating whether to invert the predicted value of the MPS are configured. .

There are two types of transition destinations, each of which represents a transition destination when an update process (normalization process) occurs by encoding or decoding LPS or MPS.

When a transition is made after encoding the MPS (MPS normalization), the transition is made so that the probability estimation value Qe becomes smaller. LPS
Is the opposite (LPS normalization). In this way, we adapt to the information source. Updating of the state number is performed at the time of normalization.

The normalization processing is performed when the value of the register indicating the area width of the arithmetic coding becomes less than 1/2 of the initial value.
The doubling process is repeated until the register value becomes 1/2 or more of the initial value. At this time, the probability estimation value is also updated. Updating the state number of the probability estimation table corresponds to rewriting the content corresponding to the context in the context RAM 401.

FIG. 20 shows a Qe having the transition table of FIG.
17 shows a configuration example of a ROM 402 (FIG. 16). As illustrated, the Qe ROM 402 has a configuration in which the address (state) is 113 and the bit width is 31 bits. Bit 0 is a switch flag, bits 1 to 14 are the next transition destination, and bits 15 to 30 are Qe (S).

FIG. 17 is a timing chart for explaining the operation of the arithmetic encoder of FIG. However, FIG. 17 shows only a case where normalization does not occur.

As shown, in synchronization with the clock,
Context generation (context det), context RAM read (context RAM RD), Qe ROM read (Qe RD), encoding and normalization (coding / renorm) are pipelined for consecutive symbols Will be done. It can be seen that if normalization does not occur, processing can be performed continuously in one cycle per pixel.

Next, a case where a normalization process has occurred will be described. FIG. 18 shows a state where normalization has occurred in the encoding of the i-th symbol (process 601).

Let the context of the i-th symbol be Si. Assume that the next symbol, i.e., the (i + 1) -th symbol has the same context Si. Then, when the normalization occurs, the Qe ROM 402 has already read, but the value Qe (Si) cannot be used. This is because the probability estimate of the context Si is updated by the normalization, and the value read in the process 602 is an old value. Therefore, it is necessary to read the ROM again after waiting for the update. This disrupts the pipeline.

A specific description will be given. The updating of the context RAM 401 is executed in a process 604. An invalid cycle 603 is entered for the (i + 1) th symbol, and in step 605, the updated Qe
(Si) can be read. The processing is delayed due to this effect even after the (i + 2) th symbol. Therefore, in the circuit configuration of FIG.
When normalization occurs and the symbol immediately after the normalization has the same context, the pipeline is disturbed, and it takes extra time for one cycle.

The above is the description of the comparative example. Next, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a block diagram showing a configuration of an arithmetic encoder according to a first embodiment of the present invention.

As shown, the encoder comprises a context generator 700 and a context table (context R).
AM) 701, a probability estimator (Qe ROM) 702, and an arithmetic code calculator 703, each of which executes one process in one clock. That is, the arithmetic encoder of FIG. 1 has a four-stage pipeline structure.

The processing contents of these components are the same as those of the general encoder of FIG. 8 (and the comparative example of FIG. 16). The feature of the present embodiment lies in the configuration of the Qe ROM and the circuit configuration of its peripheral part.

The contents of the table mounted on the Qe ROM 702 are as shown in FIG. As compared with the table of the comparative example of FIG. 19, in the case of FIG. 2, the bit width is expanded to 63 bits,
It can be seen that the data of “next Qe (LPS)” and “next Qe (MPS)” are added.

Here, “next Qe (MPS)” means that when the arithmetic encoder 703 encodes the MPS, the orgen becomes less than 初期 of the initial value and normalization processing occurs. Since the state of the transition destination of the context ROM 701 has been updated, and the next coded symbol has the same context as the previous time, an access to the same address as the previous time occurs in the context RAM 701, and as a result, the Qe ROM702
Is the width (Qe) of the LPS that will be output from the Qe ROM 702 if the address corresponding to the updated transition destination state is accessed.

Similarly, “next Qe (LPS)” means that normalization processing is inevitably generated by the encoding of LPS in the arithmetic encoder 703, and the context table is updated by turning a loop in response to this. If you access the same address, Qe
This is the width (Qe) of the LPS that will be output from the ROM 702.

That is, a normalization process occurs, the table in the context RAM 701 is updated, and a future Qe value that would occur if the same address is accessed again is stored in advance in the Qe ROM 702. In the table in the current Q
There is a feature of the present embodiment in that it is described together with the value of e.

The control circuit 709 of FIG. 1 receives all information such as the context of the encoded symbol and whether or not normalization has occurred in the arithmetic encoder. Therefore, the control circuit 70
9 selects the current Qe from those information, or selects the future Qe (M
PS) or Qe (LPS) can be selected in real time. To enable such selection, a selector 706 is provided.

Thus, even if the normalization process occurs, it is not necessary to wait for the process while updating the table by turning the loop, and the selector can use the future Qe (MPS) or Q
Just select e (LPS). Therefore, no disturbance occurs in the pipeline.

The selector 707 in FIG. 1 corresponds to the selector 404 in FIG. In addition, selector 704,
705 was used last time after the normalization process occurred, considering that there is a possibility that the normalization process may also occur next.
It is provided so that the MPS value and the number of the state of the transition destination can be reused. This will be described later.

Hereinafter, a specific description will be given.

The state number of the state transition table is input to Qe ROM 702 as an address. The output signal is the current probability estimate Qe (s) (signal 713) and the new Qe (S) when the state transition occurs due to normalization is the signal 71 for LPS and MPS normalization.
4. It is output as a signal 715, and two kinds of state transition numbers by normalization (signal 716 and signal 717) are similarly output, and a flag (swi) indicating whether or not to invert MPS (S).
tch-MPS, signal 718) is output.

The exclusive OR of this flag and the current predicted symbol MPS (S) is obtained by the EOR circuit 708, whereby a new predicted symbol is created. This value and the output of the selector 707 become the memory contents of the index 724 to be normalized.

In the selectors 704 and 705, when the coded symbol immediately after “normalization has occurred” is coded in the “same context”, the lower signal is selected. That is, the MPS for update and the next state number that are overwritten in the context RAM 701 are selected.

In such a case, since the probability estimation is also deviated next and the normalization processing may be continued, the MPS for updating and the next state number are used again. I have. In this case, the Qe ROM 702 is accessed using the state number output via the selector 705 as an address variable, and Qe713, next Qe714, and 715 having the same value as the previous time are output in parallel. One of them will be selected.

The selection signal of each selector is appropriately output while the control circuit 709 checks a necessary state signal.
The details of the control signal are omitted because the figure becomes complicated.

As described above, FIG. 2 shows a configuration example of the Qe ROM. As described in the comparative example, the reason why the pipeline is disrupted is that the Qe ROM needs to be read again.

In this embodiment, in such a case, Qe
The transition destination Qe at the time of LPS normalization and the transition destination Qe at the time of MPS normalization are stored at the same address so that it is not necessary to reread the ROM. Bits 15 to 46 correspond to this part.

According to the state transition table of FIG. 19 described above,
Transition destination of MPS normalization and LPS normalization when Qe-index is 0
It can be seen that (Qe-index) is 1. Also, it can be seen that Qe when Qe-index is 1 is 0x2586. Therefore, 0x2586 is stored in bits 15 to 30 in FIG. Similarly, 0x2586 is stored in bits 31 to 46. Other components are the same as those of the comparative example.

By doing so, even when encoding of the same context is performed immediately after the occurrence of normalization, it is not necessary to read the ROM again.
You only need to select what you need according to your situation.

Next, an outline of the operation of the arithmetic encoder of FIG. 1 will be described with reference to FIG.

The encoding of the i-th symbol is synchronized with the clock to generate a context (context det), read a context RAM (context RAM RD), and read a Qe ROM.
(Qe RD), coding operation and normalization operation (coding / renorm)
Are processed in this order.

The coded symbol and its context are detected by a context generator 700. The encoded symbol is sent to the arithmetic code calculator 703 through a delay circuit 710 for adjusting the timing of the pipeline.

The context index s, which is the identification number of the context, becomes an input signal of the context RAM 701. At the same time, when normalization occurs in that context, as address information for updating the contents of RAM,
Input to the normalization index 712. The normalization index 712 is a delay circuit that delays three clocks. The output signal 724 of the normalization index 712 becomes a signal (context index) for specifying an address at the time of updating the next transition destination state or the MPS value when the normalization processing occurs.

The context RAM 701 is constituted by a dual-port RAM capable of performing reading and writing in parallel. As a result, even when the RAM needs to be updated due to the normalization process, the next context (the arrangement of 1s and 0s in the reference pixels when the template in FIG. 10 is shifted to the right) is different from the previous context. For example, reading (reading) of context information for encoding and updating (write) of context information when normalization occurs can be performed simultaneously in the same cycle.

Therefore, even if the normalization process occurs, if the next context is different, there is no contention for access to the ROM, so there is no need to wait for overwriting, and the disturbance of the pipeline occurs. Absent.

The output signal of the context RAM includes the predicted value MPS (S) of the coded symbol and the state number (st in the figure) of the probability estimator.
ate No). The prediction value MPS (S) is sent to the arithmetic code calculator 703 through the delay adjustment circuit 711 in the pipeline.

These two output signals are supplied to selectors 704 and 7
Enter 05. The control circuit 709, when normalization does not occur,
The upper signal (that is, M output from the context RAM)
Selectors 704 and 705 so that the PS value and the state number are selected.
Control.

The Qe ROM 702 is accessed using the state number input via the selector 705 as an address variable. As shown in FIG. 2, since three types of Qe are written together in one address, from the Qe ROM 702, 3
The type value is always output. Then, the control circuit 709
However, the presence or absence of normalization and the continuation of context are determined, and one of them is selected in real time according to the situation.

The operation in the case where the normalization processing has occurred will be described below with reference to FIG.

In process 801 in FIG. 3, Qe (Si) (signal 7
Assume that 13) has been selected. Here, the i-th context is Si.

In processing 802, encoding operation and normalization processing of the i-th symbol are performed. Here, it is assumed that LPS is encoded and normalization has occurred. The i-th symbol for the (i + 1) -th symbol
Reading of the Qe ROM 702 is executed in the same cycle as the symbol encoding operation (process 804).

The context of the (i + 1) th symbol is also Si
Assume that Then, since LPS normalization has occurred in the ith symbol, the selector 706 selects the Qe value 714 to which the transition is made by LPS normalization.

In the process 805, an encoding operation using this value is executed. At this time, in process 803, the context RAM 70
The content of the context Si of 1 is updated.

The updating process is performed as follows. That is, in the selector 707, the next state number 716 at the time of LPS normalization
Is selected. On the other hand, the EOR circuit 708 generates a new predicted value (signal 721) from the switch-MPS (signal 718) and the current predicted value MPS (Si) (signal 723).

As described above, if the signal 718 is “1”, M
The value of PS (Si) is inverted. These two pieces of information are written at the address Si of the context RAM 701.

At this time, the address Si is output from the delay circuit 712 as a signal 724. At the timing of this update processing, it is necessary to read the Qe ROM 702 for the (i + 2) th symbol.

At this time, if the (i + 2) th symbol is also in the same context Si, the selectors 704 and 705 control so that the lower signal is selected. The reason is, as described above, the processing 805
Because normalization may occur again. When the updating of the Si context information is completed, the selector 704
, 705 are selected.

For the (i + 3) th symbol, the context RAM is read in this cycle (process 808). As described above, if the context of the (i + 3) th symbol is different from Si and is Sj, the context read to the dual port ROM 701 and the update of the context Si are performed simultaneously.

If the context of the (i + 3) th symbol is Si, the content is updated in step 803. At this time, selector 7
In 04 and 705, the lower signal is selected.

Even when encoding is performed continuously in the context where normalization has occurred in this way, an invalid cycle unlike the conventional example does not occur, and the pipeline is not disturbed.
Therefore, one symbol can be continuously encoded with one clock for any image pattern.

FIG. 7 shows the results of an experiment (computer simulation) supporting the effect of the present invention.

[0094] Pipeline disturbances are likely to occur
This is an image pattern in which both the frequency of normalization and the continuity of context are high. In a document image, the context is often continuous, but normalization does not occur much. Conversely, in a random image with a black ratio of about 50%, normalization occurs frequently, but there is little context continuity. Then, it seems that the disturbance of the pipeline is likely to occur in the image pattern near the compression ratio 0.5, which is the intermediate point. FIG. 7 shows an encoding simulation result of the QM-coder using such a test image.

In FIG. 7, the number of cycles in which one symbol can be encoded for each line is plotted. The upper characteristic line A shows the conventional example, and the lower characteristic line B shows the data according to the present invention.

As is clear from the simulation results, it can be seen that the conventional example may exceed 1.1 cycles / symbol. This means that the processing capacity is reduced to about 90 M symbols / sec even when operated with a clock of 100 MHz. On the other hand, it can be seen that the encoder according to the present invention can obtain a processing capability of 100 M symbols / sec in any case regardless of the image pattern.

FIG. 21 shows the main procedure of the encoding of the present invention described above. That is, the current Qe, the Qe (next Qe) that would be output if normalization processing occurred in MPS coding, and the output if normalization processing occurred in LPS coding Qe (next Qe)
And are output in parallel (step 30).

When normalization occurs and the next context is the same (step 31), depending on whether the normalization is based on MPS coding or LPS coding, One of the future Qe (next Qe) is selected (step 32). If normalization does not occur, the current Qe is selected (step 33).

(Embodiment 2) Next, an embodiment of the arithmetic decoder according to the present invention will be described with reference to FIG. FIG.
FIG. 2 is a block diagram showing a configuration of an embodiment of an arithmetic decoder according to the present invention.

The decoder also has a configuration in which one symbol is continuously decoded in one cycle. That is, like the encoder, context generation, context RAM read, Qe ROM
, And a four-stage pipeline process is executed in the order of decoding operation.

The arithmetic decoding determines whether the input code belongs to the MPS or the LPS on the divided number line, and determines whether the MPS or LPS at that time is “1” or “0”. By knowing this, the symbol to be restored (restored symbol) is restored.

The restored symbol is used as a reference pixel for decoding a code to be input next. Usually, restoration of one symbol by such a method requires four clocks or more, and pipeline processing cannot be realized as it is. Unlike the case of encoding, in the case of decoding, the value of the pixel to be processed is unknown until the decoding is actually finished, and after the restoration of the pixel,
Since there is no choice but to perform encoding (generation of Qe) using the restored pixel as a reference pixel, the number of steps is inevitably increased.

Therefore, in the present embodiment, first, the same idea as in the case of encoding (the idea of predicting the future and outputting in parallel ahead of time) is also introduced into decoding.

That is, in the case of a binary arithmetic code, since there are only "1" or "0" restored symbols, both the case where the currently restored symbol is "1" and the case where the symbol is "0" are determined. Assuming, in each case, Qe for restoring the next symbol (one symbol ahead) is output simultaneously while restoring the current symbol. That is, two Qe ROMs are provided and each is operated simultaneously. Then, one of Qe is selected according to the result of restoration of the current symbol.

Similarly, reading from the context RAM, which is necessary for restoring the next symbol to be restored next (symbol two ahead), is simultaneously executed during restoration of the current symbol.

At this time, the symbol currently being restored is "0".
When the next symbol is “1” and the current symbol is “
0, the next symbol is “0”, the current symbol is “1”, the next symbol is “1”, and the current symbol is “1” and the next symbol is “0”. Therefore, four context RAMs (dual-port memories) are provided and operated simultaneously.

Also, each of the four context indices (S) necessary for restoring the next next symbol (three symbols ahead) is stored in four contexts R
Simultaneously input and write to the input port of AM (dual port memory).

The four states assumed in this case are as follows: the first symbol is “0” and the second symbol is “1”; and the first symbol is “0” and the second symbol is “2”. Is “0”, the first symbol is “1” and the second symbol is “1”, and the first symbol is “1”.
The symbol is roughly divided into four when the symbol two ahead is "0" at "1".

As described above, while the current symbol is being restored,
A method in which information necessary for restoring symbols one to three ahead is proactively input and output in parallel, and when the restoration result is determined, one of the outputs is selected accordingly. , The arithmetic decoding process can be pipelined.

However, normalization occurs as in the case of encoding, and
And when the context is continuous, the pipeline will be disrupted. Therefore, as in the case of encoding, a method is employed in which the current Qe and the updated Qe are output in parallel and one of them is selected according to the actual decoding result.

Hereinafter, a specific description will be given.

As described above, in order to perform decoding continuously in one cycle, it is necessary to start decoding the next (i + 1) -th pixel before the i-th pixel is determined. For that purpose, it is necessary to perform parallel processing separately for the case where the i-th pixel is “0” and “1”. Similarly, the i + 2 pixel is subjected to parallel processing for each value of the i + 1 pixel. The contents of these parallel processes are determined by the configuration of the pipeline.

In FIG. 4, two Qe ROMs 913, 914 are operated simultaneously, and four context RAMs 905, 906, 90
7, 908 are operated simultaneously. Then, the arithmetic decoding unit 91
The selectors 909, 910, 911, 912, 915, 916 also use the value (1 or 0) of the restored symbol 7 as a selection control signal.
To output the output corresponding to the restored symbol,
The configuration is appropriately selected.

FIG. 5 is a block diagram showing more specifically only the periphery of the Qe ROM 913 and the context RAMs 905 and 906 in FIG. As is clear from comparison with FIG. 1, the detailed configuration of the circuit is almost the same.
This is a matter of course because the decoding apparatus also performs the same encoding operation as the encoding side to generate the MPS value and Qe and supplies them to the decoder.

According to the overall configuration of FIG. 4, it is possible to temporarily form a pipeline of the decoder. However, when normalization occurs and the context is continuous, the pipeline is disturbed. Therefore, as shown in FIG. 5, both the current Qe and the updated Qe are generated and output, and either Qe is selected according to the actual decoding result. As a result, regardless of the image pattern and the state of the decoder, the disturbance of the pipeline does not occur.

The output signal of the Qe ROM 913 and the functions of the selectors 1008 and 1009 shown in FIG. 5 are the same as those of the selector in the case of the encoding described above. Also, the function of the selectors 1003 and 1004 on the input side of the Qe ROM 913 is for selecting the lower signal when decoding in the same context when updating the context RAM by normalization, as in the case of encoding.

The delay circuit 901 is a delay circuit for adjusting timing, and outputs a context index to be normalized as an address of a context RAM.

When the decoder is configured in this manner, even when decoding is continuously performed in the context in which normalization has occurred, no invalid cycle occurs and the pipeline is not disturbed. Therefore, one symbol can be decoded continuously with one clock for any image pattern.

The basic operation of the arithmetic decoder shown in FIG.
This will be specifically described with reference to the timing chart of FIG.

When decoding the ith symbol (process 1100), the (i + 1) th symbol
For the symbol (the next restored symbol), it is assumed that the i-th symbol is “0” and “1”, and Qe R
OM913 and 914 are read (processes 1101 and 1102).

At the same time, for the (i + 2) th symbol (the second restored symbol), the context RAMs 905 to
908 is read (processes 1104-1107).

At the same time, for the (i + 3) th symbol,
The (i + 1) th pixel which has not been restored yet from the arrangement of the reference pixels in FIG.
Assuming the value of the symbol and the (i + 2) th symbol, four types of context indexes are generated.

When the arrangement of the reference pixels is different from that in FIG. 10 and extends to the left on the decoding line, at the pipeline stage n stages away from the pipeline stage of the arithmetic decoding unit, 2 @ n powers Data is processed in parallel,
When the symbols of these parallel data are determined by decoding the i-th symbol, one of them is selected,
It is sent to the next pipeline stage.

Next, the operation of the specific circuit shown in FIG. 5 will be described. Here, the arithmetic decoding unit
Assuming that the decoding process of the i-th symbol is executed in 917 (FIG. 4), the operation will be described with reference to that time.

At this timing, the context generator
900 generates a context index Si + 3 for decoding the i + 3 pixel.

In FIG. 5, when the i-th symbol is Di, Si + 3 has four combinations of Di + 1 and Di + 2.
It is represented as, for example, Si + 3 (Di + 2 = 0 / Di + 1 = 0). This represents the context index of the (i + 3) th symbol assuming that both the Di + 2 symbol and the Di + 1th symbol are “0”. Reference numerals 901 to 904 are delay circuits for outputting a context index to be normalized to a context RAM. Reference numerals 905 to 908 denote context RAMs.

Each has the same configuration as that for encoding.
The outputs of the context RAMs 905 and 906 are Qe ROM state numbers for decoding the (i + 2) th symbol. Where the symbol Qe-i
ndexi + 2 (Di + 1 = 0 / Di = 0) indicates a Qe-index assuming that both the i-th symbol and the i + 1-th symbol are “0”. Others are the same. MPSi + 2 is the predicted value of the (i + 2) th symbol.
The assumed conditions are omitted because they are the same as those of the corresponding Qe-index.

The selectors 909 to 912 select an input signal according to the value of the restored symbol Di. If Di is decoded and the value is “0”, the signal above the selector is selected. As a result, for example, the output of the selector 909 includes D
Qe-index for i + 1 restoration is selected. Similarly, selector 9
For the output of 10, the predicted value of Di + 1 when Di = 0 MPSi + 1 (Di = 0)
Is chosen.

A Qe value for restoring Di + 1 is output to the output of the Qe ROM 913. This is Qei + 1 (Di = 0). This signal contains three types of Qe values as in the case of encoding. Since they become complicated, they are expressed together.

In the selector 915, Qei + 1 (Di = 0) and Qei + 1 (Di
= 1) is selected by the value of Di, and the MPS of the output of the selector 916 is selected.
The data is input to the arithmetic decoding arithmetic unit 917 together with i, and after decoding of Di, decoding of Di + 1 is executed. A control signal such as a selector selection signal is supplied to each unit by a control circuit 918.

FIG. 22 shows a summary of the main steps in the pipeline of the arithmetic decoding method of the present invention described above.

That is, the first symbol, the second symbol, and the third symbol are processed in advance, and information (probability estimates) corresponding to each of the states that can be actually taken is parallelized. (Step 40). Then, using the actual decoding result, the selector is controlled to select one of the information output in parallel (step 41).

Then, in order to prevent the pipeline from being disturbed in the case where the normalization process occurs and the context is the same, the generation of each probability estimation value corresponding to each state (context) is shown in FIG. , The same method as in the arithmetic coding is executed.

In the above description, the probability estimation table is
Although the example of the configuration using the ROM has been described, the configuration using the RAM may be used. In addition to the QM-coder, the same idea as that of the present invention can be applied to an encoding / decoding device that operates by supplying an encoder while updating a probability estimation value adaptively for each context. .

Although the present embodiment has been described with reference to the example of image encoding, such encoders and decoders can be applied to general data compression other than image data. In addition, the probability estimation ROM
There is no need to configure the output data, and a plurality of output data may be used as in the embodiment. Also, Qe ROM
The same function as that described above can be realized by real-time calculation using a DSP or the like.

In the above-described embodiment, an example has been described in which the disturbance of the pipeline is completely prevented.
Even if some disturbance occurs, it is of course possible to reduce the disturbance in the pipeline by a method of parallel output / selection of a plurality of pieces of information by future prediction.

The arithmetic coding / decoding device of the present invention described above is suitable for being mounted on a multifunction device (a device having functions of a scanner, a facsimile machine, and a copier) as shown in FIG. In other words, applications that read images and temporarily store them in memory, such as scanners, faxes,
In order to apply QM-coder to multifunction devices, high-speed processing is required as scanners and printers increase in speed. By applying the present invention, it is possible to perform very high-speed encoding / decoding without disturbing the pipeline processing for any image.

The multifunction peripheral shown in FIG.
, An encoding circuit 103 such as MH, an image processing circuit 104,
A coding / encoding circuit 105, an image line memory 106, a code memory 107, a communication interface 108 such as a modem,
An image input device 111 such as a scanner and an image recording / display device 112 such as a printer are provided. The arithmetic code / decoder of the present invention is mounted on the QM code / coding circuit 105.

(Embodiment 3) In the present embodiment, when the context is continuous, the encoding proposed by the applicant of the present invention is stopped and the encoding for each symbol is stopped and the collective encoding is performed. The method is used in combination with the method described in the first and second embodiments for preventing the disturbance of the pipeline due to future prediction.

FIG. 15 shows an example of an image. As shown, areas A, C, etc. are character areas, and areas B, D
Is a white-only area (inter-line area). And the area E,
On the right side of F, there are high-definition images 10 and 20 in which the continuity of the context is high but the probability estimation is difficult.

In the character area, since the probability estimation is easy and the frequency of normalization is low, the disturbance of the pipeline is not considered to be a serious problem. In addition, high-resolution images 10,
As for 20, even by using the above-described present invention, the disturbance of the pipeline can be prevented.

In the present invention, a method is employed in which information based on future prediction is output in parallel with the current information and is selected a posteriori. For example, in the all-white (or all-black) line spacing area, such a method is adopted. There is no need for a simple method. Therefore, when an all-white area appears, encoding (decoding) is performed collectively, thereby reducing waste and encoding (decoding) one image.
It is possible to perform the operation at a higher speed.

Even for non-white lines, some collective encoding
Decoding can be performed, but with respect to all white lines, a larger number of symbols can be collectively processed than the number of collectively processed symbols of non-white lines. Thereby, the processing speed can be improved.

In order to collectively encode all white areas,
As shown in FIG. 12, in a state where data input to the context generator 3200 is latched in the line memory 2000, the sequence control unit 4000 detects a white line and sends an identification signal thereof to the multi-symbol processing determination unit 3300. , The maximum number of symbols that can be collectively processed is determined. The configuration of the present invention for preventing (reducing) the turbulence of the pipeline is as follows:
The context generator 3200, the context memory 3400, and the probability estimator 3600 are also employed in the same manner as in the above-described embodiment.

As shown in FIG. 14, batch encoding of white lines (for example, encoding of MPS) is performed for Qe for a plurality of times within a range from the original (Areg) to not less than 1/2 (0x8000) of the initial value. Can be easily realized by subtracting all at once. If normalization occurs, there is a concern that the processing will be complicated. Therefore, in general, it is desirable that no normalization occurs as a condition for batch processing of consecutive symbols.

FIG. 13 shows the procedure of the batch encoding process. That is, it is determined whether or not the Qe is greater than or equal to the median when the Qe is subtracted in a lump (step 10), and the continuity of the context and the MPS is determined (step 20). Select the encoding process (steps 30, 4
0).

[0147]

As described above, according to the present invention, encoding and decoding can be executed at a constant speed regardless of the image pattern without any disturbance of the pipeline. As a result, a high-performance encoding / decoding device that can perform encoding / decoding at a higher speed than before can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an arithmetic encoder according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration example of a probability estimation memory according to the present invention.

FIG. 3 shows the operation (pipeline operation) of the arithmetic encoder shown in FIG.
Timing diagram to explain

FIG. 4 is a block diagram showing a configuration of an arithmetic decoder according to a second embodiment of the present invention;

FIG. 5 is a block diagram showing in detail the periphery of a Qe ROM of the arithmetic encoder of FIG. 4;

FIG. 6 shows the operation of the arithmetic decoder shown in FIG. 4 (pipeline operation);
Timing diagram to explain

FIG. 7 is a diagram for explaining the effect of the arithmetic encoder according to the present invention;

FIG. 8 is a block diagram showing a general configuration of an arithmetic encoder.

FIG. 9 is a diagram showing the principle of an arithmetic code.

FIG. 10 is a diagram showing an example of a template used for arithmetic coding.

FIG. 11 is a block diagram showing a configuration of a multifunction peripheral equipped with an arithmetic code / decoder of the present invention.

FIG. 12 is a block diagram showing a configuration of an arithmetic encoder according to a third embodiment of the present invention.

FIG. 13 is a flowchart showing a main operation procedure of the arithmetic encoder of FIG. 12;

FIG. 14 is a diagram for explaining the principle of collective encoding;

FIG. 15 is a diagram showing an example of an image to be encoded.

FIG. 16 is a block diagram illustrating a configuration example of an arithmetic encoder according to a comparative example.

17 is a timing chart showing a pipeline operation when there is no normalization in the circuit of FIG. 16;

FIG. 18 is a timing chart showing a pipeline operation when normalization occurs in the circuit of FIG. 16;

FIG. 19 is a diagram for explaining the contents of a probability estimation table.

FIG. 20 is a diagram illustrating a configuration example of a probability estimation memory in a comparative example;

FIG. 21 is a flowchart showing main steps of an arithmetic coding method (prevention of pipeline disturbance) according to the present invention;

FIG. 22: Arithmetic decoding method of the present invention (pipelining)
Flow chart showing the main steps of

[Explanation of symbols]

700 Context generator 701 Context RAM 702 Qe ROM 703 Arithmetic code calculator 704, 705, 706, 707 Selector 708 Exclusive OR circuit 709 Control circuit 710, 711 Timing adjustment circuit 712 Normalized index circuit (update address generation circuit)

 ──────────────────────────────────────────────────続 き Continued on the front page F-term (reference)

Claims (17)

[Claims] 1. An encoding apparatus for estimating an occurrence probability of an encoded symbol from a state of an already encoded symbol sequence, supplying the estimated value and a predicted value of the symbol to an encoder, and encoding the encoded symbol. A current probability estimate and a probability estimate after an update has occurred in a predetermined situation are generated in parallel, and depending on the state of the encoder, the current probability estimate or the updated probability estimate An encoding device for selecting one of the values. 2. An encoding apparatus for estimating an occurrence probability of an encoded symbol from a state of an already encoded symbol sequence, and supplying the estimated value and a predicted value of the symbol to an encoder to perform encoding. Coding having a memory for storing a probability estimate, and storing, at the same address of the memory, a current probability estimate and a probability estimate after an update has been performed due to occurrence of a predetermined situation. apparatus. 3. A context generator for generating a state (context) of an already coded symbol sequence, a context memory storing a predicted value (MPS) and a state number of a symbol for each context; A probability estimate (Qe), a probability estimate (next Qe) after a predetermined situation has occurred and updated, and an updated state when the state number stored in the context memory has been updated Number, and the current probability estimate, the updated probability estimate,
And a probability estimating memory that outputs each of the updated state numbers in parallel, and selecting one of the current probability estimating value and the updated probability estimating value output from the probability estimating memory. 1 and one of the state number output from the context memory and the updated state number output from the probability estimation memory, and the probability estimation memory
Arithmetic code arithmetic using a second selector supplied as address information, a probability estimation value selected by the first selector, and a predicted value (MPS) of the symbol output from the context memory An encoder comprising: an encoder. 4. The processing of generating a context, the processing of reading a probability estimation memory, the processing of reading a context memory, and the arithmetic encoding operation are executed and pipelined in the same cycle, and one pixel is encoded in one cycle. 4. The encoding device according to claim 3, wherein: 5. The method according to claim 5, wherein the context memory is a dual port.
5. The encoding device according to claim 3, wherein the encoding device is configured by a RAM. 6. A decoding device for estimating a probability of occurrence of a decoded symbol from a state of a symbol sequence that has already been decoded, and supplying the estimated value and a predicted value of the symbol to a decoder for decoding. The values of the pixels to be restored in the future are predicted, and the probability estimation values are generated in parallel for each state determined according to each predicted value, and are generated in parallel according to the actual decoding result by the decoder. A decoding device for selecting any one of the probability estimation values. 7. A decoding apparatus for estimating the probability of occurrence of a decoded symbol from the state (context) of a symbol sequence already decoded and supplying the estimated value and the predicted value of the symbol to a decoder for decoding. A context generator, a plurality of probability estimation memories storing probability estimation values, and storing predicted symbol and address information of the probability estimation memory for each context.
A plurality of context memories and an arithmetic decoding operation unit, and decodes the (i + 1) th symbol in the same cycle as the arithmetic decoding operation of the ith (i is an arbitrary natural number) symbol Decoding processing of the plurality of probability estimation memories, and reading processing of the plurality of context memories for decoding the (i + 2) th symbol, in parallel. . 8. Each of the plurality of probability estimation memories stores, at the same address, a current probability estimation value and a probability estimation value that has been updated after a predetermined situation has occurred. The decoding device according to claim 7. 9. A decoding apparatus for estimating a probability of occurrence of a decoded symbol from a state of a symbol series already decoded, and supplying the estimated value and a predicted value of the symbol to a decoder for decoding. A current probability estimate and a probability estimate after an update is performed in a predetermined situation are generated in parallel, and depending on the state of the decoder, the current probability estimate or the updated A decoding apparatus, wherein one of the probability estimation values is selected and supplied to the decoder. 10. A decoding device for estimating a probability of occurrence of a decoded symbol from a state of a symbol sequence already decoded, and supplying the estimated value and a predicted value of the symbol to a decoder for decoding. Decoding having a memory for storing the probability estimation value, and storing at the same address of the memory the current probability estimation value and the probability estimation value after being updated due to the occurrence of a predetermined situation. Device. 11. A decoding apparatus for estimating a probability of occurrence of a decoded symbol from a state (context) of a symbol sequence already decoded and supplying the estimated value and a predicted value of the symbol to a decoder for decoding. A context generating means, a probability estimating memory for outputting in parallel each of a current probability estimate, an updated probability estimate, and address information indicating an address at which the updated probability estimate is stored; First selecting means for selecting one of the current probability estimate and the updated probability estimate output in parallel to the probability estimation memory; a prediction symbol and an address of the probability estimation memory for each context; A context memory storing information; and an output of the context memory or the probability estimation memo as an address of the probability estimation memory. Output from the second selection means for selecting one of said address information indicating the address of probability estimation value updated is stored, the probability estimation value selected by the first selection means,
An arithmetic decoding unit that performs an arithmetic decoding operation using the predicted value (MPS) of the symbol output from the context memory. 12. Executing context generation processing, probability estimation memory read processing, context memory read processing, and arithmetic decoding operation in the same cycle to form a pipeline, thereby decoding one pixel in one cycle. The decoding device according to claim 11, wherein: 13. The current inferior symbol occurrence probability (Qe)
And the first future inferior symbol occurrence probability (next Qe1) that would be output if normalization processing occurred in encoding of the superior symbol (MPS), and the normality in encoding of the inferior symbol (LPS). Probability of the occurrence of the second inferior symbol in the future (next Qe2) that will be output if the conversion process occurs
In parallel with the encoding of the most significant symbol (MPS) or the least significant symbol (L
If the normalization process occurs in the coding of PS) and the next context is also the same, the first or second future lesser occurrence symbol (next Qe1, next Qe2) is selected and arithmetically performed. Supplying to an encoder and, if not applicable to the above case, selecting the current inferior symbol occurrence probability (Qe) and supplying the same to an arithmetic encoder. . 14. A process which is performed in advance for each of a first pixel to be decoded, a second pixel to be decoded, and a third pixel to be decoded, and a context that can be actually taken. Generating in parallel the inferior symbol occurrence probabilities (Qe) corresponding to each of the following; and selecting one of the inferior symbol occurrence probabilities (Qe) occurring in parallel according to the actual decoding result. Supplying the signal to an arithmetic decoder. 15. When generating the inferior symbol occurrence probability (Qe) corresponding to one context for the next pixel to be decoded, a predetermined symbol in addition to the current inferior symbol occurrence probability (Qe). The method according to claim 1, wherein the less probable symbol occurrence probabilities (next Qe) after the situation has been updated are generated in parallel, and one of them is selected according to the state and context of the arithmetic decoder. Item 15. The arithmetic decoding method according to Item 14. 16. An encoding method for predicting an encoded symbol based on a value of a reference pixel around the encoded symbol and encoding the prediction result, detects that both the encoded line and the reference line are white lines. In this case, the coding lines are collectively encoded with a larger number of symbols than when collectively encoding non-white lines, and the non-white lines are encoded symbols. Of the probability of occurrence, and an estimated probability estimate and a future probability estimate that would be obtained if a predetermined situation occurred and a predetermined parameter was updated were generated in parallel, respectively. ,
An encoding method, wherein either the current probability estimate or the updated probability estimate is selected according to an actual state, and encoding is performed using the selected probability estimate. 17. A facsimile device equipped with the encoding device according to any one of claims 1 to 5, or the decoding device according to any one of claims 6 to 12.