JP2001175798A - Floating binarization circuit and information code reader - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information code reader which can precisely read a recorded information code at high speed even in the label of low quality, which has thinning, and to provide a floating binarization circuit which is suitable for constituting the information code reader. SOLUTION: The output terminal of a comparator 10 binarizing an analog signal Ai with a follow-up signal TH as a threshold is pulled up by pull-up voltage Vpu which can arbitrarily be set by a data processing part 7 through a resistor R1. A follow-up signal generation part 11 generating the follow-up signal TH usually makes current flow via first routes R4 and D1 or second routes D2 and R5 in accordance with the signal level of the analog signal Ai and binarized signal Db obtained by binarizing the analog signal Ai by the comparator 10. When a control signal CL is in the high level and the binarized signal Db is in the high level, both routes are turned off and the waveform of the follow-up signal TH changes in accordance with the size of pull-up voltage Vpu.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a floating binarization circuit for binarizing an input signal with a tracking signal following the input signal as a threshold value, and a configuration using the floating binarization circuit. Further, the present invention relates to an information code reading device that irradiates light to an object to be read and receives reflected light to read an information code recorded on the object to be read.

[0002]

2. Description of the Related Art Heretofore, a light-emitting element such as a light-emitting diode emits light to irradiate an object to be read such as a bar code printed or adhered to a product or the like with light reflected from the object to be read. Is formed on a light-receiving sensor on which light-receiving elements are arranged, and an electric signal obtained by photoelectric conversion by the light-receiving sensor (hereinafter, referred to as “light-receiving signal”) is converted into a binary signal corresponding to either light or dark. 2. Description of the Related Art There is known an information code reading device that decodes an information code by performing a conversion process and performing a decoding process on a light and dark pattern in the binary signal.

In such an information code reading device, it is required that a light receiving signal obtained from a light receiving sensor can be properly binarized in accordance with an actual light / dark pattern of an information code in order to successfully decode data. As one of the binarization circuits for this purpose, for example, as shown in FIG. 8A, an analog signal Ai to be binarized is supplied to an inverting input terminal.
Is input, and the output terminal is connected to the power supply voltage VDD by the resistor R1.
Comparator 10 pulled up to (for example, + 5V)
And a tracking signal generator 11 for generating a tracking signal TH obtained by attenuating and delaying the input analog signal Ai, and applying the tracking signal TH to the non-inverting input terminal of the comparator 10. 106 are known.

In the floating binarization circuit 106, a follow-up signal generator 11 has a resistor R2 connected between the output terminal and the non-inverting input terminal of the comparator 10, one end connected to the non-inverting input terminal, and A resistor R3 whose end is grounded via a capacitor C1, a diode D1 whose cathode is connected to the non-grounded end side of the capacitor C1 and whose anode is connected to the inverting input terminal via a resistor R4, and whose anode is connected to the capacitor C1. A diode D2 connected to the non-ground end and having a cathode connected to the inverting input terminal via a resistor R5;
And Hereinafter, the current path including the diode D1 and the resistor R4 is referred to as a first path, and the diode D2
The current path including the resistor R5 and the resistor R5 is referred to as a second path. The output of the comparator 10 is configured by an open collector.

The floating binarizing circuit 10 constructed as described above
6, when the input analog signal Ai is lower than the signal level of the tracking signal TH and the binary signal Db output from the comparator 10 is at a high level (≒ VDD), the resistance R2 , R3, and a second path, a current flows from the output terminal side of the comparator 10 to the inverting input terminal side. As a result, an equivalent circuit of the tracking signal generator 11 is shown in FIG.
As shown in the figure, the first path (D
1, R4) is omitted, and the follow-up signal TH having a signal level obtained by dividing the voltage difference between the voltage level of the power supply voltage VDD and the signal level of the analog signal Ai by the combined resistors R1 + R2 and R3 + R5 is obtained. Will be generated. In addition, since the diode D2 is inserted in the second path, the follow-up signal TH is more than the analog signal Ai.
The signal level becomes at least as large as the forward voltage of the diode D2.

On the other hand, when the input analog signal Ai is higher than the signal level of the follow-up signal TH and the binary signal output from the comparator 10 is at a low level (≒ 0 V),
In the tracking signal generation unit 11, a current flows from the inverting input terminal side of the comparator 10 to the output terminal side in the current path including the first path, the resistor R3, and the resistor R2. As a result, as shown in FIG. 10B (however, the resistance R9 is disregarded), the equivalent circuit of the tracking signal generation unit 11 is such that the second path (R5, D2) indicated by a dotted line in the figure is omitted. , The voltage difference between the signal level of the analog signal Ai and the ground level,
A follow-up signal TH having a signal level divided by the combined resistor R4 + R3 and the resistor R2 is generated. Since the diode D1 is inserted in the first path, the follow-up signal TH has a signal level lower than the analog signal by at least the forward voltage of the diode D1.

However, since the capacitor C1 is included in any of the current paths, the generated follow-up signal TH is
The analog signal Ai has a delay corresponding to a time constant determined by the capacitance of the capacitor C1 and the other resistors R1 to R5. That is, the tracking signal TH generated by the tracking signal generation unit 11 has a lower maximum level and a higher minimum level than the analog signal Ai, as shown in FIG.
Further, the signal level changes slightly similarly to the analog signal Ai with a slight delay from the analog signal Ai.

Note that the 2 output from the comparator 10
The binarized signal Db is applied to the non-inverting input terminal, and a threshold obtained by dividing the power supply voltage VDD by a voltage dividing circuit including resistors R6 and R7 is applied to the inverting input terminal. The output terminal is shaped by the comparator 12 pulled up to the power supply voltage VDD by the resistor R8,
The binarized signal Do whose waveform has been shaped is input to the data processing unit 107 that performs a decoding process and the like.

[0009]

When a bar code is read by an information code reading device, the light receiving signal output from the light receiving sensor generally has a high signal level in a bar portion printed in black. Conversely, the signal level is low in the white printed space.

[0010] For example, when a low-quality label having blurring in printing or the like is read, the signal level of the light-receiving signal from the light-receiving sensor is increased in the blurred portion of the printing despite the bar portion. (Section K in FIG. 8B
reference). Then, in order for the information code reader to binarize the light receiving signal, the floating binarization circuit 10 described above is used.
6, the follow-up signal TH also follows a change in signal level due to such blurring of printing or the like, so that the analog signal Ai and the follow-up signal TH intersect at that part, and , The signal level of the binarized signal Db is inverted,
This causes so-called bar cracking.

On the other hand, as shown in FIG.
The output port Pc of the data processing unit 107 is connected to a connection portion (hereinafter, referred to as “connection point X”) between the diode D2 and the resistor R5 in the second path via the resistor R9, and the output port Pc is set to high impedance or Floating binary circuit 1 improved to control the signal level of follow-up signal TH by setting it to high level (power supply voltage level VDD)
06a is known.

That is, in the floating binary circuit 106a,
As is clear from the equivalent circuit shown in FIG. 10, when the output port Pc is set to high impedance, it can be considered that the resistor R9 is not connected, so that the configuration is completely the same as that of the floating binarization circuit 106 described above. On the other hand, when the output port Pc is at a high level, a current flows into the resistor R5 via the resistor R9, so that the potential of the connection point X increases.

As a result, as shown in FIG. 9B, the signal level of the follow-up signal TH is high when a current flows through the second path, that is, when the binary signal Db is at a high level (Db> Ai). Since the peak portion of the analog signal Ai caused by the blurring of the bar portion does not intersect with the follow-up signal TH, it is possible to prevent the blurring of the bar portion from being erroneously recognized as a space.

However, in this case, since the tracking signal TH is always held at a high signal level, such a tracking signal T
The binarized signal Db generated with H as a threshold has a thicker bar portion and a narrower space portion than the original information code. Then, the data processing unit 107 that decodes the binarized signal may fail in decoding, or may recognize that a nonstandard label has been read in some cases, and the decoding itself may not be performed. was there.

Also, the light receiving signal from the light receiving sensor is directly converted into an analog signal without binarization and converted into a data processing unit 1.
07, and the effect of blurring or the like is determined from the signal level, and binarization is considered. In this case, the inversion timing of the binarized signal and, consequently, the width of each level are accurately reproduced. For this purpose, it is necessary to increase the number of samples of the received light signal, and the load on the data processing unit 107 for processing the sampled data becomes heavy, and there is a problem that it takes time until a reading result is obtained.

The present invention has been made in order to solve the above problems.
An information code reading device capable of reading recorded information codes accurately and at high speed even with a low-quality label having blurring and the like, and a floating binarization suitable for configuring the information code reading device It is intended to provide a circuit.

[0017]

According to the first aspect of the present invention, a signal level of an analog signal to be binarized is generated by a voltage dividing means and a capacitor. When the binarized signal, which is the output of the comparator, is lower than the signal level of the following signal, the current flows through the first path in the voltage dividing means, and conversely, the analog signal is smaller than the following signal. , 2
If the binarized signal is at a high level, the second
Current flows through the path. However, a capacitor is connected between the follower signal extraction end and the first and second paths, and the capacitor is charged and discharged by a current flowing through the voltage dividing means. As a result, the following signal whose signal level changes according to the analog signal is delayed from the analog signal. In addition, since the first and second paths are both configured using diodes, when the binarized signal is at a low level, the first and second paths have a signal level higher than the analog signal by at least the forward voltage of the diode. When the value signal is at the high level, a follow-up signal having a signal level lower than that of the analog signal by at least the amount of the diode voltage in the forward direction is obtained.

When the potential on the cathode side of the diode in the second path is raised by the level shift means, the current is accordingly flowing through the second path, that is, when the binary signal is at the high level. The signal level of the tracking signal also shifts upward. Therefore, for example, in an analog signal representing a binary value of light and dark, a portion having a low signal level represents a dark portion of an information code (a bar portion of a barcode, etc.), and a portion having a high signal level represents a bright portion of the information code (a barcode) , Etc.), due to factors such as blurred printing,
Even if the signal level of the analog signal in the portion corresponding to the dark portion slightly increases, if the signal level of the following signal is increased by the level shift means, the signal is erroneously determined to be a bright portion of the information code, and so-called Bar cracking does not occur.

In particular, in the present invention, the pull-up voltage of the comparator output can be adjusted by the adjusting means, and the waveform of the follow-up signal when the binary signal is at a high level can be appropriately controlled. I have. That is, for example, if the voltage level of the pull-up voltage is set to be lower than the cathode potential of the diode in the second path, the diode in the second path is kept in the off state, so that the binary signal becomes high level. The follow-up signal generated at the time of (1) does not follow the analog signal, and is pulled up at a speed according to a time constant determined by the resistance of the portion other than the first and second paths of the voltage dividing means and the capacitance of the capacitor. The capacitor operates to be charged or discharged toward the voltage.

In particular, when the pull-up voltage is smaller than the signal level at which the analog signal and the following signal intersect when the binary signal changes from the low level to the high level,
While the binarized signal is at the high level, only discharging is performed in the capacitor, and accordingly, the signal level of the following signal continues to decrease. Then, when the binarized signal changes from the high level to the low level, the signal level at which the analog signal and the follow-up signal intersect decreases, and the high level of the binarized signal is terminated earlier, and this high level is terminated. The level period can be shortened (in other words, the low-level period of the binarized signal can be lengthened).

That is, according to the floating binarization circuit of the present invention, even when the signal level of the follow-up signal is raised by the level shift means, the pull-up voltage is appropriately set by the adjustment means, so that the binary value can be obtained. Since the high level period of the digitized signal can be adjusted to be shorter, it is possible to generate a binarized signal that accurately reproduces the light / dark pattern of the original information code represented by the analog signal.

Even if the absolute width of the bar portion or the ratio of the bar portion to the space portion is out of the standard to be satisfied by the information code due to printing blur or the like, the By appropriately adjusting the up-voltage and generating a binarized signal in which the width of the level corresponding to the bar portion is shortened by the amount corresponding to the printing blur, it is possible to correct the signal to conform to the standard.

The range of adjustment of the pull-up voltage by the adjusting means may be set to a voltage range lower than the cathode side potential of the diode on the second path shifted by the level shift means. desirable. With this setting, the diode in the second path can be reliably turned off, and the control can be reliably performed to the side where the width of the high level of the binarized signal becomes shorter.

When the pull-up voltage is adjusted by the adjusting means so that the diode on the second path is turned off,
Since the output terminal of the comparator is pulled up by this pull-up voltage, the high-level value of the binarized signal output by the comparator also changes with the change of the follow-up signal.

Therefore, the output terminal of the comparator is provided with a waveform shaping means for shaping the waveform of the output signal from the comparator using the divided voltage value of the pull-up voltage as a threshold voltage. It is desirable to output the binary signal shaped by the waveform shaping means.

That is, since the output of the comparator has a high level substantially equal to the pull-up voltage and a low level substantially equal to the ground level, the divided voltage value of the pull-up voltage is used as the threshold voltage of the waveform shaping means. The output waveform can always be correctly shaped.

Next, in the information code reading device according to the present invention, when the irradiating means irradiates the reading object with the irradiating light, the light receiving means receives the reflected light from the reading object and photoelectrically converts the reflected light. An electric signal having a signal level corresponding to the level is generated. Then, the binarizing means comprising a floating binarizing circuit according to any one of claims 1 to 3 converts the electric signal input from the light receiving means into a binary signal corresponding to one of light and dark. The decoding means decodes the light / dark pattern sequence represented by the binarized signal,
Read the information code recorded on the object to be read. Also,
When the decoding means fails to decode the light and dark pattern sequence, the setting changing means changes the settings of the level shift means and the adjusting means of the floating binarization circuit.

That is, in the information code reading apparatus according to the present invention, since the floating binarizing circuit according to any one of claims 1 to 3 is used as the binarizing means, a low quality label having blurring or the like can be used. The information code can be read accurately and at high speed, and even if the label is normally determined to be out of standard due to printing blur or the like, the light and shade represented by the binarized signal. The pattern sequence can be corrected so as to conform to the standard.

Also, even if decoding fails, the setting change means appropriately changes the settings of the level shift means and the adjustment means and changes the signal waveform of the follow-up signal, so that it can be flexibly adapted to various reading objects. In addition, it is possible to always suitably read the information code.

[0030]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram illustrating a schematic configuration of the information code reading device according to the embodiment. As shown in FIG. 1, the information code reading device 1 irradiates light to an object to be read, and reads a barcode printed or attached on the object to be read. In order to irradiate light, a light emitting circuit 2 as an irradiating means including a plurality of light emitting diodes and a driving circuit for emitting the light emitting diodes in accordance with an external exposure command Sd, and a light source to be read when the light emitting circuit 2 emits light. A light receiving circuit 4 is provided as a light receiving unit that receives light reflected by the object and captures image information representing a light and dark pattern image on the object to be read.

The light receiving circuit 4 includes a light receiving sensor in which light receiving elements are arranged in a line, an imaging lens for forming reflected light on the light receiving sensor, and image information which is taken into the light receiving sensor and photoelectrically converted. , And a sensor control circuit that generates a light receiving signal Ar by sequentially taking out the light. The light receiving signal Ar output from the light receiving circuit 4 has a low signal level in a portion corresponding to the light pattern (bar code space) of the light and dark pattern image, and has a low signal level in a portion corresponding to the dark pattern (bar code bar). Assume that the level is higher.

The information code reading device 1 also includes an amplifier circuit 5 for amplifying the light receiving signal Ar from the light receiving circuit 4 and an analog signal Ai obtained by amplifying the light receiving signal Ar by the amplifier circuit 5. A floating binarization circuit (hereinafter simply referred to as a “binarization circuit”) as binarization means for binarizing a tracking signal TH generated based on the analog signal Ai as a threshold value
6) and a data processing unit which takes in the binarized signal Do generated by the binarization circuit 6, executes decoding processing and the like, and decodes (decodes) an information code represented by a bar code. 7, a buzzer device 8 that sounds when the bar code is successfully decoded by the data processing unit 7, and an output circuit 9 for outputting the processing result of the data processing unit 7 to the outside.

As shown in FIG. 2, the amplifier circuit 5 includes a preamplifier circuit 5a and a main amplifier circuit 5b. The preamplifier circuit 5a, together with the resistors R11 and R12,
A light receiving signal Ar from the light receiving circuit 4 is applied to the inverting input terminal via a resistor R12, and a non-inverting input terminal is supplied from the data processing unit 7 to an inverting input terminal. The bias signal Sb to be applied is applied. In order to remove high frequency noise, a capacitor C11 connected in parallel with the resistor R11 is provided between the output terminal and the inverting input terminal of the operational amplifier 20, and the non-inverting input terminal is connected via the capacitor C12. Grounded.

The preamplifier circuit 5a thus configured
Inverts and amplifies the light receiving signal according to the difference from the bias signal Sb. Note that the bias signal Sb is appropriately set within a range of 0 V to 5 V (power supply voltage VDD) according to the state of the light receiving signal Ar. That is, the barcode is not always printed on a white background, and the reflectance changes greatly if the background is colored. Specifically, the light receiving circuit 4
The light receiving signal Ar output by the device has a high bias level waveform including a large DC component as shown in FIG. 3A when the reflectance of the underlying portion is high, while the reflectance of the underlying portion is low. When it is low, the waveform has a low bias level as shown in FIG. Therefore, if the light receiving signal Ar is simply amplified, the output of the amplifier circuit 5 is saturated when the bias level is high, and a binarized signal that accurately reflects the light / dark pattern of the bar code is generated. May not be possible. Therefore, an appropriate bias level is set by the bias signal Sb.

Next, the main amplifier circuit 5b includes resistors R21 and R21.
22 and an operational amplifier 22 configured as a well-known non-inverting amplifier circuit. The non-inverting input terminal is configured to apply a signal from the preamplifier circuit 5a. Also, a resistor array 24 is connected in series with a resistor R22 whose inverting input terminal is grounded so that the amplification factor of the main amplifier circuit 5b can be variably set. Further, the preamplifier circuit 5a
Similarly, to remove high frequency noise,
A capacitor C21 connected in parallel with the resistor R21 is provided between the output terminal and the inverting input terminal of No. 2 and a capacitor C22 connected in series between the resistor R22 and the resistor array 24. Is provided.

The main amplifying circuit 5b thus configured is
The signal from the preamplifier circuit 5a is connected to the resistors R21, R22,
And an amplification factor determined by the resistance value of the resistance array 24. Here, each resistor R constituting the resistor array 24
30 to R3n have different resistance values, respectively.
One end (hereinafter, referred to as “common end”) of each of the resistors R30 to R3n is commonly connected to the capacitor C22, and the other end (hereinafter, referred to as “individual end”) is connected to the output ports Pa0 to Pan of the data processing unit 7. Connected to each other.

However, as the output ports Pa0 to Pan, those which can be arbitrarily set to a low level (that is, a ground level) and a high impedance, respectively, are used. That is, the connected output port Pai (i
= 0 to n) is set to a high impedance.
Since i can be treated as equivalently not connected, the connected output port Paj (j = 0 to n)
Is the low level, the combined resistance value of all the resistors R3j becomes the resistance value of the entire resistor array 24.

That is, in the main amplifier circuit 5b, the output port P
By appropriately setting a0 to Pan, the amplification factor of the main amplifier circuit 5b can be set to various values. For example, the resistor array 24 is composed of nine resistors R30 to R38 (resistance values: 430 kΩ, 110 kΩ, 56 kΩ, 39 kΩ,
20kΩ, 16kΩ, 5.6kΩ, 3kΩ, 1.2k
Ω), by setting the output ports Pa0 to Pa8, as shown in the following [Table 1], it is possible to set 16 types of amplification factors having different magnifications by about 0.7. .

[0039]

[Table 1]

Next, a binarizing circuit 6 which is a main part of the present invention.
Will be described. However, the binarization circuit 6 in this embodiment is the same as the binarization circuit 10 described in the section of the prior art.
6A (see FIG. 9A), the same components are denoted by the same reference numerals, and the description thereof will be omitted. The following description focuses on portions having different configurations.

As shown in FIG. 4A, the binarizing circuit 6 in the present embodiment comprises a resistor R1 for pulling up the output terminal of the comparator 10, and a voltage dividing resistor R6 for generating the threshold value of the comparator 12. Instead of applying the power supply voltage VDD, the pull-up generated by the D / A converter in the data processing unit 7 via a well-known buffer circuit including an operational amplifier 14 whose output terminal and inverting input terminal are short-circuited. It is configured to apply an up voltage Vpu (2 to 3 V in the present embodiment). Other configurations are exactly the same as those of the binarization circuit 106a. Note that the tracking signal generator 11
Is the voltage dividing means of the present invention, the resistor R9 and the output port Pc to which the resistor R9 is connected are level shifting means, and the operational amplifier 14
And the output port Pp corresponds to the adjusting means.

In the binarization circuit 6 configured as described above,
When the output signal Db of the comparator 10 is at a low level, the operation is not related to the pull-up voltage Vpu (see FIG. 10B), so that the operation is exactly the same as that of the conventional binarization circuit 106a. When the output signal Db of the comparator 10 is at the high level, the operation differs depending on the setting of the output port Pc (high impedance / high level).

That is, first, when the output port Pc is set to high impedance, as shown in FIG. 5 (a), the resistor R9 can be treated as not being connected. Similarly to the circuit 106a, the signal level of the follow-up signal TH is higher than the signal level of the analog signal Ai by at least the forward voltage of the diode D2.

On the other hand, when the output port Pc is set to the high level (that is, the power supply voltage VDD), the voltage Vx at the connection point X (the cathode side of the diode D2) is set to the resistance R9,
The magnitude is larger than the power supply voltage VDD divided by R5. The voltage Vx at the connection point X is
1 is smaller than the charging voltage VC1, as shown in FIG. 5B, the connection point voltage Vc due to the high level of the output port Pc, as in the conventional binarization circuit 106b.
The signal level of the follow-up signal TH is also increased by the voltage rise of x.

Further, the connection point voltage Vx is set to the value of the capacitor C1.
Is higher than the charging voltage VC1, the diode D2 is turned off as shown in FIG.
1 and the signal level of the follow-up signal TH depend on the capacitance of the capacitor C1 and the combined resistance R1 + R2 + R3.
At a speed according to the time constant determined by the pull-up voltage Vpu.

That is, the output signal Db of the comparator 10
Signal T when the signal changes from low level to high level
When the pull-up voltage Vpu is lower than the signal level of H, as shown in FIG. 4B, the follow-up signal TH decreases toward the pull-up voltage Vpu. In addition,
In the present embodiment, when the output port Pc is set to a high level, the connection point voltage Vx is set to be higher than the pull-up voltage Vpu.

Therefore, the tracking signal TH and the analog signal A
Compared with i when the pull-up voltage Vpu is set to the power supply voltage VDD (= 5 V) as in the conventional device (see FIG. 9B), the signal intersects at a lower signal level, and the pull-up voltage Vpu
The lower the is, the lower the intersecting signal level.

When the pull-up voltage Vpu is set low as described above, the signal level of the output signal Db output from the output terminal of the comparator 10 composed of an open collector in the high-level section is equal to the charge of the capacitor C1. It will decrease with the voltage. For this reason, in the binarization circuit 6 of the present embodiment, the waveform of the output signal Db is shaped by the comparator 12, and the shaped binarized signal Db
o to the data processing unit 7.

In addition, since the comparator 12 generates the threshold voltage for waveform shaping based on the pull-up voltage Vpu, the output of the comparator 10 is always irrespective of the set value of the pull-up voltage Vpu. The waveform of the signal Db can be shaped without error.

As described above, the binarization circuit 6 not only binarizes the analog signal Ai from the amplifier circuit 5 using the tracking signal TH that follows the analog signal Ai, and supplies the binary signal to the data processing unit 7. By changing the setting of the output port Pc and the pull-up voltage Vpu as appropriate to change the waveform of the follow-up signal TH, erroneous binarization is performed following the peak of the analog signal Ai based on blurred printing or the like. And the width of the high level / low level of the binarized signal Do can be appropriately adjusted.

Next, the data processing unit 7 includes a CPU, an RO
An output port Pd for outputting an exposure command Sd to the light emitting circuit 2; a preamplifier circuit 5;
output port P for outputting a bias signal Sb to a
b, output ports Pa0 to Pan for setting the resistance value of the resistance array 24 of the main amplifier circuit 5b, an output port Pc for adjusting the voltage Vx at the connection point X of the binarization circuit 6, and the binarization circuit 6 Signal level of the output port Pp for setting the pull-up voltage Vpu, the input level Pi for inputting the binary signal Do from the binarization circuit 6, and the binary signal input from the input port Pi , A one-chip microcomputer having a bias signal Sb output from output ports Pb and Pp, a D / A converter for generating a pull-up voltage Vpu, and the like.

Here, the adjustment processing executed by the data processing section 7 and the decoding processing as decoding means will be described. First, the adjustment process is performed by the light emitting circuit 2 and the light receiving circuit 4.
Since the performance of the light-emitting element and light-receiving element that compose the data varies from product to product, this is performed to correct this and suppress the variation from product to product.A standard bar code is read, and the analog signal at that time is read. The output ports Pa0 to Pan are set so that the amplitude of Ai falls within a preset range.
Set.

Next, the decoding process is a process executed when a bar code is read. First, by setting output ports Pb, Pc and Pp in accordance with a preset exposure table, the bias signal Sb is connected. The voltage Vx and the pull-up voltage Vpu at the point X are set, and an exposure command Sd is output, so that the light emitting circuit 2 emits light during a preset exposure time.

After that, the light receiving signal Ar output from the light receiving circuit 4 is amplified and binarized by the amplifying circuit 5 and the binarizing circuit 6, and the binarized signal Do is subjected to data processing via the input port Pi. Take it into the unit 7. At this time, the duration of the high level of the binarized signal Do, that is, the bar width of the bar code is measured by a timer which starts at the rising edge of the binarized signal Do and stops at the falling edge, and The duration of the low level, that is, the space width of the bar code, is measured by a timer that starts at the rising edge of the digitization signal Do and stops at the falling edge. Based on the bar width and the space width converted into digital data in this way, what kind of information code the bar code represents is decoded (decoded).

When the decoding is successful, the buzzer device 8 is caused to sound and the output circuit 9 outputs
The contents decoded by decoding are output to the outside. on the other hand,
If the decoding fails, the settings of the output ports Pb, Pc, Pp are changed according to the above exposure table,
The same processing as described above is repeatedly executed until decoding succeeds. Note that, according to the exposure table, the output port P
The process of changing the settings of c and Pp corresponds to the setting change means of the present invention.

As described above, in the information code reading device 1 of the present embodiment, the bias signal Sb for amplifying the light receiving signal Ar and the analog signal Ai can be set by appropriately setting the output ports Pb, Pc and Pp. Can be adapted to the state of the barcode to be read (the color of the background or the quality of printing) used for binarizing the following.

In the information code reader 1 of this embodiment, when the signal level of the tracking signal TH is shifted to the higher side, the tracking signal Tpu is pulled up by the pull-up voltage Vpu.
H and the signal level at which the analog signal Ai crosses, that is,
The output signal Db of the comparator 10 (that is, the binary signal D
The timing at which o) is inverted, that is, the high / low level width of the binarized signal Do can be adjusted.

Therefore, according to the information code reading device 1 of the present embodiment, not only can the bar break due to blurring of printing or the like be prevented, but also the high level / low level of the binarized signal Do is always set to a normal level conforming to the standard. Can be width. Also, as described above, the high level /
Since the width of the low level can be appropriately adjusted, even when the width of the bar portion is wider than the standard due to printing bleeding or the like, the binarized signal Do corrected to conform to the standard. Can be generated, and it is possible to improve the usability of the apparatus because it is not impossible to read the data because it is out of the standard.

The information code reading device 1 of the present embodiment
In the above, the bias signal Sb of the preamplifier circuit 5a and the pull-up voltage Vpu of the binarization circuit 6 are set using a D / A converter provided in the data processing unit 7, and
The adjustment of the amplification factor of the main amplifier circuit 5b and the connection point voltage Vx of the binarization circuit 6 are performed by setting the output ports Pa0 to Pan and Pc, so that various settings can be realized with an extremely simple configuration. Can be reduced in size.

In the present embodiment, the amplification factor of the main amplifier circuit 5b is set in the adjustment process and is not changed during the decoding process. However, the settings of the output ports Pa0 to Pan are also set in the exposure table. A configuration may also be adopted in which the amplification factor of the main amplifying circuit 5b is variable during decoding.

In this embodiment, the preamplifier 5a
The bias signal to be supplied to the operational amplifier 20 is set in accordance with the exposure table. However, as shown in FIG. 6, the operational amplifier 21, the diode D4, and the resistor R4
1, a well-known peak hold circuit constituted by R42, detects the peak level of the light receiving signal Ar, and takes it into the data processing unit 7 via the input port Pr.
The data may be converted into digital data using an A / D converter provided in the data processing unit 7, and the bias signal Sb may be set according to the digital data representing the peak level of the light receiving signal Ar. In this case, once the peak level can be read, after that, even if decoding of the information code fails, the bias signal Sb
Need not be changed, the number of combinations of settings in the exposure table can be reduced, and the decoding of the information code can be completed more quickly.

Further, in this embodiment, the pull-up voltage Vpu in the binarization circuit 6 is generated by the D / A converter in the data processing unit 7, but the D / A converter In the case where the circuit is not provided, or when it is desired to omit the D / A converter and reduce the size of the data processing unit 7 and thus the entire device, as shown in FIG. 7A, the resistors R51 and R52 are used.
And a resistor R53, a voltage dividing circuit is formed. Similarly to the resistor array of the main amplifier circuit 5b, individual ends of the resistors R51 and R52 forming the resistor array are provided in the data processing unit 7. Connect to output ports Pq1 and Pq2,
The voltage level of the pull-up voltage Vpu may be changed by setting the output ports Pq1 and Pq2.

In this embodiment, the pull-up voltage V
Although a buffer circuit configured using the operational amplifier 14 is used to supply pu, if it is necessary to control the pull-up voltage Vpu over a wider range, FIG.
, A transistor TR whose collector is connected to the power supply voltage VDD, whose emitter is connected to the output terminal of the operational amplifier 14, and whose base is connected to the output port Px of the data processing unit 7 are added.
Normally, the pull-up voltage Vpu output from the D / A conversion output of the data processing unit 7 is supplied via the buffer circuit including the operational amplifier 14 by turning off the transistor TR by setting the output port Px to low level, When a voltage higher than the control range is applied, the output port Px is set to the high level to turn on the transistor TR, so that the maximum pull-up voltage Vpu substantially equal to the power supply voltage VDD may be supplied. .

In this case, however, in order to prevent an excessive current from flowing into the operational amplifier 14 when the transistor TR is turned on, it is necessary to connect a diode D3 having a forward current source to the output terminal of the operational amplifier 14. There is. Also, as shown in FIG. 7C, in FIG. 7B, an analog switch 1 is used instead of the transistor TR.
6, the output of the operational amplifier 14 or the power supply may be connected to the supply line of the pull-up voltage Vpu according to the signal level of the output port Py. In this case, unlike the case of FIG. 7B, the diode D3 can be omitted.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of an information code reading device.

FIG. 2 is a circuit diagram illustrating a detailed configuration of an amplifier circuit.

FIG. 3 is an explanatory diagram showing a function of a preamplifier circuit.

FIG. 4 is a circuit diagram illustrating a detailed configuration of a binarization circuit.

FIG. 5 is an equivalent circuit for explaining the operation of the binarization circuit.

FIG. 6 is a circuit diagram illustrating another configuration of the preamplifier circuit.

FIG. 7 is a circuit diagram illustrating another configuration for supplying a pull-up voltage.

FIG. 8 is a circuit diagram illustrating a configuration of a conventional binarization circuit.

FIG. 9 is a circuit diagram illustrating another configuration of a conventional binarization circuit.

FIG. 10 is an equivalent circuit for explaining the operation of a conventional binarization circuit.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Information code reader, 2 ... Light emitting circuit, 4 ... Light receiving circuit, 5 ... Amplifier circuit, 5a ... Preamplifier circuit, 5b ... Main amplifier circuit, 6 ... Binarization circuit, 7 ... Data processing part, 8 ... Buzzer device 9, 9 output circuit, 10, 12 comparator, 11
... Follow-up signal generation unit, 14, 20, 21, 22 ... Op amp, 16 ... Analog switch, 24 ... Resistor array, C
1, C11, C12, C21, C22 ... capacitor, D
1 to D4: diode, Pa0 to Pan, Pb, Pc, P
d, Pp, Px, Py: output port, Pi: input port, R1 to R9, R11, R12, R21, R22, R
30 to R3n, R41, R51 to R53 ... resistance, TR ...
Transistor

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kunihiko Ito 50 Kojiri-cho, Hittsugi-cho, Kariya-shi, Aichi F-term in DENSO ELEX Co., Ltd. 5B072 AA01 AA02 CC24 DD02 FF09 5D044 CC08 FG06 FG16

Claims (4)

[Claims] An analog signal representing two levels of light and dark is applied to an inverting input terminal, and a comparator having an open collector output terminal pulled up and a voltage difference generated between the output terminal and the inverting input terminal of the comparator are separated. A first path in which a diode for flowing a current from the inverting input terminal to the output terminal is connected between the output end of the tracking signal that is the divided voltage output and the inverting input terminal; A voltage dividing means having a second path to which a diode for flowing a current toward the inverting input terminal is connected; and a voltage dividing means connected between the extraction end and the first and second paths,
A capacitor for delaying the follow-up signal whose signal level changes in accordance with the analog signal by being charged / discharged by a current flowing through the voltage dividing means from the analog signal; and a cathode-side potential of a diode in the second path. Level shift means for shifting the signal level of the following signal by adjusting the following signal, wherein the following signal is provided to a non-inverting input terminal of the comparator as a threshold value for binarizing the analog signal. An applied floating binarization circuit, comprising an adjusting means for adjusting a pull-up voltage for pulling up an output terminal of the comparator. 2. The adjustment range of the pull-up voltage adjusted by the adjustment unit is set to a voltage range lower than the cathode side potential of the diode of the second path shifted by the level shift unit. Claim 1
A floating binarization circuit according to claim 1. 3. The output terminal of the comparator is provided with a waveform shaping means for shaping a waveform of an output signal from the comparator using a divided value of the pull-up voltage as a threshold voltage. 3. The floating binarization circuit according to claim 1 or 2. 4. An irradiating means for irradiating an object to be read with irradiation light, and a light receiving means for receiving reflected light from the object to be read and performing photoelectric conversion to generate an electric signal having a signal level corresponding to the amount of received light. Binarizing means for converting an electric signal input from the light receiving means into a binary signal corresponding to one of light and dark; and a light / dark pattern sequence in the binarized signal taken in through the binarizing means. 4. An information code reading apparatus comprising: decoding means for decoding to read an information code recorded on the object to be read; and wherein the binarizing means comprises: And a setting change means for changing settings of the level shift means and the adjustment means of the floating binarization circuit when the decoding means fails to decode the light and dark pattern sequence. An information code reading device, comprising: