JP2001144213A - Method for manufacturing semiconductor device and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance reliability of electrical connection between a semiconductor device and a resin printed board by relaxing strain between them. SOLUTION: Major surface of a semiconductor substrate 1 is coated with sealing resin 11 including the interior of grooves 10 and solder bumps 12 are formed on the upper surface of metal posts 8. Subsequently, the semiconductor substrate 1 and the sealing resin 11 are diced along dividing regions 9 to produce individual semiconductor devices where the major surface and the side faces of the semiconductor substrate 1 are covered with the sealing resin 11. According to the method, difference in the coefficient of thermal expansion can be reduced between the semiconductor device and the resin printed board.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device manufacturing method and a semiconductor device technology, and more particularly to a technology effective when applied to a semiconductor device packaging technology.

[0002]

2. Description of the Related Art As electronic devices become smaller and lighter, semiconductor device packages are also required to be thinner and smaller and lighter. CSP (Chip Size Package) is a general term for packages that are equal to or slightly larger than the size of a semiconductor chip. The CSP can be reduced in size and weight, and can reduce the internal wiring length. It has been put to practical use as a package structure that can reduce the amount of light.
There are various methods for manufacturing a CSP, but it is common to cut a semiconductor chip from a semiconductor wafer, mount the semiconductor chip on a wiring board equivalent to or slightly larger than the semiconductor chip, and seal the resin in that state. It is a target.

On the other hand, as another manufacturing technique of such a CSP, there is a wafer process package (Wafer Process Pack).
age; hereinafter abbreviated as WPP) technology. This technology is
This is a technique in which a plurality of semiconductor chips formed on a semiconductor wafer through a wafer process are collectively sealed with a resin in a state of a semiconductor wafer, and then individual semiconductor devices are cut out from the semiconductor wafer. In this technology, the manufacturing process can be simplified, the manufacturing cost can be reduced, and the CSP
Has an excellent feature that it can be significantly reduced in size.

[0004] This type of technology is described, for example, in Nikkei BP, February 1, 1999, "Nikkei Microdevice February 1999", p. 56, and a CSP for assembling a package in a wafer process. In a state in which individual semiconductor devices are cut out from a semiconductor wafer, the cross section has a structure in which a sealing resin is overlapped on a main surface of a semiconductor chip.

[0005]

However, in this WPP, after a plurality of semiconductor chips on a semiconductor wafer are collectively resin-sealed, individual semiconductor chips are cut out from the semiconductor wafer. The back surface is not resin-sealed. For this reason, there is a problem that improvement in package characteristics such as moisture resistance and light shielding properties of the semiconductor device is hindered. In addition, since the sealing resin only overlaps the main surface of the semiconductor chip, the adhesiveness between the semiconductor chip and the sealing resin is deteriorated, and the semiconductor chip is peeled off due to bending of the semiconductor chip. In this case, the solder connection to the outside of the semiconductor chip may be broken, or the reliability of resin sealing may be reduced.

Further, in WPP, the mechanical properties of the semiconductor device depend on the semiconductor chip because the thickness of the sealing resin is smaller than that of the semiconductor chip. Therefore, since the distortion due to the difference in the coefficient of thermal expansion between the semiconductor device and the resin substrate outside the semiconductor device made of glass epoxy or the like cannot be reduced, the mechanical reliability of the solder of the external connection portion of the semiconductor device cannot be reduced. Decrease.

An object of the present invention is to provide a technique capable of improving the moisture resistance reliability of a package of a semiconductor device and the effect of reinforcing a connecting post to the outside.

It is another object of the present invention to provide a technique for improving the electrical connectivity between the semiconductor device and an external substrate.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) In the semiconductor device of the present invention, a plurality of semiconductor chips formed on a semiconductor wafer through a wafer process are collectively sealed with a resin in a state of a semiconductor wafer, and then cut out from the semiconductor wafer. A semiconductor device in which a part or the whole of a side surface of a semiconductor substrate is covered with a sealing resin.

(2) In the semiconductor device of the present invention, a semiconductor element is formed on a main surface of a semiconductor substrate, the main surface and side surfaces of the semiconductor substrate are covered with a sealing resin, and the semiconductor substrate is exposed on a back surface. Things.

(3) In the semiconductor device according to the present invention, after the main surface of the semiconductor substrate and the side surface of the semiconductor substrate are covered with a sealing resin, the back surface of the semiconductor substrate is polished, and the entire surface of the side surface of the semiconductor substrate is polished. In a resin-sealed shape.

(4) The method of manufacturing a semiconductor device according to the present invention comprises:
It includes the following steps.

(A) A semiconductor wafer having a plurality of chip forming regions partitioned by divided regions, wherein each of the plurality of chip forming regions has a plurality of semiconductor elements and a plurality of bonding pads is prepared. (B) forming a conductor electrically connected to each of the plurality of bonding pads in the chip forming region; (c) forming a groove in the divided region; and (d).
Forming a sealing insulating film on the main surface of the semiconductor wafer including the inside of the groove, and (e) cutting the semiconductor wafer along the groove to form the conductor, Forming a plurality of semiconductor chips in which a part of the insulating film is formed on a side surface.

(5) The method of manufacturing a semiconductor device according to the present invention
It includes the following steps.

(A) A semiconductor wafer having a plurality of chip forming regions partitioned by divided regions, wherein each of the plurality of chip forming regions has a plurality of semiconductor elements and a plurality of bonding pads is prepared. (B) forming a conductor electrically connected to each of the plurality of bonding pads in the chip forming region; (c) forming a groove in the divided region; and (d).
Forming a sealing insulating film on the main surface of the semiconductor wafer including the inside of the groove, and (e) polishing the back surface of the semiconductor wafer to form the sealing insulating film formed in the groove on the semiconductor wafer. Exposing the back surface of the semiconductor wafer from the bottom surface,
(F) forming a plurality of semiconductor chips in which the conductor portion is formed by cutting the semiconductor wafer along the groove, and a part of the sealing insulating film is formed on a side surface;

According to the above steps (4) and (5), the sealing resin covers the main surface and the side surfaces of the semiconductor substrate, so that the adhesive strength between the sealing resin and the semiconductor substrate is increased. Therefore, peeling of the sealing resin and the semiconductor substrate can be prevented, and for example, the moisture resistance reliability of the semiconductor substrate can be improved, and the post for connection to the outside can be reinforced.

Further, the post for connection to the outside is
The semiconductor device is held by a sealing resin having good adhesion to the semiconductor substrate, and the mechanical properties of the semiconductor device are close to those of the sealing resin. Therefore, the semiconductor device and the resin printed board on which the semiconductor device is mounted are mounted. In addition, distortion due to the difference in thermal expansion coefficient can be reduced, and the reliability of electrical connection can be improved.

Further, according to the step (5), since the side surfaces of the semiconductor substrate are completely covered with the sealing resin and reinforced, the mechanical strength of the semiconductor device is increased. Therefore, it is possible to form the solder bumps in the state of the semiconductor wafer before cutting the semiconductor substrate and dividing the semiconductor substrate into individual semiconductor chips, thereby improving the production efficiency of the thin wafer level CSP. it can.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, members having the same functions are denoted by the same reference numerals, and the repeated description thereof will be omitted.

(Embodiment 1) In Embodiment 1, the present invention is applied to a DRAM included in a small and portable electronic device such as a portable telephone, a portable personal computer, or a portable information processing device. (Dynamic Random
Access Memory), SRAM (Static Random Access Me)
mory) or CSP used for microcomputer
A case where the present invention is applied to a method of manufacturing a semiconductor device of a die type will be described.

FIG. 1A is a cross-sectional view showing an example of a semiconductor device manufactured according to the first embodiment, and FIG.
FIG. 2 is a partially cutaway perspective view of the semiconductor device.

Semiconductor substrate 1 is made of, for example, silicon single crystal and has, for example, a MISFET (Meta
l Insulator Semiconductor Field Effect Transistor
) Etc. and a plurality of wiring layers 2
Is a semiconductor chip formed by cutting the semiconductor wafer on which is formed in the divided region.

The wiring layer 2 is made of, for example, aluminum, aluminum-copper alloy or aluminum-silicon-copper alloy. This wiring layer 2 is protected by the insulating film 3.

The insulating film 3 is made of, for example, an organic film such as polyimide, a silicon nitride film, or a silicon oxide film. An opening 4 is formed in the insulating film 3, and the wiring layer 2 and the wiring layer 5 formed on the upper surface of the insulating film 3 are electrically connected to each other through the opening 4. The wiring layer 5 is made of, for example, copper or a copper alloy.

The wiring layer 5 is a wiring for rearranging the bonding pad, and is used for setting the position of the connection terminal with the outside to the metal post 8. The surface of the wiring layer 5 is covered with a surface protection film 6 made of an organic film such as polyimide. In this case, for example, it is possible to improve the ability to block α rays.

An opening 7 is formed in a part of the surface protection film 6 so that a part of the wiring layer 5 is exposed. The wiring part exposed from the opening 7 forms a bonding pad. The bonding pad is an electrode for extracting an electrode of the semiconductor element or circuit formed on the semiconductor chip to the outside. Further, a solder bump 12 is electrically connected to the bonding pad via a metal post 8. The metal post 8 is made of, for example, copper. The solder bumps 12 are made of, for example, gold or lead-tin alloy solder.

The sealing resin (sealing insulating film) 11 also covers the side wall of the semiconductor substrate 1, and has excellent adhesion to the semiconductor substrate 1 due to the anchor effect of biting with the semiconductor substrate 1. . Therefore, the moisture resistance reliability of the semiconductor substrate 1 and the wiring layer 2 is improved, and the metal posts 8 are formed.
Increases the reinforcing effect. The sealing resin 11 is made of an epoxy resin.

FIG. 2 is a sectional view showing an example of a state in which the semiconductor device manufactured according to the first embodiment is mounted on a resin printed board 13. The metal post 8 is held by a sealing resin 11 having good adhesion to the semiconductor substrate 1.
Since the mechanical properties of the semiconductor device are close to those of the encapsulating resin 11, even if a distortion due to a difference in thermal expansion coefficient occurs between the semiconductor device and the resin printed board 13 having the connection pads 14, the solder bump Since the distortion of No. 12 can be suppressed, the reliability of the electrical connection can be improved.

Next, a method of manufacturing the semiconductor device according to the first embodiment will be described with reference to FIGS.

First, as shown in FIG.
A wiring layer 2 is formed on a main surface of a semiconductor substrate 1 which is a semiconductor wafer having a plurality of semiconductor elements such as FETs formed on the main surface. Subsequently, an insulating film 3 is formed on the main surface of the semiconductor substrate 1, and an opening 4 reaching the wiring layer 2 is formed in the insulating film 3. The opening 4 is usually used also as a bonding pad, but the present invention does not necessarily require an opening area that can be used as a bonding pad.

Next, as shown in FIG. 4, a wiring layer 5 is formed on the surface of the insulating film 3 including the inside of the opening 4. The wiring layer 5 is formed by sequentially depositing chromium, copper, and chromium by a sputtering method, and processing the laminated film by photolithography and etching. The wiring layer 5 is used for rearranging the position of the connection terminal to the outside from the opening 4 to an arbitrary position. The wiring layer 5 is formed by depositing, for example, chromium or titanium or the like on the surface of the insulating film 3 including the inside of the opening 4 by a sputtering method to form a seed film, and then plating copper or nickel by a plating method. It may be formed by depositing.

Next, as shown in FIG. 5, a surface protective film 6 is deposited on the main surface of the semiconductor substrate 1. Subsequently, an opening 7 reaching the wiring layer 5 is opened at a terminal formation position on the main surface of the surface protective film 6, and then the wiring layer 5 and a solder bump 12 described later are passed through the opening 7. Metal posts 8 for electrical connection are formed. This metal post 8
Is formed, for example, by depositing copper by a plating method and then processing by etching. Further, the surface protective film 6 also has an effect of flattening the underlayer of a seed film deposited before forming copper to be the metal posts 8 by plating.

Next, as shown in FIG. 6, a groove 10 having a width of, for example, about 100 μm is formed in the divided region 9 on the main surface of the semiconductor substrate 1 by dicing.

Next, as shown in FIG. 7, a sealing resin 11 is applied on the main surface of the semiconductor substrate 1 including the inside of the groove 10 so that the upper surface of the metal post 8 is exposed.

Next, as shown in FIG. 8, a solder bump 12 is connected to the exposed upper surface of the metal post 8. The solder bumps 12 are formed by printing a solder paste using, for example, a metal mask and heating the solder paste.

Subsequently, the semiconductor substrate 1 and the sealing resin 1
1 by dicing and dividing,
The semiconductor device shown in (a) and (b) is substantially completed.

In the semiconductor device shown in the first embodiment, since the sealing resin 11 covers the main surface and the side surfaces of the semiconductor substrate 1, the adhesive strength between the sealing resin 11 and the semiconductor substrate is increased. Therefore, peeling of the sealing resin 11 and the semiconductor substrate 1 can be prevented, and for example, the moisture resistance reliability of the semiconductor substrate 1 can be improved and the metal posts 8 for connection to the outside can be reinforced. That is, a plurality of semiconductor chips formed on a semiconductor wafer through a wafer process are collectively resin-sealed in the state of the semiconductor wafer, and then the WPP technique of cutting individual semiconductor devices from the semiconductor wafer is used. A highly reliable semiconductor device can be manufactured.

Further, since the semiconductor device shown in the first embodiment has a shape in which the semiconductor substrate 1 is exposed on the back surface, the semiconductor device has an excellent heat radiation effect, and the heat radiation fins can be directly attached to the exposed semiconductor substrate. Heat can be dissipated effectively.

(Embodiment 2) In the method of manufacturing a semiconductor device according to Embodiment 2, the back surface of the semiconductor substrate 1 of the semiconductor device described in Embodiment 1 is polished, and the sealing deposited inside the groove 10 is formed. The stopper resin is exposed from the bottom surface of the groove 10 to the back surface of the semiconductor substrate 1. Other members and steps are the same as in the first embodiment. Therefore,
A description of those similar members and steps will be omitted.

FIG. 9A is a cross-sectional view showing an example of a semiconductor device manufactured according to the second embodiment, and FIG.
FIG. 2 is a partially cutaway perspective view of the semiconductor device.

Since the semiconductor substrate 1 and the sealing resin 11 are both back-polished, the semiconductor device manufactured according to the second embodiment has a small thickness of the semiconductor substrate 1 and the sealing resin 11. Are completely covered on the side surfaces of the semiconductor substrate 1. Since the thickness of the semiconductor substrate 1 is small, the mechanical properties of the semiconductor device described in the second embodiment are closer to the sealing resin than those of the semiconductor device described in the first embodiment.

FIG. 10 is a sectional view showing an example of a state in which the semiconductor device manufactured according to the first embodiment is mounted on the resin printed circuit board 13. Since the mechanical properties of the semiconductor device described in the second embodiment are closer to the sealing resin 11 than the mechanical properties of the semiconductor device described in the first embodiment, the semiconductor device includes the semiconductor device and the connection pads 14. Even when distortion due to a difference in thermal expansion coefficient between the resin printed circuit board 13 and the resin printed circuit board 13 occurs, the distortion of the solder bumps 12 can be suppressed more than in the semiconductor device described in the first embodiment. It can be improved over the semiconductor device described in Embodiment 1.

Next, a method of manufacturing the semiconductor device according to the second embodiment will be described with reference to FIG.

The method of manufacturing the semiconductor device according to the second embodiment is the same as the method of manufacturing the semiconductor device of the portable device 1 up to the steps shown in FIGS.

Thereafter, as shown in FIG. 11, the back surface of the semiconductor substrate 1 is polished, and the thickness of the semiconductor substrate 1 is set to, for example, about 30 μm to 250 μm. At this time, the groove 1
The sealing resin 11 deposited inside the semiconductor substrate 1 has a shape exposed from the bottom surface of the groove 10 to the back surface of the semiconductor substrate 1.

Subsequent steps are the same as the steps after FIG. 8 in the first embodiment.

When the material of the semiconductor substrate is, for example, silicon single crystal and the plate thickness is 250 μm or less, the semiconductor substrate may be broken in the step of forming solder bumps. The semiconductor device manufactured by the method has high mechanical strength because the side surface of the semiconductor substrate 1 is completely covered with the sealing resin 11 and reinforced. Therefore, it is possible to form the solder bumps in the state of the semiconductor wafer before the semiconductor substrate 1 is cut at the division region 9 and divided into individual semiconductor chips,
The production efficiency of the CSP at the thin wafer level can be improved.

FIG. 12 is a sectional view showing a state where a plurality of the semiconductor devices shown in the second embodiment are mounted on the resin printed circuit board 13. Since the semiconductor devices 15, 16, 17, and 18 are electrically insulated by the sealing resin 11, respectively, they can be mounted in a state where they are in contact with each other without leaving a space between the semiconductor devices. The mounting density of the semiconductor device on the resin printed board 13 can be improved.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. Needless to say, it can be changed.

[0052]

The effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.

(1) Since the peeling of the sealing resin and the semiconductor substrate can be prevented, the moisture resistance of the semiconductor device can be improved, and the reinforcing effect of the external connection post can be enhanced.

(2) The difference in the coefficient of thermal expansion between the semiconductor device and the resin printed circuit board on which the semiconductor device is mounted is reduced, and the distortion generated in the solder bumps at the external connection portions of the semiconductor device is reduced. The reliability of electrical connection between the semiconductor device and the resin substrate can be improved.

(3) Since the semiconductor device is reinforced with a sealing resin, solder bumps are formed in the state of the semiconductor wafer before being divided into individual semiconductor chips without breaking the semiconductor wafer by mechanical stress. can do.

[Brief description of the drawings]

FIG. 1A is a sectional view of a main part showing an example of a semiconductor device manufactured according to a first embodiment of the present invention, and FIG. 1B shows an example of a semiconductor device manufactured according to the first embodiment; It is a partially broken perspective view.

FIG. 2 is a fragmentary cross-sectional view showing an example of a state in which the semiconductor device manufactured in Embodiment 1 is mounted on a resin printed board.

FIG. 3 is an essential part cross sectional view showing an example of a manufacturing method of the semiconductor integrated circuit device of Embodiment 1 in the order of steps;

FIG. 4 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 3;

5 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 4;

6 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 5;

7 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 6;

8 is a fragmentary cross-sectional view of the semiconductor integrated circuit device during a manufacturing step following that of FIG. 7;

FIG. 9A is a sectional view of a main part showing an example of a semiconductor device manufactured according to a second embodiment of the present invention, and FIG. 9B is an example of a semiconductor device manufactured according to the second embodiment; It is a partially broken perspective view.

FIG. 10 is a fragmentary cross-sectional view showing an example of a state where the semiconductor device manufactured in the second embodiment is mounted on a resin printed board;

FIG. 11 is a fragmentary cross-sectional view showing one example of the method for manufacturing the semiconductor integrated circuit device of the second embodiment.

FIG. 12 is an essential part cross-sectional view showing one example of a state in which a plurality of semiconductor devices manufactured in Embodiment 2 are mounted on a resin printed board;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Wiring layer 3 Insulating film 4 Opening 5 Wiring layer 6 Surface protective film 7 Opening 8 Metal post 9 Dividing area 10 Groove 11 Sealing resin 12 Solder bump 13 Resin printed board 14 Connection pad 15 Semiconductor device 16 Semiconductor Device 17 Semiconductor device 18 Semiconductor device

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 21/301 H01L 21/78 A 21/60 21/92 602F 23/29 604B 23/31 604S 604E 23 / 30 DF term (reference) 4M109 AA01 BA07 CA04 DB17 5F061 AA01 BA07 CA04

Claims (6)

[Claims] 1. A semiconductor wafer having a plurality of chip forming regions partitioned by divided regions, wherein each of the plurality of chip forming regions has a plurality of semiconductor elements and a plurality of bonding pads. (B) forming a conductor portion electrically connected to each of the plurality of bonding pads in the chip formation region; (c) forming a groove portion in the divided region;
(D) a step of forming a sealing insulating film on the main surface of the semiconductor wafer including the inside of the groove, and (e) cutting the semiconductor wafer along the groove to form the conductor. Forming a plurality of semiconductor chips in which a part of the sealing insulating film is formed on a side surface. 2. (a) A semiconductor wafer having a plurality of chip forming regions partitioned by divided regions, wherein each of the plurality of chip forming regions has a plurality of semiconductor elements and a plurality of bonding pads. (B) forming a conductor portion electrically connected to each of the plurality of bonding pads in the chip formation region; (c) forming a groove portion in the divided region;
(D) forming a sealing insulating film on the main surface of the semiconductor wafer including the inside of the groove, and (e) polishing the back surface of the semiconductor wafer to remove the sealing insulating film formed in the groove. Exposing the semiconductor wafer from the bottom surface of the groove to the back surface of the semiconductor wafer; and (f) cutting the semiconductor wafer along the groove to form the conductor portion, and a part of the sealing insulating film is formed on a side surface. Forming a plurality of semiconductor chips formed in the semiconductor device. 3. The method for manufacturing a semiconductor device according to claim 1, wherein solder bumps are electrically connected to terminal positions on a main surface of the semiconductor wafer before forming the plurality of semiconductor chips. A method for manufacturing a semiconductor device, comprising the steps of: 4. A semiconductor device having a plurality of semiconductor elements formed on a main surface of a semiconductor chip, wherein an upper surface and side surfaces of the semiconductor chip are covered with a sealing insulating film, and a lower surface of the semiconductor chip is formed on a lower surface. A semiconductor device having a structure in which a bottom surface is exposed. 5. The semiconductor device according to claim 4, wherein a part or the whole of a side surface of said semiconductor chip is covered with a sealing insulating film. 6. The semiconductor device according to claim 4, wherein the semiconductor chip has a structure in which the lower surface is polished after being covered with a sealing insulating film.