JP2001084363A - Graphic system controller and computer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To grade up graphic/video sub-system and to completely use a resource between different graphic processors by allocating the resource between the outer/inner graphic processors based on the aresult of inspection by a snooper. SOLUTION: An integrated graphic/video sub-system 32 is installed in a north bridge system controller 30 and it is connected to an outer monitor 36. Thus, various pieces of video/graphic data can be displayed. The integrated graphic/video sub-system 32 is connected to a general AGP bus through a virtual AGP (VAGP) bus. When a graphics coprocessor 34 exists, the VAGP bus and the AGP bus can share the resource of the same band width. The resources of the inner/outer graphic processors are effectively used and the processing efficiency of a graphic processing can be improved by the snooper and an arbiter, which are contained in bus structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexed graphics capable of improving the processing capability of an AGP (Advanced Graphics Port) bus, which is the most advanced graphics / video bus in the personal computer field. The present invention relates to a graphics system controller and a computer system having a bus architecture.

[0002]

2. Description of the Related Art In a conventional computer system, a graphics / video subsystem is generally connected to the computer system by a plug-in card system.
In this case, the graphics / video subsystem incorporated in the plug-in card is implemented on an expansion bus in the computer system. This expansion bus is an early IS
A (Industry Standard Architecture) bus to PCI
(Peripheral Componenet Interface) The bus has progressed to the latest AGP bus.

FIG. 1 is a block diagram of a graphics / video subsystem in a conventional computer system. The graphics / video subsystem is connected to the computer system via an AGP bus. In the figure, reference numeral 12 denotes a north bridge system controller, which includes a CPU 10, a graphics / video subsystem 20, and a south bridge system controller 14.
And data transfer between different devices such as the memory 16 and control of information. The north bridge system controller 12 includes a CPU interface circuit, a memory controller, a PCI controller, and an AG.
P controllers are provided inside, and these are used to connect to the various devices, respectively.

[0004] The AGP bus technology uses a graphics / video bus protocol led by Intel Corporation in the United States. In addition, the commercially available PCI bus and the AGP bus based on the communication protocol use dedicated and pipelined channels for graphics acceleration chips (graphics a).
c graphics chip), various graphics data can be instantaneously obtained from the system memory. The details of the AGP bus are omitted because they are described in various AGP standards. However, here, the above-described conventional PCI bus and ISA bus are not one-to-one dedicated buses, and therefore, compared with the AGP bus. Note that the operation frequency is much lower.

[0005] Most of the conventional graphics / video subsystems are connected to the computer system by a plug-in card system, but an increasing number of computers incorporate the graphics / video subsystem directly on the motherboard. Such a graphics / video subsystem is called an integrated graphics / video subsystem. FIG. 2 is a block diagram of a computer system using the integrated graphics / video subsystem. 2, the same reference numerals as those in FIG. 1 indicate the same or functionally similar components.

The integrated graphics / 22
The video subsystem is mounted on the motherboard 1, and is connected to the north bridge system controller 1 via a bus such as the PCI bus on the motherboard 1.
It is connected to 2. Also, on the motherboard 1, a CP
U10, memory 16, and south bridge sustain controller 14 are also mounted.

[0007]

By the way, when the graphics / video subsystem is integrated on the motherboard, it is advantageous in manufacturing, but a serious problem arises when upgrading the graphics / video subsystem. . Integrating the graphics / video subsystem on the motherboard means that the graphics processor and frame buffer need to be fixed on the motherboard, and only the graphics processor cannot be upgraded. The result is to replace the entire motherboard and upgrade the integrated graphics / video subsystem, but at a significant cost.

Another way to upgrade the graphics / video subsystem is to insert a plug-in card containing a graphics / video subsystem 24 from an AGP slot, as shown in FIG.
A method for improving the processing capability of graphics processing is conceivable. With such an arrangement, it is possible to improve the processing capacity of graphics processing without replacing the motherboard. However, such a method creates a new problem of resource waste. Since the integrated graphics / video subsystem 22 fixed on the motherboard 1 and the graphics / video subsystem 24 added to the computer system via the AGP slot are formed of separate chips, two graphics / videos are provided. Many resources are duplicated between subsystems, resulting in increased costs for the entire system.

[0009] It is therefore an object of the present invention to provide a graphics system capable of upgrading the graphics / video subsystem and fully utilizing resources between different graphics processors without improving conventional bus protocols. It is in providing a controller and a computer system.

[0010]

In order to solve the above-mentioned problems, a graphics system controller according to the present invention comprises:
An external graphics bus operable to couple to an external graphics processor; an internal graphics processor coupled to the external graphics bus via a virtual graphics bus within the graphics system controller; and the graphics system Coupled to the external graphics bus within a controller, wherein at least the external graphics processor is coupled to the external graphics processor;
A snooper for checking requests transferred between the internal graphics processor and any other circuitry in the graphics system controller, wherein the internal graphics processor is coupled to the external graphics processor. In this case, resources are allocated between the external graphics processor and the internal graphics processor based on a result of the inspection by the snooper.

Preferably, provided between the external graphics bus and the virtual graphics bus, when the external graphics processor is coupled, the external graphics processor, the internal graphics processor, and the It further comprises a set of multiplexers that control the transfer of data to and from any other circuits in the graphics system controller.

Preferably, when the external graphics processor is combined, the external graphics processor and the internal graphics processor are respectively allocated to different system address spaces, and the snooper is configured to transmit the transferred request. The destination of the request is determined based on the information of the system address space. Specifically, the external graphics bus is an AGP (Advanced Graph
ics Port) bus, wherein the virtual graphics bus contains control signals for controlling the set of multiplexers.

A computer system having a graphics system controller connectable to an external graphics processor, the computer system having an external graphics bus connectable to the external graphics processor, and mounted on a motherboard of the computer system. An internal graphics processor coupled to the external graphics bus via a virtual graphics bus within the graphics system controller;
The external graphics processor, the internal graphics processor, provided in the graphics system controller, coupled to the external graphics bus within the graphics system controller, at least when the external graphics processor is coupled; And a snooper for checking requests transferred between any other circuits in the graphics system controller, wherein the internal graphics processor is configured to use the snooper when the external graphics processor is coupled. The resources of the external graphics processor and the internal graphics processor are allocated based on the result of the inspection.

[0014] Preferably, the external graphics processor is provided in the graphics system controller between the external graphics bus and the virtual graphics bus, and when the external graphics processor is coupled, And a set of multiplexers for controlling the transfer of data between the internal graphics processor and any other circuitry in the graphics system controller.

Preferably, the internal graphics processor is provided in the graphics system controller. Also preferably, when the external graphics processor is combined, the external graphics processor and the internal graphics processor are respectively allocated to different system address spaces,
The snooper determines the destination of the request based on the information of the transferred system address space. Specifically, the external graphics bus is an AGP (Advanc
ed Graphics Port) bus, wherein the virtual graphics bus contains control signals for controlling the set of multiplexers.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described in detail with reference to FIGS. In the present embodiment, the present invention will be described by exemplifying a computer system having a multiple AGP bus architecture according to the present invention.
The multiple graphics bus architecture according to the present invention incorporates a conventional AGP bus, a virtual AGP bus (hereinafter abbreviated as VAGP) coupled to an internal integrated graphics / video subsystem, and a north bridge chipset. Inspect all transferred data and requests,
This can be achieved by using a snooper that efficiently allocates the resources of the internal and external graphics / video subsystems.

FIG. 3 is a block diagram of a computer system having the multiple AGP bus architecture. In addition,
3, the same reference numerals as those in FIG. 1 denote the same or functionally similar components, and a description thereof will be omitted. As shown in FIG. 3, in this computer system, an integrated graphics / video subsystem 32 is provided in a north bridge system controller 30, and is connected to an external monitor 36. Graphics data can be displayed. The bus architecture of the computer system is characterized in that the integrated graphics / video subsystem 32
It is connected to a general AGP bus via a virtual AGP (VAGP) bus.

First, the VAGP bus will be described. First, when no plug-in card is inserted in a general AGP slot, that is, when the graphics coprocessor 34 of FIG. 3 does not exist, the VAGP bus functions in the same manner as the standard AGP bus, and the entire bandwidth of the AGP bus is used. Occupies width resources. The integrated graphics / video subsystem 32 also functions similarly to the graphics / video subsystem on a conventional AGP bus.

When an additional graphics / video plug-in card is inserted in a general AGP slot, that is, when the graphics coprocessor 34 shown in FIG. 3 is present, the VAGP bus and the AGP bus have the same bandwidth. Width resources can be shared. Furthermore, the snooper and the arbiter included in the bus structure can effectively utilize the resources of the internal and external graphics processors and improve the processing efficiency of the graphics processing. The snooper and arbiter will be described later in detail.

Next, the AGP / VAG according to the present embodiment
The P bus architecture will be described in detail. FIG. 4 is a partial block diagram of the north bridge system controller 30 according to the present embodiment.
Only the components included in the VAGP bus architecture are shown. As shown in FIG. 4, the north bridge system controller 30 has a buffer 301, an encoder 303, a set of multiplexers 305, a snooper 307, and a multiplexer 309.

The buffer 301 and the encoder 303 are standard components included in a general AGP interface circuit, and are used for buffering data and coding signals.

The snooper 307 is mounted on an extension of the AGP bus in the north bridge system controller 30 and is provided between the buffer 301 and the encoder 303. The snooper 307 is provided between the graphics coprocessor 34 on the AGP bus and the VAGP bus. Used to check (snoop) requests transferred between the integrated graphics / video subsystem 32 and other components within the northbridge system controller 30, such as, for example, a CPU interface circuit and a memory controller. You.

In the present embodiment, the above-described inspection (snooping) is performed by allocating the graphics coprocessor 34 and the integrated graphics / video subsystem 32 to different system address spaces.
If no plug-in card is inserted in the AGP slot, the system will launch the integrated graphics / video subsystem 32 at standard AGP
Address space. At this time, the integrated graphics / video subsystem 32 functions as a plug-in card inserted into the AGP slot,
All resources of the P system can be used.

If a plug-in card, that is, a graphics coprocessor 34 is inserted in the AGP slot, the system will be an integrated graphics / graphics processor.
Designate the video subsystem 32 in an unused PCI-I / O address space. When a request is forwarded, snooper 307 checks whether the request is related to a request being processed by internal integrated graphics / video subsystem 32. If the result is YES, snooper 307 passes control signal HI through multiplexer 309.
Generate T / MISS and set 305 of multiplexers
Transfer to This sets the multiplexer set 305
Prevents the data in the buffer 301 from passing through the general AGP bus and is processed by the integrated graphics / video subsystem 32.

Thus, the integrated graphics / video subsystem 32 in the north bridge system controller 30 and the external graphics processor 3
4 can achieve the purpose of sharing resources.

The set of multiplexers 305 includes AGP
Used to control the transfer of data, request and control signals to and from the bus, VAGP bus, and other components in the system. Multiplexer set 305
Consists of a plurality of multiplexers. FIG. 5 is a circuit diagram of a multiplexer set 305 for processing data transfer according to the present embodiment. Here, FIG. 5 illustrates a general data exchange case, and the number of necessary multiplexers is determined by the number of physical data signals.

In FIG. 5, reference numeral 323 denotes a first-in first-out (FIFO) input register, and reference numeral 321 denotes a first-in first-out (FIFO) output register. Registers 323 and 321 function as input and output registers on the VAGP bus of integrated graphics / video subsystem 32, respectively. In FIG.
Two multiplexers M1, M2 and M3 are shown. The multiplexer M1 is used for controlling data transferred from the AGP bus or the VAGP bus to the system, and the multiplexer M2 is used for controlling the system or the VA.
The multiplexer M3 is used to control transfer data from the GP bus to the AGP bus.
Used to control data transferred from the bus to the VAGP bus.

FIG. 6 shows a multiplexer set 3 for handling the transfer of request and control signals according to this embodiment.
It is a circuit diagram of 05. Again, requests from the graphics coprocessor 34 and the integrated graphics / video subsystem 32 can be selectively input to the system via a multiplexer M4 controlled by an arbiter 322. Here, arbiter 322
Is installed inside the integrated graphics / video subsystem 32 or snooper 307. In this way, the set of multiplexers 305 functions as a device that controls the direction of the data to be transferred and the request.

North Bridge System Controller 30
The integrated graphics / video subsystem 32 within
It is capable of monitoring and managing internal and external graphics-related resources, and is a functionally important configuration within the system.

For example, in the present embodiment, the graphics coprocessor 34 processes geometric graphics, front rendering process (front rendering process).
ng) and back rendering process
ssing), etc., to improve the efficiency of one or more specific graphics processes. for that reason,
The integrated graphics / video subsystem 32 divides one graphics processing job into a plurality of sub-jobs and forms a pipeline, and executes the graphics coprocessor 34 and the integrated graphics / video subsystem 3.
2, respectively.

For example, the graphics coprocessor 34
Is a geometry processor and integrated graphics /
The video subsystem 32 has a rendering engine (rend
ering engine). Alternatively, graphics coprocessor 34 may be a front rendering processor,
Integrated graphics / video subsystem 32 may also function as a back rendering processor. Alternatively, both can be used as graphics rendering and each connected to an external monitor.

As described above, in a computer system using the multiple graphics bus architecture according to the present invention, a complicated graphics processing job can be simplified by pipelining. That is,
A complicated job can be divided into a plurality of simplified partial processes and processed by the graphics processors on the AGP bus and the VAGP bus, respectively. As a result, a user can selectively construct a graphics system.

Also, by using the graphics coprocessor in the AGP slot, the processing capability of the graphics / video subsystem mounted on the motherboard or incorporated in the system controller can be improved. For example, by adding a high-performance geometric processor in an AGP slot, it becomes possible to upgrade a general personal computer to a high-level graphics terminal capable of performing graphics / video processing.

Further, the resources related to graphics in the computer system can be completely used. That is, even if the entire motherboard is not replaced, the processing capability of graphics processing can be improved only by introducing a new graphics processor on the expansion slot of the AGP. Further, the graphics processors on the AGP bus and VAGP bus can share various internal resources such as a memory. as a result,
The cost required for system upgrade can be reduced, and various system resources can be used efficiently.

Note that the present invention is not limited to the present embodiment, and various suitable modifications are possible. For example, in the present embodiment, the case where the AGP bus is used is described as an example, but the multiple graphics bus architecture according to the present invention can be applied to other graphics buses or video buses as well. Further, in the present embodiment, the integrated graphics / video subsystem 32 is incorporated in the system controller. Alternatively, the integrated graphics / video subsystem 32 may be directly mounted on the motherboard to achieve the purpose of system integration.

Since the snooper 307 needs time to determine the destination of transfer data, one or more layers of data buffers are added to the write buffer of the AGP bus, and the time required for inspection (snooping) is reduced. You can make up for it. Since the AGP bus is pipelined, the addition of a data buffer does not affect the processing power of the system.

[0037]

As described above, according to the present invention, the processing capability of the integrated graphics / video subsystem in graphics processing is upgraded, and various graphics-related resources are allocated between the graphics / video subsystems. It becomes possible to allocate efficiently. As a result, there is provided a graphics system controller and a computer system capable of realizing upgrade of a graphics / video subsystem and full utilization of resources between different graphics processors without improving a conventional bus protocol. can do.

[Brief description of the drawings]

FIG. 1 is a block diagram of a conventional computer system including a graphics / video subsystem.

FIG. 2 is a block diagram of a conventional computer system including an integrated graphics / video subsystem.

FIG. 3 is a block diagram of a computer system according to one embodiment of the present invention, including a multiple AGP / VAGP bus architecture.

FIG. 4 is a partial block diagram of a northbridge system controller according to one embodiment of the present invention.

FIG. 5 is a circuit diagram of a multiplexer set for data transfer processing according to an embodiment of the present invention.

FIG. 6 is a circuit diagram of a multiplexer set for request and control signal transfer processing according to an embodiment of the present invention.

[Explanation of symbols]

10 CPU 12, 30 North Bridge System Controller 14 South Bridge System Controller 16 Memory 20 Graphics / Video Subsystem 22, 32 Integrated Graphics / Video Subsystem 24 Graphics / Video Subsystem 34 Graphics Coprocessor 36 External Monitor 301 Buffer 303 Encoder 305 Multiplexer set 307 Snooper 309 Multiplexer 321 FIFO output register 322 Arbiter 323 FIFO input register

Claims (7)

[Claims] 1. A graphics system controller couplable with an external graphics processor, comprising: an external graphics bus couplable with the external graphics processor; and virtual graphics within the graphics system controller. An internal graphics processor coupled to the external graphics bus via a bus; coupled to the external graphics bus within the graphics system controller, wherein at least the external graphics processor is coupled; A snooper for checking a request transferred between an external graphics processor, the internal graphics processor, and any other circuits in the graphics system controller. A graphics processor for allocating resources between the external graphics processor and the internal graphics processor based on a result of the inspection by the snooper when the external graphics processor is coupled; System controller. 2. An external graphics processor, said internal graphics processor, and said graphics, provided between said external graphics bus and said virtual graphics bus and coupled to said external graphics processor. 2. The graphics system controller according to claim 1, further comprising a set of multiplexers for controlling data transfer to and from any other circuits in the system controller. 3. When the external graphics processor is combined, the external graphics processor and the internal graphics processor are allocated to different system address spaces, respectively, and the snooper is configured to transfer the system address space of the transferred request. 2. The graphics system controller according to claim 1, wherein a destination of the request is determined based on the information of (1). 4. The external graphics bus includes an AGP.
The graphics system controller according to claim 2, wherein the virtual graphics bus is a (Advanced Graphics Port) bus, and the virtual graphics bus contains a control signal for controlling the set of the multiplexers. 5. A computer system having a graphics system controller connectable to an external graphics processor, an external graphics bus connectable to an external graphics processor, and mounted on a motherboard of the computer system. An internal graphics processor coupled to the external graphics bus via a virtual graphics bus within the graphics system controller; and an internal graphics processor provided within the graphics system controller and within the graphics system controller. Coupled to an external graphics bus, wherein at least the external graphics processor is coupled to the external graphics processor, the internal graphics processor, and the graphics processor. A snooper for checking requests transferred between any other circuits in the fixed system controller, wherein the internal graphics processor, when the external graphics processor is coupled, the result of the check by the snooper. A computer system for allocating resources for the external graphics processor and the internal graphics processor based on 6. An external graphics processor provided between the external graphics bus and the virtual graphics bus in the graphics system controller, wherein the external graphics processor is connected to the external graphics processor. 6. The system of claim 5, further comprising a set of multiplexers for controlling the transfer of data between a graphics processor and any other circuitry in the graphics system controller.
The computer system according to 1. 7. The external graphics bus includes an AGP.
7. The computer system according to claim 6, wherein the virtual graphics bus is a (Advanced Graphics Port) bus, and the virtual graphics bus contains a control signal for controlling the set of the multiplexers.