JP2001077360A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a method for manufacturing a DMOS transistor having small variation in threshold voltage by a method wherein ions are restrained from diffusing long in the lateral direction. SOLUTION: A gate electrode 105 is patterned, and then a resist 104 used for patterning is thermally treated at temperature of 150 to 250 deg.C as being irradiated with UV rays, by which the resist 104 is cured. The resist 104 is left unremoved, a resist 106 is applied, an exposure and development process are carried out to form an opening, and then ions are implanted using the resists 104 and 106 and a gate electrode 105 as masks. Then, the resist 104 that is previously cured is hardly shrunk when the resist 106 is exposed to light and developed, so that implanted ions are blocked and restrained from diffusing long in the lateral direction by the resist 104.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a DMOS (double diffusion type MOS) transistor.

[0002]

2. Description of the Related Art In recent years, due to miniaturization of equipment and the like, miniaturization of semiconductor devices by design rules has been progressing, and the diffusion depth of impurity layers constituting the semiconductor devices has tended to be reduced. Therefore, in the past, after impurity ions were implanted, impurities were diffused by high-temperature heat treatment to form an impurity layer. However, recently, a method of forming a shallow impurity layer by performing low-temperature heat treatment for recovering implantation damage after ion implantation with a large implantation energy is often used.

A DMOS transistor known as a power device forms a gate electrode on a silicon substrate,
Using the gate electrode as a mask during ion implantation, the body layer and the source layer are formed in a self-aligned manner. Then, a channel portion is constituted by a difference in diffusion length between the body layer and the source layer.

Here, a method for manufacturing a conventional DMOS transistor will be described with reference to the drawings.

FIGS. 4 and 5 are process flow charts for explaining a conventional method of manufacturing a DMOS transistor. 4 and 5, 1 is a semiconductor substrate, 2 is a gate insulating film, 3 is a gate electrode material, 4, 6, and 8 are resists, 5 is a gate electrode, 7 is a body layer, 9 is a source layer, and 10 is a drain. It is a contact layer.

First, a gate insulating film 2 is formed on an N-type silicon substrate 1, and a gate electrode material 3 is formed thereon (see FIG. 4A). Then, a resist 4 is applied on the gate electrode material 3 (see FIG. 4B).

Next, the resist 4 is exposed, developed and patterned. Using the patterned resist 4 as a mask,
The gate electrode material 3 and the gate insulating film 2 are etched to form the gate electrode 5 (see FIG. 4C).

Next, a resist 6 is applied with the resist 4 remaining on the gate electrode 5, exposed and developed, and the resist 6 is selectively opened to form an opening for forming a body layer ( FIG. 5 (d)). When the resist 6 is exposed and developed, the resist 4 on the gate electrode 5 slightly shrinks.

[0009] Next, after performing rotation implantation for rotating while implanting ions of the P-type impurity from an oblique direction, the resist 4 and the resist 6 are removed and heat treatment is performed to form a body layer 7 of the P-type impurity. (See FIG. 5E).

Then, after a resist 8 is applied to the whole,
Exposure and development are performed to form an opening at a predetermined portion of the resist 8. Then, heat treatment is performed after ion implantation of the N-type impurity in the vertical direction, so that the source layer 9 of the N-type impurity is implanted.
And a drain contact layer 10 is formed (FIG. 5F).
See).

Thus, the DMOS transistor is
Using the same gate electrode 5 as a mask, a body layer 7 and a source layer 9 are formed. By making the lateral diffusion lengths of the body layer 7 and the source layer 9 immediately below the gate electrode different, a short channel portion is formed. I have.

[0012]

When the body layer 7 of the DMOS transistor is formed, ions are implanted into the gate electrode 5, the resist 4, and the resist 6 in a self-aligned manner. However, when exposing and developing the resist 6, the gate electrode 5
Since the upper resist 4 contracts and the shape of the resist 4 becomes smaller than that of the gate electrode 5, the shielding effect against ion implantation is reduced. Therefore, even immediately below the gate electrode 5, ions implanted with high energy penetrate the edge of the gate electrode 5 and are implanted into the semiconductor substrate 1, and the body layer 7
Becomes larger near the surface of the semiconductor substrate 1. In addition, the degree of shrinkage of the resist 4 varies, and the profile of the body layer 7 tends to fluctuate.

Since the source layer 9 is formed by ion implantation from the vertical direction, it is formed along the edge of the gate electrode 5. On the other hand, since the body layer 7 is formed by ion implantation from an oblique direction, the body layer 7 is formed so as to slightly enter from the edge of the gate electrode 5 directly below the gate electrode 5. Accordingly, the lateral diffusion length of the body layer 7 directly below the gate electrode 5 is substantially equal to the channel length. For this reason, when the profile of the body layer 7 fluctuates as described above, a problem arises in that the electrical characteristics (such as the threshold voltage) of the DMOS transistor vary.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and provides a method of manufacturing a semiconductor device with less manufacturing variations such as a threshold voltage.

[0015]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising the steps of: laminating an insulating film and a gate electrode material on a semiconductor substrate; A second step of patterning a first resist on the gate electrode material layer, a third step of curing the first resist, and then removing the first resist. Using a fourth step of etching the insulating film and the gate electrode material and patterning the gate electrode, and then patterning a second resist on the first resist and the semiconductor substrate, A fifth step of performing ion implantation using the first and second resists and the gate electrode as a mask to form an impurity layer on the semiconductor substrate.

According to this configuration, the first resist is cured before etching the gate electrode material. Therefore, even if the second resist is exposed and developed while the first resist remains on the gate electrode, The first resist does not shrink, and the impurity layer can be formed at a position where there is little variation with respect to the gate electrode.

According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a first step of laminating an insulating film and a gate electrode material on a semiconductor substrate of a first conductivity type; A second step of patterning a first resist on the layer, a third step of curing the first resist, and then using the first resist to form the insulating film and the A fourth step of etching the gate electrode material and patterning the gate electrode, and then patterning a second resist on the first resist and the semiconductor substrate; A fifth step of implanting ions of the second conductivity type into the semiconductor substrate from an oblique direction using the resist and the gate electrode as a mask, and then removing the first and second resists, and then removing the third resist. Pattern forming Using the third resist and the gate electrode as a mask, performing a sixth step of performing ion implantation directly above the semiconductor substrate to form a second diffusion layer of the first conductivity type. .

According to this structure, the first resist is cured before the gate electrode material is etched. Therefore, even if the second resist is exposed and developed while the first resist remains on the gate electrode, The first resist does not shrink, and the first resist is located at a position with little variation with respect to the gate electrode.
Can be formed. Then, the relative positions of the first diffusion layer and the second diffusion layer on the side of the gate electrode are improved with accuracy, the length of the channel portion is made substantially constant, and a DMOS having a small variation in threshold voltage is manufactured. can do.

In the third step, the first resist is subjected to a heat treatment at 150 to 250 ° C. while irradiating the first resist with ultraviolet light, so that the first resist is cured in advance. Cure is ensured, and contraction of the first resist at the time of exposing and developing the resist in a subsequent process can be prevented. Even if an impurity layer is formed by performing ion implantation using the gate electrode as a mask,
The impurity layer can be formed at a stable position.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

FIGS. 1 to 3 are process flow charts for explaining a method of manufacturing a DMOS transistor. 1 to 3, reference numeral 101 denotes a silicon substrate made of an N-type impurity; 102, a gate insulating film; 103, a gate electrode material such as polycrystalline silicon; 104, a resist (first resist) for forming a gate electrode 105; 105 is a gate electrode, 1
06 is a resist for forming the body layer 107 (second resist), 107 is a body layer made of P-type impurities, 108 is a resist for forming the source layer 109 and the drain contact layer 110 (third resist), and 109 is N A source layer 110 made of an N-type impurity is a drain contact layer made of an N-type impurity.

First, a gate insulating film 102 is formed on an N-type silicon substrate 101, and a gate electrode material 1 is formed thereon.
No. 03 is formed (see FIG. 1A). Then, after a resist 104 is applied on the gate electrode material 103, exposure and development are performed to pattern the resist 104 (see FIG. 1B). Since the resist 104 shrinks in the subsequent step of curing the resist 104, the resist 104 is patterned to be relatively large in anticipation of the shrinkage dimension.

Thereafter, in the prior art, the gate electrode material 3 is etched using the resist 4 as a mask, but in this embodiment, before the gate electrode material 103 is etched, UV light (ultraviolet light) is applied to the resist 104. While irradiating,
After gradually increasing the temperature over 20 to 30 minutes, the maximum temperature is set in the range of 150 to 250 ° C., and heat treatment is performed for 20 to 50 minutes to cure the resist 104 (FIG. 1C).
See). A better result is obtained when the temperature at which the resist 104 is cured is 170 to 230 ° C. When the resist 104 is heat-treated in this step, the resist 104 is hardened and the pattern shrinks. Therefore, it is necessary to experimentally determine the degree (dimension) in which the resist 104 shrinks in advance and to pattern the resist 104 in the above-described step of FIG.

Next, the gate electrode material 103 is etched using the cured resist 104 as a mask to form a gate electrode 105 (see FIG. 2D). And
A resist 106 is applied to the entire surface of the semiconductor substrate 101 including the cured resist 104, and is exposed and developed to selectively open the resist 106 to form a body layer (107 in FIG. 3) of the DMOS transistor. Is formed (see FIG. 2E). Since the resist 104 is cured in advance (see FIG. 1C), even if the resist 106 is exposed and developed, the resist 104 hardly shrinks, and the edge of the resist 104 is
It almost overlaps with the edge of 05.

Thereafter, a P-type impurity is added to the gate electrode 105,
P-type impurities are ion-implanted into the resist 104 and the resist 106 in a self-aligned manner. At this time, since the resist 104 on the gate electrode 105 also acts to shield the ion implantation, there occurs a phenomenon that the lateral diffusion length of the body layer becomes abnormally large near the surface of the semiconductor substrate 101, which occurs in the related art. Disappears (see FIG. 3 (f)).

In the ion implantation of the P-type impurity for the body layer 107, the implantation energy is set to a high energy level of 80 KeV or more, and an angle of 7 ° to 50 ° with respect to the normal direction of the silicon substrate 101 is set. , 10 ¹³ cm ^-2 to 10
Ion implantation is performed at an ion implantation amount of ¹⁴ cm ^-2 . In addition, rotational ion implantation is performed in which ions are implanted while rotating the direction of implantation. After the completion of the ion implantation, the resist 104 and the resist 106 are removed, and then a low-temperature (900 ° C.) heat treatment is performed.
The P-type body layer 107 is formed by activating the type ions. In this embodiment, rotation injection is adopted,
In the case where a plurality of semiconductor devices are formed side by side in a specific direction on a silicon substrate, the semiconductor device may be implemented by means for implanting ions obliquely from one specific direction.

Next, a resist 108 is applied to the entire surface of the semiconductor substrate 101 and exposed and developed, and a predetermined portion of the resist 108 is opened to form openings for the source layer 109 and the drain contact layer 110. N-type ions are implanted into the silicon substrate from directly above (normal direction) (FIG. 3).
(G)).

At this time, the ion implantation is performed at an implantation energy of 40 KeV or less and an ion implantation amount of 10 ¹⁵ cm ⁻² to 10 ¹⁵
Set to about ¹⁶ cm ^-2 . Since the implantation energy level at this time is much lower than that of the ion implantation for the body layer 107, the ions do not penetrate the gate electrode 105 and are implanted into the silicon substrate 101.

According to the above-described method of manufacturing the DMOS transistor of the present embodiment, the position of the region to be ion-implanted into the silicon substrate 101 hardly varies with respect to the gate electrode 105, and
Also, the lateral diffusion length of the DMOS transistor 7 does not vary, the channel length becomes almost constant, and the variation in characteristics of the DMOS transistor such as the threshold voltage is reduced.

[0030]

As described above, according to the first invention of the present invention, the first resist is pre-cured before etching the gate electrode material. The first resist does not shrink, and the impurity layer can be formed at a position where there is little variation with respect to the gate electrode.

According to the second invention, the relative positions of the first diffusion layer and the second diffusion layer on the gate electrode side are improved with accuracy, the length of the channel portion becomes substantially constant, and the threshold is increased. A DMOS transistor having small value voltage variation can be manufactured.

[Brief description of the drawings]

FIG. 1 is a process flow chart of a DMOS transistor according to an embodiment of the present invention.

FIG. 2 is a process flow chart of the DMOS transistor in the embodiment of the present invention, and is a process flow diagram following FIG. 1 (c).

FIG. 3 is a process flowchart of the DMOS transistor according to the embodiment of the present invention, which is a process flowchart following FIG. 2 (e).

FIG. 4 is a process flow chart of a conventional DMOS transistor.

FIG. 5 is a conventional process flow diagram, which is a process flow diagram following FIG. 4 (c).

[Explanation of symbols]

Reference Signs List 101 silicon substrate 102 gate insulating film 103 gate electrode material 104 first resist (for forming gate electrode 105) 105 gate electrode 106 second resist (for forming body layer 107) 107 body layer 108 third resist (source layer and (For forming drain contact layer) 109 source layer 110 drain contact layer

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 29/78 301G F-term (Reference) 2H025 AA00 AB16 DA11 FA03 FA14 FA29 FA30 FA39 2H096 AA25 EA00 GA00 HA01 HA03 HA11 HA30 JA04 KA02 4M104 AA01 BB01 CC05 DD02 DD26 DD62 DD71 GG09 5F040 DA06 DC01 EB01 EC28 EF18 EM01 EM03 FC13

Claims (3)

[Claims] A first step of laminating an insulating film and a gate electrode material on a semiconductor substrate; and a second step of patterning a first resist on the gate electrode material layer. Next, a third step of curing the first resist, and a fourth step of patterning the gate electrode by etching the insulating film and the gate electrode material using the first resist. Next, after patterning a second resist on the first resist and the semiconductor substrate, the first and second resists are formed.
Ion implantation using the resist and the gate electrode as a mask to form an impurity layer on the semiconductor substrate.
A method for manufacturing a semiconductor device, comprising the steps of: 2. A first step of laminating an insulating film and a gate electrode material on a semiconductor substrate of a first conductivity type; and a step of forming a first resist pattern on the layer of the gate electrode material. Step 2, Step 3 for curing the first resist, Next, the insulating film and the gate electrode material are etched using the first resist, and the gate electrode is patterned. A fourth step, and after patterning a second resist on the first resist and the semiconductor substrate, the first and second resists are formed.
A fifth step of implanting ions of the second conductivity type into the semiconductor substrate from an oblique direction using the resist and the gate electrode as masks, and then removing the first and second resists, and then removing the third resist. Forming a second diffusion layer of the first conductivity type by ion-implanting the semiconductor substrate from directly above, using the third resist and the gate electrode as a mask. Of manufacturing a semiconductor device having the same. 3. The method according to claim 1, wherein in the third step, the first resist is cured by performing a heat treatment at 150 ° C. to 250 ° C. while irradiating the first resist with ultraviolet light. A method for manufacturing a semiconductor device according to claim 2.