JP2001057409A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of sufficiently improving surface withstand voltage and achieving higher voltage and miniaturization. SOLUTION: An insulating plate 2 is disposed on one surface of a base substrate 1. A circuit side conductor 3 is provided on the other surface of this insulating plate 2 via a metallic layer 4. There is provided a semiconductor element 5 on this circuit side conductor 3. In this semiconductor device for power, a recessed portion 20 having a curved surface on peripheral end portions is formed in the insulating plate surface 2 in advance. By forming the metallic layer 4 in this recessed portion 20, the end portions of the metallic layer 4 become curved. Since the end portions of the metallic layer 4 do not have corner portions, electric field can be relaxed at the end portions of the metallic layer 4 where the electric field is easily most concentrated, and thus the surface withstand voltage of the insulating plate can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device, and more particularly to a semiconductor device suitable for a high voltage semiconductor having a module structure.

[0002]

2. Description of the Related Art In recent years, for example, IGBTs (insulated gates)
An inverter device using a semiconductor switching element such as a bipolar transistor has been widely used, but this inverter device requires a plurality of switching semiconductor elements such as six.

Therefore, conventionally, a metal plate having a predetermined strength and also functioning as a heat sink is used as a base substrate, for example, a plurality of sets of semiconductor elements for an inverter main circuit.
(Switching element and flywheel diode) are used as semiconductor devices.

The planar arrangement of the semiconductor device having the module structure is, for example, as shown in FIG.
A base substrate 1 made of a metal such as another predetermined alloy is used, and a plurality of insulating substrates 2 made of a ceramic material such as alumina porcelain are arranged on one surface thereof. The semiconductor elements 5 such as the IGBT element S and the diode element D are provided.
Necessary electrical insulation is maintained in each circuit portion, and modularization is obtained.

FIG. 10 is a sectional view showing an example of a conventional semiconductor device. As shown in the figure, the insulating substrate 2 is joined to one surface of the base substrate 1 and the other surface (the upper surface in the figure) is made of copper or the like having a predetermined conductivity as a conductor pattern. A circuit-side conductor 3 made of a metal foil or film is formed, and a semiconductor element 5 is provided on a predetermined portion of an upper surface thereof.

At this time, a metal layer 4 is provided between the circuit-side conductor 3 and the insulating substrate 2 separately from the circuit-side conductor 3, and the circuit-side conductor 3 has the metal layer 4 interposed therebetween. In this state, it is formed on the surface of the insulating substrate 2. Although a predetermined metal such as a nickel alloy is used as the metal layer 4, the metal layer 4 may be joined by using a soft brazing material having a relatively low melting temperature.

Then, a casing or a cover (not shown) is fixed to the base substrate 1 so as to cover the surface of the base substrate 1 including the semiconductor elements 5, and the base substrate 1 is used as a bottom plate member. A semiconductor device is completed by forming a container and sealing an adhesive resin or an insulating resin inside in some cases.

[0008] By the way, miniaturization is always a major issue in most devices, and is not an exception for the semiconductor device targeted here, and in recent years, along with miniaturization, the semiconductor device for power use has become a major issue. There is also a strong demand for voltage.

Here, in such a semiconductor device, generally, along with the miniaturization of the semiconductor element itself, the creepage distance between the insulating substrate and the circuit-side conductor is reduced to the minimum insulating distance obtained from the insulation design. It is customary to reduce the size by reducing the size, and while the operating voltage remains in a low range, the insulation performance of the insulating substrate can be secured by reducing the insulation distance to this extent.

[0010] However, when the required operating voltage is higher than, for example, 2 kV, the surface (creeping surface) of the insulating substrate is also reduced to 2 kV.
When a high voltage of kV or more is applied, and the creepage distance of the insulating substrate is reduced for miniaturization, the insulation distance is insufficient for the voltage used, and the withstand voltage performance of the creepage of the insulating substrate is reduced. Will be reduced and will not be able to respond to requests.

Therefore, in order to increase the voltage of a semiconductor device having such a module structure, it is necessary to improve the withstand voltage performance of the insulating substrate.
Japanese Patent Publication No. 66963 proposes a structure in which a thin portion having a concave shape is formed on an insulating substrate to enhance heat dissipation.

In Japanese Patent Application Laid-Open No. 9-135057, the end of the collector electrode is processed into a gentle curved surface so that the end enters the inside without protruding at the joint surface between the collector electrode and the insulating substrate. A structure that suppresses an electric field is disclosed.

[0013]

In the above prior art, no consideration is given to electric field concentration due to a metal layer provided between the insulating substrate and the circuit-side conductor, and there is a problem in improving the withstand voltage performance. . In a semiconductor device modularized using an insulating substrate, as described above, the circuit-side conductors and metal members become high in potential during operation due to the increase in voltage.
If the creeping insulation distance of the insulating substrate is reduced for miniaturization, the electric field strength increases on the upper surface of the insulating substrate where the conductor end and the metal member are close to each other, and the electric field concentrates on this portion.

In particular, the metal layer disposed between the insulating substrate and the circuit-side conductor is extremely thin, for example, on the order of several μm to 100 μm, and the end of this metal layer is formed with respect to the surface of the insulating substrate. Because of the acute angle, the electric field is strongly concentrated at this end.

If the electric field concentration becomes extreme, a partial discharge will occur, leading to dielectric breakdown.
(Creepage insulation withstand voltage) is reduced. Therefore, in the related art, a problem arises in increasing the voltage of the semiconductor device.

An object of the present invention is to provide a semiconductor device capable of sufficiently improving the creepage withstand voltage performance of an insulating substrate and easily achieving a high voltage and a small size.

[0017]

The above object is achieved by providing a circuit-side conductor provided on one surface of an insulating substrate with a metal layer interposed therebetween.
In a semiconductor device having a semiconductor element disposed on the other surface of the circuit-side conductor, a concave portion whose peripheral end is formed in a curved surface is provided on one surface of the insulating substrate, and the metal is provided in the concave portion. This is achieved in that the circuit-side conductor is provided via a layer.

Here, the present inventors have conducted a numerical analysis of the state of the electric field in the semiconductor device according to the prior art, and as a result, it has been found that the vicinity of the end of the metal layer disposed between the insulating substrate and the circuit-side conductor is most significant. It was found that the electric field became high.

FIG. 11 illustrates the state of the electric field concentration. FIG. 11 is an enlarged view of a main part of the semiconductor device according to the prior art shown in FIG. As is clear from this figure, on the surface of the insulating substrate 2, the equipotential line A is bent so as to be largely refracted toward the end of the metal layer 4. The interval between the potential lines A is narrowed, and it is shown that electric field concentration occurs at the portion A shown in the figure. The electric field at the portion A has an extremely high intensity compared to the electric fields at other portions. It turned out to be.

The inventors of the present invention have numerically analyzed how the shape of the end of the metal layer affects the potential distribution, and have found that the shape of the end of the metal layer can be changed between the insulating substrate and the circuit-side conductor. By forming a curved surface having a predetermined radius of curvature at the boundary portion, it has been found that electric field concentration can be greatly reduced, and based on this finding, forming a recess on the surface of the insulating substrate and providing a metal layer in the recess. As a result, a curved surface is formed at the end of the metal layer, thereby achieving the above object.

As a result, the concentration of the electric field can be greatly reduced at the end of the metal layer where the electric field is most likely to be concentrated, and the withstand voltage of the insulating substrate can be improved. In addition, as a result, since the spread of the metal layer is limited to the concave portion of the insulating substrate, the protrusion of the metal layer, which is the brazing material, is suppressed, and there is no fear that the creeping insulation distance is reduced on the insulating substrate. In addition, the surface withstand voltage performance can be improved.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor device according to the present invention will be described in detail with reference to the illustrated embodiments. FIG.
1 is a cross-sectional view of a power semiconductor device according to an embodiment of the present invention. This embodiment is different from the prior art shown in FIG. 10 only in the configuration of the insulating substrate 2 and the metal layer 4 being different. The configuration is the same as that of the semiconductor device, and the entire configuration is also the same as the semiconductor device according to the related art shown in FIG.

Therefore, in FIG. 1, an insulating substrate 2 is provided on one surface of a base substrate 1 using a metal such as an aluminum alloy or another alloy, and a circuit-side conductor 3 is provided on the upper surface of the insulating substrate 2. It is the same as the prior art in that it is formed and the metal layer 4 is present between them. Further, the terminals of the plurality of semiconductor elements 5 and the terminals of the external conductors connected to the external terminals are previously formed. The same applies to the case where the wires are electrically connected by wires, brazing, or the like via the wiring portions of the plurality of circuit-side conductors 3 set in the circuit.

Here, the embodiment of FIG. 1 is significantly different from the prior art in that the surface of the insulating substrate 2 on which the circuit-side conductor 3 is formed has a plane shape of the circuit-side conductor 3, that is, FIG. In the figure, a recess 20 having a slightly larger size and substantially the same shape is formed in advance corresponding to the shape when viewed from above, and the metal layer 4 is accommodated in the recess 20 so that the circuit-side conductor is formed. 3 is formed on the insulating substrate 2.

In the vicinity of the recess 20, the end buried in the insulating substrate 2, that is, the bottom end, is formed as a curved surface having a predetermined radius of curvature R as shown in the figure. When the planar shape has a corner portion (corner portion), the corner portion is also formed such that the planar shape is a curved surface.

As a result, the metal layer 4 is placed on the concave portion 2 of the insulating substrate 2.
By setting it to 0, the lower end (in FIG. 1) of the metal layer 4 is similarly formed by the curved surface formed at the end of the recess 20.

Therefore, according to this embodiment, the metal layer 4
Is formed linearly on a curved surface, so that there is no corner near the metal layer 4 where the electric field is most likely to concentrate. As a result, when a voltage is applied, The electric field concentration can be greatly reduced, and the partial electric discharge starting voltage can be increased by the relaxation of the electric field concentration, so that the surface withstand voltage performance of the insulating substrate 2 can be easily improved.

The metal layer 4 is usually made of an alloy of nickel (Ni) or titanium (Ti), and is formed on the surface of the insulating substrate 2 by a method such as vapor deposition or plating. Is formed, but a joining member having a relatively low melting temperature, for example, a soft brazing material may be used.
The circuit-side conductor 3 is brazed to the insulating substrate 2 via a brazing material maintained at a melting temperature.

In this case, the metal layer 4 made of the molten brazing material is solidified in the recess 20 of the insulating substrate 2. Therefore, in this case, after brazing, the metal layer 4 eventually spreads over the entire concave portion 20 and can be left in a curved portion having a predetermined radius of curvature around the concave portion 20. The corners can be easily and reliably eliminated from the end of the metal layer 4.

Next, the electric field relaxation according to the above embodiment will be described with reference to FIGS. 2 and 3. FIG.
Enlarged main portion of a semiconductor device according to the present invention shown in, there calculated by numerical analysis Genru potential distribution, in view illustrating the equipotential line, first 2, the radius of curvature of the concave portion 20 is as R ₁ relatively small, that is, relatively shallow depth of the recess 20, in the example of the case of the same degree as the thickness of the conventional brazing material shown in FIG. 10, then 3, the radius of curvature of the concave portion 20 and the R ₂ This is an example in which the recess 20 is relatively large, that is, the depth of the recess 20 is relatively large, and is about five times the thickness of the conventional brazing material shown in FIG.

First, in the case of FIG. 2, as is apparent from the figure,
In the portion B near the end of the metal layer 4 on the upper surface of the insulating substrate 2, a potential distribution in which the equipotential lines A are substantially perpendicular to the surface of the insulating substrate 2 is exhibited, and FIG. It can be seen that the interval between the equipotential lines A is wider than that of FIG.

In the case of FIG. 3, as is apparent from the figure, the equipotential line A at the portion C on the upper surface of the insulating substrate 2 near the end of the metal layer 4 is smaller than that of FIG. Then, the potential becomes closer to the surface of the insulating substrate 2 and becomes a potential distribution in accordance with a curved surface having a large radius of curvature at the end of the metal layer 4.
As a result, it is understood that the interval between the equipotential lines A is further increased, and the electric field is further alleviated.

Next, FIG. 4 shows how the value of the maximum electric field appearing on the upper surface of the insulating substrate 2 depends on the radius of curvature at the end of the metal layer 4 in the relationship between the radius of curvature and the relative electric field value. In the characteristic diagram shown, the points indicated by the triangles in the figure are the electric field values at the portion A in the prior art shown in FIG.

In FIG. 4, the electric field in the portion B in FIG. 2 is reduced to about 75% as compared with the portion A in the prior art.
Furthermore, the electric field at the part C in FIG. 3 is reduced to about 37%, which is actually less than half that of the part A of the prior art. Therefore, according to the embodiment of the present invention, the electric field can be greatly reduced, and as a result, the effective electric field can be alleviated, and the creepage withstand voltage performance of the insulating substrate 2 can be easily improved.

In FIG. 4, the symbol Δ indicates the electric field at the end on the side of the base substrate 1 in the portion D of FIG. 3, that is, in the periphery of the recess 20 of the insulating substrate 2 (end of the metal layer 4). From this characteristic, the radius of curvature is 0.18.
mm, smaller than the electric field on the surface of the insulating substrate 2,
Preferred electric field values are shown.

However, this radius of curvature is 0.19 m.
When the distance exceeds m, the electric field becomes larger than the electric field on the surface of the insulating substrate 2 and the electric field reaches the limit.
It can be said that the radius of curvature at the periphery of the recess 20 (the end of the metal layer 4) of the insulating substrate 2 is preferably in the range of 0.01 mm to 0.18 mm.

As can be seen from FIG. 4, the maximum electric field decreases as the radius of curvature R increases.
It is understood that the electric field is remarkably reduced by providing a curved surface portion having a radius of curvature in the periphery of 0, and the creepage of the insulating substrate 2 can be improved by the relaxation of the electric field. High breakdown voltage can be achieved without increasing the size. That is, according to the embodiment of the present invention, the size of the insulating substrate 2 can be reduced.

By the way, in such a semiconductor device, the circuit-side conductor is joined to the surface of the insulating substrate by the brazing material. At this time, in the related art, the surface of the insulating substrate is a substantially smooth flat surface. Since the circuit-side conductor is also formed with a substantially smooth plane, the brazing material tends to protrude from the end of the circuit-side conductor after brazing.

However, in the embodiment of the present invention, since the brazing material is formed in the concave portion 20 of the insulating substrate 2, the protruding range of the brazing material can be limited by the concave portion 20, and as a result, the insulation distance is reduced. It is always kept as designed. Therefore,
According to the embodiment of the present invention, the substantial insulation distance along the surface of the insulating substrate can always be maintained correctly, so that it is not necessary to increase the size of the insulating substrate with a margin, and the size of the insulating substrate can be sufficiently reduced.

Next, another embodiment of the present invention will be described. First, FIG. 5 shows a second embodiment of the present invention. This embodiment is different from the embodiment of FIG. 1 in that the depth of the concave portion 20 of the insulating substrate 2 is not uniform, and the periphery of the concave portion 20 is not changed. The point is that a curved surface portion 20A having a predetermined radius of curvature is provided at a portion where the end of the circuit-side conductor 3 is located at the edge.

The metal layer 4 is formed so as to fill the concave portion 20 including the curved surface portion 20A. As a result, as in the embodiment of FIG. Electric field concentration is relaxed. Therefore, according to the embodiment of FIG. 5, the concentration of the electric field at the end of the metal layer 4 can be effectively reduced, and the average thickness of the insulating substrate 2 due to the recess 20 can be reduced. Since the reduction in mechanical strength of the substrate 2 can be suppressed and the volume of the recess 20 can be reduced, the material required for the metal layer 4 can be reduced.

Next, FIG. 6 shows a third embodiment of the present invention.
This embodiment differs from the embodiment of FIG.
The point of this is that the depth of 0 is increased, and the circuit-side conductor 3 enters the concave portion 20 so that the upper surface thereof and the upper surface of the insulating substrate 2 are arranged substantially on the same plane.

In this embodiment, since the concave portion 20 is formed deep, the circuit-side conductor 3 is disposed on the insulating substrate 2 in a state where it enters the concave portion 20, and the metal layer 4 is formed. Is formed between the wall surface rising around the concave portion 20 and the side end surface of the circuit-side conductor 3. At this time, the bottom end around the concave portion 20 has a curved surface. 1 is the same as the embodiment of FIG. 1, and the point that the electric field concentration is reduced here is also the same as the embodiment of FIG.

Therefore, according to the embodiment shown in FIG.
As in the embodiment of FIG. 1, the electric field concentration can be effectively alleviated, and the metal layer 4 is embedded in the insulating substrate 2.
Since the dimension in the height direction is reduced, there is an advantage that the size of the semiconductor device can be further reduced.

Next, FIG. 7 shows another embodiment of the present invention. The embodiment shown in FIG. 7 is a modification of the third embodiment shown in FIG. The difference is that the metal layer 4 is not formed on the entire concave portion 20, but the end portion is formed in a curved surface by the relatively thin metal layer 4.

For this reason, the metal layer 4 is not filled in the entire recess 20, but is formed only on the bottom surface and the surrounding wall surface of the recess 20 while leaving the space around the circuit-side conductor 3. Become.

Therefore, according to the embodiment shown in FIG.
As in the embodiment of FIG. 6, the electric field concentration can be effectively alleviated, and the dimension in the height direction can be reduced because the metal layer 4 is also embedded in the insulating substrate 2, so that the semiconductor device can be downsized. become.

FIG. 8 shows the results of conducting a commercial frequency dielectric strength test and measuring the dielectric strength characteristics of the semiconductor device according to the embodiment of the present invention in order to confirm the dielectric strength in a high voltage use state. When the withstand voltage of the semiconductor device according to the prior art is 100%, the withstand voltage of the semiconductor device according to the embodiment of the present invention is about 130%.

As described above, according to the embodiment of the present invention,
It can be seen that as a result of forming the end portion of the metal film on a curved surface by the concave portion formed in the insulating substrate, the withstand voltage characteristic of the semiconductor device has been significantly improved. In addition, the concave portion formed in the insulating substrate makes it possible to eliminate a corner from the end of the metal layer where the electric field is most likely to concentrate, and as a result, the electric field concentration is greatly reduced.

[0050]

According to the present invention, a concave portion is provided in an insulating substrate, and an end portion of a metal layer provided in this portion is formed into a curved surface so that a corner portion is eliminated from the end portion of the metal layer. Therefore, the electric field intensity in the portion where the electric field is most likely to be concentrated is greatly reduced, and the creepage withstand voltage performance of the insulating substrate can be greatly improved.

Further, since the metal layer is formed in the concave portion of the insulating substrate, there is no possibility that the metal member protrudes. As a result, the creepage insulation distance of the insulating substrate can be effectively utilized, so that the insulating substrate can be enlarged. Without this, it is possible to sufficiently maintain the surface withstand voltage.

Therefore, according to the present invention, it is possible to sufficiently reduce the size of the semiconductor device without deteriorating the high withstand voltage characteristics thereof, and it is possible to easily provide a small and high withstand voltage semiconductor device.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention.

FIG. 2 is an explanatory diagram showing an equipotential distribution of a semiconductor device according to the present invention.

FIG. 3 is an explanatory diagram showing an equipotential distribution of a semiconductor device according to the present invention.

FIG. 4 is a characteristic diagram showing an electric field relaxation effect of the semiconductor device according to the present invention.

FIG. 5 is a sectional view showing a second embodiment of the semiconductor device according to the present invention.

FIG. 6 is a sectional view showing a third embodiment of the semiconductor device according to the present invention.

FIG. 7 is a sectional view showing a fourth embodiment of the semiconductor device according to the present invention.

FIG. 8 is a characteristic diagram showing withstand voltage characteristics of the semiconductor device according to the present invention and the semiconductor device according to the related art.

FIG. 9 is a plan view showing an example of a power semiconductor module.

FIG. 10 is a cross-sectional view illustrating an example of a semiconductor device according to the related art.

FIG. 11 is an explanatory diagram showing an equipotential distribution of a semiconductor device according to a conventional technique.

[Explanation of symbols]

 Reference Signs List 1 base substrate 2 insulating substrate 3 circuit-side conductor 4 metal layer 5 semiconductor element 20 concave portion 20A curved surface portion

Claims (2)

[Claims] 1. A semiconductor device comprising: a circuit-side conductor disposed on one surface of an insulating substrate with a metal layer interposed therebetween; and a semiconductor element disposed on the other surface of the circuit-side conductor. A semiconductor device, wherein a concave portion whose peripheral end is formed as a curved surface is provided on the surface of the semiconductor device, and the circuit-side conductor is provided in the concave portion via the metal layer. 2. The semiconductor device according to claim 1, wherein a radius of curvature of the curved surface is in a range of 0.01 mm to 0.18 mm.