JP2001035148A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor, for which a timer circuit is not required for refresh control outside a DRAM, concerning the data processor provided with the DRAM. SOLUTION: A refresh timer circuit 4 for self-refresh mode inside a DRAM 1 periodically generates a time-up signal 6 for performing refresh operation for holding cell data. This time-up signal 6 is generated at all the time in spite of the refresh mode and outputted to an outside of the DRAM 1. This time-up signal 6 is transferred to a DRAM control circuit 5 inside a logic LSI 3. In the DRAM control circuit 5, all access requests from plural control parts inside the logic LSI 3 are waited according to this time-up signal 6 and a control signal 7 is outputted to the DRAM 1 at timing required for the refresh operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device or a data processing device including the semiconductor memory device, and more particularly to a refresh technique for a dynamic random access memory.

[0002]

2. Description of the Related Art Conventionally, refresh control of a dynamic random access memory (hereinafter simply referred to as DRAM) is generally performed by a user of a DRAM (system creator or the like) separately in a data processing device (on a system board). This is performed by creating a control circuit and inputting a refresh control signal (address signal, command signal, etc.) from the refresh control circuit to the DRAM. As a specific refresh control method, for example, a self-refresh method is known. In the following description, the logical negation of a signal is represented by adding "/" in front of the name of the target signal.

[0003] The self-refresh system incorporates a refresh timer and enables a refresh to be performed automatically when the time is up. / CAS
DRAM at before / RAS refresh timing
, And after that, the DRAM is automatically refreshed by fixing the potentials of / CAS and / RAS. When refreshing is performed by this method, since the potentials of / CAS and / RAS need to be fixed, normal operation cannot be performed between refresh operations.

FIG. 4 shows a block diagram of a conventional data processing apparatus. The DRAM 51 has a refresh timer circuit 54 for a self-refresh mode. The refresh timer circuit 54 periodically generates a time-up signal for performing a refresh operation for holding data of the DRAM cell, and operates only in the self-refresh mode.

[0005] The logic LSI 53 has a DRAM control circuit 55 for controlling access to the DRAM 51. The DRAM control circuit 55 has a timer circuit 58 for performing a refresh operation while performing a normal operation for the DRAM 51. That is, in the self-refresh method, the refresh timer circuit 54 in the DRAM 51 operates only in the self-refresh mode and cannot be used during the normal operation. Therefore, the timer circuit 58 is used to perform the refresh control during the normal operation. Is required. The timer circuit 58 generates a time-up signal by counting the number of external clocks or internal clocks.
The control circuit 55 performs a refresh operation of the DRAM 51 via the control signal 7.

The MPU 2 is connected to a logic LSI 5 via a bus.
3 is controlled. The cycle setting of the time-up signal generated by the timer circuit 58 is also controlled by the MPU.

As a technique of the DRAM control circuit, for example, a "refresh control circuit of a storage device" described in Japanese Patent Application Laid-Open No. 7-320481 is known.

[0008]

However, in the conventional configuration, it is necessary to redesign the timer circuit 58 when the clock frequency of the logic LSI is changed, and there is a problem that the development period is lengthened.

The hold time, which is the refresh cycle of the DRAM, differs depending on the type of the DRAM. Therefore, a means (for example, a register) for changing the count value is required in the timer circuit 58 to cope with the change.
There is a problem that the chip area is enlarged. Further, when the means for changing the count value is constituted by a register, a software write operation to the register is required, and there is a problem that the development cost increases.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a data processing apparatus including a DRAM which realizes a reduction in development period, cost, and area. Is to provide.

[0011]

According to a first aspect of the present invention, there is provided a data processing apparatus comprising: a semiconductor memory device comprising a dynamic memory cell; and a refresh operation of the semiconductor memory device. A timer circuit that constantly and periodically generates a time-up signal for performing the control, and a control circuit that generates a signal for performing a refresh control of the semiconductor memory device according to an output signal of the timer circuit. The main point is to do.

According to such a configuration, the timer circuit of the semiconductor memory device can generate a time-up signal regardless of whether the self-refresh mode is set. The time-up signal is taken in by the control circuit that controls the refresh operation, so that the control circuit can output the control signal at the refresh timing every time the time-up signal is output. As a result, the control circuit does not need a timer circuit for refreshing the semiconductor memory device.

The data processing apparatus according to the second aspect of the present invention is characterized in that a circuit for setting a cycle for generating the time-up signal is provided.

According to such a configuration, a time-up signal is generated according to a circuit in which a frequency is set in advance so as to satisfy a refresh time required by the semiconductor memory device, so that setting of a refresh cycle is not required.

According to a third aspect of the present invention, there is provided a data processing apparatus, comprising: a semiconductor memory device comprising a dynamic memory cell; and a timer for periodically generating a time-up signal for performing a refresh operation of the semiconductor memory device. In a data processing device including a circuit and a control circuit that controls a refresh operation of the semiconductor memory device, the timer circuit includes a circuit that constantly oscillates a basic clock and a circuit that divides the basic clock. A circuit that sets a refresh cycle, and a circuit that selects one of a plurality of clocks generated by the frequency dividing circuit based on an output signal of the setting circuit and outputs the selected signal to the outside, and the control circuit includes:
The gist of the invention is that a signal for performing refresh control of the semiconductor memory device is generated according to an output signal of the timer circuit.

According to this configuration, since the basic clock is always generated, the time-up signal generated by the timer circuit of the semiconductor memory device can be generated regardless of whether the self-refresh mode is set. . The time-up signal is taken in by the control circuit that controls the refresh operation, so that the control circuit can output the control signal at the refresh timing every time the time-up signal is output. As a result, the control circuit does not need a timer circuit for refreshing the semiconductor memory device.

Further, since a time-up signal is generated according to a circuit whose frequency is set in advance so as to satisfy a refresh time required by the semiconductor memory device, it is not necessary to set a refresh cycle.

The time-up signal is a timing signal for starting a refresh operation of the semiconductor memory device.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data processing apparatus according to the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram schematically showing a configuration of a data processing device according to an embodiment of the present invention. DR
AM1 has a refresh timer circuit 4 for the self-refresh mode. The refresh timer circuit 4 periodically generates a time-up signal 6 in order to perform a refresh operation for holding data of the DRAM cell. This time-up signal 6 is generated irrespective of whether or not the self-refresh mode has been entered, and is output to the outside of the DRAM 1.

Then, the time-up signal 6 is input to the logic LSI 3 and transmitted to the DRAM control circuit 5 provided inside the logic LSI 3. The DRAM control circuit 5 arbitrates DRAM access requests from a plurality of control units inside the logic LSI 3.
According to the time-up signal 6 from AM1, the logic L
All the access requests from the plurality of control units inside the SI 3 are made to wait, and the control signal 7 is output to the DRAM 1 at a timing necessary for the refresh operation. Note that the DRAM 1 corresponds to the semiconductor memory device of the present invention.

FIG. 2 shows a DRAM according to an embodiment of the present invention.
One example of the internal refresh timer circuit 4 is shown. The conventional refresh timer circuit for self-refresh uses / CAS before / R to reduce current consumption.
The circuit operation is started only when the self-refresh mode is set by the DRAM control signal input method AS, but in the present invention, the refresh timer circuit is always operated regardless of this input method.

That is, in the prior art, the NA inside the ring oscillator is
The oscillation of the ring oscillator is stopped by arranging the ND gate and adopting the method of inputting "L" to one side of the NAND gate except in the self-refresh mode. Reference numeral 8 always oscillates the basic clock 9 by not using a gate for stopping oscillation depending on the mode.

The internal basic clock 9 generated by the ring oscillator 8 is a TFF (Toggle Flip Flood).
In p) 10, the frequency is divided into two and four times. The selector 12 selects and outputs one of the divided clocks of the plurality of basic clocks output from the TFF 10. That is, TFF
A plurality of signals having a frequency multiplied by an integer (power of 2) of the basic clock 9 are generated by 10, and one of them is selected by the selector 12, and this is used as the time-up signal 6.

The frequency signal to be selected by the selector 12 is determined according to the signal from the frequency setting ROM 11. A refresh time required by the DRAM 1 is given in advance to the frequency setting ROM 11 by a register, a fuse, or the like.

In this way, the time-up signal 6 is generated and output to the outside. Further, the time-up signal 6 is also an original signal of the refresh operation inside the DRAM. In the present embodiment, the refresh operation signal inside the DRAM includes a signal for a refresh operation inside the DRAM so that the signal does not operate internally in a mode other than the self refresh mode.
Internal / RAS 14 which is a signal obtained by gating the output of self-refresh mode determination circuit 13 to a time-up signal
Use Note that the ring oscillator 8 corresponds to a circuit for constantly oscillating the basic clock of the present invention. Also, TFF1
0 corresponds to the circuit for dividing the basic clock of the present invention.
Further, the frequency setting ROM 11 corresponds to a circuit for setting a cycle for generating a time-up signal of the present invention or a circuit for setting a refresh cycle. Also, the selector 12
Is one of a plurality of clocks generated by the frequency dividing circuit of the present invention.
One is selected by the output signal of the setting circuit, and corresponds to a circuit that outputs the time-out signal to the outside.

FIG. 3 shows an example of a timing chart of signals between the DRAM 1 and the logic LSI 3 in the data processing apparatus according to the embodiment of the present invention. The logic LSI 3 has a DRA as a temporary storage of instructions and data for arithmetic processing.
A write operation and a read operation are performed on M1. This write operation or read operation is called a normal operation. Until the time-up signal 6 is generated (a positive pulse in this example), the logic LSI 3 performs a normal operation on the DRAM 1 via the control signal 7.

In the example of FIG. 3, the signals are output to / RAS and / CAS at timings necessary for the page mode operation. When the time required for the refresh operation of the DRAM 1 elapses from the previous refresh operation, the DRAM 1 outputs a time-up signal 6, which is input to the logic LSI 3.

Since the time-up signal 6 from the DRAM 1 to the logic LSI 3 is asynchronous with an external (internal) clock of the logic LSI 3,
Synchronize with the external (internal) clock of SI3. Due to the generation of this synchronization signal, the DRAM inside the logic LSI 3
The control circuit 5 interrupts the output of the control signal for the normal operation to the DRAM 1 and shifts to the output of the control signal for the refresh operation (outputs the / CAS before / RAS refresh signal in the figure).

That is, upon receiving the synchronized time-up signal, the DRAM control circuit 5 returns / RAS and / CAS to "H" to interrupt the normal operation. Subsequently, signals are applied to / RAS and / CAS at the timing of / CAS before / RAS refresh. At the timing of / CAS before / RAS refresh, DRAM 1 outputs / RAS and / C
The refresh operation is performed by inputting AS. After the refresh operation ends, the operation returns to the normal operation before the refresh operation again. Time-up signal is DRAM
The above operation is repeated every time the signal is output from 1 to the logic LSI 3.

As described above, according to the data processing apparatus of the above embodiment, the following effects can be obtained.

(1) According to the present embodiment, since the ring oscillator 8 is always operated, the time-up signal 6 generated by the refresh timer 4 in the DRAM 1 is output regardless of whether or not the self-refresh mode is set. Can be generated. The time-up signal 6 is taken in by the logic LSI 3, so that the DRAM inside the logic LSI 3 is output every time the time-up signal is output.
The control circuit 5 can output the control signal 7 at a refresh timing. As a result, the DRAM control circuit 5 in the logic LSI 3 does not need a timer circuit for refreshing the DRAM 1, so that the development period and the chip area can be reduced.

(2) According to the present embodiment, the time-up signal 6 is generated in advance according to the frequency setting ROM 11 composed of registers, fuses and the like so as to satisfy the refresh time required by the DRAM 1, and this signal is output. Every time the DRAM control circuit 5 in the logic LSI 3
Automatically outputs the control signal 7 for the refresh operation. This eliminates the need for the MPU 2 to set the refresh cycle for the logic LSI 3.
Software can be simplified and MPU development cost can be reduced.

It is to be noted that each of the above-described embodiments can be implemented by changing the configuration as follows.

(1) In the above embodiment, the DRAM
Although the control circuit 5 is configured inside the logic LSI 3, the DRAM control circuit 5 may be an independent LSI.

(2) In the above embodiment, the logic LSI 3 may be the MPU 2.

(3) In the above embodiment, the logic LSI 3 may include the MPU 2.

(4) In the above embodiment, the MPU 2
And the logic LSI 3 and the DRAM 1 may be blocks constituting the same LSI.

[0039]

According to the data processing apparatus of the present invention, the timer circuit for performing the refresh operation at the time of the normal operation, which is conventionally built in the control circuit, becomes unnecessary, and the development period is shortened, the cost is reduced, and the area is reduced. Reduction can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a data processing device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a refresh timer inside the semiconductor memory device according to the embodiment of the present invention;

FIG. 3 is a timing chart of signals between a DRAM and a logic LSI in the data processing device according to the embodiment of the present invention;

FIG. 4 is a block diagram of a conventional data processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... DRAM 2 ... MPU 3 ... Logic LSI 4 ... Refresh timer 5 ... DRAM control circuit 6 ... Time-up signal 7 ... DRAM control signal 8 ... Ring oscillator 9 ... Refresh basic clock 10 ... TFF 11 ... Refresh cycle setting ROM 12 ... Selector 13: Self-refresh mode determination circuit 14: Internal / RAS

Claims (3)

[Claims] A semiconductor memory device comprising a dynamic memory cell; a timer circuit for constantly generating a time-up signal for performing a refresh operation of the semiconductor memory device; and a timer circuit according to an output signal of the timer circuit. A control circuit for generating a signal for performing refresh control of the semiconductor memory device;
A data processing device comprising: 2. The data processing apparatus according to claim 1, further comprising a circuit for setting a cycle for generating the time-up signal. 3. A semiconductor memory device comprising a dynamic memory cell, a timer circuit for periodically generating a time-up signal for performing a refresh operation of the semiconductor memory device, and controlling a refresh operation of the semiconductor memory device. A timer circuit, a circuit that constantly oscillates a basic clock, a circuit that divides the basic clock, a circuit that sets a refresh cycle, and a frequency divider circuit. A circuit which selects one of a plurality of clocks generated by the output circuit from the output signal of the setting circuit and outputs the selected signal to the outside as a time-up signal, wherein the control circuit controls the semiconductor in response to an output signal of the timer circuit. A data processing device for generating a signal for performing refresh control of a storage device.