JP2000243917A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and its manufacturing method, in which an enhancement-type transistor and a depression-type transistor with good reproducible threshold voltages are formed on the same substrate. SOLUTION: A thickness (da) of an electron feeding layer 4 of an enhancement-type transistor is made smaller than a thickness (db) of an electron feeding layer 4 of the depression-type transistor. The thickness (da) of the electron feeding layer 4 of the enhancement-type transistor is 75 to 90% of the thickness (db) of the electron feeding layer 4 of the depression-type transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device in which two types of transistors, an enhancement type transistor and a depletion type transistor, are formed on the same substrate, and a method of manufacturing the same.

[0002]

2. Description of the Related Art In recent years, with the demand for higher speed of computer systems, higher speed and lower power consumption of integrated circuit devices are required. In particular, GaAs has a large electron mobility as compared with Si, and is therefore expected to be applied to small computers.

When a compound semiconductor integrated circuit device is constructed, a DCFL (Direct FLASH) is used as a basic inverter circuit.
Coupled FET Logic) circuit is often used.
An enhancement type FET (hereinafter, referred to as E-type FET) is a driving element, and a depletion type FET (hereinafter, D-type FET).
Is used as a load element. The threshold voltage Vth of the E-type and D-type FETs is determined by the thickness of the carrier supply layer or the threshold voltage control layer.

Japanese Patent Application Laid-Open No. 2-148740 discloses an E type and a D type.
A method for manufacturing a FET of the same type on the same substrate is disclosed. That is, as shown in FIG. 9, a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 2-148740 has a semi-insulating GaAs.
An undoped GaAs layer 203 having a thickness of 500 nm serving as a channel layer and a thickness 3 serving as an electron supply layer
A 0 nm n-type AlGaAs layer 204, and a 10 nm thick fourth n-type Ga layer serving as a threshold voltage control layer in a D-type FET.
An As layer 205a, an n-type AlGaAs layer 206a having a thickness of 5 nm as a third etching stopper layer, a third n-type GaAs layer 205b having a thickness of 15 nm as a contact layer,
5 nm-thick n-type A serving as a second etching stopper layer
lGaAs layer 206b, contact layer thickness 60n
m second n-type GaAs layer 207, 5 nm-thick n-type AlGaAs layer 20 serving as a first etching stopper layer
8. First n-type Ga having a thickness of 40 nm as a contact layer
An As layer 209 is sequentially formed, and a Schottky gate electrode of the E-type FET is an n-type AlGaAs as an electron supply layer.
In contact with the s layer 204, the Schottky gate electrode of the D-type FET is n-type AlGa as a third etching stopper layer.
It is in contact with the As layer 206a.

[0005]

However, in the above-mentioned conventional semiconductor device, there is a problem that the epitaxial growth is considerably complicated, so that defects are likely to occur, and that the manufacturing cost is increased. In addition, n of the E-type FET
-Type GaAs layer 207 and n-type GaAs layer 20 of D-type FET
9 are simultaneously isotropically selectively etched, since the thicknesses of the n-type GaAs layers to be etched are greatly different, the thinner D-type FET has a larger over-etching amount and a larger side etching amount. There is a problem that it will increase.

According to the present invention, the threshold voltage Vth of an enhancement transistor is increased without increasing the manufacturing cost.
It is an object of the present invention to provide a semiconductor device capable of manufacturing a threshold voltage Vth of a depletion type transistor on the same substrate with good reproducibility and a method for manufacturing the same.

[0007]

According to a first aspect of the present invention, a channel layer, an electron supply layer, and a contact layer are sequentially stacked on a semiconductor substrate to form an enhancement transistor. A semiconductor device in which two types of depletion type transistors are formed over the same substrate, wherein the thickness of the electron supply layer of the enhancement type transistor is smaller than the thickness of the electron supply layer of the depletion type transistor, The thickness of the electron supply layer of the enhancement transistor is 75% of the thickness of the electron supply layer of the depression transistor.
It is characterized by a thickness of about 90%.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, a first step of sequentially stacking a channel layer, an electron supply layer, and a contact layer on the semiconductor substrate; A second step of forming an etching mask having an opening in the gate forming region, selectively etching the contact layer in the gate forming region of the enhancement transistor with respect to the electron supply layer through the etching mask; A third step of forming an oxide layer, and a fourth step of selectively etching the contact layer in the gate formation region of the depletion transistor with respect to the electron supply layer through an etching mask having an opening in the gate formation region of the depletion transistor. And etching the oxide layer formed in the third step. And a fifth step of grayed, are characterized by performing the fourth step and the fifth step simultaneously.

According to a third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, an electron beam resist is used as the etching mask.

According to a fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, an insulating film is used as the etching mask.

[0011]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration example of a semiconductor device according to the present invention. Referring to FIG. 1, in this semiconductor device, a buffer layer 2, a channel layer 3, an electron supply layer 4, and a contact layer 5 are sequentially stacked on a semiconductor substrate 1. Then, the enhancement type transistor (E type FET region) and the depletion type transistor (D type FE
An element isolation region 6 for isolating the element isolation region (T region) is formed. In the enhancement type transistor, a source electrode 7 and a drain electrode 8 are formed on the contact layer 5, and a recess groove 9 is formed in the contact layer 5 and the electron supply layer 4 to a predetermined depth. The gate electrode 10 is formed on the electron supply layer 4 opened by 9. In the depletion type transistor, a source electrode 11 and a drain electrode 12 are formed on the contact layer 5, and a recess 13 is formed in the contact layer 5, and the electron supply layer opened by the recess 13 is formed. 4, a gate electrode 14 is formed.

In the present invention, the thickness da of the electron supply layer 4 of the enhancement transistor is smaller than the thickness db of the electron supply layer 4 of the depression transistor. In this case, the electron supply layer 4 of the enhancement transistor is formed. Is 75 to 90% of the thickness db of the electron supply layer 4 of the depletion type transistor.

More specifically, the threshold voltage Vth of a HEMT (high mobility field effect transistor) is generally given by the following equation.

[0014]

Vth = ΦΒ−ΔΦc−Φf−V _dep

Here, ΦΒ is a Schottky barrier potential between the gate metal (gate electrode) and the electron supply layer.
For example, when the gate electrode is Ti / Pt / Au and the electron supply layer is n-AlGaAs, the Schottky barrier potential Φ バ リ ア is about 0.9V.
ΔΦc is the potential difference between the conduction band of the electron supply layer and the conduction band of the channel layer. For example, an electron supply layer _{n-Al x Ga (1-} x) As (x = 0.3), when the channel layer is GaAs, the potential difference between these conduction band is 0.3V. Φf is a Fermi potential depending on the conduction band of the channel layer, and depends on the two-dimensional electron gas concentration.
f = Φf ₀ + γNs ^2/3 Here, Φf ₀ is 57 meV, γ is 1.39E-6, Ns is the sheet carrier concentration of the two-dimensional electron gas, and Ns =
ε / ｛q (d + di)｝ Vth. Also, V
_dep = qN _d d ² / 2ε. From these equations, the relationship between the threshold voltage Vth and the thickness of the electron supply layer can be obtained. FIG. 2 shows that the carrier concentration of the electron supply layer is 2E18.
Relationship between the thickness of the case of [cm ^-3] and 1E18 [cm ^-3] threshold voltage Vth and the electron supply layer in the case is shown.

FIG. 2 shows that the DCF is formed by using the enhancement type transistor and the depletion type transistor.
In the case of configuring the L circuit, the thickness da of the electron supply layer 4 of the enhancement transistor is equal to the thickness db of the electron supply layer 4 of the depletion transistor, depending on the operating voltage.
Is preferably 75% to 90%. That is, the thickness da of the electron supply layer 4 of the enhancement type transistor is changed to the thickness db of the electron supply layer of the depression type transistor 4.
75% to 90% of the threshold voltage Vth of the enhancement type transistor and the threshold voltage Vth of the depletion type transistor on the same substrate with high reproducibility without increasing the manufacturing cost, as described later. Can be.

The semiconductor device shown in FIG. 1 can be manufactured by the following manufacturing steps. That is, a first step of sequentially stacking a buffer layer 2, a channel layer 3, an electron supply layer 4, and a contact layer 5 on a semiconductor substrate 1, and forming an etching mask having an opening in a gate formation region of an enhancement transistor. A second step of selectively etching the contact layer 5 in the gate formation region of the enhancement transistor with respect to the electron supply layer 4 through an etching mask; and a third step of forming an oxide layer on the surface of the electron supply layer 4. A fourth step of selectively etching the contact layer 5 in the gate formation region of the depletion type transistor with respect to the electron supply layer 4 through an etching mask having an opening in the gate formation region of the depletion type transistor; And a fifth step of etching the oxide layer formed in the step. By performing degree and the fifth step simultaneously it is produced.

In the above manufacturing process, an electron beam resist can be used as an etching mask. When an electron beam resist is used as an etching mask, a fine resist pattern can be formed, and a transistor with a short gate length can be manufactured.

In the above manufacturing process, an insulating film can be used as an etching mask. When an insulating film is used for the etching mask, the adhesion to the substrate is improved, and the occurrence of defects in the wet etching step can be prevented.

[0020]

Embodiments of the present invention will be described below.

Example 1 In Example 1, the semiconductor device of FIG. 1 was manufactured as follows. That is, a buffer layer 2 is epitaxially grown on a semi-insulating GaAs substrate 1 as a non-GaAs layer having a thickness of 100 nm.
A non-InGaAs layer having a thickness of 5 nm is epitaxially grown, an n-AlGaAs layer having a thickness of 50 nm (concentration: 1 × 10 ¹⁸ cm ⁻³ ) is epitaxially grown as the electron supply layer 4, and a contact layer 5 is formed. 50
n-GaAs layer with a thickness of nm (concentration: 3 × 10 ¹⁸ cm ⁻³ )
Was epitaxially grown.

And an enhancement type transistor
(E type FET region) and depletion type transistor (D
An element isolation region 6 for isolating the element isolation region 6 is formed.

In the enhancement type transistor, a source electrode 7 and a drain electrode 8 are formed on the contact layer 5, and a recess groove 9 is formed in the contact layer 5 and the electron supply layer 4 to a predetermined depth. The gate electrode 10 was formed on the electron supply layer 4 opened by the recess groove 9. In the depletion type transistor, the source electrode 11 and the drain electrode 12
In addition, a recess groove 13 was formed in the contact layer 5, and a gate electrode 14 was formed on the electron supply layer 4 opened by the recess groove 13.

That is, in the enhancement type transistor, the gate electrode 10 is formed on the high concentration n-AlGaAs layer 4 with the recess groove 9 formed. At this time, the depth of the recess groove 9 is n-AlGaAs as the electron supply layer.
It is about 10 nm in the s layer 4.

In the depletion type transistor, similarly to the enhancement type transistor, the gate electrode 14 has a high concentration n-A in which the recess groove 13 is formed.
Although arranged on the lGaAs layer 4, in the depletion type transistor, the depth of the recess groove 13 does not penetrate into the n-AlGaAs layer 4 which is an electron supply layer.

Further, the source electrodes 7, 1 of the enhancement type transistor and the depletion type transistor are provided.
The drain electrodes 8 and 12 are formed of ohmic contact electrodes (ohmic electrodes) made of an AuGe / Ni / Au alloy. In addition, the gate electrode 1 of the enhancement type transistor and the depletion type transistor
Reference numerals 0 and 14 are formed by electrodes of a Schottky contact of Ti / Au.

FIGS. 3 to 5 are diagrams showing more detailed examples of the manufacturing process. Referring to FIGS. 3 to 5, semi-insulating G
On the aAs substrate 1, the MBE method or the MOVPE method is used.
A buffer layer 2, a channel layer 3, an electron supply layer 4, and a contact layer 5 are sequentially grown (FIG. 3A). Next, the source electrodes 7, 11 and the drain electrodes 8, 1 are lifted off.
2 is formed (FIG. 3B). Next, the element region is covered with a photoresist, and etched to a depth of about 150 nm with a phosphoric acid-based etchant to form an element isolation region 6 (FIG. 3C).

Next, after an electron beam resist 20 is applied to the entire surface, an electron beam is irradiated to the gate formation region of the enhancement type transistor by electron beam exposure. Thereafter, development is performed to form an opening 21 in the electron beam resist 20. Next, the contact layer 5 in the gate formation region is removed with a citric acid-based etchant that is a selective etchant of GaAs / AlGaAs, and the recess groove 9 is formed. It is formed (FIG. 4D). At this time, the AlGaAs layer 4 serving as the electron supply layer is exposed.
Next, in order to remove the electron beam resist 20, ashing (ashing treatment) is performed with oxygen plasma. The conditions at this time are as follows: RF power is 200 W, pressure is 1 Toor, and 20
Do for a minute. At this time, an oxide layer 30 is formed on the surface of the AlGaAs layer 4 by oxygen plasma (FIG. 4E).

Next, an electron beam resist 31 is applied again on the entire surface, and openings 32 are opened in the gate formation region of the depletion type transistor and the gate formation region of the enhancement type transistor by electron beam exposure (FIG. 4F).

Next, it is immersed in a thin alkaline solution for several seconds.
In this step, the oxidized AlGaAs layer 30 of the enhancement transistor is removed, and the n-AlGaAs layer 4 is etched to a depth of about 5 nm. Also, the contact layer 5 of the depletion type transistor has a thickness of 5 nm.
Etching is performed to a depth of about (FIG. 5 (g)).

Next, the contact layer 5 in the gate formation region of the depletion type transistor is etched with a citric acid based etchant which is a selective etchant of GaAs / AlGaAs, exposing the n-AlGaAs layer 4 on the substrate surface (FIG. 5 (h)). After that, Ti to be a gate electrode
/ Au is deposited on the entire surface and then lifted off to form gate electrodes 10 and 14 (FIG. 5 (i)).

The Vth and ft of the FET having a gate length of 0.3 μm obtained by such a manufacturing method are as shown in the following table.

[0033]

[Table 1]

That is, the threshold voltage Vth of the enhancement type transistor can be set to 0.02 V, and the threshold voltage Vth of the depletion type transistor is set to -0.0.
It could be set to 52V.

As described above, in Example 1, the enhancement type transistor and the depletion type transistor could be formed on the same substrate without complicating the epi structure.

Example 2 In Example 2, a semiconductor device was manufactured by the manufacturing steps shown in FIGS. 6 to 8, the semi-insulating GaAs substrate 1 is similar to the process example of FIGS.
On top of this, a buffer layer 2 of 10
A non-GaAs layer having a thickness of 0 nm, a non-InGaAs layer having a thickness of 15 nm as the channel layer 3, an n-AlGaAs layer having a thickness of 50 nm as the electron supply layer 4 (concentration is 1 × 10 ¹⁸ cm ⁻³ ), 50 nm as the contact layer 5
N-GaAs layers (concentration: 3 × 10 ¹⁸ cm ⁻³ ) were sequentially laminated. Next, the source electrode 7,
11 and drain electrodes 8 and 12 are formed. Next, an element isolation region 6 is formed by covering the element region with a photoresist and etching it to a depth of about 150 nm with a phosphoric acid-based etchant. Next, an SiO ₂ film 4 is formed by PCVD.
0 is formed to a thickness of 2000 ° (FIG. 3A).

Next, after an electron beam resist 41 is applied to the entire surface, an electron beam is irradiated to the gate forming region of the enhancement type transistor by electron beam exposure, and then development is performed to form an opening 42 in the electron beam resist 41. Then R
An opening 43 is formed in the SiO ₂ film 40 by an IE (Reactive Ion Etching) method (FIG. 6B).

Next, the contact layer 5 in the gate formation region of the enhancement transistor is removed with a citric acid-based etchant, and a recess groove 9 is formed. At this time, A
The lGaAs layer 4 is exposed (FIG. 6C). Next, in order to remove the electron beam resist 41, ashing (ashing process) is performed with oxygen plasma. The condition at this time is that the RF power is 200 W and the pressure is 1 Toor for 20 minutes. At this time, an oxide layer 50 is formed on the surface of the AlGaAs layer 4 by oxygen plasma (FIG. 7D).

Next, an electron beam resist 51 is applied again on the entire surface, an opening 52 is opened in the gate formation region of the depletion type transistor by electron beam exposure, and then RIE is performed again.
An opening 53 is formed in the SiO ₂ film 40 by a (Reactive Ion Etching) method (FIG. 7E). Next, in order to remove the electron beam resist 51, ashing (ashing treatment) is performed with oxygen plasma. The condition at this time is
RF power is 200 W, pressure is 1 Toor, and it is performed for 20 minutes. At this time, an oxide layer 54 is formed on the surface of the AlGaAs layer 4 by oxygen plasma (FIG. 7F).

Next, a resist pattern 62 having openings 60 and 61 in the gate formation regions of both the enhancement type transistor and the depletion type transistor is formed by photolithography.
When an alkaline developer is used to form the resist pattern 62, the oxidized AlGaAs layer 50 in the gate formation region of the enhancement transistor is removed, and the n-AlGaAs layer 4 is etched to a depth of about 5 nm. (FIG. 8 (g)). Next, the contact layer 5 in the gate formation region of the depletion type transistor is etched with a citric acid-based etchant to expose the n-AlGaAs layer 4 on the substrate surface (FIG. 8 (h)). Thereafter, Ti / Au serving as a gate electrode is deposited on the entire surface, and then lift-off is performed to form gate electrodes 10 and 14 (FIG. 8).
(i)).

The Vth and ft of the FET having a gate length of 0.3 μm obtained by such a manufacturing method are as shown in the following table.

[0042]

[Table 2]

That is, the threshold voltage Vth of the enhancement type transistor can be set to 0.21 V, and the threshold voltage Vth of the depletion type transistor is set to -0.0.
It could be 35V.

As described above, in the second embodiment, the enhancement transistor and the depletion transistor can be formed on the same substrate without complicating the epi structure, and the FET having the gate structure can be formed. .

[0045]

As described above, according to the first aspect of the present invention, a channel layer, an electron supply layer, and a contact layer are sequentially stacked on a semiconductor substrate to form an enhancement transistor and a depletion transistor. 2
A semiconductor device in which different types of transistors are formed on the same substrate, wherein the thickness of the electron supply layer of the enhancement transistor is smaller than the thickness of the electron supply layer of the depression transistor; Since the thickness of the supply layer is 75% to 90% of the thickness of the electron supply layer of the depletion type transistor, the threshold voltage Vth of the enhancement type transistor and the threshold voltage of the depletion type transistor can be increased without increasing the manufacturing cost. The voltage Vth can be manufactured on the same substrate with good reproducibility.

According to the second aspect of the present invention, in the semiconductor device according to the first aspect, a first step of sequentially laminating a channel layer, an electron supply layer, and a contact layer on the semiconductor substrate; Forming an etching mask having an opening in the gate formation region of the type transistor,
A second step of selectively etching a contact layer in a gate formation region of the enhancement transistor with respect to the electron supply layer through an etching mask, a third step of forming an oxide layer on the surface of the electron supply layer, A fourth step of selectively etching the contact layer in the gate formation area of the depletion type transistor with respect to the electron supply layer through an etching mask having an opening in the gate formation area; and an oxide layer formed in the third step. A fifth step of etching,
Since the fourth step and the fifth step are performed at the same time, that is, the etching of the contact layer of the depletion type transistor and the etching of the oxide layer on the surface of the electron supply layer of the enhancement type transistor are simultaneously performed. In addition, the process can be simplified.

According to the third aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, since an electron beam resist is used as the etching mask, fine processing can be performed and high-frequency characteristics can be improved. Become.

According to the fourth aspect of the present invention, in the method of manufacturing a semiconductor device according to the second aspect, since an insulating film is used as the etching mask, the adhesion to the substrate can be improved and the wetness can be improved. Generation of defects in the etching step can be prevented. Further, a T-type gate structure as shown in Embodiment 2 can be easily manufactured.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration example of a semiconductor device according to the present invention.

FIG. 2 is a diagram illustrating a relationship between a threshold voltage of a HEMT and a thickness of an electron supply layer.

FIG. 3 is a diagram illustrating an example of a manufacturing process of a semiconductor device according to the present invention.

FIG. 4 is a diagram showing an example of a manufacturing process of the semiconductor device according to the present invention.

FIG. 5 is a diagram showing an example of a manufacturing process of the semiconductor device according to the present invention.

FIG. 6 is a diagram showing another example of the manufacturing process of the semiconductor device according to the present invention.

FIG. 7 is a diagram showing another example of the manufacturing process of the semiconductor device according to the present invention.

FIG. 8 is a diagram showing another example of the manufacturing process of the semiconductor device according to the present invention.

FIG. 9 is a diagram showing a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Buffer layer 3 Channel layer 4 Electron supply layer 5 Contact layer 7, 11 Source electrode 8, 12 Drain electrode 9, 13 Recessed groove 10, 14 Gate electrode 6 Element isolation region

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 29/812

Claims (4)

[Claims] 1. A semiconductor device comprising: a semiconductor substrate having a channel layer, an electron supply layer, and a contact layer, which are sequentially stacked to form an enhancement transistor and a depletion transistor;
A semiconductor device in which different types of transistors are formed on the same substrate, wherein the thickness of the electron supply layer of the enhancement transistor is smaller than the thickness of the electron supply layer of the depression transistor; A semiconductor device, wherein the thickness of the supply layer is 75% to 90% of the thickness of the electron supply layer of the depletion type transistor. 2. The semiconductor device according to claim 1, further comprising: a first step of sequentially stacking a channel layer, an electron supply layer, and a contact layer on the semiconductor substrate; and an opening in a gate formation region of the enhancement transistor. A second step of forming an etching mask and selectively etching a contact layer in a gate formation region of the enhancement transistor with respect to the electron supply layer through the etching mask; and a third step of forming an oxide layer on the surface of the electron supply layer. A fourth step of selectively etching the contact layer in the gate formation region of the depletion transistor with respect to the electron supply layer through an etching mask having an opening in the gate formation region of the depletion transistor; and the third step Fifth to etch the oxide layer formed by
And a step of performing the fourth step and the fifth step at the same time. 3. The method of manufacturing a semiconductor device according to claim 2, wherein an electron beam resist is used as said etching mask. 4. The method for manufacturing a semiconductor device according to claim 2, wherein an insulating film is used as said etching mask.