JP2000228097A - Non-volatile semiconductor memory, and its data write-in method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a non-volatile semiconductor memory and its data write-in method in which erroneous write-in of data can be prevented at the time of write-in operation though memory cell array constitution of a shared bit line type is adopted, while operation margin can be enlarged. SOLUTION: Relating to a NAND type flash memory having memory cell array structure of a shared bit line type, at the time of write-in operation, all NAND strings in a NAND string group sharing bit lines are selected, channels of all NAND strings are pre-charged to a first level by charging from a bit line side, while channels are made to be in a floating state, channels of all NAND string in a string group sharing bit lines are boosted to a second level being higher than the first level by capacity coupling with word lines. After that, NAND strings to be written out of a NAND string group sharing bit lines are selected, while a potential of each bit line is set to a potential in accordance with write-in data, effective write-in operation of data for a memory cell is started.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device and a data writing method thereof,
This is suitable for application to a so-called shared bit line type NAND flash memory in which one bit line is shared by a plurality of NAND strings.

[0002]

2. Description of the Related Art Conventionally, in a write operation of a NAND flash memory, as a method of preventing electron injection into a floating gate of a non-write cell existing on a word line to be written (selected word line), the non-write operation is performed. A self-boost method is known in which a NAND string including a cell is separated from a bit line by the action of a select transistor, and the channel potential of a non-written cell is raised to a predetermined write inhibit potential by capacitive coupling with a word line. I have.

A data writing method for a conventional NAND flash memory in which data is written to a memory cell using a self-boost method will be described below.

FIGS. 6 and 7 are an equivalent circuit diagram and a timing chart of a memory cell array used for explaining a data writing method of a conventional NAND flash memory using a self-boost method. This NAND
Type flash memory has one N per bit line.
It has a memory cell array structure to which AND strings are connected.

In FIG. 6, a NAND string A1 is connected to a bit line BL1, and a NAND string A2 is connected to a bit line BL2. The source line SL is N
This is common to the AND strings A1 and A2. These NAND strings A1 and A2 share word lines and select gate lines, and are NAND strings arranged in the same block of the memory cell array.

[0006] Of the select gate lines shared by the NAND strings A1 and A2, SGL1 indicates a select gate line on the bit line side, and SGL2 indicates a select gate line on the source line side. SWL indicates a selected word line, and PWL indicates a password line (non-selected word line).

In FIG. 7, bit lines BL1, BL2, select gate lines SGL1, SGL2,
Selected word line SWL, password line PWL, source line S
L is set, and the NAND string A
The potentials (channel potentials) of nodes N1 and N2 of A1 and A2 are indicated by Vch1 and Vch2.

Referring to the timing chart of FIG. 7, a specific operation in a conventional data writing method using the self-boost method will be described. here,
The bit line BL1 will be described as a non-write bit line (data “1” write), and the bit line BL2 will be described as a write bit line (data “0” write).

As shown in FIG. 7, first, a select gate line S
GL1, SGL2, the selected word line SWL, (the V _SS ground potential for example, 0V) password line PWL and the source line SL potential V _SS in a state of being set in each bit line BL
1 and BL2 are connected to a sense amplifier / data latch circuit (not shown), and the potentials of these bit lines BL1 and BL2 are set to potentials corresponding to the contents of write data set in the data latch circuit (time t0). ). In this case, the potential V _CC (V _CC is a power supply potential, for example, 3 V) is applied to the bit line BL1 which is a non-write bit line for writing data “1”.
, And a potential V _SS is supplied to a bit line BL2 which is a write bit line for writing data “0”. At this time, since the selection transistor connected to the selection gate line SGL1 on the bit line side is off, the NAN
The channels of the D strings A1 and A2 are separated from the bit lines BL1 and BL2, respectively.
1 and N2 are both at the potential V _SS .

In this state, when the potential of the select gate line SGL1 on the bit line side is set to the potential V _CC at time t1,
NAND string A1 written with data "1"
Node N1 of is charged to the potential (V _CC -Vthsg), node N2 of the NAND string A2, which is the data "0" is written is set to a potential V _SS. Here, Vthsg is a threshold voltage of the selection transistor on the bit line side connected to the selection gate line SGL1, and is, for example, about 1.5V. Therefore, in this case, the potential of the node N1 of NADN string A1 is charged to a potential (V _CC -Vthsg) is about 1.5V.

Next, at time t2, the potential of the selected word line SWL is raised to a predetermined program potential VPGM (for example, about 16 V), and the potential of the password line PWL is raised to a predetermined pass potential Vpass (<VPGM, for example, about 10 V). )
By raising the voltage to the maximum, writing of substantial data to the selected memory cell is started. At this time, in the NAND string A1 unwritten side, the entire channel potential becomes a potential (V _CC -Vthsg), select transistors on the bit line side are cut off. Therefore, the channel of the NAND string A1 is in a floating state, and is boosted to a write inhibit potential by capacitive coupling with a word line, mainly a password line. The channel potential of this time, the writing-side NAND string A2 is held at a potential V _SS.

[0012] The channel potential Vch1 of NAND string A1, which has been boosted to a write inhibit potential is, (V _CC -Vths
g) + α. Here, one item of this equation is the channel potential before the boost (when the selection transistor is cut off). Further, α of the two items is a boosted amount (> 0) by the self-boost, and in this case, ΔVpass−V
th− (V _CC −Vthsg)｝ × capacitive coupling ratio. Here, Vth is the threshold voltage of the memory cell after writing. Here, for example, when V _CC is 3 V, the threshold voltage Vth of the memory cell is 1 V, and the pass potential Vpass is 10 V, N
Assuming that the capacitance coupling ratio between the channel of the AND string and the word line is 0.5, (V _cc −V thsg) + α = 1.5 +
(10-1-1.5) × 0.5 = 5.25V. Therefore, in the memory cell on the selected word line SWL in the non-writing-side NAND string A1, the control gate has the program potential VPGM = 16V.
Is applied, the potential difference between the channel and the control gate is about 10.75 V, and data is not written because electron injection into the floating gate is prevented. On the other hand, in the memory cell on the selected word line SWL of the NAND string A2 on the write side, electrons are injected into the floating gate due to the electric field between the program potential VPGM and the channel potential applied to the control gate, and data writing is performed. Done.

After data is written to the selected memory cell for a predetermined time in this manner, at time t3,
When the selected word line SWL and the password line PWL have the potential V
Reset to _SS . As a result, the channel of the NAND string A1 charged to the write prohibition voltage has the potential V
Discharged to _SS . After a lapse of a predetermined time, at time t4,
Selection gate SGL1 the bit line side is reset to the potential V _SS. Thus, a series of write operations ends.
Thereafter, a write verify operation is performed.

As described above, a series of write operations in the conventional data write method using the self-boost method includes a step of “selecting a NAND string by a select gate line and setting a bit line potential according to write data”. This is roughly divided into the step of “floating and boosting the channel of the NAND string with the rise of the word line potential”.

[0015]

However, the conventional data writing method using the above-described self-boost method is different from a so-called shared bit line in which a plurality of NAND strings share one bit line.
) Type NAND flash memory,
Inconveniences such as erroneous writing of data occur.

Here, a shared bit line type NAND
Problems when the conventional data writing method using the above-mentioned self-boost method is applied to a flash memory of the type, for example, IEICE TRANCE.ELECTRON., Vol.E78-C
The configuration disclosed in No. 7 will be specifically described using an example.

FIGS. 8 and 9 are equivalent circuit diagrams of a memory cell array used to explain a write operation when a conventional data write method using a self-boost method is applied to a shared bit line type NAND flash memory. And a timing chart.

In FIG. 8, NAND strings A1,
A2 is both connected to bit line BL1, and NAND strings A3 and A4 are both connected to bit line BL2. The source line SL is common to the NAND strings A1 to A4. These NAND strings A1 to A1
A4 shares a word line and a select gate line,
They are arranged in the same block of the memory cell array.

Of the select gate lines shared by the NAND strings A1 to A4, SGL1 and SGL2 indicate select gate lines on the bit line side, and SGL3 indicates select gate lines on the source line side. SWL indicates a selected word line, and PWL
WL indicates a password line. Here, of the NAND strings A1 and A3, the select transistors connected to the select gate line SGL2 and the NAND strings A2 and A4
Among them, the selection transistor connected to the selection gate line SGL1 is a depletion type transistor having a threshold voltage of about -1.5 V, and the other selection transistors have a threshold voltage of about 1.5 V It is an enhancement type transistor of a certain degree.

In FIG. 9, bit lines BL1 and BL2, select gate lines SGL1 to SGL3, and
Selected word line SWL, password line PWL, source line S
L is set, and NAND strings A1,
The potential (channel potential) of the nodes N1 to N4 of A4 is Vch
1 to Vch4.

With reference to the timing chart of FIG. 9, a specific operation when a conventional data writing method using a self-boost method is applied to a shared bit line type NAND flash memory will be described.
Here, the bit line BL1 is used as a non-write bit line (data “1” write), the bit line BL2 is used as a write bit line (data “0” write), and a NAND string group sharing a bit line is selected. NAND string A selected by gate line SGL1
Description will be made assuming that data writing is performed using 1, A3 as a selected string. As shown in FIG. 9, first, when the selection gate lines SGL1 to SGL3, the selected word line SWL, the password line PWL, and the source line SL are set to the potential V _SS , each of the bit lines BL1 and BL2 is sensed / datad. The bit lines BL1 and BL2 are connected to a latch circuit (not shown), and the potentials of these bit lines BL1 and BL2 are set to potentials according to the contents of the write data set in the data latch circuit (time t0). In this case, the potential V _CC is supplied to the bit line BL1 which is a non-write bit line for writing data “1”, and the potential V _SS is supplied to the bit line BL2 which is a write bit line for writing data “0”. . At this time, since the select transistors connected to the select gate lines SGL1 and SGL2 on the bit line side are off, the NAND strings A1 to A4 are connected to the bit lines BL1 and BL1.
It is disconnected from BL2, node N1~N4 shall each a potential V _SS.

In this state, when the potential of the select gate line SGL1 on the bit line side is set to the potential V _CC at time t1,
NAND string A1 written with data "1"
Node N1 is charged to a potential (V _CC -Vthsg), the node N3 of the NAND string A3 which is the data "0" is written is held at a potential V _SS. Where Vthsg is
The threshold voltage of the selection transistor on the bit line side,
For example, it is about 1.5V. Therefore, in this case, NAND string A is charged to a potential (V _CC -Vthsg)
The potential of one node N1 is about 1.5V. Also, N
For the AND strings A2 and A4, the set potential of the select gate line SGL2 is the potential V _SS , so that the enhancement type select transistor connected to the select gate line SGL2 is off, and the channel is in a floating state.

Next, at time t2, the potential of the selected word line SWL is raised to the program potential VPGM (for example, about 16 V), and the potential of the password line PWL is raised to the pass potential Vpass (<VPGM, for example, about 10 V). As a result, writing of substantial data to the selected memory cell is started. At this time, the selected word line S
Threshold voltage of the potential of WL and password line PWL memory cell, at a higher voltage than (V _CC -Vthsg), the entire channel potential of the NAND string A1 is the potential (V _CC -Vthsg), the bit line The enhancement-type selection transistor on the side is cut off. For this reason, the channel of the NAND string A1 is in a floating state, and is boosted to a write potential by capacitive coupling with a word line, mainly an unselected word line. At this time, the node N3 of the NAND string A3 is set at the potential V
_Held by _SS .

[0024] The channel of potential Vch1 of write-protected NAND string has been boosted to the potential A1 is, (V _CC -Vth
sg) + α, for example, V _CC is 3 V, the threshold voltage Vth of the memory cell is 1 V, and the write pass potential Vpass is 1
In the case of 0 V, assuming that the capacitance coupling ratio between the channel of the NAND string and the word line is 0.5, (V _CC -Vthsg) +
α = 1.5V + (10-1-1.5) × 0.5 = 5.2
It becomes 5V. Therefore, in the memory cell on the selected word line SWL in the non-write-side NAND string A1, even if the program potential VPGM = 16 V is applied to the control gate, the potential difference between the channel and the control gate is about 10 Since the voltage is about 0.75 V and electron injection into the floating gate is prevented, no data is written. Further, in the memory cell on the selected word line SWL of the NAND string A3 on the write side, electrons are injected into the floating gate due to the electric field between the program potential VPGM and the channel potential applied to the control gate, and data writing is performed. Done. On the other hand, at this time, since the channels of the NAND strings A2 and A4, which are unselected strings, are also in a floating state, the voltage is boosted by capacitive coupling with the word line, but the word line potential is lower than the threshold voltage of the memory cell. In this case, since the channel is not formed, the capacitance coupling ratio is very small, and the substantial boosting operation is started when the word line potential becomes equal to or higher than the threshold voltage of the memory cell. These NAND string A2, A4 can not be charged from the bit line side, therefore, the boosting operation is started from the state of being floating at a potential V _SS. Therefore, these N
The boosted channel potentials of the AND strings A2 and A4 are lower than the boosted channel potentials of the NAND string A1. In this case, the channel potentials Vch2 and Vch4 of the boosted NAND strings A2 and A4 are V _SS + α.
. One item of this equation is the channel potential before boost. Further, α ′ of the two items is the boosted amount (> 0) by the self boost, and in this case, (Vpass−Vth
−V _SS ) × capacitive coupling ratio. Here, Vth is the threshold voltage of the memory cell after writing. Here, for example, V _SS is 0 V, and the threshold voltage Vth of the memory cell is 1 V.
When the pass potential Vpass is 10 V and the capacitance coupling ratio between the channel of the NAND string and the word line is 0.5, V _SS + α ′ = 0 + (10−1−0) × 0.5 = 4.
It becomes 5V.

As a result, electrons are injected into the floating gates of the memory cells on the selected word line in the NAND strings A2 and A4 that are not originally selected as the write targets, so that the operation margin is reduced, and in some cases, the operation margin is reduced. May cause incorrect data to be written.

Therefore, an object of the present invention is to provide a memory cell array configuration of a shared bit line type,
An object of the present invention is to provide a nonvolatile semiconductor memory device that can prevent erroneous writing of data during a writing operation and can increase an operation margin, and a data writing method thereof.

[0027]

According to a first aspect of the present invention, a string is constituted by a predetermined number of memory cells having channels connected in series.
A shared bit line type memory cell array to which a plurality of strings sharing a word line for each bit line are connected, and at the time of a write operation, a string to be written is selected from a group of strings sharing the bit line, and In a nonvolatile semiconductor memory device in which the potential of each bit line is set to a potential corresponding to write data and data is written to a memory cell on a selected word line in a selected string, channels of all strings in the string group are set to A precharge means for precharging to a level of 1 and bringing a channel into a floating state; and a booster for boosting the channels of all strings in a string group to a second level higher than the first level by capacitive coupling with a word line. Means.

According to a second aspect of the present invention, there is provided a shared bit line type in which a string is formed by a predetermined number of memory cells having channels connected in series, and a plurality of strings sharing a word line for each bit line are connected. During a write operation, a string to be written is selected from a group of strings sharing a bit line, and the potential of each bit line is set to a potential according to write data. In a data writing method for a nonvolatile semiconductor memory device in which data is written to a memory cell on a word line, a channel of all strings in a string group is precharged to a first level and a channel is set to a floating state. Step and check all strings in the string group. It is characterized in that it has a boosting step which boosts a channel at a second level higher than the first level by capacitive coupling with the word lines.

In the present invention, in the memory cell, the amount of charge stored in the charge storage portion changes according to the voltage applied to the word line and the bit line, and the threshold voltage changes according to the change. It stores data of a value corresponding to the threshold voltage, and is electrically rewritable. This memory cell stores n bits (n ≧ 1) of data, and therefore has 2 ⁿ −1 programmed states and one erased state. Typically, a floating gate transistor is used as such a memory cell. In a string, typically, one end of a memory cell connected in series is connected to a bit line via a selection transistor, and a gate of the selection transistor is connected to a selection gate line.

In the first and second aspects of the present invention, the memory cell array typically comprises a predetermined number of strings arranged in a matrix in a row direction and a column direction, and in a column direction. It is divided into multiple blocks. Each block is composed of a plurality of strings arranged in the row direction, and strings in the same block share a word line. During a write operation, a block to be written is selected from a plurality of blocks. Here, the string groups in the first invention and the second invention of the present invention are arranged in the same block. In this case, the channels of all the strings in the string group are precharged to the first level in the precharge means (precharge step), and the channels of all the strings in the selected block are set to the floating state. When the channels of all the strings in the string group are boosted to the second level by the boosting means (boost step), the channels are precharged to the first level and floated.
The channels of all the strings in the selected block are boosted to the second level.

In the first aspect of the present invention, the precharge means typically precharges the channel to the first level by charging from the bit line side. In the second aspect of the present invention, in the precharge step, typically, the channel is first charged by charging from the bit line side.
Precharge to level. Here, the first level is typically an upper limit potential that can be applied to the channel of the string from the bit line side, and is a potential lower than the bit line potential by the threshold voltage of the selection transistor. is there. At this time, the bit line potential is preferably set to, for example, the power supply potential V _CC .

In the first aspect of the present invention, the booster typically further boosts the channel precharged to the first level by the precharger to the second level. Preferably, the booster sets the channel to the second level by setting the potential of the word line to a pass potential higher than the first level by at least the threshold voltage of the memory cell after writing. Increase the pressure. In the second aspect of the present invention, in the boosting step, typically, the channel precharged to the first level by the precharge means is further boosted to the second level. In the boosting step, preferably, the potential of the word line is set to:
By setting the pass potential higher than the first level by at least the threshold voltage of the memory cell after writing, the channel is boosted to the second level. Here, the second
Is typically set to a channel potential (write inhibit potential) required to prevent data from being written to a memory cell in a selected string and a memory cell in an unselected string which are write-inhibited. ). In addition, the pass potential can sufficiently raise the channel of the selected string on the non-write side and the channel of the unselected string to the write inhibit potential within a range lower than the program potential applied to the selected word line during the write operation. Selected for potential.

In the first aspect of the present invention, the nonvolatile semiconductor memory device includes a data latch means for storing write data and a potential of each bit line set to a potential corresponding to the write data stored in the data latch means. Bit line potential setting means for setting, and string selecting means for selecting one string from a group of strings,
Preferably, the channel is precharged to the first level by the precharge means, and the channel is boosted to the second level by the boosting means. The bit line potential is set by the line potential setting means. In the second aspect of the present invention, preferably, the channel is precharged to a first level in a precharge step, and further, the channel is boosted to a second level in a boosting step. One string is selected from among them, and the potential of each bit line is set to a potential corresponding to write data.

According to the first and second aspects of the present invention configured as described above, at the time of the write operation, all the strings in the string group sharing the bit line are selected, and all of the strings are selected. By precharging the channel to the first level and making it floating, and further boosting the channel to a second level higher than the first level by capacitive coupling with the word line, the strings in the string group sharing the bit line Channels of all strings can be charged to a sufficient write inhibit potential. And
Thereafter, a write target string is selected from the string group, the potential of each bit line is set to a potential corresponding to write data, and data is written to a memory cell on a selected word line in the selected string. Erroneous writing of data to the memory cells in the selected string can be prevented, and the operation margin can be increased.

[0035]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an NA according to an embodiment of the present invention.
FIG. 2 is a schematic diagram illustrating a configuration example of an ND type flash memory.
As shown in FIG. 1, in this NAND flash memory, a row circuit 2, a column circuit 3, a substrate potential control circuit 4, and the like are connected to a memory cell array 1.

The memory cell array 1 includes a plurality of NAND strings arranged in a matrix in the row and column directions, and word lines, bit lines, select gate lines, source lines, and the like connected to these NAND strings. ing. The specific configuration of the memory cell array 1 will be described later in detail with reference to FIG. The memory cell array 1 is divided into a plurality of blocks (blocks 1 to K) in a column manner. In each block, a predetermined number of NAND strings sharing a word line and a select gate line are arranged in parallel in the row direction.
This block is an erasing unit when erasing data stored in a memory cell.

The row circuit 2 and the column circuit 3 are for selecting an arbitrary memory cell in the memory cell array 1 by the operation thereof. In this case, the row circuit 2 includes a row decode circuit of each block, and is connected to a booster circuit that supplies a predetermined word line potential during operation. The column circuit 3 includes a column decode circuit, a sense amplifier circuit and a data latch circuit connected to each bit line, a bit line potential setting circuit, and the like. The substrate potential control circuit 4 controls the potential of the semiconductor substrate region where the memory cell array 1 is formed.

Further, the NAND flash memory has a control circuit 5 for controlling a write operation, a read operation, an erase operation and the like. From the control circuit 5, a signal line for supplying a control signal to the row circuit 2, the column circuit 3, and the substrate potential control circuit 4 is led out.

FIG. 2 is an equivalent circuit diagram showing a configuration example of the memory cell array 1 of this NAND flash memory. In this embodiment, as an example, a NAND string group sharing the same bit line has two NANs.
D string, and eight memory cell transistors are connected in series (NAN) in each NAND string.
D connection) will be described.

As shown in FIG. 2, in the memory cell array 1, the NAND strings A1, A1 are connected to the bit line BL1.
A2 is connected, and NAND strings A3 and A4 are connected to the bit line BL2. These NAND strings A1 to A4 share word lines and select gate lines, and are NAND strings arranged in the same block.

NAN connected to bit line BL1
The D string A1 includes an enhancement-type selection transistor SGT11, a depletion-type selection transistor SGT12, memory cells M10 to M17, and an enhancement-type selection transistor SGT13. The NAND string A2 includes a depletion-type selection transistor SGT22. And a memory cell M20 to M27 and an enhancement-type selection transistor SGT23. The NAND string A3 connected to the bit line BL2 includes an enhancement type selection transistor SGT31, a depletion type selection transistor SGT32, and memory cells M30 to M37.
And enhancement type selection transistor SGT3
3, the NAND string A4 includes a depressin type selection transistor SGT42, an enhancement type selection transistor SGT41, and a memory cell M4.
0 to M47 and an enhancement type selection transistor SGT43. Enhancement type selection transistors SGT11, SGT21, SGT
31 and the threshold voltage Vthsg1 of the SGT 41, and the enhancement type select transistors SGT13 and SG
Threshold voltage Vthsg of T23, SGT33, SGT43
3 is, for example, about 1.5 V, and is a depletion type selection transistor SGT12, SGT22, SGT.
32, the threshold voltage Vthsg2 of the SGT 42 is, for example, about -1.5V.

In the NAND string A1, the drain of the memory cell M10 is connected to the selection transistor SGT1.
2, the memory cell M17 is connected to the bit line BL1 via SGT11, and the source of the memory cell M17 is connected to the selection transistor SGT13.
Is connected to the source line SL via In the NAND string A2, the drain of the memory cell M20 is connected to the bit line BL1 via the selection transistors SGT21 and SGT22, and the source of the memory cell M27 is connected to the source line SL via the selection transistor SGT23. The control gates of the memory cells M10 to M17 and the memory cells M20 to M27 are connected to word lines WL0 to WL7, respectively. The gates of the select transistors SGT11 and SGT22 are connected to a select gate line SGL1, and the select transistors SGT1
2, the gate of SGT21 is connected to the select gate line SGL2, and the gates of the select transistors SGT13, SGT23 are connected to the select gate line SGL3.

The NAND strings A3 and A4 connected to the bit line BL2 and the two NAND strings connected to other bit lines (not shown) have the same connection relationship as described above.

In the memory cell array 1, data is written and read in page units.
At this time, each memory cell of the memory cell array 1 has 1-bit binary data, that is, data "
FIG. 3 shows the correspondence between the distribution of the threshold voltage of the memory cell and the data content when one-bit binary data is stored in one memory cell. Show the relationship.

As shown in FIG. 3, the threshold linear pressure Vth of the memory cell takes two states corresponding to data "0" and "1". That is, in FIG. 3, distribution A is a distribution of memory cells in which data "0" is written and brought into a positive threshold voltage programmed state. In this case, threshold voltage V
The target value of th is about 1V. The distribution B is a distribution of memory cells in which data "1" is written and in an erased state with a negative threshold voltage. In this case, the target value of the threshold voltage Vth is about -3V. .

Next, a method of writing data to the NAND flash memory according to the embodiment having the above-described configuration will be described. NAN according to this embodiment
A method of writing data in a D-type flash memory is to select all NAND strings in a write selection block in a shared bit line type memory cell array configuration,
After charging the channels of all the strings, setting these channels to a floating state, and boosting the voltage by capacitive coupling with a word line, one NA string is selected from a group of NAND strings sharing a bit line.
The ND string is selected, and the potential of each bit line is set to a potential corresponding to write data. That is, after "floating the channel of the NAND string and boosting 0 according to the rise of the word line potential,""selection of NND string by selection gate line and setting of bit line potential according to write data"
Is performed.

FIG. 4 is a timing chart for explaining a data writing method of the NAND flash memory according to the embodiment. In FIG. 4, the bit lines BL1 and BL2 and the select gate line SG during the write operation are shown.
L1 to SGL3, word lines WL0 to WL7, source line S
L is set, and the NAND string A1
Potentials (channel potentials) of nodes N1 to N4 of.
ch1 to Vch4.

Hereinafter, a specific operation in the data write method of the NAND flash memory according to the embodiment will be described with reference to the timing chart shown in FIG.

As shown in FIG. 4, first, select gate line S
With GL1 to SGL3, word lines WL0 to WL7, and source line SL set to the potential V _SS , all bit lines BL1 and BL2 in the selected block are disconnected from the sense amplifier / data latch circuit of the column circuit 3 and set to the potential. It is set to V _SS (time t0). At this time, the NAND strings A1 to A4 are disconnected from the bit lines BL1 and BL2, respectively, and the potentials Vch1 to Vch of the nodes N1 to N4 are set.
It is assumed that ch4 is at the potential V _SS .

In this state, at time t1, first, the potentials of the select gate lines SGL1 and SGL2 are set to the potential V _CC . As a result, all the strings in the string group connected to each bit line, that is, in this case, all the NAND strings in the selected block are selected. With this,
The potentials of all the bit lines BL1 and BL2 in the selected block are set to the potential V _CC , and the precharge operation to the channels of all the NAND strings A1 to A4 in the selected block is started. As a result, the nodes N1 to N4 of the NAND strings A1 to A4 are precharged to the potential (Vth-Vthsg1). Here, Vthsg1 is a threshold voltage of the enhancement type select transistor on the bit line side in each of the NAND strings A1 to A4.
It is about 5V. Therefore, in this case, the potentials of the nodes N1 to N4 of the NAND strings A1 to A4 are all about 1.5V.

Next, with all bit lines in the selected block set to the potential V _CC and all NAND strings selected, at time t2, all word lines W in the selected block are set.
The potentials of L0 to WL7 are set to a predetermined pass potential Vpass. This pass potential Vpass is equal to a program potential V
The voltage is lower than PGM and higher than Vth-Vthsg1 at least by the threshold voltage of the memory cell after writing. Here, the pass potential Vpass is selected to be, for example, about 10V. At this time, in each of the NAND strings A1 to A4, when the entire channel potential becomes the potential (Vth-Vthsg1), the selection transistor SGT
11, SGT21, SGT31, and SGT41 are cut off. Thereby, each NAND string A1
Channels A1 to A4 are bit lines BL1 and BL2, respectively.
, And becomes a floating state, and is boosted to a predetermined write inhibit potential by capacitive coupling with a word line.

The channel potentials of the NAND strings A1 to A4 boosted to the write inhibit potential in this manner are:
(Vth−Vthsg1) + α, for example, when V _CC is 3V,
When the threshold voltage of the memory cell after writing is 1 V and the pass potential Vpass is 10 V, if the capacitance coupling ratio between the channel of the NAND string and the word line is 0.5, (V
th−Vthsg1) + α = 1.5 + (10-1-1.5) ×
0.5 = 5.25V.

Thus, the precharging operation and the boosting operation of the channel of the NAND string are completed. Thereafter, a NAND string to be written is selected from a group of NAND strings sharing the bit line, and the potential of each bit line is set to a potential corresponding to write data. Here, for example, the bit line BL1 is set to a non-write bit line (data “1” is written) and the bit line B
L2 is a write bit line (data “0” write), and NAN selected by the select gate line SGL1 in the NAND string group sharing the bit line.
It is assumed that data is written using the D strings A1 and A3 as the selected strings. In addition, word lines WL0 to WL0
It is assumed that word line WL2 of WL7 is selected as a selected word line.

That is, all NAND strings A1 to A
4 is charged to the write-protect potential,
At time t3, for selecting a predetermined NAND string from the NAND strings that share bit lines, while maintaining the selected gate line SGL1 to the potential V _CC, the potential of the select gate line SGL2 is set to the potential V _SS You. As a result, the potential V _CC is applied to the gates of the enhancement type select transistors SGT11 and SGT31 of the NAND strings A1 and A3, and the NAND strings A2 and A3
4 enhancement type selection transistor SGT2
1, a state where the potential V _SS is applied to the SGT 41. Therefore, among the NAND strings that share the bit line, the NAND strings A1 and A3 are selected as write targets, and the paths connected to the bit lines BL1 and BL2 are cut off for the NAND strings A2 and A4 of the unselected strings.

Next, after a predetermined time has elapsed, at time t4, all the bit lines in the selected block are connected to the sense amplifier / data latch circuit of the column circuit 3, and the potential of each bit line is loaded into the data latch circuit. The potential is set according to the write data. In this case, the potential V _CC is applied to the bit line BL1 which is a non-write bit line for writing data “1”.
, And a potential V _SS is supplied to a bit line BL2 which is a write bit line for writing data “0”. As a result, of the selected string, the write-side bit line B
In the NAND string A3 connected to L2,
When the enhancement type select transistor SGT31 is turned on, the entire channel potential charged to the write inhibit potential by the above-described precharge operation and boost operation is discharged to the potential V _SS . On the other hand, in the NAND string A1 connected to the non-write-side bit line BL1 of the selected string, the channel is charged to the write inhibit potential because the enhancement type select transistor SGT11 is held in the cutoff state. Will be retained. In the NAND strings A2 and A4, which are unselected strings, the selection transistors SGT21 and SGT41 of the enhancement type are selected by the selection gate line SGL2 (the set potential is the potential V _SS ).
Are turned off, so that these channels are also kept charged to the write inhibit potential.

At the same time, at time t4, the word line WL0
By increasing the potential of the word line WL2, which is the selected word line among the word lines WL7 to a predetermined program potential VPGM (for example, about 16 V), substantial data writing to the selected memory cell is started. At this time,
Password lines other than the word line WL2 (word lines WL0, WL0,
WL1, WL3 to WL7) are held at the pass potential Vpass. Thereby, in the memory cell M32 on the selected word line WL2 in the NAND string A3, the program voltage VPG applied to the control gate is
Electrons are injected into the floating gate by the electric field of M and the channel potential, and data is written. On the other hand, the channel potentials of the NAND string A1 and the non-selected NAND strings A2 and A4 are at the write inhibit potential (for example, about 5.25 V) due to the precharge operation and the boosting operation described above.
Selected word line WL in ND strings A1, A2, A4
2 in the memory cells M12, M22, M42
The potential difference between the control gate and the channel is about 1
At about 0.75 V, no electrons are injected into the floating gate, and no data is written.

Next, the writing of data to the memory cell on the word line WL2 is finished, the time t5, the potential of the word line WL0~WL7 is reset to the potential V _SS. As a result, the N which is charged to the write inhibit potential
AND string A1 and NAND string A2
A4 channels are both discharged to the potential V _SS. Then, at time t6, the potential of the select gate line SGL1 and bit line BL1 are reset to the potential V _SS, a series of writing operations is completed.

Thereafter, a write verify operation is performed by a known method, but the description is omitted here.

As described above, according to this embodiment,
During the write operation, first, the select all NAND strings write select block, to precharge to the potential (V _CC -Vthsg1) by the charging of the channel of all these NAND string from the bit line side, these channels a floating state, further, by boosting the capacitive coupling with the word lines (V _CC -Vthsg1) + α, it is possible to charge the channels of all strings in the selected block to a sufficient write inhibit potential. Thereafter, a NAND string to be written is selected from a group of strings sharing the bit line, and the potential of each bit line is set to a potential corresponding to the write data, so that substantial data transfer to the memory cell is performed. By starting the write operation, correct data is written only to the memory cells on the selected word line in the selected string without erroneous electron injection into the floating gate of the memory cell on the selected word line in the unselected string. be able to. In other words, after performing “floating and boosting of the channel of the NAND string as the word line potential rises”, “N by the selection gate line
By selecting the AND string and setting the bit line potential according to the write data, it is possible to prevent erroneous writing of data during a write operation while employing a shared bit line type memory cell array structure. And the advantage that the operation margin can be increased.

Further, according to this embodiment, all NAs
After pre-charged to a channel ND string potential (V _CC -Vthsg1), before setting the bit line potential corresponding to the NAND string selection and write data, capacitive coupling between the word line and channels of all the NAND strings By raising the voltage to (V _CC -Vthsg1) + α, the following advantages can be obtained.

That is, a shared bit line type NAN
In the D-type flash memory, in order to solve the problem of the related art that the channel of the non-selected string is not charged to a sufficient write inhibit potential, it is necessary to set each bit line to a potential corresponding to write data. ,
It is considered that a certain effect can be obtained by precharging the channel of the non-selected string in the NAND string group sharing the bit line in advance. Therefore, in addition to method according to the embodiment, as shown in FIG. 5, the channel of the unselected string at time t1 leave charged to the potential (V _CC -Vthsg1), to a subsequent substantial memory cell At the time of write operation (time t5 to t6)
In addition, a method of raising the channel potential by capacitive coupling with a word line is also conceivable.

Here, for comparison, a data writing method of the NAND flash memory according to the operation shown in the timing chart of FIG. 5 will be specifically described. In this case, it is assumed that the memory cell array has the same configuration as that shown in FIG. 2 of this embodiment. FIG. 5 shows the set potentials of the bit lines BL1 and BL2, the selection gate lines SGL1 to SGL3, the selected word line SWL, the password line PWL, and the source line during the write operation.
The potentials (channel potentials) of the nodes N1 to N4 of the NAND strings A1 to A4 are indicated by Vch1 to Vch4.
Further, here, the bit line BL1 is a non-write bit line (data “1” write), the bit line BL2 is a write bit line (data “0” write), and a select gate of a NAND string group sharing the bit line is selected. Line SG
NAND strings A1, A3 selected by L1
Will be described assuming that data is written as a selected string.

As shown in FIG. 5, first, select gate line S
With GL1 to SGL3, word lines WL0 to WL7, and source line SL set to the potential V _SS , all bit lines BL1 and BL2 in the selected block are disconnected from the sense amplifier / data latch circuit of the column circuit 3 and set to the potential. V _SS is set (time t0). At this time, the NAND string A
1~A4 each is disconnected from the bit lines BL1, BL2, the potential of the node N1~N4 shall each a potential V _SS.

In this state, at time t1, select gate line S
GL1, the potential of SGL2 is set to the potential V _CC. As a result, all NAND strings in the selected block are selected. At the same time, all bit lines BL in the selected block
1, BL2 potential of is set to the potential V _CC, a precharge operation is started to channels of all the NAND strings A1~A4 in the selected block. As a result, the nodes N1 to N4 of the NAND strings A1 to A4 are set at the potential (Vth
−Vthsg1) (for example, about 1.5 V).

Next, at time t2, all the bit lines in the selected block are reset to the potential V _SS , and the selection gate lines SGL1 and SGL2 are reset to the potential V _SS . As a result, the channels of all the NAND strings A1 to A4 are disconnected from the bit lines BL1 and BL2, respectively.
It is floating in a state of being charged to a potential (V _CC -Vthsg1). Thereafter, according to the same operation as in the conventional data writing method shown in FIG. 9, setting of the bit line potential according to the write data (time t3) and selection of the NAND string by the selection gate line (time t4) are sequentially performed. The channel of the NAND string is boosted by the rise of the word line potential, and substantial data is written to the selected memory cell (time t5). After this,
The selected word line SWL and the password line PWL are set to the potential V
_When reset to _SS (time t6), the selection gate line S
Reset the GL1 to potential V _SS (time t7), a series of writing operation is completed.

However, in this case, the state of the threshold voltage of the memory cell in each NAND string can be such that the entire NAND string can be sufficiently charged during the precharge operation period (time t1 to t2). May not. That is, since the case shown in FIG. 5 described above, the memory cells in the NAND string, the potential of the word line, by the threshold voltage of at least the memory cell, which is not turned on unless a potential higher than the potential V _SS, In the NAND string, when the threshold voltage of the memory cell near the bit line is high and the memory cell is off, the channel of the memory cell closer to the source line (farther from the bit line) than the memory cell is connected to the bit line No charging from the side. Therefore, the precharge operation as described above is ineffective for the NAND string. For this reason, in a non-selected string in which the potential V _CC cannot be supplied from the bit line side during the boosting operation due to the capacitive coupling with the word line, in some cases, only up to V _SS + α ′ (for example, 4.5 V). Since the voltage cannot be boosted, it is not a fundamental improvement in preventing erroneous writing of data to a memory cell in a non-selected string.

On the other hand, in this embodiment, all the NAND strings in the selected block are selected,
The channels of all the NAND strings are set to the potential (V _CC
−Vthsg1), before selecting the NAND strings by the selection gate line and setting the bit line potential according to the write data, all the NAND strings in the selected block are selected and all of them are selected. the channel of the NAND string by capacitive coupling between the word line (V _CC -Vthsg1) + α (e.g. 5.25V)
Due to the step-up in, even when the threshold voltage in the NAND string there is a high memory cell than the potential V _SS, when the word line potential is higher than a predetermined potential, all in the NAND string The memory cell is turned on. In addition, at this time, since the bit line connected to the NAND string is set to the potential V _CC ,
Entire channel of ND string selection transistor is raised to a potential cut-off (V _CC -Vthsg1).
Then, from this state, a boosting operation by capacitive coupling with the word line is started. Therefore, even when a memory cell having a threshold voltage of, for example, a potential V _SS or higher is included in the NAND string, the channel of the NAND string is reliably entire potential (V _CC -Vthsg1) + α, that is, to boost the write inhibit potential. Therefore, according to this embodiment, by adopting the above configuration,
The advantage that the effect of preventing erroneous writing of data can be enhanced can be obtained.

Although the embodiments of the present invention have been specifically described above, the present invention is not limited to the above embodiments, and various modifications based on the technical idea of the present invention are possible. For example, the configurations, numerical values, operation timings, and the like described in the above-described embodiment are merely examples,
If necessary, different configurations, numerical values, and operation timings may be used.

Specifically, in the above-described embodiment, two NAND strings are connected for each bit line, but this is done by connecting three or more NAND strings for each bit line. Is also good.

In the above-described embodiment, the bit line potential is set to the potential corresponding to the write data at the time t4 at the time of the write operation, and the potential of the selected word line is raised to the program potential VPGM. ,this is,
For example, the potential of the selected word line may be raised to the program potential VPGM after a predetermined time has elapsed since the bit line potential was set to a potential corresponding to the write data.

Further, in the above-described embodiment, the channel of the NAND string is boosted to the write inhibit potential by the same method as the self-boost method.
The channel of the ND string may be boosted to the write inhibit potential.

In the above-described embodiment, a case has been described in which the present invention is applied to a NAND-type flash memory which stores one-bit binary data for one memory cell. Can be applied to a so-called multi-level NAND flash memory in which three or more values of data are stored in one memory cell.

[0074]

As described above, according to the nonvolatile semiconductor memory device and the data writing method thereof according to the present invention, at the time of the write operation, all the strings in the string group sharing the bit line are selected, and all the strings are selected. A group of strings sharing a bit line by precharging a channel of the string to a first level and making the channel floating, and further boosting to a second level higher than the first level by capacitive coupling with a word line Channels of all the strings can be charged to a sufficient write-inhibit potential, after which a string to be written is selected from a group of strings and the potential of each bit line is set to a potential corresponding to the write data And write data to the memory cells on the selected word line in the selected string. Thereby, while employing a shared bit line type memory cell array structure in which a plurality of strings are connected for each bit line, it is possible to prevent erroneous writing of data at the time of a writing operation and to increase an operation margin. This has the effect.

[Brief description of the drawings]

FIG. 1 is a schematic diagram illustrating a configuration example of a NAND flash memory according to an embodiment of the present invention;

FIG. 2 is an equivalent circuit diagram of a memory cell array of the NAND flash memory according to one embodiment of the present invention.

FIG. 3 shows a relationship between a threshold voltage distribution of a memory cell and data contents when one-bit binary data is stored in one memory cell in a NAND flash memory according to an embodiment of the present invention; FIG. 4 is a schematic diagram for explaining a correspondence relationship.

FIG. 4 is a timing chart for explaining a data writing method of the NAND flash memory according to the embodiment of the present invention;

FIG. 5 shows a comparison with a data write method of a NAND type flash memory according to an embodiment of the present invention. 5 is a timing chart used to explain a data writing method in which a channel potential is boosted by capacitive coupling.

FIG. 6 is an equivalent circuit diagram of a memory cell array used for explaining a data writing method of a conventional NAND flash memory using a self-boost method.

FIG. 7 is a timing chart used to explain a data writing method of a conventional NAND flash memory using a self-boost method.

FIG. 8 is an equivalent circuit diagram of a memory cell array used to explain an operation when a data writing method of a conventional NAND flash memory using a self-boost method is applied to a shared bit line type NAND flash memory. .

FIG. 9 is a timing chart used to explain an operation when a data writing method of a conventional NAND flash memory using a self-boost method is applied to a shared bit line type NAND flash memory.

[Explanation of symbols]

1 ... memory cell array, 2 ... row circuit, 3 ...
-Column circuit, 4-Substrate potential control circuit, 5-Control circuit, A1 to A4-NAND string, BL1
... BL4 ... bit line, WL0-WL7 ... word line, SGL1-SGL3 ... select gate line, SL ...
・ Source line

Claims (10)

[Claims] 1. A shared bit line type memory cell array in which a string is constituted by a predetermined number of memory cells having channels connected in series and a plurality of the strings sharing a word line for each bit line are provided. ,
During a write operation, a string to be written is selected from a group of strings sharing a bit line, and the potential of each bit line is set to a potential according to write data, and data is stored in a memory cell on a selected word line in the selected string. A precharge means for precharging the channels of all the strings in the string group to a first level and setting the channels in a floating state; and A non-volatile semiconductor memory device, comprising: boosting means for boosting a channel of the string to a second level higher than the first level by capacitive coupling with a word line. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said precharge means precharges said channel to said first level by charging from a bit line side. 3. The nonvolatile memory according to claim 1, wherein said boosting means further boosts said channel precharged to said first level by said precharge means to said second level. Semiconductor memory device. 4. The boosting means sets the potential of the word line to a pass potential higher than the first level at least by a threshold voltage of a memory cell after writing, thereby setting the channel to the first level. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the voltage is boosted to a level of 2. 5. The nonvolatile semiconductor memory device according to claim 1, wherein: a data latch means for storing write data; and a bit line potential for setting a potential of each bit line to a potential corresponding to the write data stored in said data latch means. Setting means;
String selecting means for selecting one string from the string group; precharging the channel to the first level by the precharging means; 2. The non-volatile memory according to claim 1, wherein after boosting the voltage to the second level, a string is selected by the string selecting means and a bit line potential is set by the bit line potential setting means. Semiconductor storage device. 6. A shared bit line type memory cell array in which a string is constituted by a predetermined number of memory cells having channels connected in series, and a plurality of the strings sharing a word line for each bit line are connected. ,
During a write operation, a string to be written is selected from a group of strings sharing a bit line, and the potential of each bit line is set to a potential according to write data, and data is stored in a memory cell on a selected word line in the selected string. A pre-charging step of precharging the channels of all the strings in the string group to a first level and setting the channels in a floating state; and Boosting the channels of all strings in the group to a second level higher than the first level by capacitive coupling with a word line. 7. The data writing method for a nonvolatile semiconductor memory device according to claim 6, wherein in the precharging step, the channel is precharged to the first level by charging from a bit line side. 8. The non-volatile memory according to claim 6, wherein in the boosting step, the channel precharged to the first level in the precharging step is further boosted to the second level. Data writing method for nonvolatile semiconductor memory device. 9. In the boosting step, the potential of the word line is set to a pass potential higher than the first level at least by a threshold voltage of a memory cell after writing, and the channel is set to the second level. 7. The method according to claim 6, wherein the voltage is boosted to a level. 10. The channel is precharged to the first level in the precharging step;
After boosting the channel to the second level in the boosting step, one string is selected from the string group, and the potential of each bit line is set to a potential according to write data. Claim 6
The data writing method of the nonvolatile semiconductor memory device described in the above.