JP2000223673A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high reliability and high integration by employing a thin gate insulation film having required breakdown strength for MOSFETs and capacitors in each circuit element where only a power supply voltage is applied to the gate insulation film and employing a thick gate insulation film for those where a voltage two times as high as the power supply voltage is applied to the gate insulation film. SOLUTION: Voltages being applied to respective elements constituting a boosted voltage generating circuit is sorted into two types of VDD and 2VDD wherein a thin gate insulation film is employed in MOSFET Q3, TQ4, Q8, Q9 and MOS capacitors C1-6 being applied only with VDD. A thick gate insulation film is employed in the MOSFETs Q1, Q2, Q5, Q11, Q12 in first booster circuit and the MOSFETs Q6, Q7, Q10 in second booster circuit being applied with a large voltage such as 2VDD thus ensuring a required breakdown strength of element.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technology effective when used in a dynamic RAM (random access memory) having a triple boosted voltage generation circuit.

[0002]

2. Description of the Related Art A dynamic RAM having a pumping circuit for forming a substrate back bias voltage and a boosted voltage.
For example, Japanese Patent Application Laid-Open No. 3-214669 is disclosed.

[0003]

When writing a high level of a bit line to a dynamic memory cell comprising a storage capacitor and an address selection MOSFET, the word line selection level is set with respect to the bit line high level. It is necessary to use a high voltage that is boosted by the threshold voltage of the MOSFET. That is, the word line selection level is determined based on the high level of the bit line. With the miniaturization of elements due to the increase in storage capacity, the gate oxide film of the address selection MOSFET is also made thinner than that of the previous generation, and the electric field strength of the gate oxide film becomes a problem.

For example, the power supply voltage VDD supplied from an external terminal is reduced to about 3.3 V, and the operating voltage of the sense amplifier is reduced to about 2.2 V. Thus, the selection level of the word line can be suppressed as low as about 3.8V. In this case, the boosted voltage of about 3.8 V can be obtained theoretically even by using a double boosting circuit. However, the power supply voltage VDD is allowed to have a relatively large fluctuation range. When the voltage VDD is 2.2
Even in a state where the voltage has dropped to around V, a certain current supply capacity is necessary to stably secure the boosted voltage VPP such as the above 3.8 V in the word line selecting operation requiring a relatively large drive current. It is preferable to use a pumping circuit that forms a triple boosted voltage.

However, in such a pumping circuit, a boosted voltage that is three times as high as the power supply voltage is formed.
In order to prevent the gate insulating film of the S capacitor from being broken, it is necessary to form the gate insulating film thick. As a result, the current in the ON state is reduced in the MOSFET, and the capacitance value is reduced in the MOS capacitor. Therefore, in the double boost type pumping circuit, there is a problem that the size of each element must be increased in order to obtain the necessary current supply capacity and capacitance value.

An object of the present invention is to provide a semiconductor integrated circuit device provided with a boosted voltage generation circuit that realizes high reliability and high integration. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a triple boosting pumping circuit, of each circuit element, the MOSFET and the capacitor which only apply the power supply voltage to the gate insulating film are thin gate insulating films having the required withstand voltage, and the double power supply voltage is applied to the gate insulating film. Such a film is a thick gate insulating film having a required breakdown voltage.

[0008]

FIG. 1 is a circuit diagram showing one embodiment of a pumping circuit for performing a triple boosting operation used in a boosting voltage circuit according to the present invention. In the figure, the P-channel MOSFET is distinguished from the N-channel MOSFET by placing a mark on the gate electrode portion like the MOSFET Q1. Further, a channel portion indicated by a thick line indicates a thick gate insulating film, and a thin line indicates a thin gate insulating film.

The oscillation pulses OSCT and OSCB are pulses having phases opposite to each other. The pumping circuit of this embodiment is generally composed of a first booster circuit for forming a boosted voltage to be output and the first booster circuit. Each switch MOSF to configure
It is configured in combination with a second booster circuit for forming the ET switch control signal. Oscillation pulse OSCT
Is a P-channel type MO through an inverter circuit IV1.
The signal is transmitted to the input node N3 of the CMOS inverter circuit including the SFET Q1 and the N-channel MOSFET Q2.

The output signal of the inverter circuit IV1 is
It is supplied to one electrode (node N1) of MOS capacitor C1 via inverter circuit IV2. The other electrode (node N2) of MOS capacitor C1 and power supply voltage V
A precharge MOSFET Q3 is provided between the power supply and the power supply DD. The boosted voltage (2VDD) formed by the booster circuit including the inverter circuit IV2, the MOS capacitor, and the MOSFET Q3 is applied to the P-channel type MOS.
The MOSFET Q1 is supplied to the source of the FET Q1.
And Q2 as the operating voltage of the CMOS inverter circuit. The MOSFET Q1 is formed in an independent N-type well region, and the N-type well region is connected to a source. In the circuit diagram, the source and the channel portion of the MOSFET Q1 are shown as being shared.

A CM comprising the MOSFETs Q1 and Q2
The output signal of the OS inverter circuit is a MOS capacitor C
3 is supplied to one electrode (node N4). This MO
A P-channel type precharge M is provided between the other electrode (node N5) of the S capacitor C4 and the power supply voltage VDD.
An OSFET Q5 is provided. The triple boosted voltage 3VDD formed at the node N5 is transmitted to the boosted output terminal VPP by a P-channel type output switch MOSFETQ.
11 are provided.

When the oscillation pulse OSCT is at a low level,
The output signal of the inverter circuit IV1 becomes high level, the output signal of the inverter circuit IV2 becomes low level,
The S capacitor C1 is precharged to VDD through the precharge MOSFET Q3 which is turned on at this time. The high level of the output signal of the inverter circuit IV1 turns on the N-channel MOSFET Q2 and sets the node N4 to low level. At this time, the N-channel type precharge MOSFET Q
5 is turned on, and the MOS capacitor C3 is precharged to the power supply voltage VDD.

When the oscillation pulse OSCT changes from the low level to the high level, the output signal (node N1) of the inverter circuit IV2 becomes a high level such as the power supply voltage VDD. At this time, the precharge MOSFET Q3 is turned off and the node N2 is turned off. The potential is set to a boosted voltage such as 2VDD. The low level of the output signal of the inverter circuit IV1 turns on the P-channel MOSFET Q1 and transmits the boosted voltage 2VDD of the node N2 to the node N4. As a result, the potential of the node N5 of the other electrode of the MOS capacitor C3 becomes equal to the potential of the inverter circuit I5.
The output voltage VDD of V2, the voltage VDD held in the MOS capacitor C1, and the voltage VDD held in the MOS capacitor C3 are added to form a boosted voltage 3VDD that is three times the power supply voltage VDD.

In synchronization with the triple boosting, the P-channel MOSFET Q11 is turned on, and the boosted voltage 3
VPP is transmitted to a parasitic capacitance provided at the output terminal VPP. The output terminal VPP has a parasitic capacitance of a load circuit such as a word line driving circuit (not shown), that is, a wiring capacitance or a PN junction capacitance such as an N-type well region where a P-channel MOSFET in which the word line driving circuit is formed is formed. Is connected, and the boosted voltage VPP
Holding. N-channel type MO with diode connection
The SFET Q12 charges up the above-described parasitic capacitance connected to the output terminal VPP by the power supply voltage VDD when the power is turned on.

The precharge MOSFETs Q3 and Q5
In addition, a boosted voltage generation circuit having an oscillation pulse OSCB as an input is provided for switch control of the output switch MOSFET Q11. That is, the MOS capacitor C1
And precharge MOSFET Q for precharging C3
When the gate voltages of 3 and Q5 are set to a high level like the power supply voltage VDD, the potentials of the nodes N2 and N5 become VDD-Vth
(Respective threshold voltages of MOSFETs Q3 and Q5)
It will drop like Therefore, the oscillation pulse OSCB
Is supplied to the MOS capacitor C5 through the inverter circuits IV7 and IV8, and the MOSFET Q
9 and the precharged voltage is added, and 2VDD
-Vth to form a boosted voltage
3 and Q5.

Since the oscillation pulse OSCT transmitted to the capacitors C1 and C3 and the oscillation pulse OSCB transmitted to the capacitor C5 have an opposite phase relationship to each other, when precharging the MOS capacitors C1 and C3, That is, when the precharge MOSFETs Q3 and Q5 are turned on, the MOS capacitor C5
As a result, a boosted voltage can be formed.

Inverter circuits IV5 and IV6 receiving oscillation pulse OSCB, MOS capacitor C4, P-channel MOSFET Q6 and N-channel MOSFET
The CMOS inverter circuit including the TQ7, the MOS capacitor C6, and the precharge MOSFET Q10 are booster circuits for forming a triple boosted voltage 3VDD, and form a control signal supplied to the gate of the output MOSFET Q11. That is, when precharging the node N4, the gate voltage of the P-channel MOSFET Q11 is set to the boosted voltage 3VDD to turn off the MOSFET Q11, thereby preventing the charge from leaking from the output terminal VPP to the node N4.

Each of these circuits is constituted by a circuit similar to the circuit for forming the triple boosted voltage to be output, except that the oscillation pulse OSCB has a phase opposite to that of the oscillation pulse OSCT. Therefore, also in the booster circuit for forming the switch control signal, the precharge MO
Inverter circuits IV3 and IV4 receiving the above-mentioned oscillation pulse OSCT, MOS capacitor C2 and diode-type precharge MOSFET Q which require a boosted voltage for switch control of SFETs Q8 and Q10.
4 is provided.

The MOS capacitors C1 to C6 are:
Although not particularly limited, an N-channel MOSFET formed in an N-type well, that is, a depletion type M
The OSFET is composed of a MOS capacitor having a gate and a substrate (source, drain). These gate insulating films are thin gate insulating films as shown in FIG.

FIG. 2 is a timing chart for explaining the operation of the booster circuit according to the present invention. The oscillation pulses OSCT and OSCB have a complementary relationship such that when one is at a high level, the other is at a low level, in other words, the oscillation pulses are in an inverse relationship. Oscillation pulse OSC
When T is low level and OSCB is high level,
The node N1 associated with the capacitor C1 is at a low level,
The node N2 is set to the power supply voltage VDD by the ON state of the precharge MOSFET Q3. Similarly, the node N4 related to the capacitor C3 is at a low level,
Reference numeral 5 is set to the power supply voltage VDD by turning on the precharge MOSFET Q5. Therefore, at the precharge timing as described above, a potential difference corresponding to the power supply voltage VDD is not generated in the capacitors C1 and C3, and the gate and the source of the MOSFET Q1 are set to the same potential.

When the oscillation pulse OSCT becomes high level,
When CB changes to low level, a high-level (VDD) output signal of the inverter circuit IV2 is supplied to the node N1 associated with the capacitor C1. Therefore, the potential of the node N2 is set to a boosted voltage such as 2VDD obtained by adding the voltage VDD held in the capacitor C1 to the high-level output signal. However, the capacitor C
1, the potential difference between both electrodes remains at VDD,
Only such a voltage VDD is applied to the gate insulating film of the capacitor. The boosted voltage 2VDD is transmitted to the node N4 related to the capacitor C3 through the P-channel MOSFET Q1 which is turned on by the low level of the output signal of the inverter circuit IV1. Therefore, the potential of the node N5 becomes equal to the boosted voltage 2VDD and the capacitor C
The boosted voltage is 3VDD, to which the voltage VDD held at 3 is added. However, the potential difference between both electrodes of the capacitor C1 remains at VDD, and only the voltage VDD is applied to the gate insulating film of the MOS capacitor.

At the boost output timing, the low level of the node N3 is supplied to the gate of the P-channel MOSFET Q1, and the boost voltage 2VDD is applied to the gate. At this time, also in the N-channel MOSFET Q2 which is turned off, a large voltage such as 2VDD is applied between the gate and the drain similarly to the above. And the precharge MOSFET Q
5, the potential of the node N5 is 3VDD at the above-described boosting timing, so that about 2VDD
Is applied. Output MOSFET Q
11 is a MOSFET Q at the gate at the output timing.
Since the power supply voltage VDD is supplied through 10, a voltage of about 2 VDD at the maximum is applied to the gate insulating film.

A precharge MOSFET and an output MOS constituting a first booster circuit for forming the boosted voltage VPP
The second booster circuit for forming the switch control signal of the FET also uses the booster circuit having the same circuit configuration, and the voltage applied to each of them is the same as above.

In the actual boosting operation, the nodes N2 and N
The potentials of N4 and N5 decrease due to charge sharing with the output capacitance (parasitic capacitance) due to the ON state of the output MOSFET Q11. As described above, the boosted voltage VPP is increased to 3.8 V in accordance with the word line selection level. In this case, since the average value of the potential of the output terminal VPP is about 3.8 V, the state of the voltage difference is not maintained during the entire period in which the oscillation pulse OSCT is at the high level. However, in the second booster circuit, since the load of the booster circuit is a MOSFET, a potential difference as shown in FIG. 2 is applied to the gate insulating film of each MOSFET and capacitor.

As described above, in each element constituting the boosted voltage generating circuit, the voltage applied to each element is divided into two types, VDD and 2VDD. Therefore, the MOSF to which only VDD is applied corresponding to the voltage applied to each element.
The ET and MOS capacitors have a thin gate insulating film, increase the operating current in the ON state in a MOSFET, and secure a large capacitance value in a small occupied area in a MOS capacitor.

On the other hand, the MOSFET of the first booster circuit to which a large voltage such as 2VDD is applied.
The gate insulating films of Q1, Q2 and Q5, Q11 and Q12, and the MOSFETs Q6, Q7 and Q10 of the second booster circuit are formed thick so as to prevent gate dielectric breakdown. Thus, the boosted voltage generation circuit can have a desired current supply capability with a small element size while securing a necessary element withstand voltage.

FIG. 3 is an overall schematic block diagram of one embodiment of a dynamic RAM on which the boosted voltage generation circuit according to the present invention is mounted. An address signal input from the address terminal Ai in a time-division manner is taken into the address buffer 101. The address buffer 101
It is composed of an X address buffer (X ADDRESS BUFFER) and a Y address buffer (Y ADDRESS BUFFER), and takes in respective address signals input from the address terminals Ai in a time-division manner.

X captured in the X address buffer
The address signal consists of an X latch (XLATCH) and a predecoder (P
RE-DEC) 102. The Y address signal taken into the Y address buffer is a Y latch (YLATCH).
And a Y-decoder (Y) via a pre-decoder (PRE-DEC) 103
DEC) 104. A part of the signal of the Y address is supplied to a mat control circuit included in the word line selection circuit 105.
(MAT CONTROL), an amplifier circuit (WA / MA) 114, and a read / write control circuit (R / W CONTROL) 110. The word line selection circuit 105 is connected to the mat control circuit
It consists of a decoder (XDEC). The memory section includes a memory mat (MAT) 106 and a sense amplifier (SA) 107.

The memory mat 106 has a dynamic memory cell composed of an address selection MOSFET and a storage capacitor arranged in a matrix at the intersection of a word line and a bit line.
In a memory having a large storage capacity such as 6 Mbits, the memory section is divided into a number of sub-arrays. The word line of the memory mat specified by the address signal is selected from among a large number of memory mats by the X decoder included in the word line selection circuit 105, and the Y decoder 104 selects the word line of the memory mat specified by the address signal. The bit line is selected.

During a read operation, the main amplifier MA of the amplifier circuit 114 is controlled by the read / write control circuit 110.
Operates to amplify the read signal from the memory unit and output it from the data terminal DQ through the data output circuit (DOUT BUFFER) 111. During a write operation,
The write amplifier WA of the amplifier circuit 114 is operated by the read / write control circuit 110, and the write signal input from the data terminal DQ is transmitted to the selected memory cell of the memory unit through the data input circuit (DIN BUFFER) and the write amplifier WA. Is written to. Clock buffer (CLOCK BU
F) 108 is a row address strobe signal / RAS,
Upon receiving a column address strobe signal / CAS, a write enable signal / WE and an output enable signal / OE, a clock control circuit (CLOCK CONTROL) 109
To form various control signals necessary for the internal operation.

In this embodiment, an internal voltage generating circuit 113 for generating an operating voltage of the memory circuit is provided. The internal voltage generating circuit 113 includes a booster circuit VPP-GEN,
A step-down circuit VDL-GEN, VPERI-GEN and a negative voltage generation circuit VBB-GEN are included. The step-down circuit V
DL-GEN uses low power consumption and miniaturized MOSFE
An internal voltage VDL obtained by stepping down the power supply voltage VDD is formed, for example, to protect the gate withstand voltage of T. This internal voltage VDL
Is used as an operating voltage of the sense amplifier 7, although there is no particular limitation. The step-down circuit VPERI-GEN also has an internal voltage V which is reduced from the power supply voltage VDD for low power consumption and protection of the gate breakdown voltage of the miniaturized MOSFET.
Form PERI. This internal voltage VPERI is used as the operating voltage of peripheral circuits other than the circuit that transmits and receives signals to and from the external terminal.

The word line to which the memory cell is connected needs to be higher than the internal step-down voltage VDL corresponding to the high level of the bit line by the threshold voltage of the address selection MOSFET or more. In order to form such a high voltage, a booster circuit VPP- using a charge pump circuit is used.
A GEN is provided. The booster circuit VPP-GEN includes:
A boosted voltage of about 3.8 V is formed using a pulse signal generated by an oscillation circuit or the like that operates at the power supply voltage VDD.

The booster circuit VPP-GEN corresponds to FIG.
The boosting voltage generation circuit as shown in FIG. 5 monitors the formed boosting voltage VPP, stops the oscillation pulse when the desired voltage reaches 3.8 V, and raises the boosting voltage VPP to 3.8 V by a word line selecting operation or the like. The control circuit is configured to supply an oscillating pulse to perform the above-mentioned boosting operation when the potential drops to the following potential.

A negative voltage VBB such as -1.0 V is supplied to a semiconductor region or a substrate on which the memory cell is formed. Address selection MOSF constituting the memory cell
The threshold voltage of the ET is as large as about 1.6 V because the gate insulating film is formed thicker than MOSFETs of peripheral circuits such as a sense amplifier and an address selection circuit and the above-described supply of the negative voltage VBB. Thus, the leakage current in the off state can be reduced to extend the information retention time of the storage capacitor.

FIG. 5 is a circuit diagram of a simplified embodiment from address input to data output centering on the sense amplifier section of the dynamic RAM according to the present invention. In the figure, a sense amplifier 16 sandwiched between two sub-arrays 15 from above and below and a circuit provided in the intersection area 18 are exemplarily shown, and others are shown as block diagrams. In FIG.
Although the circuit symbols assigned to the SFETs partially overlap those in FIG. 1, it should be understood that each has a separate circuit function.

The dynamic memory cell is typically exemplified by one provided between the sub-word line SWL provided in the one sub-array 15 and one of the complementary bit lines BL and BLB. Is shown in The dynamic memory cell has an address selection MOS
It comprises an FET Qm and a storage capacitor Cs. The gate of the address selection MOSFET Qm is connected to the sub word line S
The drain of the MOSFET Qm is connected to the bit line BL, and the source is connected to the storage capacitor Cs. The other electrode of the storage capacitor Cs is shared and supplied with the plate voltage VPLT. MOS above
A negative back bias voltage VBB is applied to the substrate (channel) of the FET Qm. Although not particularly limited, the back bias voltage VBB is set to a voltage such as -1V. The selection level of the sub-word line SWL is higher than the address selection MO with respect to the high level of the bit line.
High voltage V increased by the threshold voltage of SFET Qm
PP.

When the sense amplifier is operated at the internal step-down voltage VDL, the high level amplified by the sense amplifier and given to the bit line is equal to the internal voltage VD
The level is set to L level. Therefore, the high voltage VPP corresponding to the word line selection level is set to VDL + Vth + α. A pair of complementary bit lines BL and BLB of the sub-array provided on the left side of the sense amplifier are arranged in parallel as shown in FIG. These complementary bit lines BL and BLB are connected to input / output nodes of a unit circuit of the sense amplifier by shared switch MOSFETs Q1 and Q2.

The unit circuit of the sense amplifier is composed of N-channel type amplifying MOSFETs Q5 and Q6, whose gates and drains are cross-connected to form a latch, and P-channel type amplifying MOSFETs Q7 and Q8.
It is composed of a MOS latch circuit. N-channel type MOS
The sources of the FETs Q5 and Q6 are connected to a common source line CSN. The sources of the P-channel MOSFETs Q7 and Q8 are connected to a common source line CSP. The common source lines CSN and CSP each have a power switch M
OSFET is connected. Although not particularly limited, the cross area 18 is connected to the common source line CSN to which the sources of the N-channel type amplification MOSFETs Q5 and Q6 are connected.
N-channel type power switch MOSF provided in
An operation voltage corresponding to the ground potential is applied by ETQ14.

Although not particularly limited, the common source line CSP to which the sources of the P-channel amplification MOSFETs Q7 and Q8 are connected is connected to the N-channel power MO for overdrive provided in the cross area 18.
An SFET Q16 and an N-channel power MOSFET Q15 for supplying the internal voltage VDL are provided.
The power supply voltage VDD supplied from an external terminal is used for the overdrive voltage, although there is no particular limitation. Alternatively, the power supply voltage VDD of the sense amplifier operating speed
VPP is applied to the gate to reduce the dependency,
The voltage may be slightly reduced as the voltage is obtained from the source of the N-channel MOSFET whose power supply voltage VDD is supplied to the drain.

The N-channel type power MOSFET
The sense amplifier overdrive activation signal SAP1 supplied to the gate of Q16 is the N-channel type MO.
Activation signal SAP supplied to the gate of SFET Q15
2, and SAP1 and SAP2 are set to a high level in time series. Although not particularly limited, SAP1
And the high level of SAP2 is a signal of the boosted voltage VPP level. That is, the boosted voltage VPP is about 3.8 V, so that the N-channel MOSFETs Q15, Q16
Can be sufficiently turned on. MOSFET
After Q16 is off (signal SAP1 is low), a voltage corresponding to internal voltage VDL can be output from the source side by turning on MOSFET Q15 (signal SAP2 is high).

An equalizing MOSF for short-circuiting a complementary bit line is connected to an input / output node of the unit circuit of the sense amplifier.
ETQ11 and switch MOSFETs Q9 and Q10 for supplying half precharge voltage VBLR to complementary bit lines
A precharge (equalize) circuit is provided. The gates of these MOSFETs Q9 to Q11 are commonly supplied with a precharge signal PCB. A cross area 18 sandwiched between the sub-word driver 17 and the sense amplifier 16 has an IO switch circuit IOSW (local IO).
Switch MOSFET Q19 connecting the
Q20) is placed.

In the cross area 18, in addition to the circuits shown, if necessary, a half precharge circuit for the common source lines CSP and CSN of the sense amplifier, a half precharge circuit for the local I / O line LIO, a main input line A VDL precharge circuit for the output line, a distributed driver circuit for the shared selection signal lines SHR and SHL, and the like are also provided.

The unit circuit of the sense amplifier is connected to the similar complementary bit lines BL and BLB of the lower sub-array 15 via shared switch MOSFETs Q3 and Q4. For example, when the sub-word line SWL of the upper sub-array is selected, the upper shared switch MOSFETs Q1 and Q2 of the sense amplifier are turned on, and the lower shared switch MOSFETs Q3 and Q4 are turned off. The switch MOSFETs Q12 and Q13 constitute a column (Y) switch circuit, and are turned on when the selection signal YS is set to a selection level (high level). I / O lines LIO1 and LIO1B, LIO2
LIO2B etc. are connected.

As a result, the input / output node of the sense amplifier is connected to the upper complementary bit lines BL and BLB to amplify the minute signal of the memory cell connected to the selected sub-word line SWL. Circuit (Q
12 and Q13) through the local input / output lines LIO1, L
Communicate to IO1B. The local input / output lines LIO1, L
IO1B extends along the sense amplifier row, that is, in the horizontal direction in FIG. The local input / output line LI
O1 and LIO1B are the N provided in the cross area 18.
IO consisting of channel type MOSFETs Q19 and Q20
The input terminals of the main amplifier 61 are connected to main input / output lines MIO and MIOB via a switch circuit. The IO switch circuit is switch-controlled by a selection signal formed by decoding an X-system address signal, and its selection level is not particularly limited as described later in order to increase the operating speed. Is used. As will be described later, a CMOS switch configuration in which P-channel MOSFETs are connected in parallel to the N-channel MOSFETs Q19 and Q20, respectively, may be used.

As described above, according to the column selection signal YS,
In the configuration for selecting two pairs of complementary bit lines, the local input / output line LIO and the main input / output line MIO indicated by two dotted lines in the embodiment of FIG. 2 correspond to the two pairs of input / output lines. It is. In the burst mode of the synchronous DRAM, the column selection signal YS is switched by a counter operation, and the local input / output lines LIO1, LIO1B
And the connection between LIO2, LIO2B and two pairs of complementary bit lines BL, BLB of the sub-array is sequentially switched.

The address signal Ai is supplied to the address buffer 5
1 is supplied. The address buffer operates in a time-division manner to receive the X address signal and the Y address signal.
The X address signal is supplied to the predecoder 52, and a selection signal for the main word line MWL is formed via the main row decoder 11 and the main word driver 12. Since the address buffer 51 receives the address signal Ai supplied from the external terminal, it is operated by the power supply voltage VDD supplied from the external terminal, and the predecoder 52 is operated by the step-down voltage VPERI. The main word driver 12 has a boosted voltage VPP
Is operated. A selection signal for the main word line MWL is formed corresponding to the selection signal of the predecoder 52.
The column decoder (driver) 53 receives the Y address signal supplied by the time-division operation of the address buffer 51, and operates with the step-down voltage VPERI. YS is formed.

The main amplifier 61 has a step-down voltage VPE
The signal is output from the external terminal Dout through the output buffer 62 operated by the RI and operated by the power supply voltage VDD supplied from the external terminal. The write signal input from the external terminal Din is taken in through the input buffer 63, and is passed through a write amplifier included in the main amplifier 61 in FIG.
A write signal is supplied to IO and MIOB. The input section of the output buffer is provided with a level shift circuit and a logic section for outputting the output signal in synchronization with a timing signal corresponding to the clock signal.

Although not particularly limited, the power supply voltage VDD supplied from the external terminal is 3.3 V in the first embodiment, and the step-down voltage VPERI supplied to the internal circuit is 2.
5V, and the operating voltage VDL of the sense amplifier is 2.2V. Then, the word line selection signal (boosted voltage) is set to 3.8V. The precharge voltage VBLR of the bit line corresponds to VDL / 2. 1 V, and the plate voltage VPLT is also set to 1.1 V. Then, the substrate voltage VBB is set to -1.0V. The power supply voltage VDD supplied from the external terminal is set to a low voltage of 2.5 V in the second embodiment. The power supply voltage VDD is used as it is as the operating voltage VPERI of the peripheral circuit. In this configuration, when the power supply voltage VDD such as 2.5 V is used, the above 3.8
Since the writing voltage such as V is formed, the boosted voltage generation circuit according to the present invention effectively functions.

Power supply voltage VD supplied from the external terminal
D is set to 3.3 V in the same manner as described above, the step-down voltage VPERI supplied to the internal circuit is set to 2.5 V, the operating voltage VDL of the sense amplifier is set to 1.8 V, and a word line selection signal (step-up voltage) is set. ) May be 3.6V. At this time, the precharge voltage VBLR of the bit line is VDL /
2, and the plate voltage VPLT is also set to 0.9V. And the substrate voltage VBB is -1.0
V. Power supply voltage VD supplied from the external terminal
D may be a low voltage such as 2.5 V in the second embodiment, and the internal step-down voltage VPERI may be reduced to 2 V.

In the address selection MOSFET Qm, the gate insulating film is formed relatively thick, and the threshold voltage is increased by the application of the substrate voltage VBB as described above. On the other hand, in a MOSFET such as a sense amplifier or an address decoder circuit, a thin gate insulating film is formed in order to reduce a threshold voltage and allow a large current to flow. Therefore, in the boosted voltage generation circuit of FIG. 1, MOSFETs Q1 and Q2 having thick gate insulating films
Are formed by the same manufacturing process as the address MOSFET Qm, and the gate insulating film is formed to be thin.
The ETQ3 and the like are formed by the same manufacturing process as the MOSFET constituting the sense amplifier.

The above-described sub-word line is driven by the sub-word line driving circuit, and its substantial operating voltage is
The selection level of the sub-word line is set as PP and the boosted voltage VPP
Or a shared switch MO
In a configuration where the boosted voltage is used also for the switch control of the SFET and VPP is used for controlling the overdrive of the sense amplifier SA, the boosted voltage VP
The load current of P becomes relatively large, and the pumping circuit needs to have a relatively large current supply capability.
The pumping circuit according to the present invention can sufficiently cope with the small element size.

In a triple well configuration in which the boosted voltage VPP is supplied to a well region DWELL having a deep depth and a P-type well region for forming an N-channel MOSFET is formed in the DWELL.
And a P-type substrate have a relatively large parasitic capacitance.
Therefore, as the capacitor provided on the output side of the pumping circuit and holding the boosted voltage VPP, the DWEL
It is possible to utilize the parasitic capacitance of L, stabilize VPP, and reduce the area occupied by the pumping circuit.

The operation and effect obtained from the above embodiment are as follows. That is, (1) In a three-fold boosting pumping circuit, a MOS in which only a power supply voltage is applied to a gate insulating film in each circuit element
FETs and capacitors are thin gate insulating films with the required withstand voltage, and those that require twice the power supply voltage on the gate insulating film are thick gate insulating films with the required withstand voltage to achieve the required element withstand voltage. An effect is obtained that a desired current supply capability can be obtained with a small element size while securing.

(2) As the boosted voltage generating circuit, a first driving circuit which receives a periodic first pulse signal and is operated by a power supply voltage, and an output terminal of the first driving circuit. A first MOS capacitor having one end connected thereto;
A current is provided between the other end of the first MOS capacitor and the power supply voltage, and a current is supplied from the power supply voltage to the other end of the first capacitor during a period when the output signal of the first drive circuit is at a low level. First switch MOS adapted to flow
An FET, a first CMOS inverter circuit that receives an inverted signal of the periodic first pulse signal, and uses the voltage at the other end of the first MOS capacitor as an operating voltage;
A second MOS capacitor having one end connected to the output terminal of the CMOS inverter circuit; and a second MOS capacitor provided between the other end of the second MOS capacitor and the power supply voltage.
Is turned on during the period when the output signal of the CMOS inverter circuit is at the low level, and the second M
A boosted voltage is generated by a second switch MOSFET that charges up the OS capacitor, and a control signal of the first and second switch MOSFETs is inverted with a second pulse signal having a phase opposite to that of the periodic pulse signal. The MOSFETs formed by the same booster circuit and constituting the first and second CMOS inverter circuits, and the second, fourth, and fifth switch MOSFETs correspond to twice the power supply voltage. A MO that constitutes each of the circuits including the first to fourth capacitors is a thick gate insulating film having a withstand voltage.
By making the SFET a thin gate insulating film with a withstand voltage corresponding to the power supply voltage,
An effect that a desired current supply capability can be obtained with a small element size can be obtained.

(3) The second and fourth switch MOSs
The control signal supplied to the gate of the FET is controlled by a control voltage that is approximately twice as high as the power supply voltage using the above-described periodic pulse signal and capacitor, and thereby the threshold voltage of the switch MOSFET is controlled. Since the precharge voltage can be increased without being affected by the voltage, an effect that a desired current supply capability can be obtained with a small element size can be obtained.

(4) The boosted voltage generated by the boosted voltage generating circuit is used for a selection level of a word line to which an address selection terminal of a plurality of dynamic memory cells is connected, so that the dynamic RAM has a high level. The effect that integration and high reliability can be realized is obtained.

(5) The MOSFET for address selection constituting the dynamic memory cell is constituted by the thick gate insulating film, and constitutes a peripheral circuit for forming a selection signal for the word line and the complementary bit line.
By using a thin gate insulating film, it is possible to obtain an effect that a manufacturing process of a dynamic RAM can be used to form a MOSFET and a MOS capacitor of a boosted voltage generation circuit built therein.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say. For example, although the boosted output voltage is double, a booster circuit that internally generates a triple boosted voltage may be used. Further, the booster circuit may be provided separately with a booster circuit which does not have a current supply capability enough to compensate for the leakage current, and may operate it steadily. A specific configuration of the booster circuit can employ various embodiments depending on a combination of a device that forms a boosted voltage to be output and a device that forms a control signal of a boosted level necessary for the operation.

Dynamic RA to which the present invention is applied
Various embodiments can be adopted for the configuration of the sub-array constituting M or the arrangement of a plurality of memory arrays mounted on the semiconductor chip according to the storage capacity and the like. Also,
The configuration of the sub-word driver can take various embodiments. The portion of the input / output interface may be a synchronous dynamic RAM which operates in synchronization with a clock signal. The present invention can be widely used for a semiconductor integrated circuit device provided with a boosted voltage raised to a power supply voltage supplied from an external terminal, in addition to the dynamic RAM.

[0060]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a triple boosting pumping circuit, of each circuit element, the MOSFET and the capacitor which only apply the power supply voltage to the gate insulating film are thin gate insulating films having the required withstand voltage, and the double power supply voltage is applied to the gate insulating film. By forming such a thick gate insulating film having a required breakdown voltage, a desired current supply capability can be obtained with a small device size while securing a required device breakdown voltage.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a boosted voltage generation circuit according to the present invention.

FIG. 2 is a timing chart for explaining an operation of the boosted voltage generation circuit of FIG. 1;

FIG. 3 is an overall schematic block diagram showing one embodiment of a dynamic RAM according to the present invention.

FIG. 4 is a circuit diagram showing a simplified embodiment from address input to data output centering on the sense amplifier section of the dynamic RAM according to the present invention.

[Explanation of symbols]

Q1 to Q20: MOSFET, C1 to C6: MOS capacitor, IV1 to IV7: CMOS inverter circuit, 1
01 ... address buffer, 102 ... X latch predecoder, 103 ... Y latch and predecoder, 104 ... Y decoder, 105 ... word line selection circuit, 106 ... memory mat, 107 ... sense amplifier, 108 ... clock buffer, 109 ... clock Control circuit, 110: read / write control circuit, 111: data output circuit, 112:
Data input circuit, 113 ... internal voltage generation circuit, 114 ...
Amplifying circuit, DRAM: memory chip, 11: main row decoder area, 12: main word driver area, 13
... column decoder area, 14 ... peripheral circuit, bonding pad area, 15 ... meseli cell array (sub-array),
16: sense amplifier area, 17: sub-word driver area, 18: cross area (cross area), 51: address buffer, 52: predecoder, 53: decoder, 61
... Main amplifier, 62 ... Output buffer, 63 ... Input buffer, SBARY ... Subarray, SWD ... Subword driver, SA ... Sense amplifier, IOSW ... IO switch circuit, MA ... Main amplifier, WD ... Write driver.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Eiji Yamazaki, Inventor 5-22-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Hitachi Super SII Systems (72) Inventor Tsuyuki Suzuki Kodaira, Tokyo 5-22-1, Kamimizu Honcho Nippon Cho SII Systems (72) Inventor Hitoshi Tanaka 5-22-1, Kamimizu Honcho, Kodaira City, Tokyo Nichicho Cho LSI Systems F-term (reference) 5B024 AA07 BA27 CA27 5F083 AD00 LA07 LA09 LA16 ZA07

Claims (5)

[Claims] 1. A first booster circuit for forming a boosted voltage twice as high as the operating voltage by using a periodic pulse signal corresponding to an operating voltage level and a first MOS capacitor, and the first capacitor And the second boosted voltage formed by the above and the operation voltage level
And a second booster circuit for forming a boosted voltage three times as high as the operating voltage by adding the voltage of the MOS capacitor of the above. The MOSFET to which the potential difference corresponding to the operating voltage is applied is composed of a thin gate insulating film having a withstand voltage corresponding to the voltage, and the MOSFET to which the potential difference corresponding to the double operating voltage is applied to the gate insulating film. A semiconductor integrated circuit device comprising a thick gate insulating film having a withstand voltage corresponding to a voltage. 2. The first drive circuit according to claim 1, wherein the boosted voltage generating circuit receives the periodic first pulse signal, and operates at a power supply voltage. A first terminal having one end connected to the output terminal of the circuit
And the other end of the first capacitor is provided between the other end of the first MOS capacitor and the power supply voltage, and when the output signal of the first drive circuit is at a low level from the power supply voltage. Switch MOS adapted to allow current to flow toward
An FET, a first CMOS inverter circuit that receives the first pulse signal and uses the voltage at the other end of the first MOS capacitor as an operating voltage, and one end connected to an output terminal of the first CMOS inverter circuit And the second MOS capacitor provided between the other end of the second MOS capacitor and the power supply voltage. The output signal of the first CMOS inverter circuit is turned on during a low level period, and A second switch MOSFET for charging up the second MOS capacitor by a power supply voltage; and a second pulse signal having a phase opposite to that of the periodic pulse signal, and operated at the power supply voltage. A second driving circuit; and a third driving circuit having one end connected to an output terminal of the second driving circuit.
And the other end of the third capacitor is provided between the other end of the third MOS capacitor and the power supply voltage, and when the output signal of the second drive circuit is at a low level from the power supply voltage. Switch MOS adapted to allow current to flow toward
An FET, a second CMOS inverter circuit that receives the second pulse and uses the voltage at the other end of the third MOS capacitor as an operating voltage, and one end connected to an output terminal of the second CMOS inverter circuit A fourth MOS capacitor provided between the other end of the second MOS capacitor and the power supply voltage, wherein the output signal of the second CMOS inverter circuit is turned on during a low level period, and A fourth switch MOSFET for charging up the second MOS capacitor by a voltage, wherein the triple boosted voltage formed by the second capacitor is replaced by a triple boosted voltage formed by the fourth capacitor Output through a fifth switch MOSFET which is turned off by the first and second CMOS inverter circuits. M to be formed
OSFET and the second, fourth and fifth switches M
The OSFET is formed of a thick gate insulating film having a withstand voltage corresponding to a voltage twice as large as the power supply voltage. MOSFETs constituting each of the circuits including the first to fourth capacitors have a withstand voltage corresponding to the power supply voltage. A semiconductor integrated circuit device comprising a thin gate insulating film. 3. The control signal according to claim 2, wherein the control signal supplied to the gates of the second and fourth switch MOSFETs is twice as high as the power supply voltage using the periodic pulse signal and a capacitor. A semiconductor integrated circuit device, which is switch-controlled by the control voltage. 4. The semiconductor integrated circuit device according to claim 3, further comprising: a word line to which address selection terminals of a plurality of dynamic memory cells are connected; and the plurality of word lines and orthogonal to the word lines. And
An input / output terminal of the dynamic memory cell includes a dynamic RAM having a plurality of complementary bit line pairs connected to one of the dynamic memory cells, and the word line is set to a selected level formed by using the boosted voltage. And a semiconductor integrated circuit device. 5. The address selection MOSFET according to claim 4, wherein the address selection MOSFET constituting the dynamic memory cell is constituted by the thick gate insulating film, and a peripheral for forming a selection signal for the word line and the complementary bit line. A semiconductor integrated circuit device, wherein a MOSFET constituting a circuit is constituted by a thin gate insulating film.